CS5509 single-supply, 16-bit, serial-output CMOS converter. CS5509 use

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

CS5509 single-supply, 16-bit, serial-output CMOS converter. CS5509 use

Datasheet Thumbnail

Top Searches for this datasheet

CS5509 Single-supply, 16-bit Converter
CS5509 single-supply, 16-bit, serial-output CMOS converter. CS5509 uses charge-balanced (delta-sigma) techniques provide low-cost, high-resolution measurements output word rates samples second. on-chip digital filter offers superior line rejection 50Hz 60Hz when device operated from 32.768 clock (output word rate Sps). CS5509 on-chip self-calibration circuitry which initiated time temperature ensure minimum offset full-scale errors. power, high resolution, small package size make CS5509 ideal solution loop-powered transmitters, panel meters, weigh scales, battery powered instruments. ORDERING INFORMATION
CS5509-ASZ 16-pin SOIC Lead Free
Delta-sigma Converter
16-bit, Missing Codes Linearity Error: ±0.0015%FS
Differential Input
Pin-selectable Unipolar/Bipolar Ranges Common Mode Rejection
Either 3.3V Digital Interface On-chip Self-calibration Circuitry Output Update Rates 200/second Ultra Power:
VREF+
VREF10
SCLK SDATA DRDY
AIN+
AIN-
Differential order delta-sigma modulator
Serial Interface Logic Digital Filter
Calibration Calibration SRAM CONV XOUT
BP/UP
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2009 (All Rights Reserved)
DS125F3
CS5509
ANALOG CHARACTERISTICS ±5%; 3.3V ±5%; VREF+ 2.5V, VREF- fCLK 32.768 kHz; Bipolar Mode; Rsource with AIN; AIN- 2.5V; unless otherwise specified.) (Notes
Parameter* Accuracy Linearity Error fCLK 32.768 fCLK fCLK 247.5 fCLK (Note (Note (Note (Note (Note (Note Unipolar Bipolar (Note ITotal IAnalog IDigital (Note 0.0015 0.0015 0.0015 0.005 ±0.25 ±0.25 ±0.5 ±0.5 ±0.5 ±0.25 ±0.25 0.16 +2.5 ±2.5 0.003 0.003 0.003 0.0125 ±0.5 LSBrms Unit
Differential Nonlinearity Full-scale Error Full-scale Drift Unipolar Offset Unipolar Offset Drift Bipolar Offset Bipolar Offset Drift Noise (Referred Output) Analog Input Analog Input Range Common Mode Rejection fCLK 32.768 Input Capacitance Bias Current Power Supplies Power Supply Currents (Notes (Note
2.25
Power Dissipation Power Supply Rejection
Notes: Both source resistance shunt capacitance critical determining CS5509's source impedance requirements. Refer text section Analog Input Impedance Considerations. Specifications guaranteed design, characterization and/or test. Applies after calibration temperature interest. Total drift over specified temperature range since calibration power-up input differential. Therefore, Signal Common Mode Voltage VA+. CS5509 accept input voltages analog supply. unipolar mode CS5509 will output input magnitude ((AIN+) (AIN-)) exceeds ((VREF+) (VREF-)) will output input becomes more negative than Volts. bipolar mode CS5509 will output input magnitude ((AIN+) (AIN-)) exceeds ((VREF+) (VREF-)) will output input becomes more negative magnitude than -((VREF+) (VREF-)). outputs unloaded. inputs CMOS levels. Refer Specification Definitions immediately following Description Section.
DS125F3
CS5509
DYNAMIC CHARACTERISTICS
Parameter Modulator Sampling Frequency Output Update Rate (CONV Filter Corner Frequency Settling Time Step) Symbol fout f-3dB Ratio fclk/2 fclk/1622 fclk/1928 1/fout Unit
DIGITAL CHARACTERISTICS
Parameter High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voiltage Input Leakage Current 3-State Leakage Current Digital Output Capacitance
VA+, ±5%; (Notes Symbol (VD+) -1.0 Unit
Pins Except Pins Except (Note Iout
Cout
Notes: measurements performed under static conditions. Iout -100 This guarantees ability drive load. (VOH Iout µA).
3.3V DIGITAL CHARACTERISTICS
(Notes Parameter High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input Leakage Current 3-state Leakage Current Digital Output Capacitance
±5%; 3.3V ±5%; Symbol (VD+) -0.3 0.16 Unit
Pins Except Pins Except (Note Iout
Cout
Specifications subject change without notice
DS125F3
CS5509
SWITCHING CHARACTERISTICS VA+, ±5%; Input Levels: Logic Logic VD+; (Note
Parameter Master Clock Frequency Master Clock Duty Cycle Rise Times Fall Time Start-Up Power-On Reset Period Oscillator Start-up Time Wake-up Period Calibration CONV Pulse Width (CAL CONV High Start Calibration Start Calibration Calibration Conversion CONV Pulse Width CONV High Start Conversion Time Hold Time BP/UP stable prior DRDY falling BP/UP stable after DRDY falls (Note tcpw tscn tbus tbuh tcon 82/fclk 1624/fclk 2/fclk+200 (Note tccw tscl tcal 3246/fclk 2/fclk+200 (Note XTAL 32.768 (Note (Note tres tosu twup 1800/fclk Digital Input Digital Output Digital Input Digital Output (Note trise (Note tfall Internal Oscillator External Clock Symbol fclk 30.0 32.768 53.0 Unit
Start Conversion Conversion
Notes: Specified using points waveform interest. internal power-on-reset activated whenever power applied device. Oscillator start-up time varies with crystal parameters. This specification does apply when using external clock source. wake-up period begins once oscillator starts; when using external fclk, after power-on reset time elapses. Calibration also initiated pulsing high while CONV=1. Conversion time will 1622/fclk CONV remains high continuously.
DS125F3
CS5509
3.3V SWITCHING CHARACTERISTICS ±5%; 3.3V ±5%; Input Levels: Logic Logic VD+; (Note
Parameter Master Clock Frequency Master Clock Duty Cycle Rise Times Fall Time Start-Up Power-On Reset Period Oscillator Start-up Time Wake-up Period Calibration CONV Pulse Width (CAL CONV High Start Calibration Start Calibration Calibration Conversion CONV Pulse Width CONV High Start Conversion Time Hold Time BP/UP stable prior DRDY falling BP/UP stable after DRDY falls (Note tcpw tscn tbus tbuh tcon 82/fclk 1624/fclk 2/fclk+200 (Note tccw tscl tcal 3246/fclk 2/fclk+200 (Note XTAL 32.768 (Note (Note tres tosu twup 1800/fclk Digital Input Digital Output Digital Input Digital Output (Note trise (Note tfall Internal Oscillator External Clock Symbol fclk 30.0 32.768 53.0 Unit
Start Conversion Conversion
DS125F3
CS5509
XIN/2 CONV STATE Standby Calibration Standby
Figure Calibration Timing (Not Scale)
XIN/2 CONV DRDY BP/UP STATE Standby Conversion Standby
Figure Conversion Timing (Not Scale)
DS125F3
CS5509
SWITCHING CHARACTERISTICS
Logic VD+; (Note Parameter Serial Clock Serial Clock Access Time Pulse Width High Pulse Width data valid (Note (Note tfd1 tfd2 Symbol fsclk tcsd Unit
VA+, ±5%; Input Levels: Logic
Maximum Delay Time SCLK falling SDATA Output Float Delay
High output Hi-Z (Note SCLK falling Hi-Z
Notes: activated asynchronously DRDY, will recognized occurs when DRDY high clock cycles. propagation delay time great fclk cycles plus guarantee proper clocking SDATA when using asynchronous SCLK(i) should taken high sooner than fclk after goes low. SDATA transitions falling edge SCLK. Note that rising SCLK must occur enable serial port shifting mechanism before falling edges recognized. returned high before data bits output, SDATA output will complete current data then high impedance.
3.3V SWITCHING CHARACTERISTICS ±5%; 3.3V ±5%; Input Levels: Logic Logic VD+; (Note
Parameter Serial Clock Serial Clock Access Time Pulse Width High Pulse Width data valid (Note (Note tfd1 tfd2 Symbol fsclk tcsd 1.25 Unit
Maximum Delay Time SCLK falling SDATA Output Float Delay
High output Hi-Z (Note SCLK falling Hi-Z
DS125F3
CS5509
DRDY SDATA(o) SCLK(i) Hi-Z MSB-1 MSB-2
DRDY SDATA(o) Hi-Z SCLK(i)
Figure Timing Relationships (Not Scale)
MSB-1
LSB+2
LSB+1
tfd2
DS125F3
CS5509
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supplies Positive Digital Positive Analog (Note (Note Unipolar Bipolar Symbol (VREF+) (VREF-) VAIN VAIN 3.15 4.75 -((VREF+) (VREF-))
(DGND (Note (VREF+) (VREF-) (VREF+) (VREF-) Unit
Analog Reference Voltage Analog Input Voltage
Notes: voltages with respect ground. CS5509 operated with reference voltage with corresponding reduction noise-free resolution. common mode voltage voltage reference value long +VREF -VREF remain inside supply values GND.
ABSOLUTE MAXIMUM RATINGS*
Parameter Power Supplies Ground Positive Digital Positive Analog (Note (Note Symbol Iout (Note VREF pins VINA VIND Tstg -0.3 -0.3 -0.3 -0.3 -0.3 (VD+)-0.3 (VA+)+0.3 (VD+)+0.3 Unit
Input Current, Except Supplies Output Current Power Dissipation (Total) Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
(Notes
Notes: should more positive than (VA+) must always less than (VA+) never exceed +6.0 Applies pins including continuous overvoltage conditions analog input (AIN) pin. Transient currents will cause latch-up. Maximum input current power supply Total power dissipation, including input currents output currents. *WARNING:Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
DS125F3
CS5509
GENERAL DESCRIPTION
CS5509 power, 16-bit, monolithic CMOS converter designed specifically measurement signals. CS5509 includes delta-sigma charge-balance converter, voltage reference, calibration microcontroller with SRAM, digital filter serial interface. CS5509 optimized operate from 32.768 crystal driven external clock whose frequency between 30kHz 330kHz. When digital filter operated with 32.768 clock, filter zeros precisely line frequencies multiples thereof. CS5509 uses "start convert" command start convolution cycle digital filter. Once filter cycle completed, output port updated.When operated with 32.768kHz clock converts updates output port samples/sec.The output port operates synchronous externally-clocked interface format.
Calibration
After initial application power, CS5509 must enter calibration state prior performing accurate conversions. During calibration, chip executes two-step process. device first performs offset calibration then follows this with gain calibration. calibration steps determine zero reference point full scale reference point converter's transfer function. From these points calibrates zero point gain slope used properly scale output digital codes when doing conversions. calibration state entered whenever CONV pins high same time. state CONV pins power-on recognized commands, will executed until 1800 clock cycle wake-up period. CONV become active (high) during 1800 clock cycle wake-up time, converter will wait until wake-up period elapses before executing calibration. wake-up time elapsed, converter will standby mode waiting instruction will enter calibration cycle immediately CONV become active. calibration lasts 3246 clock cycles. Calibration coefficients then retained SRAM (static RAM) during conversion. state BP/UP ignored during calibration should remain stable throughout calibration period minimize noise. When conversions performed unipolar mode bipolar mode, converter uses same calibration factors compute digital output code. only difference that bipolar mode onchip microcontroller offsets computed output word code value 8000H. This means that bipolar measurement range calibrated from full scale positive full scale negative. Instead calibrated from bipolar zero scale point full scale positive. slope factor then extended below bipolar zero accommodate negative inDS125F3
THEORY OPERATION Basic Converter Operation
CS5509 converter three operating states. These stand-by, calibration, conversion. When power first applied, internal power-on reset delay about resets logic device. oscillator must then begin oscillating before device considered functional. After power-on reset applied, device enters wake-up period 1800 clock cycles after clock present. This allows deltasigma modulator other circuitry (which operating with very currents) reach stable bias condition prior entering into either calibration conversion states. During 1800 cycle wake-up period, device accept input command. Execution this command will occur until complete wake-up period elapses. command given, device enters standby state.
CS5509
signals. converter used convert both unipolar bipolar signals changing BP/UP pin. Recalibration required when switching between unipolar bipolar modes. calibration cycle, on-chip microcontroller checks logic state CONV signal. CONV input device will enter standby mode where waits further instruction. CONV signal high calibration cycle, converter will enter conversion state perform conversion input channel. signal returned time after calibration initiated. CONV also returned low, should never taken then taken back high until calibration period ended converter standby state. CONV taken then high again with high while converter calibrating, device will interrupt current calibration cycle start one. taken CONV taken then high during calibration, calibration cycle will continue conversion command disregarded. state BP/UP important during calibrations. "end calibration" signal desired, pulse signal high while leaving CONV signal high continuously. Once calibration completed, conversion will performed. conversion, DRDY will fall indicate first valid conversion after calibration been completed. BP/UP latched input. BP/UP controls output word from digital filter processed. bipolar mode output word computed digital filter offset 8000H (see Understanding Converter Calibration). BP/UP changed after conversion started long stable clock cycles conversion period prior DRDY falling. wishes intermix measurement bipolar unipolar signals various input signals, best switch BP/UP immediately after DRDY falls leave BP/UP stable until DRDY falls again. digital filter CS5509 Finite Impulse Response designed settle full accuracy conversion time. CONV left high, CS5509 will perform continuous conversions. conversion time will 1622 clock cycles. conversion initiated from standby state, there clock cycles uncertainty when conversion actually begins. This because internal logic operates half external clock rate exact phase internal clock 180° phase relative clock. When conversion initiated from standby state, will take clock cycles begin. Actual conversion will 1624 clock cycles before DRDY goes indicate that serial port been updated. Serial Interface Logic section data sheet information reading data from serial port. event conversion command (CONV going positive) issued during conversion state, current conversion will terminated conversion will initiated.
Conversion
conversion state entered calibration cycle, whenever converter idle standby mode. CONV taken high initiate calibration cycle also high), remains high until calibration cycle completed (CAL taken after CONV transitions high), converter will begin conversion upon completion calibration period.
Voltage Reference
CS5509 uses differential voltage reference input. positive input VREF+ negative input VREF-. voltage between VREF+ VREF- range from volt minimum volts maximum. gain slope will track changes
DS125F3
CS5509
reference without recalibration, accommodating ratiometric applications.
Unipolar Input Voltage (VREF LSB) VREF VREF/2 +0.5 Output Codes
FFFF FFFF -FFFE 8000-7FFF 0001 -0000 0000
Analog Input Range
analog input range magnitude voltage between VREF+ VREF- pins. unipolar mode input range will equal magnitude voltage reference. bipolar mode input voltage range will equate plus minus magnitude voltage reference. While voltage reference great volts, common mode voltage value long reference inputs VREF+ VREFstay within supply voltages GND. differential input voltage also have common mode value long maximum signal magnitude stays within supply voltages. converter intended measure frequency inputs. designed yield accurate conversions even with noise exceeding input voltage range long spectral components this noise will filtered digital filter. example, with volt reference unipolar mode, converter will accurately convert input signal 3.0volts with overrange 60Hz noise. 3.0volt signal could have 60Hz component which 0.5volts above maximum input (3.5 volts peak; volts plus volts peak noise) still accurately convert input signal (XIN 32.768 kHz). This assumes that signal plus noise amplitude stays within supply voltages. CS5509 converters output data binary format when converting unipolar signals offset binary format when converting bipolar signals. Table outlines output coding both unipolar bipolar measurement modes.
Bipolar Input Voltage (VREF LSB) VREF -0.5 -VREF
(-VREF LSB) (+0.5 LSB) Note: Table excludes common mode voltage signal reference inputs.
Table Output Coding
offset gain. CS5509 device missing code performance 16-bits. Figure4 illustrates CS5509. converter achieves Common Mode Rejection (CMR) 105dB typical, 60Hz 120dB typical. CS5509 experience some drift temperature changes. CS5509 uses chopper-stabilized techniques minimize drift. Measurement errors offset gain drift eliminated time recalibrating converter.
Analog Input Impedance Considerations
analog input CS5509 modeled illustrated Figure Capacitors each) used dynamically sample each inputs (AIN+ AIN-). Every half cycle switch alternately connects capacitor output buffer then directly pin. Whenever sample capacitor switched from output buffer pin, small packet charge dynamic demand current) required from input source settle voltage sample capacitor final value. voltage output buffer differ from actual input voltage offset voltage buffer. Timing allows half clock cycle voltage sample capacitor settle final value.
Converter Performance
CS5509 converter excellent linearity performance. Calibration minimizes errors
DS125F3
CS5509
Figure CS5509 Differential Nonlinearity Plot
AIN+ AINV Internal Bias Voltage
VREF+ VREF- inputs have nearly same structure AIN+ AIN- inputs. Therefore, discussion analog input impedance applies voltage reference inputs well.
Digital Filter Characteristics
digital filter CS5509 combination comb filter pass filter. comb filter zeros transfer function which optimally placed reject line interference frequencies their multiples) when CS5509 clocked 32.768 kHz. Figures illustrate magnitude phase characteristics filter. Figure illustrates filter attenuation from exactly 100, filter provides over rejection. Table indicates filter attenuation each potential line interference frequencies when converter operating with 32.768 clock. converter yields excellent attenuation these interference frequencies even fundamental line frequency should vary from specified frequency. corner frequency filter when operating from 32.768 clock Figure illustrates that phase characteristics filter precisely linear phase. CS5509 operated clock rate other than 32.768kHz, filter characteristics, including comb filter zeros, will scale with operating clock frequency. Therefore, optimum rejection
Figure Analog Input Model
equation maximum acceptable source resistance derived.
2XIN 15pF -15pF 100mV -15pF
This equation assumes that offset voltage buffer which worst case. value maximum error voltage which acceptable. CEXT combination external stray capacitance. maximum error voltage (Ve) CS5509 (1/4LSB 16-bits), above equation indicates that when operating from 32.768 XIN, source resistances acceptable absence external capacitance (CEXT=0).
DS125F3
CS5509
32.768kHz 330.00kHz
Attenuation (dB)
Phase (Degrees)
-100 -120 -140 32.768
32.768
-135
-180
-160
402.83 805.66 1208.5 1611.3 2014.2 2416.9
Frequency (Hz)
Frequency (Hz)
Figure Filter Magnitude Plot
Flatness Frequency -0.010 -0.041 -0.093 -0.166
-0.259 -0.374 -0.510
Figure Filter Phase Plot
Frequency (Hz)
Notch Depth (dB)
125.6
Frequency (Hz)
126.7 145.7 136.0
118.4 132.9 102.5 108.4
-0.667 -0.846 -1.047 -3.093
-100 -120 -140
32.768
Minimum Attenuation (dB) 55.5 58.4 62.2 68.4 74.9 87.9 94.0 104.4
Attenuation (dB)
Table Filter Notch Attenuation (XIN 32.768 kHz)
Frequency (Hz)
Figure Filter Magnitude Plot
Anti-Alias Considerations Spectral Measurement Applications
Input frequencies greater than half output word rate (CONV aliased converter. prevent this, input signals should limited frequency greater than half output word rate converter (when CONV =1). Frequencies close modulator sample rate (XIN/2) multiples thereof also aliased. signal source includes spectral components above half output word rate (when CONV these components should removed means low-pass filtering prior input
DS125F3
line frequency interference will occur with CS5509 running 32.768kHz.
CS5509
prevent aliasing. Spectral components greater than half output word rate VREF inputs (VREF+ VREF-) also aliased. Filtering reference voltage remove these spectral components from reference voltage desirable.
Serial Interface Logic
digital filter CS5509 takes 1624 clock cycles compute output word once conversion begins. conversion cycle, filter will attempt update serial port. clock cycles prior update DRDY will high. When DRDY goes high just prior port update checks port either empty unselected port empty unselected, digital filter will update port with output word. When data into port DRDY will low.
Crystal Oscillator
CS5509 designed operated using 32.768kHz "tuning fork" type crystal. crystal should connected input. other should attached XOUT. Short lead lengths should used minimize stray capacitance. Over industrial temperature range (-40 on-chip gate oscillator will oscillate with other crystals range 30kHz kHz. chip will operate with external clock frequencies from 30kHz 330kHz over industrial temperature range. 32.768 crystal normally specified time-keeping crystal with tight specifications both initial frequency drift over temperature. maintain excellent frequency stability, these crystals specified only over limited operating temperature ranges (i.e. manufacturers. Applications these crystals with CS5509 does require tight initial tolerance tempco drift. Therefore, lower cost crystal with looser initial tolerance tempco will generally adequate with CS5509. Also check with manufacturer about wide temperature range application their standard crystals. Generally, even those crystals specified limited temperature range will operate over much larger ranges frequency stability over temperature requirement. frequency stability ±3000 over operating temperature range still typically better than line frequency 60Hz) stability over cycle-to-cycle during course day.
Reading Serial Data
SDATA output serial data. When goes after data becomes available (DRDY goes low), SDATA comes Hi-Z with data present. SCLK input serial clock. data SDATA pin, first rising edge SCLK enables shifting mechanism. This allows falling edges SCLK shift subsequent data bits port. Note that data output SCLK signal high, first falling edge SCLK will ignored because shifting mechanism become activated. After first rising edge SCLK, each subsequent falling edge will shift serial data. Once present, falling edge SCLK will cause SDATA output Hi-Z DRDY return high. serial port register will updated with data word upon completion another conversion serial port been emptied, inactive (high). operated asynchronously DRDY signal. DRDY signal need monitored long signal taken least clock cycles plus 200ns prior SCLK being toggled. This ensures that gained control over serial port.
DS125F3
CS5509
Power Supplies Grounding
analog digital supply pins CS5509 brought separate pins minimize noise coupling between analog digital sections chip. digital section chip supply current flows into pin. CMOS device, CS5509 requires that supply voltage always more positive than voltage other device. this requirement met, device latch-up damaged. circumstances voltage must remain more positive than pins; must remain more positive than pin. Figure illustrates System Connection Diagram CS5509. Note that supply pins bypassed with capacitors that digital supply derived from supply. Figure illustrates CS5509 operating from analog supply +3.3V digital supply. When using separate supplies VD+, must established first. should never become more positive than under operating condition. Remember investigate transient power-up conditions, when power supply have faster rise time.
DS125F3
CS5509
Analog Supply Optional Clock Source 32.768
XOUT
SCLK SDATA
Serial Data Interface
CS5509
Analog Signal
AIN+ AINCS CONV Control Logic
Voltage Reference
VREF+ VREFGND BP/UP DRDY
Figure System Connection Diagram Using Single Supply
DS125F3
CS5509
Note: must never more positive than Analog Supply Optional Clock Source 32.768 +3.3V Digital Supply
XOUT
SCLK SDATA
Serial Data Interface
CS5509
Analog Signal AIN+ AINCS CONV Voltage Reference VREF+ VREFGND BP/UP DRDY Control Logic
Figure System Connection Diagram Using Split Supplies
DS125F3
CS5509
DESCRIPTIONS*
CHIP SELECT
CONVERT CALIBRATE
CONV XOUT BP/UP AIN+ AIN-
DRDY SDATA SCLK VREFVREF+
DATA READY
SERIAL DATA OUTPUT SERIAL CLOCK INPUT
CRYSTAL
CRYSTAL BIPOLAR UNIPOLAR DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT
POSITIVE DIGITAL POWER
GROUND POSITIVE ANALOG POWER VOLTAGE REFERENCE INPUT VOLTAGE REFERENCE INPUT
Pinout applies both PDIP SOIC Clock Generator XIN; XOUT Crystal Crystal Out, Pins gate inside chip connected these pins used with crystal provide master clock device. Alternatively, external (CMOS compatible) clock supplied into provide master clock device. Loss clock will device into lower powered state (approximately power reduction). Serial Output Chip Select, This input allows external device access serial port. DRDY Data Ready, Data Ready goes digital filter convolution cycle indicate that output word been placed into serial port. DRDY will return high after data bits shifted serial port master clock cycles before data becomes available inactive (high). SDATA Serial Data Output, SDATA output serial output port. Data from this will output rate determined SCLK. Data output first advances next data falling edges SCLK. SDATA will high impedance state when transmitting data. SCLK Serial Clock Input, clock signal this determines output rate data from SDATA pin. This must allowed float.
DS125F3
CS5509
Control Input Pins Calibrate, When taken high same time that CONV taken high converter will perform self-calibration which includes calibration offset gain scale factors converter. CONV Convert, CONV initiates calibration cycle taken from high while high, initiates conversion taken from high with low. CONV held high (CAL low) converter will continuous conversions. BP/UP Bipolar/Unipolar, BP/UP selects conversion mode converter. When high converter will convert bipolar input signals; when will convert unipolar input signals. Measurement Reference Inputs AIN+, AIN- Differential Analog Inputs, Pins Analog differential inputs delta-sigma modulator. VREF+, VREF- Differential Voltage Reference Inputs, Pins differential voltage reference these pins operates voltage reference converter. voltage between these pins voltage between volts. Power Supply Connections Positive Analog Power, Positive analog supply voltage. Nominally volts. Positive Digital Power, Positive digital supply voltage. Nominally volts +3.3 volts. Ground, Ground.
DS125F3
CS5509
SPECIFICATION DEFINITIONS Linearity Error deviation code from straight line which connects endpoints Converter transfer function. endpoint located below first code transition other endpoint located beyond code transition ones. Units percent full-scale. Differential Nonlinearity deviation code's width from ideal width. Units LSBs. Full Scale Error deviation last code transition from ideal [{(VREF+) (VREF-)} LSB]. Units LSBs. Unipolar Offset deviation first code transition from ideal above voltage AINpin.) when unipolar mode (BP/UP low). Units LSBs. Bipolar Offset deviation mid-scale transition (011.111 100.000) from ideal below voltage AIN- pin.) when bipolar mode (BP/UP high). Units LSBs
DS125F3
CS5509
PACKAGE DIMENSIONS
pins
MILLIMETERS 9.91 10.16 10.41 12.45 12.70 12.95 14.99 15.24 15.50 17.53 17.78 18.03 MILLIMETERS
INCHES 0.390 0.400 0.410
0.490 0.500 0.510 0.590 0.600 0.610 0.690 0.700 0.710
INCHES
SOIC
2.41 0.127 2.29
0.33
2.54 2.67 0.095 0.100 0.105 0.300 0.005 0.012 2.41 2.54 0.090 0.095 0.100
0.46 0.51 0.013 0.018 0.020 0.203 0.280 0.381 0.008 0.011 0.015 table above
10.11 10.41 10.67 0.398 0.410 0.420 7.42 7.49 7.57 0.292 0.295 0.298 1.14 0.41 1.27 1.40 0.040 0.050 0.055 0.89 0.016 0.035
DS125F3
CS5509
ENVIRONMENTAL, MANUFACTURING, HANDLING INFORMATION
Model Peak Relfow Temp Rating* Maximum Floor Life
CS5509-ASZ (lead free)
Days
(Moisture Sensitivity Level) specified IPC/JEDEC J-STD-020.
DS125F3
CS5509
REVISION HISTORY
Revision Date Changes
First "final" release. Added lead-free device ordering info. Added legal notice. Added data. Removed PDIP leaded (Pb) devices from ordering information.
Contacting Cirrus Logic Support
product questions inquiries contact Cirrus Logic Sales Representative. find nearest www.cirrus.com
IMPORTANT NOTICE Cirrus Logic, Inc. subsidiaries ("Cirrus") believe that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). Customers advised obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, indemnification, limitation liability. responsibility assumed Cirrus this information, including this information basis manufacture sale items, infringement patents other rights third parties. This document property Cirrus furnishing this information, Cirrus grants license, express implied under patents, mask work rights, copyrights, trademarks, trade secrets other intellectual property rights. Cirrus owns copyrights associated with information contained herein gives consent copies made information only within your organization with respect Cirrus integrated circuits other products Cirrus. This consent does extend other copying such copying general distribution, advertising promotional purposes, creating work resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS DESIGNED, AUTHORIZED WARRANTED PRODUCTS SURGICALLY IMPLANTED INTO BODY, AUTOMOTIVE SAFETY SECURITY DEVICES, LIFE SUPPORT PRODUCTS OTHER CRITICAL APPLICATIONS. INCLUSION CIRRUS PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK CIRRUS DISCLAIMS MAKES WARRANTY, EXPRESS, STATUTORY IMPLIED, INCLUDING IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE, WITH REGARD CIRRUS PRODUCT THAT USED SUCH MANNER. CUSTOMER CUSTOMER'S CUSTOMER USES PERMITS CIRRUS PRODUCTS CRITICAL APPLICATIONS, CUSTOMER AGREES, SUCH USE, FULLY INDEMNIFY CIRRUS, OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS OTHER AGENTS FROM LIABILITY, INCLUDING ATTORNEYS' FEES COSTS, THAT RESULT FROM ARISE CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, Cirrus Logic logo designs trademarks Cirrus Logic, Inc. other brand product names this document trademarks service marks their respective owners.
DS125F3

CS5509 single-supply, 16-bit, serial-output CMOS converter. CS5509 use

Top Searches for this datasheet

Other recent searches