EBJ42HE8BAFA (512M words bits, Ranks) Density: Organization 512M

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

EBJ42HE8BAFA (512M words bits, Ranks) Density: Organization 512M

Datasheet Thumbnail

Top Searches for this datasheet

Registered DDR3 SDRAM DIMM
EBJ42HE8BAFA (512M words bits, Ranks)
Density: Organization 512M words bits, ranks Mounting pieces bits DDR3 SDRAM sealed FBGA Package: 240-pin socket type dual line memory module (DIMM) height: 30.5mm (max.) Lead pitch: 1.0mm Lead-free (RoHS compliant) Power supply: 1.5V 0.075V Data rate: 1066Mbps/800Mbps (max.) Eight internal banks concurrent operation (components) Interface: SSTL_15 Burst lengths (BL): with Burst Chop (BC) /CAS Latency (CL): /CAS write latency (CWL): Precharge: auto precharge option each burst access Refresh: auto-refresh, self-refresh Refresh cycles Average refresh period 7.8µs +85°C 3.9µs +85°C +95°C Operating case temperature range +95°C
Features
Double-data-rate architecture; data transfers clock cycle high-speed data transfer realized bits prefetch pipelined architecture Bi-directional differential data strobe (DQS /DQS) transmitted/received with data capturing data receiver edge-aligned with data READs; centeraligned with data WRITEs Differential clock inputs /CK) aligns transitions with transitions Commands entered each positive edge; data data mask referenced both edges Data mask (DM) write data Posted /CAS programmable additive latency better command data efficiency On-Die-Termination (ODT) better signal quality Synchronous Dynamic Asynchronous Multi Purpose Register (MPR) temperature read calibration drive Programmable Partial Array Self-Refresh (PASR) /RESET Power-up sequence reset function range: Normal/extended Auto/manual self-refresh Programmable Output driver impedance control piece registering clock driver piece serial EEPROM (256 bytes EEPROM) Presence Detect (PD). Class temperature sensor functionality with EEPROM Note: Warranty void removed DIMM heat spreader.
Document E1412E20 (Ver. 2.0) Date Published December 2008 Japan Printed Japan URL: http://www.elpida.com Elpida Memory, Inc. 2008
EBJ42HE8BAFA
Ordering Information
Data rate Mbps(max.) 1066 Component JEDEC speed bin* (CL-tRCD-tRP) DDR3-1066F (7-7-7) Contact Gold Mounted devices EDJ1108BASE-DG-E EDJ1108BASE-DJ-E EDJ1108BASE-AE-E EDJ1108BASE-DG-E EDJ1108BASE-DJ-E EDJ1108BASE-AE-E EDJ1108BASE-AG-E EDJ1108BASE-8A-E EDJ1108BASE-8C-E
Part number EBJ42HE8BAFA-AE-E
Package 240-pin DIMM (lead-free)
EBJ42HE8BAFA-8C-E
DDR3-800E (6-6-6)
Note: Module /CAS latency component
Data Sheet E1412E20 (Ver. 2.0)
EBJ42HE8BAFA
Configurations
Front side
Back side
name VREFDQ /DQS0 DQS0 /DQS1 DQS1 DQ10 DQ11 DQ16 DQ17 /DQS2 DQS2 DQ18 DQ19 DQ24 DQ25 /DQS3 DQS3 DQ26
name /CK1 VREFCA Par_In A10(AP) /CAS /CS1 ODT1 /CS2 DQ32 DQ33 /DQS4 DQS4 DQ34 DQ35 DQ40 DQ41 /DQS5 DQS5 DQ42
name DM0/TDQS9 /TDQS9 DQ12 DQ13 DM1/TDQS10 /TDQS10 DQ14 DQ15 DQ20 DQ21 DM2/TDQS11 /TDQS11 DQ22 DQ23 DQ28 DQ29 DM3/TDQS12 /TDQS12 DQ30 DQ31
name /CK0 /EVENT /RAS /CS0 ODT0 /CS3 DQ36 DQ37 DM4/TDQS13 /TDQS13 DQ38 DQ39 DQ44 DQ45 DM5/TDQS14 /TDQS14 DQ46 DQ47
Data Sheet E1412E20 (Ver. 2.0)
EBJ42HE8BAFA
name DQ27 /DQS8 DQS8 CKE0 /Err_Out name DQ43 DQ48 DQ49 /DQS6 DQS6 DQ50 DQ51 DQ56 DQ57 /DQS7 DQS7 DQ58 DQ59 name DM8/TDQS17 /TDQS17 /RESET CKE1 name DQ52 DQ53 DM6/TDQS15 /TDQS15 DQ54 DQ55 DQ60 DQ61 DM7/TDQS16 /TDQS16 DQ62 DQ63 VDDSPD
Data Sheet E1412E20 (Ver. 2.0)
EBJ42HE8BAFA
Description
name (AP) (/BC) BA0, BA1, DQ63 /RAS /CAS /CS0 /CS3 CKE0, CKE1 CK0, /CK0, /CK1 DQS0 DQS8, /DQS0 /DQS8 TDQS9 TDQS17, /TDQS9 /TDQS17 SA0, SA1, VDDSPD VREFCA VREFDQ /RESET ODT0, ODT1 Par_In /Err_Out /Event Function Address input address Column address Auto precharge Burst chop Bank select address Data input/output Check (Data input/output) address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input output data strobe Termination data strobe Input mask Clock input serial Data input/output serial Serial address input Power internal circuit Power serial EEPROM Reference voltage Reference voltage Ground Termination Voltage DRAM known state control Parity Address Control Parity error found Address Control Temperature event connection usable
Data Sheet E1412E20 (Ver. 2.0)
EBJ42HE8BAFA
Serial Matrix
Byte Function described Number serial bytes written/SPD device size/CRC coverage revision byte/DRAM device type byte/module type SDRAM density banks SDRAM addressing Module nominal voltage, Module organization Module memory width Fine timebase (FTB) dividend/divisor Medium timebase (MTB) dividend Medium timebase (MTB) divisor SDRAM minimum cycle time (tCK (min.)) Reserved SDRAM /CAS latencies supported, SDRAM /CAS latencies supported, SDRAM minimum /CAS latencies time (tAA (min.)) SDRAM write recovery time (tWR) SDRAM minimum /RAS /CAS delay (tRCD) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value 37.5ns 50.625ns 52.5ns 110ns Comments 176/256/0-116 Revision DDR3 SDRAM Registered bits, banks rows, columns 1.5V bits bits/ECC 1.875ns 2.5ns 13.125ns 15ns 15ns 13.125ns 15ns 7.5ns 10ns 13.125ns 15ns
SDRAM minimum active active delay (tRRD) SDRAM minimum precharge time (tRP)
SDRAM upper nibbles tRAS
SDRAM minimum active precharge time (tRAS), SDRAM minimum active active /autorefresh time (tRC), SDRAM minimum refresh recovery time delay (tRFC),
Data Sheet E1412E20 (Ver. 2.0)
EBJ42HE8BAFA
Byte Function described SDRAM minimum refresh recovery time delay (tRFC), SDRAM minimum internal write read command delay (tWTR) SDRAM minimum internal read precharge command delay (tRTP) Upper nibble tFAW Minimum four activate window delay time (tFAW) SDRAM output drivers supported SDRAM refresh options Module thermal sensor SDRAM device type
Bit7 Bit6
Bit5
Bit4 Bit3 Bit2 Bit1 Bit0 value
Comments 110ns 7.5ns 7.5ns 37.5ns 37.5ns 40ns DLL-off, RZQ/6, PASR/2X refresh rate +85°C +95°C Incorporated Standard height 31mm
Reserved Module nominal height Module maximum thickness Reference card used DIMM module attributes Heat spreader solution Register vender (LSB) (Inphi) (TI) Register vender (MSB) (Inphi) (TI) Register revision (Inphi) (TI) Register type Register control word function (RC0, Register control word function (RC2, Register control word function (RC4, Register control word function (RC6, Register control word function (RC8,
card 2row/1register Incorporated Naming bank Naming bank Actual
Rev.4 Rev.3.1 SSTE32882 Default Default Default Default Default Default Default Default
Register control word function (RC10, Register control word function (RC12, Register control word function (RC14, Module specific section
Data Sheet E1412E20 (Ver. 2.0)
EBJ42HE8BAFA
Byte Function described Module manufacturer's JEDEC code, Module manufacturer's JEDEC code, Module manufacturing location Module manufacturing date Module manufacturing date Module module serial number Cyclical redundancy code (CRC) (Inphi) (TI) (Inphi) (TI) Cyclical redundancy code (CRC) (Inphi) (TI) (Inphi) (TI) Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number
Bit7 Bit6
Bit5
Bit4 Bit3 Bit2 Bit1 Bit0 value
Comments Elpida Memory Elpida Memory
Year code (BCD) Week code (BCD)
Data Sheet E1412E20 (Ver. 2.0)
EBJ42HE8BAFA
Byte Function described Module part number Module revision code Module revision code SDRAM manufacturer's JEDEC code, SDRAM manufacturer's JEDEC code, Manufacturer's specific data Open customer
Bit7 Bit6
Bit5
Bit4 Bit3 Bit2 Bit1 Bit0 value
Comments (Space) Initial (Space) Elpida Memory Elpida Memory
Data Sheet E1412E20 (Ver. 2.0)
EBJ42HE8BAFA
Block Diagram
R[Address, BA]_A /RCS0 Rcommand_A PCK0_A /PCK0_A
PCK1_A /PCK1_A RCKE0_A RODT1_A
RCKE0_A RODT0_A
PCK0_A /PCK0_A RCKE1_A
Command
Command Address
Address
DQS8 /DQS8 DM8/TDQS17 /TDQS17
/DQS
/DQS
/DQS
Address
/DQS
TDQS
TDQS
TDQS
TDQS
/TDQS
Command
Command
Command
Address
Address
Address
Command
DQS3 /DQS3 DM3/TDQS12 /TDQS12
/DQS
/DQS
/DQS
/DQS
TDQS
TDQS
TDQS
TDQS
Command
Command
Address
Address
Command
Command
DQS2 /DQS2 DM2/TDQS11 /TDQS11
/DQS
/DQS
/DQS
/DQS
TDQS
TDQS
TDQS
TDQS
Command
Command
Command
Address
Address
Address
Command
DQS1 /DQS1 DM1/TDQS10 /TDQS10
/DQS
/DQS
/DQS
/DQS
TDQS
TDQS
TDQS
TDQS
/TDQS DQ15
/TDQS
/TDQS
/TDQS
Address
Address
Address
Command
Command
Command
Command
DQS0 /DQS0 DM0/TDQS9 /TDQS9
/DQS
/DQS
/DQS
/DQS
TDQS
TDQS
TDQS
TDQS
/TDQS
TDQS
/TDQS
/TDQS
Block Diagram
Data Sheet E1412E20 (Ver. 2.0)
Address
Address
/TDQS DQ16 DQ23
/TDQS
/TDQS
/TDQS
Address
Address
/TDQS DQ24 DQ31
/TDQS
/TDQS
/TDQS
Address
/TDQS
/TDQS
/TDQS
Command Address
Command
PCK1_A /PCK1_A RCKE1_A
/RCS1
/RCS2
/RCS3
EBJ42HE8BAFA
R[Address, BA]_B /RCS0 Rcommand_B PCK1_B /PCK1_B
PCK1_B /PCK1_B RCKE0_B RODT1_B
RCKE0_B RODT0_B
PCK0_B /PCK0_B RCKE0_B
Command
Command Address
Address
DQS4 /DQS4 DM4/TDQS13 /TDQS13 DQ32 DQ39
/DQS
/DQS
/DQS
Address
/DQS
TDQS
TDQS
TDQS
TDQS
Command
Command
Command
Address
Address
Address
Command
DQS5 /DQS5 DM5/TDQS14 /TDQS14 DQ40 DQ47
/DQS
/DQS
/DQS
/DQS
TDQS
TDQS
TDQS
TDQS
/TDQS
Command
Command
Command
Address
Address
Command
DQS6 /DQS6 DM6/TDQS15 /TDQS15 DQ48 DQ55
/DQS
/DQS
/DQS
/DQS
TDQS
TDQS
TDQS
TDQS
Command
Command
Command
Address
Address
Address
Command
DQS7 /DQS7 DM7/TDQS16 /TDQS16 DQ56 DQ63
/DQS
/DQS
/DQS
/DQS
TDQS
TDQS
TDQS
TDQS
/TDQS
/TDQS
/TDQS
/TDQS
Block Diagram
Data Sheet E1412E20 (Ver. 2.0)
Address
/TDQS
/TDQS
/TDQS
/TDQS
Address
Address
/TDQS
/TDQS
/TDQS
Address
/TDQS
/TDQS
/TDQS
/TDQS
Command Address
Command
PCK1_B /PCK1_B RCKE1_B
/RCS1
/RCS2
/RCS3
EBJ42HE8BAFA
/CS0 /CS1 /CS2 /CS3 Address Command CKE0 CKE1 ODT0 ODT1 /RCS0 /CS: SDRAMs
/RCS1 /CS: SDRAMs /RCS2 /CS: SDRAMs /RCS3 /CS: SDRAMs RBA_A BA2: SDRAMs D12, D21, D30, RBA_B BA2: SDRAMs D16, D25, RAddress_A A13: SDRAMs D12, D21, D30, RAddress_B A13: SDRAMs D16, D25, Rcommand_A /RAS, /CAS, /WE: SDRAMs D12, D21, D30, Rcommand_B /RAS, /CAS, /WE: SDRAMs D16, D25,
RCKE0_A CKE: SDRAMs D21, RCKE0_B CKE: SDRAMs RCKE1_A CKE: SDRAMs D12, D17, D30, RCKE1_B CKE: SDRAMs D16, RODT0_A ODT: SDRAMs RODT0_B-> ODT: SDRAMs RODT1_A ODT: SDRAMs D21, RODT1_B ODT: SDRAMs PCK0_A SDRAMs D12, PCK0_B SDRAMs PCK1_A SDRAMs D21, D30, PCK1_B SDRAMs D25, /PCK0_A SDRAMs D12, /PCK0_B SDRAMs
/CK0
Par_In /RESET
/RESET
/PCK1_A SDRAMs D21, D30, /PCK1_B SDRAMs D25, /Err_Out
Note: wiring changed within byte.
/RESET: SDRAMs
/CK1 VDDSPD VREFCA VREFDQ
Terminated near card edge SDRAMs D35) SDRAMs D35) SDRAMs D35) SDRAMs D35),
D35: bits DDR3 SDRAM Address, A15, Command: /RAS, /CAS, bytes EEPROM Rs1: Rs2: Rs3: Rs4: Rs5: Register: SSTE32882 Serial
/EVENT
/EVENT
Address, command control line
Block Diagram
Data Sheet E1412E20 (Ver. 2.0)
Register
EBJ42HE8BAFA
Electrical voltages referenced (GND). Absolute Maximum Ratings
Parameter Power supply voltage Input voltage Output voltage Reference voltage Reference voltage Storage temperature Power dissipation Short circuit output current Symbol VOUT VREFCA VREFDQ Tstg IOUT Value -0.4 +1.975 -0.4 +1.975 -0.4 +1.975 -0.4 -0.4 VDDQ +100 Unit Notes
Notes: Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. Storage temperature case surface temperature center/top side DRAM. VDDQ must within 300mV each other times; VREF must greater than VDDQ, When VDDQ less than 500mV; VREF equal less than 300mV. DDR3 SDRAM component specification. Caution Exposing device stress above those listed Absolute Maximum Ratings could cause permanent damage. device meant operated under conditions outside limits described operational section this specification Exposure Absolute Maximum Rating conditions extended periods affect device reliability.
Operating Temperature Condition
Parameter Operating case temperature Symbol Rating Unit Notes
Notes: Operating temperature case surface temperature center/top side DRAM. Normal Temperature Range specifies temperatures where DRAM specifications will supported. During operation, DRAM case temperature must maintained between +85°C under operating conditions. Some applications require operation DRAM Extended Temperature Range between +85°C +95°C case temperature. Full specifications guaranteed this range, following additional conditions apply: Refresh commands must doubled frequency, therefore reducing refresh interval tREFI 3.9µs. (This double refresh requirement apply some devices.) Self-refresh operation required Extended Temperature Range, then mandatory either Manual Self-Refresh mode with Extended Temperature Range capability (MR2 [A6, enable optional Auto Self-Refresh mode (MR2 [A6, 0]).
Data Sheet E1412E20 (Ver. 2.0)
EBJ42HE8BAFA
Recommended Operating Conditions +85°C)
Parameter Supply voltage Symbol VDD, VDDQ VDDSPD Input reference voltage Input reference voltage Termination voltage VREFCA (DC) VREFDQ (DC) min. 1.425 0.49 VDDQ 0.49 VDDQ VDDQ/2 typ. max. 1.575 Unit Notes
0.50 VDDQ 0.51 VDDQ 0.50 VDDQ 0.51 VDDQ VDDQ/2
Notes:
DDR3 SDRAM component specification. Under conditions VDDQ must less than equal VDD. VDDQ tracks with VDD. parameters measured with VDDQ tied together. peak noise VREF allow VREF deviate from VREF(DC) more than (for reference: approx mV). reference: approx. VDD/2
Data Sheet E1412E20 (Ver. 2.0)
EBJ42HE8BAFA
Characteristics +85°C, 1.5V 0.075V,
Parameter Operating current (ACT-PRE) Operating current (ACT-READ-PRE) Precharge power-down standby current IDD2PS Precharge quiet standby current Precharge standby current Active power-down current (Always fast exit) Active standby current Operating current (Burst read operating) Operating current (Burst write operating) Burst refresh current Self-refresh current normal temperature range bank interleave read current IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD7R 1066 Symbol IDD0 IDD1 IDD2PF Data rate (Mbps) 1066 1066 1066 1066 1066 1066 1066 1066 1066 1066 1066 max. 2260 2040 2470 2260 1520 1400 1320 1230 2020 1820 2020 1820 1470 1360 2050 1820 2970 2320 3140 2510 3910 3740 1300 3820 3490 Unit Fast Exit Slow Exit Notes
Data Sheet E1412E20 (Ver. 2.0)
EBJ42HE8BAFA
Timing Test Conditions purposes testing, following parameters utilized.
DDR3-1066 Parameter (IDD) min.(IDD) tRCD min. (IDD) min. (IDD) tRAS min.(IDD) min. (IDD) tFAW (IDD) tRRD (IDD) tRFC (IDD) 7-7-7 1.875 13.13 50.63 37.5 13.13 37.5 DDR3-800 6-6-6 52.5 37.5 Unit
Characteristics +85°C, VDD, VDDQ 1.5V 0.075V) (DDR3 SDRAM Component Specification)
Parameter Input leakage current Output leakage current Symbol Value Unit Notes VOUT
Data Sheet E1412E20 (Ver. 2.0)
EBJ42HE8BAFA
Functions
(input pin) differential clock inputs. address control input signals sampled crossing positive edge negative edge /CK. Output (read) data referenced crossings (both directions crossing). (input pin) commands masked when registered high. provides external rank selection systems with multiple ranks. considered part command code. /RAS, /CAS, (input pins) /RAS, /CAS (along with /CS) define command being entered. (input pins) Provided address active commands column address read/write commands select location memory array respective bank. (A10(AP) A12(/BC) have additional functions, below) address inputs also provide op-code during mode register commands. [Address Pins Table]
Address A13) address (RA) AX13 Column address (CA) Notes
A10(AP) (input pin) sampled during read/write commands determine whether auto-precharge should performed accessed bank after read/write operation. (high: auto-precharge; low: auto-precharge) sampled during precharge command determine whether precharge applies bank (A10 low) banks (A10 high). only bank precharged, bank selected bank addresses (BA). (/BC) (input pin) sampled during read write commands determine burst chop (on-the-fly) will performed. (A12 high: burst chop, low: burst chopped.) (input pins) BA0, define which bank active, read, write precharge command being applied. also determine mode register accessed during cycle. [Bank Select Signal Table]
Bank Bank Bank Bank Bank Bank Bank Bank
Remark: VIH. VIL.
Data Sheet E1412E20 (Ver. 2.0)
EBJ42HE8BAFA
(input pin) high activates, deactivates, internal clock signals device input buffers output drivers. Taking provides precharge power-down self-refresh operation (all banks idle), active power-down (row active bank). asynchronous self-refresh exit. After VREF become stable during power-on initialization sequence, must maintained proper operation receiver. proper self-refresh entry exit, VREF must maintained this input. must maintained high throughout read write accesses. Input buffers, excluding /CK, disabled during power-down. Input buffers, excluding CKE, disabled during self-refresh. (input output pins) Bi-directional data bus. /DQS (input output pin) Output with read data, input with write data. Edge-aligned with read data, centered write data. data strobe paired with differential signals /DQS provide differential pair signaling system during READs WRITEs. (input pins) (registered high) enables termination resistance internal DDR3 SDRAM. When enabled, only applied each DQS, /DQS, will ignored mode register (MR1) programmed disable ODT. (input pins) input mask signal write data. Input data masked when sampled high coincident with that input data during write access. sampled both edges DQS. configuration, function TDQS, /TDQS enabled mode register setting MR1. TDQS, /TDQS (output pins) TDQS /TDQS applicable configuration only. When enabled mode register MR1, DRAM will enable same termination resistance function TDQS, /TDQS that applied DQS, /DQS. When disabled mode register MR1, DM/TDQS will provide data mask function /TDQS used. configuration must disabled TDQS function mode register MR1. (power supply pins) 1.5V applied. (VDD internal circuit.) VDDSPD (power supply pin) 3.3V applied (For serial EEPROM). (power supply pin) Ground connected. (power supply pin) Termination supply. VREFDQ (power supply) Reference voltage VREFCA (power supply) Reference voltage (input pin) Clock input serial
Data Sheet E1412E20 (Ver. 2.0)
EBJ42HE8BAFA
(input output pins) Data input/output serial (input pin) Serial address input. /RESET (input pin) /RESET negative active signal (active low) referred GND. Par_In (input pin) Parity Address Control bus. /Err_Out (output pin) Parity error found Address Control bus. /Event (output pin) Temperature alert output.
Detailed Operation Part, Electrical Characteristics Timing Waveforms
Refer EDJ1104BASE, EDJ1108BASE, EDJ1116BASE datasheet (E1128E). DIMM /CAS latency component registered type.
Data Sheet E1412E20 (Ver. 2.0)
EBJ42HE8BAFA
Physical Outline
Unit:
Front side
8.50
(DATUM -A-)
(Front)
47.00
133.35
71.00
1.27 0.10
Back side
9.50
17.30
4.00
DIMM heat spreader
DIMM heat spreader
(Back)
Detail
Detail
Detail
(DATUM -A-)
2.50 0.20
1.00
0.20 0.15
(R0.65)
2.50
R0.75
0.80 0.05
3.80
5.00
1.50 0.10
ECA-TS2-0245-02
Data Sheet E1412E20 (Ver. 2.0)
3.00
2.10 0.15
30.50
EBJ42HE8BAFA
CAUTION HANDLING MEMORY MODULES
When handling inserting memory modules, sure touch components modules, such memory ICs, chip capacitors chip resistors. necessary avoid undue mechanical stress these components prevent damaging them. particular, push module cover drop modules order protect from mechanical defects, which would electrical defects. When re-packing memory modules, sure modules touching each other. Modules contact with other modules cause excessive mechanical stress, which damage modules.
MDE0202
NOTES CMOS DEVICES
PRECAUTION AGAINST DEVICES
Exposing devices strong electric field cause destruction gate oxide ultimately degrade devices operation. Steps must taken stop generation static electricity much possible, quickly dissipate when once occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS DEVICES
connection CMOS devices input pins cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. unused pins must handled accordance with related specifications.
STATUS BEFORE INITIALIZATION DEVICES
Power-on does necessarily define initial status devices. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee output levels, settings contents registers. devices initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
CME0107
Data Sheet E1412E20 (Ver. 2.0)
EBJ42HE8BAFA
information this document subject change without notice. Before using this document, confirm that this latest version.
part this document copied reproduced form means without prior written consent Elpida Memory, Inc. Elpida Memory, Inc. does assume liability infringement intellectual property rights (including limited patents, copyrights, circuit layout licenses) Elpida Memory, Inc. third parties arising from products information listed this document. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights Elpida Memory, Inc. others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. Elpida Memory, Inc. assumes responsibility losses incurred customers third parties arising from these circuits, software information. [Product applications] aware that this product typical electronic equipment general-purpose applications. Elpida Memory, Inc. makes every attempt ensure that products high quality reliability. However, users instructed contact Elpida Memory's sales office before using product aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment life support, other such application which especially high quality reliability demanded where failure malfunction directly threaten human life cause risk bodily injury. [Product usage] Design your application that product used within ranges conditions guaranteed Elpida Memory, Inc., including maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions other related characteristics. Elpida Memory, Inc. bears responsibility failure damage when product used beyond guaranteed ranges conditions. Even within guaranteed ranges conditions, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Elpida Memory, Inc. products does cause bodily injury, fire other consequential damage operation Elpida Memory, Inc. product. [Usage environment] Usage environments with special characteristics listed below considered design. Accordingly, company assumes responsibility loss customer third party when used environments with special characteristics listed below. Example: Usage liquids, including water, oils, chemicals organic solvents. Usage exposure direct sunlight outdoors, dusty places. Usage involving exposure significant amounts corrosive gas, including air, Usage environments with static electricity, strong electromagnetic waves radiation. Usage places where forms. Usage environments with mechanical vibration, impact, stress. Usage near heating elements, igniters, flammable items. export products technology described this document that controlled Foreign Exchange Foreign Trade Japan, must follow necessary procedures accordance with relevant laws regulations Japan. Also, export products/technology controlled U.S. export control regulations, another country's export control laws regulations, must follow necessary procedures accordance with such laws regulations. these products/technology sold, leased, transferred third party, third party granted license these products, that third party must made aware that they responsible compliance with relevant laws regulations.
M01E0706
Data Sheet E1412E20 (Ver. 2.0)

EBJ42HE8BAFA (512M words bits, Ranks) Density: Organization 512M

Top Searches for this datasheet

Other recent searches