SPIDER TLE7235G Channel High-Side Low-Side Relay Switch with Limp

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SPIDER TLE7235G Channel High-Side Low-Side Relay Switch with Limp

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Data Sheet, Rev. 1.0, October 2008
SPIDER TLE7235G
Channel High-Side Low-Side Relay Switch with Limp Home Mode
Automotive Power
TLE7235G
Table Contents
Table Contents
Table Contents Overview Block Diagram Terms Configuration Assignment Definitions Functions Electrical Characteristics Absolute Maximum Ratings Functional Range Thermal Resistance Power Supply Operation Modes Limp Home Mode Reset Electrical Characteristics Power Stages Input Circuit Channels Inductive Output Clamp Timing Diagrams Electrical Characteristics Command Description Protection Functions Over Load Protection Over Temperature Protection protection Reverse Polarity Protection Loss Electrical Characteristics
Diagnostic Features Electrical Characteristics Command Description Serial Peripheral Interface (SPI) Signal Description Daisy Chain Capability Protocol Register Overview Timing Diagrams Electrical Characteristics
Package Outlines Application Information Revision History
Data Sheet
Rev. 1.0, 2008-10-30
Driver Enhanced Relay Control
TLE7235G
Features
Overview
diagnostics control, providing daisy chain capability Very wide range digital supply voltage configurable input pins offer complete flexibility operation Stable behavior under voltage Green Product (RoHS compliant) Qualified PG-DSO-20-45
Description TLE7235G eight channel high-side low-side power switch PG-DSO-20-45 package providing embedded protective functions. especially designed standard relays LEDs automotive applications. output stages incorporate low-side, four high-side auto configuring high-side low-side switches. serial peripheral interface (SPI) utilized control diagnosis device load. direct control, there input pins available. TLE7235G provides micro controller fail-safe function which activated high signal limp home input pin. There power supply integrated device ensure this functionality even without digital supply voltage. power transistors built N-channel power MOSFETs. device monolithically integrated Smart Power Technology.
Type TLE7235G Data Sheet
Package PG-DSO-20-45
Marking TLE7235G Rev. 1.0, 2008-10-30
TLE7235G
Overview Table Product Summary
Operating range power supply voltage Digital supply voltage Typical On-State resistance high-side: channels (Relay) high-side: channels (Generic, LED) auto configuring: channels (Relay, Supplies) low-side: channels (Relay) Nominal load current (all channels active) Relay LED, Generic Over load switch threshold Output leakage current channel Drain source clamping voltage Source ground clamping voltage clock frequency Protective Functions Over load short circuit protection Thermal shutdown Electrostatic discharge protection (ESD)
RDS(ON)
0.85 0.85 0.85
IL(nom, min)
IDS(OVL, min) IDS(OFF, max) VDS(CL, min) Vbb(CL, max) fSCLK(max)
Diagnostic Functions Latched diagnostic information Open load detection OFF-state Over load detection ON-state Over temperature
Limp Home Fail-Safe Functions Limp home activation Limp home configuration input pins
Applications Especially designed driving relays LEDs automotive applications types resistive inductive loads Suitable switch power supply lines auto configuring channels
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Overview Detailed Description TLE7235G eight channel high-side low-side relay switch providing embedded protective functions. output stages incorporate low-side switches (0.85 channel), four high-side switches (two channels with 0.85 channels with auto-configuring high-side low-side switches (0.85 channel). auto-configuring switches utilized high-side low-side configuration just connecting load accordingly. They also suitable switch supply line high-side configuration. Protective diagnostic functions adjust automatically chosen configuration. serial peripheral interface (SPI) utilized control diagnosis device loads. interface provides daisy chain capability order assemble multiple devices chain using same number micro-controller pins. Furthermore, TLE7235G equipped with input pins that individually routed output control each channel thus offering complete flexibility design PCB-layout. input multiplexer controlled SPI. limp home mode (fail-safe mode), input pins directly routed configurable output channels limp home mode operates independently digital power supply activated LHI. device provides full diagnosis load open load, over load short circuit detection. diagnosis flags indicate latched fault conditions that have occurred. Each output stage protected against short circuit. case over load, affected channel switches off. There temperature sensors available each channel protect device against over temperature. device protects itself with build reverse polarity protection which prohibits intrinsic current flow through logic during reverse polarity. However output stages still incorporate reverse diode where current flow through during reverse polarity. power transistors built N-channel power MOSFETs. inputs ground referenced CMOS compatible. device monolithically integrated Smart Power Technology.
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Block Diagram
Block Diagram
power supply limp home mode activation
temperature sensor high -side gate control short circuit detection control, diagnostic protective functions open load detection OUT0 OUT1 OUT2 OUT3
input
input register
SCLK stand-by control
auto configuring gate control OUT6 OUT7 low-side gate control
diagnosis register
reverse polarity protection
Overview_5.emf
Figure
Block Diagram
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Block Diagram
Terms
Figure shows terms used this data sheet.
Vbat IOUT_S0 OUT0 IOUT_S1 ILHI VLHI VIN1 VSCLK IIN1 IIN2 ISCLK IGND
Terms_5.emf
VDS0 VDS1 VDS3
OUT1 SCLK OUT2 OUT3
IOUT_S2 IOUT_S3
TLE7235G
OUT6
IOUT_D4 IOUT_S4 OUT_D5 IOUT_S5 OUT_D6 OUT_D7 VDS4 VDS5 VDS6
OUT7
Figure
Terms
tables electrical characteristics valid: Channel related symbols without channel number valid each channel separately (e.g. specification valid VDS0 VDS7). order make description output currents easier, load current IOut equivalent drain current IOUT_D low-side configuration source current IOUT_S high-side configuration. register bits marked follows: ADDR.PARAMETER (e.g. ICR01.INX1). register description, values bold letters (e.g. default values.
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Configuration
Configuration
Assignment
(top view
OUT1 OUT3
OUT0 OUT2 SCLK OUT6
OUT7
P-DSO20-45.emf
Figure
Configuration PG-DSO20-45
Inputs
Definitions Functions
Symbol OUT0 OUT1 OUT2 OUT3 OUT6 OUT7 Function Digital power supply Power supply Digital, analog power ground Source high side power transistor channel Source high side power transistor channel Source high side power transistor channel Source high side power transistor channel Drain auto configuring power transistor Source auto configuring power transistor Drain auto configuring power transistor Source auto configuring power transistor Drain side power transistor channel Drain side power transistor channel Limp home activation input (pull down)
Power Supply
Power Stages
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Configuration SCLK Chip select (pull Serial clock Serial data Serial data Symbol Function Input multiplexer input (pull down) Input multiplexer input (pull down)
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Electrical Characteristics
Electrical Characteristics
Absolute Maximum Ratings
Stresses above ones listed here affect device reliability cause permanent damage device. values below considering combinations different maximum conditions time
+150 voltages with respect ground, positive current flowing into (unless otherwise specified)
Absolute Maximum Ratings1) Pos. Parameter Symbol Limit Values min. Power Supply 4.1.1 4.1.2 4.1.3 Power supply voltage Digital supply voltage Power supply voltage full short circuit protection (single pulse) Load current channel channel 4.1.5 4.1.6 4.1.7 4.1.8 Voltage power transistor Power transistor's source voltage max. -16V max. minutes Unit Test Conditions
Vbat(SC)
-0.3
Power Stages 4.1.4
-0.5 -0.25 0.25
VOut_S Power transistor's drain voltage VOut_D Max. energy dissipation channel single
pulse 4.1.9 Maximum energy dissipation channel repetitive pulses cycles cycles 4.1.10 Max. energy dissipation channel single pulse
Tj(0) ID(0) 0.35 Tj(0) ID(0)= 0.250
Tj(0) ID(0) 0.250 Tj(0) ID(0) 0.220
Tj(0) ID(0) 0.250 Tj(0) ID(0)= 0.250
subject production test
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Electrical Characteristics
+150 voltages with respect ground, positive current flowing into (unless otherwise specified)
Absolute Maximum Ratings1) Pos. Parameter Symbol Limit Values min. 4.1.11 Maximum energy dissipation channel repetitive pulses cycles cycles Logic Pins 4.1.12 Voltage input pins 4.1.13 Voltage 4.1.14 Voltage chip select 4.1.15 Voltage serial clock 4.1.16 Voltage serial input 4.1.17 Voltage serial output Temperatures 4.1.18 Junction Temperature 4.1.19 Storage Temperature Susceptibility 4.1.20 susceptibility pins max.
Unit
Test Conditions
Tj(0) ID(0) 0.180 Tj(0) ID(0) 0.180
VLHI VSCLK Tstg VESD
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3
HBM4)
subject production test Pulse shape represents inductive switch off: IL(t) IL(0) tpulse); tpulse susceptibility, according EIA/JESD 22-A114
Pos. 4.2.1 4.2.2 4.2.3
Functional Range
Parameter Supply Voltage Range Nominal Operation upper Supply Voltage Range Extended Operation lower Supply Voltage Range Extended Operation Junction Temperature Symbol Min. Limit Values Max. Parameter Deviations possible Parameter Deviations possible Unit Conditions
Vbb(nom)
Vbb(ext),up Vbb(ext),low
4.2.4
Note: Within functional range operates described circuit description. electrical characteristics specified within conditions given related electrical characteristics table.
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Electrical Characteristics
Thermal Resistance
Note: This thermal data generated accordance with JEDEC JESD51 standards. more information, www.jedec.org.
Thermal Resistance1) Pos. 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 Parameter Junction Case, bottom Junction Case, Junction (5,6,15 Junction Ambient (1s0p, min. footprint) Junction Ambient (1s0p+300mm2Cu) Junction Ambient (1s0p+600mm2Cu) Junction Ambient (2s2p) Symbol Min. Limit Values Typ. Max.
Unit
Conditions
RthJC,back RthJC,top RthJPin RthJA,min RthJA,300 RthJA,600 RthJA,2s2p
subject production test Specified RthJSP value simulated natural convection cold plate setup (all pins fixed ambient temperature). dissipating power (0.125 each). Specified RthJA value according Jedec JESD51-2,-3 natural convection 1s0p board; product (Chip+Package) simulated 76.2 114.3 board with minimal footprint copper area thickness. dissipating power (0.125 each). Specified RthJA value according Jedec JESD51-2,-3 natural convection 1s0p board; product (Chip+Package) simulated 76.2 114.3 board with additional heatspreading copper area 300mm2 thickness. dissipating power (0.125 each). Specified RthJA value according Jedec JESD51-2,-3 natural convection 1s0p board; product (Chip+Package) simulated 76.2 114.3 board with additional heatspreading copper area 600mm2 thickness. dissipating power (0.125 each). Specified RthJA value according Jedec JESD51-2,-7 natural convection 2s2p board; product (Chip+Package) simulated 76.2 114.3 board with inner copper layers Cu). dissipating power (0.125 each).
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Power Supply
Power Supply
TLE7235G supplied supply voltages VDD. supply line connected battery feed used power switches integrated power supply register banks. There under voltage reset function implemented power supply. After start-up power supply, registers reset their default values device sleep mode (standby). command CMD.WAKE switching device operation mode (ON), while command CMD.STB send device sleep mode (standby) again. supply line used shift register related circuitry driving line. result, daisy chain function available soon provided specified range independent Vbb. capacitor between pins recommended (especially case EMI).
Operation Modes
There limp home functionality implemented TLE7235G, which activated LHI. Please refer Section details. device provides sleep mode (stand minimize current consumption, which also resets register banks. entered left dedicated commands sleep mode current minimized only when limp home inactive. After limp home, device enters sleep mode automatically. following table shows operation modes depending Vbb, limp home input signal LHI.
Operation Modes Switches operating Limp Home daisy-chain Register Banks Diagnostic functions reset reset reset reset reset
Limp Home Mode
TLE7235G offers capability driving dedicated channels during fail-safe operation system. This limp home mode activated high signal LHI. limp home mode, registers reset input pins directly routed auto configuring channels (channel result, limp home operation chosen high-side low-side driven loads. integrated power supply, limp home operation independent digital power supply VDD. case stand-by, high signal will wake device. After limp home operation, device enters sleep mode case.
Reset
There several reset trigger implemented device. reset switches channels sets registers default values. After kind reset, transmission error flag (TER) set. Under Voltage Reset: During this device condition read always delivers Standard Diagnostic Frame with flag. This under voltage reset released when supply voltages levels above under voltage threshold. Data Sheet Rev. 1.0, 2008-10-30
TLE7235G
Power Supply Reset Command: There reset command available reset register bits register bank diagnosis registers. soon CMD.RST reset triggered. Limp Home Mode: limp home mode, write-registers reset. interface operating normally, limp home well diagnosis flags read, command accepted until device leaves Limp home operation.
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Power Supply
Electrical Characteristics
Unless otherwise specified: 5.5V, VBAT 16V, +150 Pos. Parameter Power Supply 5.4.1 Supply voltage full operation 5.4.2 Under voltage reset threshold voltage 5.4.3 Operating current Symbol Limit Values min. typ. max. Unit Test Conditions
Vbb(UV)
diagnosis 5.4.4 Sleep mode current with disconnected loads (stand
IS(Sleep)
VLHI
AWK= °C1)
Digital Power Supply 5.4.5 Logic supply voltage 5.4.6 Under voltage reset threshold voltage 5.4.7 Logic supply current
VDD(PO)
fSCLK
AWK=
5.4.8 Logic supply sleep mode current
IDD(Sleep)
°C1)
Timings
twu(Sleep) 5.4.10 under voltage reset delay time tbb(UVR) 5.4.11 under voltage reset delay time tDD(UVR)
5.4.9 Sleep mode wake-up time
subject production test, specified design.
Note: Characteristics show deviation parameter given supply voltage junction temperature. Typical values show typical parameters expected 13.5
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Power Stages
Power Stages
TLE7235G eight channel high-side low-side relay switch. power stages built N-channel vertical power MOSFET transistors. gates high-side switches controlled charge pumps.
Input Circuit
There input pins available TLE7235G, which configured used control output stages. INXn parameter input configuration register provide following possibilities: channel switched channel switched according signal level input channel switched according signal level input channel switched
Figure shows input circuit TLE7235G.
IIN1
Channel Channel Channel Channel Channel Channel Channel Channel
IIN2 INX0
InputLogic.emf
Figure
Input Multiplexer
current sink ground ensures that channels switch case open input pin. zener diode protects input circuit against pulses.
Channels
TLE7235G provides auto-configuring high-side low-side switches (channels They adjust diagnostic protective functions according their potentials drain source automatically. high-side configuration, load connected between ground source power transistors S5). drain power transistors connected potential between GND-pin potential VBB-pin potential. When drain connected VBB, channel behave like other high side channels. drain also connected power supply source will utilized switched supply line. low-side configuration, source power transistors connected GND. configuration chosen each these channels individually, feasible connect channel low-side other high-side configuration.
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Power Stages
Inductive Output Clamp
When switching inductive loads with low-side switches, potential rises VDS(CL) potential, because inductance intends continue driving current. high-side channels, potential drops below ground potential VS(CL). voltage clamping necessary prevent destruction device, Figure details. Nevertheless, maximum allowed load inductance limited max. clamping energy electrical characteristics "EAR" Page
high side channel
side channel VDS(CL)
DS(CL)
S(CL)
OutputClamp.emf
Figure
Output Clamp Implementation
Maximum Load Inductance During demagnetization inductive loads, energy dissipated TLE7235G. This energy calculated with following equations:
D(CL) D(CL) D(CL) S(CL) S(CL) S(CL)
Low-side
High-side
These equations simplify under assumption
D(CL)
Low-side
S(CL)
High-side
maximum energy, which converted into heat, limited thermal design component.
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Power Stages
Timing Diagrams
power transistors switched with dedicated slope bits serial peripheral interface (SPI). switching times tOFF designed equally.
tOFF
SwitchOn .emf
Figure
Switching Resistive Load
input mode, high signal input equivalent command signal command respectively. Please refer Section details protocol.
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Power Stages
Electrical Characteristics
Unless otherwise specified: 5.5V, VBAT 16V, +150 typical values: VBAT 13.5 Pos. Parameter Output Characteristics 6.5.1 On-State resistance channel Symbol Limit Values min. typ. max. 0.85 channel 6.5.2 Nominal load current Unit Test Conditions
RDS(ON)
IOut(nom)
channels Tj,max based Rthja
channel channel 6.5.3 Output leakage current sleep mode
IOut(Sleep)
13.5 °C1)
6.5.4 Output clamping voltage Input Characteristics 6.5.5 level 6.5.6 level 6.5.7 Input voltage hysteresis 6.5.8 L-input pull-down current through 6.5.9 H-input pull-down current through Timings 6.5.10 Turn-on time Vbat channel 1,4,5 channel channel 6.5.11 Turn-off time channel channel (HS) channel (LS)
subject production test, specified design.
VOUT_S(CL)
VOUT_DS(CL)
VIN(L) VIN(H) IIN(L) IIN(H)
13.5
resistive load
tOFF
IDS= IDS= 13.5
resistive load
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Power Stages
Command Description
Input Configuration Registers ICR01
INX1
000B
INX0
ICR23
INX3
001B
INX2
ICR45
INX5
010B
INX4
ICR67
INX7
011B
INX6
Field INXn
Bits [3:2], [1:0]
Type
Description Input Multiplexer Configuration Channel Channel switched Channel switched input Channel switched input Channel switched
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Protection Functions
Protection Functions
device provides embedded protective functions. Integrated protection functions designed prevent destruction under fault conditions described this data sheet. Fault conditions considered "outside" normal operating range. Protection functions designed continuous repetitive operation.
Over Load Protection
TLE7235G protected case over load short circuit load. After time tOFF(OVL), over loaded channel switches according diagnosis flag set. channel switched after clearing protection latch command CMD.CPL command clears itself with next valid communication frame. Please refer Figure details.
D0(OV tOFF(OV
OverLoad.emf
Figure
Shut Down Over Load
Over Temperature Protection
temperature sensor each channel causes overheated channel switch prevent destruction. according diagnosis flag set. This flag also state, regarding channel temperature high.The channel only switched after clearing protection latch command CMD.CPL command clears itself with next valid communication frame. Please refer "Diagnostic Features" Page information diagnosis features.
protection
There designed protection against disturbances specified limit using defined model. Please electrical characteristics "ESD susceptibility pins" Page
Reverse Polarity Protection
There reverse polarity protection implemented TLE7235G. This protection divided into parts. First protection control circuits second protection power transistors. control circuits reverse polarity protected protective measures ground connection. case reverse polarity, there current flow through control circuits. ensure this functionality, substrate connections must connected same potential. This means, copper area dedicated cooling will connected needs electrically isolated from GND. digital pins need serial resistors connected input stages floating ground. power transistors contain intrinsic body diodes that cause power dissipation. reverse current through these intrinsic body diodes limited connected loads. over temperature over load protection active during reverse polarity.
Loss
case loss connection on-state, inductances loads have demagnetized through ground connection through additional path from ground. Then example, diode (see Figure "Application Diagram" Page placed. Data Sheet Rev. 1.0, 2008-10-30
TLE7235G
Protection Functions
Electrical Characteristics
Unless otherwise specified: 5.5V, VBAT 16V, +150 typical values: VBAT 13.5 Pos. Parameter Over Load Protection 7.6.1 Over load detection current channel 0,1,4,5,6,7 7.6.3 Over load shut-down delay time Over Temperature Protection 7.6.4 Thermal shut down temperature
subject production test, specified design
Symbol min.
Limit Values typ. max. 1701)
Unit Test Conditions
IOut(OVL)
0.22
7.6.2 Over load detection current channel IOut(OVL)
tOFF(OVL) Tj(SC)
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Diagnostic Features
Diagnostic Features
TLE7235G provides diagnosis information about device about load. diagnosis information protective functions channel latched diagnosis flags cleared command CMD.CPL command clears itself with next valid communication frame. open load diagnosis channel latched diagnosis flag OLn. This flag cleared reading according diagnosis register. Following table shows possible failure modes according protective diagnostic action. Failure Mode Open Load Comment Diagnosis, when channel switched none Diagnosis, when channel switched off: according voltage level output pin, flag after time td(OL). diagnosis current enabled command DCCR.DCENn When over temperature occurs, according diagnosis flag set. affected channel active switched off. diagnosis flags latched until they have been cleared command CMD.CPL When over load detected channel affected channel switched after time tOFF(OVL) dedicated diagnosis flag set. diagnosis flags latched until they have been cleared command CMD.CPL
Over Temperature
Over Load (Short Circuit)
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Diagnostic Features
Electrical Characteristics
Unless otherwise specified: 5.5V, VBAT 16V, +150 typical values: VBAT 13.5 Pos. Parameter Symbol Limit Values min. State Diagnosis 8.1.1 8.1.2 8.1.3 Open load diagnosis delay time typ. Test Conditions max.
td(OL)
High Side Channels 0,1,2,3 Open load detection threshold voltage VD(OL0.3) Channel 0,1,2,3 Output diagnosis current channel 0,1,2,3 IL(DC0.3)
measured VD(OL) threshold
Configurable Channels 8.1.4 8.1.5 8.1.6 Open load detection threshold voltage VD(OL4,5) Channel configurations Output diagnosis current channel high side configuration Output diagnosis current channel side configuration
IL(DCHS) IL(DCLS)
measured VD(OL) threshold measured VD(OL) threshold
side Channels 8.1.7 8.1.8 Open load detection threshold voltage VD(OL6,7) Channel Output diagnosis current channel
IL(DC6,7)
measured threshold
State Diagnosis (see also Protection Chapter 8.1.9 Over load detection current channel 0,1,4,5,6,7
IL(OVL) IL(OVL)
0.22
8.1.10 Over load detection current channel
8.1.11 Over load detection delay time channel tOFF(OVL) 0,1,4,5,6,7
Open load detection voltages referenced ground
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Diagnostic Features
Command Description
Diagnosis Registers (read only, register bank DR01
DR23
DR45
DR67
Field
Bits
Type
Description Diagnostic Feedback Channel normal operation over load over temperature switch occurred Open Load Detection Channel normal operation Open load OFF-state occurred
Command Register
Wake
110B
Field Wake Data Sheet
Bits
Type
Description please refer Section description please refer Section description please refer Section description please refer Section description Rev. 1.0, 2008-10-30
TLE7235G
Diagnostic Features Diagnosis Current Configuration Register DCCR0
DCEN3 DCEN2
100B
DCEN1 DCEN0
DCCR1
DCEN7 DCEN6
101B
DCEN5 DCEN5
Field DCENn
Bits
Type
Description Diagnosis Current Enable Channel Diagnosis current disabled Diagnosis current enabled
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
diagnosis control interface based serial peripheral interface (SPI). full duplex synchronous serial slave interface, which uses four lines: SCLK Data transferred lines data rate given SCLK. falling edge indicates beginning data access. Data sampled line falling edge SCLK shifted line rising edge SCLK. Each access must terminated rising edge modulo counter ensures that data taken only, when multiple been transferred. interface provides daisy chain capability.
SCLK
time
SPI.emf
Figure
Serial Peripheral Interface
protocol described Section 9.3. reset default values after reset.
Signal Description
Chip Select: system micro controller selects TLE7235G means pin. Whenever state, data transfer take place. When high state, signals SCLK pins ignored forced into high impedance state. High transition: diagnosis information transferred into shift register. changes from high impedance state high state depending logic combination between transmission error flag (TER) signal level result, even daisy chain configuration, high signal indicates faulty transmission. details, please refer Figure This information stays available first rising edge SCLK.
SCLK
TER.emf
Figure
Transmission Error Flag Line
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Serial Peripheral Interface (SPI) High transition: Command decoding only done, when after falling edge exactly multiple eight SCLK signals have been detected. case faulty transmission, transmission error flag (TER) command ignored. Data from shift register transferred into input matrix register.
SCLK Serial Clock: This input clocks internal shift register. serial input (SI) transfers data into shift register falling edge SCLK while serial output (SO) shifts diagnostic information rising edge serial clock. essential that SCLK state whenever chip select makes transition. Serial Input: Serial input data bits shifted this pin, most significant first. information read falling edge SCLK. input data consist parts (control data). Please refer Section further information. Serial Output: Data shifted serially this pin, most significant first. high impedance state until goes state. data will appear following rising edge SCLK. Please refer Section further information.
Daisy Chain Capability
TLE7235G provides daisy chain capability. this configuration several devices activated same signal MCS. line device connected with line another device (see Figure 10), which builds chain. ends chain connected with output input master device, respectively. master device provides master clock MCLK, which connected SCLK line each device chain.
device
device
device
SCLK
SCLK
MCLK
Figure
Daisy Chain Configuration
block each device, there shift register where from line shifted each SCLK. shifted seen After SCLK cycles, data transfer device been finished. single chip configuration, line must high make device accept transferred data. daisy chain configuration data shifted device been shifted device When using three devices daisy chain, three times bits have shifted through devices. After that, line must high (see Figure 11).
Data Sheet
SCLK
SPI_DasyChain.emf
Rev. 1.0, 2008-10-30
TLE7235G
Serial Peripheral Interface (SPI)
MCLK
time
device device
device device
device device
SPI_DasyChain2.emf
Figure
Data Transfer Daisy Chain Configuration
Protocol
control diagnosis function TLE7235G based register banks which accessed following protocol. control register bank contains eight registers (with each) addressed pointer. diagnosis register bank contains four registers (with each) addressed pointer. additional indication available differentiate between standard diagnosis information data read from register bank. Control Diagnosis Mode
CS1)
ADDR ADDR
DATA
Write Register Command Read Register Command Read Standard Diagnosis Standard Diagnosis
Second Frame Read Command ADDR (Diagnosis) ADDR (Control) DATA DATA
This valid between first SCLK transition.
Note: Reading register needs frames. first frame command sent. second frame, output signal will contain requested information. command executed second frame.
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Serial Peripheral Interface (SPI)
Field
Bits
Type
Description Transmission Error Previous transmission successful (modulo clocks received) Previous transmission failed first transmission after reset
Register Bank CONTR Control Register Bank DIAG Diagnosis Register Bank (read only) Address Pointer register read write command Data Data written read from register selected address ADDR
ADDR DATA
Standard Diagnosis: Field Bits Type Description Awake, Device active Limp home mode active Failure mode alert channel
Register Overview
Control Register Bank Name ICR01 ICR23 ICR45 ICR67 DCCR0 DCCR1 unused Addr 000B 001B 010B 011B 100B 101B 110B 111B DCEN3 DCEN7 WAKE INX1 INX3 INX5 INX7 DCEN2 DCEN6 DCEN1 DCEN5 INX0 INX2 INX4 INX6 DCEN0 DCEN4
default1)
type
default values after power-on, STB-command RST-command command bits cleared transmission, respectively after execution needs valid next communication frame cleared
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Serial Peripheral Interface (SPI)
Diagnosis Register Bank (read only) Name DR01 DR23 DR45 DR67 Addr 000B 001B 010B 011B
Timing Diagrams
tCS(lead) tCS(lag) tSCLK(P) tSCLK(H) tSCLK(L)
0.7Vcc 0.2Vcc
tCS(td)
0.7Vcc 0.2Vcc
SCLK
tSI(su) tSI(h)
tSO(en) tSO(v) tSO(dis)
0.7Vcc 0.2Vcc
0.7Vcc 0.2Vcc Timing.emf
Figure
Timing Diagram
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Serial Peripheral Interface (SPI)
Electrical Characteristics
Unless otherwise specified: 5.5V, VBAT 16V, +150 typical values: VBAT 13.5 Pos. Parameter Input Characteristics (CS, SCLK, 9.6.1 level SCLK 9.6.2 level SCLK 9.6.3 L-input pull-up current through 9.6.4 H-input pull-up current through Symbol min. Limit Values typ. max. 0.2*VDD Unit Test Conditions
VCS(L) VSCLK(L) VSI(L) VCS(H) VSCLK(H) VSI(H) ICS(L) ICS(H)
0.5*VDD
0.5*VDD
9.6.5 L-input pull-down current through ISCLK(L) SCLK ISI(L) 9.6.6 H-input pull-down current through ISCLK(H) SCLK ISI(H) Output Characteristics (SO) 9.6.7 level output voltage 9.6.8 level output voltage 9.6.9 Output tristate leakage current Timings 9.6.10 Serial clock frequency 9.6.11 9.6.12 9.6.13 9.6.14
VSCLK 0.2*VDD
VDD= VSCLK -1.5
VSO(L) VSO(H) ISO(OFF)
fSCLK Serial clock period tSCLK(P) Serial clock high time tSCLK(H) Serial clock time tSCLK(L) Enable lead time (falling rising tCS(lead)
SCLK)
9.6.15 Enable time (falling SCLK rising tCS(lag) 9.6.16 Transfer delay time (rising falling 9.6.17 Data setup time (required time falling SCLK) 9.6.18 Data hold time (falling SCLK
tCS(td) tSI(su) tSI(h)
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Serial Peripheral Interface (SPI) Unless otherwise specified: 5.5V, VBAT 16V, +150 typical values: VBAT 13.5 Pos. Parameter Symbol min. 9.6.19 Output enable time (falling tSO(en) valid) 9.6.20 Output disable time (rising tSO(dis) tri-state) 9.6.21 Output data valid time with capacitive tSO(v) load
subject production test, specified design.
Limit Values typ. max.
Unit Test Conditions
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Package Outlines
Package Outlines
-0.1 STAND 2.45 -0.2
0.35
2.65 MAX.
-0.2
-0.1
0.05
1.27
0.35 +0.15
1.27 11.43
Seating Plane
MAX.
10.3 ±0.3
+0.8
Ejector Mark Depth MAX.
12.8 -0.2 Index Marking
Does include plastic metal protrusion 0.15 max. side Does include dambar protrusion side
Figure DSO20-45 (Plastic Green Dual Small Outline Package)
GPS05094
Green Product (RoHS compliant) meet world-wide customer requirements environmentally friendly products compliant with government regulations device available green product. Green products RoHS-Compliant (i.e Pbfree finish leads suitable Pb-free soldering according IPC/JEDEC J-STD-020).
further information alternative packages, please visit website: Data Sheet
Dimensions Rev. 1.0, 2008-10-30
0.23 +0.09
TLE7235G
Application Information
Application Information
Note: following information given hint implementation device only shall regarded description warranty certain functionality, condition quality device. Figure shows simplified application circuit. need externally reverse polarity protected.
Vbat
Lowside Loads
OUT0 OUT1 OUT2
OUT3
SCLK OUT6 OUT7
Highside Loads
Application _LG.emf
Figure
Application Diagram
Note: This very simplified example application circuit. function must verified real application. circuit above shows example using this device automotive target application. D1,C1 used blocking negative disturbances from Battery supply. optional loss battery other circuit this battery feed limit voltage negative max. rating device (-16 limiting battery voltage below maximum rated positive voltage stabilize digital driver, recommended value 47nF. There resistors needed internal reverse polarity protection.
further information contact http://www.infineon.com/
Data Sheet
Rev. 1.0, 2008-10-30
TLE7235G
Revision History
Revision Rev.
Revision History
Date 2008-10-30 Changes released Datasheet
Data Sheet
Rev. 1.0, 2008-10-30
Edition 2008-10-30 Published Infineon Technologies 81726 Munich, Germany 2008 Infineon Technologies Rights Reserved. Legal Disclaimer information given this document shall event regarded guarantee conditions characteristics. With respect examples hints given herein, typical values stated herein and/or information regarding application device, Infineon Technologies hereby disclaims warranties liabilities kind, including without limitation, warranties non-infringement intellectual property rights third party. Information further information technology, delivery terms conditions prices, please contact nearest Infineon Technologies Office (www.infineon.com). Warnings technical requirements, components contain dangerous substances. information types question, please contact nearest Infineon Technologies Office. Infineon Technologies components used life-support devices systems only with express written approval Infineon Technologies, failure such components reasonably expected cause failure that life-support device system affect safety effectiveness that device system. Life support devices systems intended implanted human body support and/or maintain sustain and/or protect human life. they fail, reasonable assume that health user other persons endangered.

SPIDER TLE7235G Channel High-Side Low-Side Relay Switch with Limp

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