MHz, Amps with mCal Gain Bandwidth Product: (typical) Short Circu
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MCP621/2/5
MHz, Amps with mCal
Gain Bandwidth Product: (typical) Short Circuit Current: (typical) Noise: nV/Hz (typical, MHz) Calibrated Input Offset: ±200 (maximum) Rail-to-Rail Output Slew Rate: V/µs (typical) Supply Current: (typical) Power Supply: 2.5V 5.5V Extended Temperature Range: -40°C +125°C
Description
Microchip Technology, Inc. MCP621/2/5 family operational amplifiers features offset. power these amps self-calibrated using mCal. Some package options also provide calibration/chip select (CAL/CS) that supports power mode operation, with offset calibration time normal operation re-started. These amplifiers optimized high speed, noise distortion, single-supply operation with rail-to-rail output input that includes negative rail. This family offered single with CAL/CS (MCP621), dual (MCP622) dual with CAL/CS pins (MCP625). devices fully specified from -40°C +125°C.
Typical Applications
Driving Converters Power Amplifier Control Loops Barcode Scanners Optical Detector Amplifier
Typical Application Circuit
VDD/2 VOUT MCP62X
Design Aids
SPICE Macro Models FilterLab® Software MindiCircuit Designer Simulator Microchip Advanced Part Selector (MAPS) Analog Demonstration Evaluation Boards Application Notes
Power Driver with High Gain
Package Types
MCP621 SOIC
VIN- VIN+ CAL/CS VOUT VCAL
MCP622
VOUTA VINA- VINA+ VOUTB VINB- VINB+
MCP625
VOUTA VINA- VINA+ CALA/CSA VOUTB VINB- VINB+ CALB/CSB
MCP622 SOIC
VOUTA VINA- VINA+ VOUTB VINB- VINB+
MCP625 MSOP
VOUTA VINA- VINA+ CALA/CSA VOUTB VINB- VINB+ CALB/CSB
Includes Exposed Thermal (EP); Table 3-1.
2009 Microchip Technology Inc.
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MCP621/2/5
NOTES:
DS22188A-page
2009 Microchip Technology Inc.
MCP621/2/5
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Notice: Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device those other conditions above those indicated operational listings this specification implied. Exposure maximum rating conditions extended periods affect device reliability. Section 4.2.2 "Input Voltage Current Limits".
.6.5V Current Input Pins Analog Inputs (VIN+ VIN-) 1.0V 1.0V other Inputs Outputs 0.3V 0.3V Output Short Circuit Current Continuous Current Output Supply Pins .±150 Storage Temperature .-65°C +150°C Max. Junction Temperature +150°C protection pins (HBM, 200V
Specifications
ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, +25°C, +2.5V +5.5V, GND, VDD/3, VOUT VDD/2, VDD/2, CAL/CS (refer Figure 1-2).
Parameters
Input Offset Input Offset Voltage Input Offset Voltage Trim Step Size Input Offset Voltage Drift Power Supply Rejection Ratio Input Current Impedance Input Bias Current Across Temperature Across Temperature Input Offset Current Common Mode Input Impedance Differential Input Impedance Common Mode Common-Mode Input Voltage Range Common-Mode Rejection Ratio Open-Loop Gain Open-Loop Gain (large signal) Output Maximum Output Voltage Swing
VOSTRM VOS/TA PSRR ZDIFF VCMR CMRR CMRR VOL, VOL,
-200
±2.0 1700 1013||9 1013||2
+200 5,000 ±130 ±110
Units
||pF ||pF (Note
Conditions
After calibration (Note (Note
µV/°C -40°C +125°C
+85°C +125°C
2.5V, -0.3 1.2V 5.5V, -0.3 4.2V 2.5V, VOUT 0.3V 2.2V 5.5V, VOUT 0.3V 5.2V 2.5V, 0.5V Input Overdrive 5.5V, 0.5V Input Overdrive 2.5V (Note 5.5V (Note
Output Short Circuit Current Note
Describes offset (under specified conditions) right after power just after CAL/CS toggled. Thus, noise effects apparent wander VOS; Figure 2-35) included. Increment between adjacent trim points; Figure shows this affects repeatability. Figure Figure temperature effects. specifications design guidance only; they tested.
2009 Microchip Technology Inc.
DS22188A-page
MCP621/2/5
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, +25°C, +2.5V +5.5V, GND, VDD/3, VOUT VDD/2, VDD/2, CAL/CS (refer Figure 1-2).
Parameters
Calibration Input Calibration Input Voltage Range Internal Calibration Voltage Input Impedance Power Supply Supply Voltage Quiescent Current Amplifier Input Threshold, Input Threshold, High Note
VCALRNG VCAL ZCAL VPRL VPRH
0.323VDD 1.15
0.333VDD 1.40 1.40
0.343VDD 1.65
Units
k||pF
Conditions
VCAL externally driven VCAL open
Describes offset (under specified conditions) right after power just after CAL/CS toggled. Thus, noise effects apparent wander VOS; Figure 2-35) included. Increment between adjacent trim points; Figure shows this affects repeatability. Figure Figure temperature effects. specifications design guidance only; they tested.
ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, +25°C, +2.5V +5.5V, GND, VDD/2, VOUT VDD/2, VDD/2, CAL/CS (refer Figure 1-2).
Parameters
Response Gain Bandwidth Product Phase Margin Open-Loop Output Impedance Distortion Total Harmonic Distortion plus Noise Step Response Rise Time, Slew Rate Noise Input Noise Voltage Input Noise Voltage Density Input Noise Current Density
GBWP ROUT THD+N
0.0018
Units
Conditions
VOUT 2VP-P, kHz, 5.5V, VOUT mVP-P
V/µs µVP-P fA/Hz
nV/Hz
DIGITAL ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, +25°C, +2.5V +5.5V, GND, VDD/2, VOUT VDD/2, VDD/2, CAL/CS (refer Figure Figure 1-2).
Parameters
CAL/CS Specifications CAL/CS Logic Threshold, Note
Units
Conditions
0.2VDD
MCP622 CAL/CS input internally pulled down (0V). This time ensures that internal logic recognizes edge. However, rising edge case, CAL/CS raised before calibration complete, calibration will aborted part will return power mode. MCP625 dual, there additional constraint. CALA/CSA CALB/CSB toggled simultaneously (within time much smaller than tCSU) make both amps perform same function simultaneously. they toggled independently, then CALA/CSA (CALB/CSB) cannot allowed toggle while calibration mode; allow more than maximum tCON time before other side toggled.
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MCP621/2/5
DIGITAL ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, +25°C, +2.5V +5.5V, GND, VDD/2, VOUT VDD/2, VDD/2, CAL/CS (refer Figure Figure 1-2).
Parameters
CAL/CS Input Current, CAL/CS High Specifications CAL/CS Logic Threshold, High CAL/CS Input Current, High Current
ICSL ICSH
Units
CAL/CS
Conditions
0.8VDD -3.5 -1.8 -2.5
CAL/CS VDD, 125°C V/V, VSS, 2.5V step VOUT (2.5V) V/V, VSS, 2.5V step VOUT (2.5V) CAL/CS Single, CAL/CS 2.5V Single, CAL/CS 5.5V Dual, CAL/CS 2.5V Dual, CAL/CS 5.5V
CAL/CS Internal Pull Down Resistor Amplifier Output Leakage Dynamic Specifications Amplifier Time (output goes High-Z) High Amplifier Time (including calibration) CAL/CS Dynamic Specifications CAL/CS Input Hysteresis CAL/CS Setup Time (between CAL/CS edges) CAL/CS High Amplifier Time (output goes High-Z) CAL/CS Amplifier Time (including calibration) Note
IO(LEAK) tPOFF tPON
VHYST tCSU tCOFF tCON
0.25
V/V, (Notes CAL/CS 0.8VDD VOUT (VDD/2) V/V, VSS, CAL/CS 0.8VDD VOUT (VDD/2) V/V, VSS, CAL/CS 0.2VDD VOUT (VDD/2)
MCP622 CAL/CS input internally pulled down (0V). This time ensures that internal logic recognizes edge. However, rising edge case, CAL/CS raised before calibration complete, calibration will aborted part will return power mode. MCP625 dual, there additional constraint. CALA/CSA CALB/CSB toggled simultaneously (within time much smaller than tCSU) make both amps perform same function simultaneously. they toggled independently, then CALA/CSA (CALB/CSB) cannot allowed toggle while calibration mode; allow more than maximum tCON time before other side toggled.
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, limits specified for: +2.5V +5.5V, GND.
Parameters
Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 8L-3x3 Thermal Resistance, 8L-SOIC Thermal Resistance, 10L-3x3 Thermal Resistance, 10L-MSOP Note
140.9
+125 +125 +150
Units
°C/W °C/W °C/W °C/W (Note (Note (Note
Conditions
Operation must cause exceed Maximum Junction Temperature specification (150°C). Measured standard JC51-7, four layer printed circuit board with ground plane vias.
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MCP621/2/5
Timing Diagram
VPRH tPON VOUT High-Z (typical) (typical) -2.5 (typical) tCOFF High-Z tCSU VPRL tCON -2.5 (typical) tPOFF High-Z
CAL/CS
(typical) (typical)
(typical) (typical)
FIGURE 1-1:
Timing Diagram.
Test Circuits
VIN+ MCP62X VIN- VOUT
circuit used most tests shown Figure 1-2. This circuit independently VOUT; Equation 1-1. Note that circuit's common mode voltage ((VP VM)/2), that VOST includes plus effects input offset error, VOST) temperature, CMRR, PSRR AOL.
VDD/2
EQUATION 1-1:
Where: Differential Mode Gain Amp's Common Mode Input Voltage VOST Amp's Total Input Offset Voltage (V/V) (mV)
FIGURE 1-2: Test Circuit Most Specifications.
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MCP621/2/5
Note:
TYPICAL PERFORMANCE CURVES
graphs tables provided following this note statistical summary based limited number samples provided informational purposes only. performance characteristics listed herein tested guaranteed. some graphs tables, data presented outside specified operating range (e.g., outside specified power supply range) therefore outside warranted range.
Note: Unless otherwise indicated, +25°C, +2.5V 5.5V, GND, VDD/3, VOUT VDD/2, VDD/2, CAL/CS VSS.
Percentage Occurrences
Signal Inputs
Samples +25°C 2.5V 5.5V Calibrated +25°C
-100 -200 -300 -400 -500 -600 -700
Input Offset Voltage (µV)
Representative Part Calibrated 6.5V +125°C +85°C +25°C -40°C
Input Offset Voltage (µV)
Power Supply Voltage
FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4: Input Offset Voltage Power Supply Voltage.
Representative Part
Percentage Occurrences
Input Offset Voltage (µV)
Samples 2.5V 5.5V -40°C +125°C Calibrated +25°C
5.5V
2.5V
Input Offset Voltage Drift (µV/°C)
Output Voltage
FIGURE 2-2:
Input Offset Voltage Drift.
FIGURE 2-5: Output Voltage.
Input Common Mode Headroom -0.1 -0.2 -0.3
Input Offset Voltage
Percentage Occurrences
Samples +25°C 2.5V 5.5V
(VCMR_L VSS)
Change (includes noise) Calibration Changed step) Calibration Changed step)
2.5V
5.5V
-0.4 -0.5 Ambient Temperature (°C)
Input Offset Voltage Calibration Repeatability (µV)
FIGURE 2-3: Input Offset Voltage Repeatability (repeated calibration).
FIGURE 2-6: Input Common Mode Voltage Headroom Ambient Temperature.
2009 Microchip Technology Inc.
DS22188A-page
MCP621/2/5
Note: Unless otherwise indicated, +25°C, +2.5V 5.5V, GND, VDD/3, VOUT VDD/2, VDD/2, CAL/CS VSS.
High Input Common Mode Headroom
High (VDD VCMR_H)
CMRR, PSRR (dB)
2.5V
PSRR CMRR, 5.5V CMRR, 2.5V
5.5V
Ambient Temperature (°C)
Ambient Temperature (°C)
FIGURE 2-7: High Input Common Mode Voltage Headroom Ambient Temperature.
1000 -200 -400 -600 -800 -1000 -0.6
FIGURE 2-10: CMRR PSRR Ambient Temperature.
Open-Loop Gain (dB) Ambient Temperature (°C)
2.5V 5.5V
Input Offset Voltage (µV)
2.5V Representative Part
+125°C +85°C +25°C -40°C
-0.4
-0.2
Input Common Mode Voltage
FIGURE 2-8: Input Offset Voltage Common Mode Voltage with 2.5V.
1000 -200 -400 -600 -800 -1000 -0.5
5.5V Representative Part
FIGURE 2-11: Open-Loop Gain Ambient Temperature.
10,000 Input Bias, Offset Currents (pA)
Input Offset Voltage (µV)
5.5V VCMR_H
1,000
+125°C +85°C +25°C -40°C
Ambient Temperature (°C)
Input Common Mode Voltage
FIGURE 2-9: Input Offset Voltage Common Mode Voltage with 5.5V.
FIGURE 2-12: Input Bias Offset Currents Ambient Temperature with +5.5V.
DS22188A-page
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MCP621/2/5
Note: Unless otherwise indicated, +25°C, +2.5V 5.5V, GND, VDD/3, VOUT VDD/2, VDD/2, CAL/CS VSS.
Input Bias, Offset Currents (pA) -0.5 Common Mode Input Voltage
Representative Part +85°C 5.5V
1.E-03 Input Current Magnitude 100µ 1.E-04 1.E-05 1.E-06 100n 1.E-07 1.E-08 1.E-09 100p 1.E-10 1.E-11
+125°C +85°C +25°C -40°C
1.E-12 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 Input Voltage
FIGURE 2-13: Input Bias Offset Currents Common Mode Input Voltage with +85°C.
1500 Input Bias, Offset Currents (pA) 1000
Representative Part +125°C 5.5V
FIGURE 2-15: Input Bias Current Input Voltage (below VSS).
-500 -1000 Common Mode Input Voltage
FIGURE 2-14: Input Bias Offset Currents Common Mode Input Voltage with +125°C.
2009 Microchip Technology Inc.
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MCP621/2/5
Note: Unless otherwise indicated, +25°C, +2.5V 5.5V, GND, VDD/3, VOUT VDD/2, VDD/2, CAL/CS VSS.
Other Voltages Currents
Output Current Magnitude (mA)
2.5V IOUT
Ratio Output Headroom Output Current (mV/mA)
5.5V
-IOUT
Supply Current (mA/amplifier) Power Supply Voltage
+125°C +85°C +25°C -40°C
FIGURE 2-16: Ratio Output Voltage Headroom Output Current.
FIGURE 2-19: Supply Voltage.
Supply Current (mA/amplifier)
2.5V
Supply Current Power
5.5V
Output Headroom (mV)
5.5V
2.5V
VPRH VPRL
Ambient Temperature (°C)
Common Mode Input Voltage
FIGURE 2-17: Output Voltage Headroom Ambient Temperature.
-100
FIGURE 2-20: Supply Current Common Mode Input Voltage.
Trip Voltages Ambient Temperature (°C)
Output Short Circuit Current (mA)
+125°C +85°C +25°C -40°C
Power Supply Voltage
FIGURE 2-18: Output Short Circuit Current Power Supply Voltage.
FIGURE 2-21: Power Reset Voltages Ambient Temperature.
DS22188A-page
2009 Microchip Technology Inc.
MCP621/2/5
Note: Unless otherwise indicated, +25°C, +2.5V 5.5V, GND, VDD/3, VOUT VDD/2, VDD/2, CAL/CS VSS.
Percentage Occurrences 33.20% 33.24% 33.28% 33.32% 33.36% 33.40% 33.44% 33.48% 33.52% Ambient Temperature (°C)
Normalized Internal Calibration Voltage; VCAL/VDD
FIGURE 2-22: Normalized Internal Calibration Voltage.
FIGURE 2-23: Temperature.
Internal Resistance
Samples 2.5V 5.5V
VCAL Input Resistance
2009 Microchip Technology Inc.
DS22188A-page
MCP621/2/5
Note: Unless otherwise indicated, +25°C, +2.5V 5.5V, GND, VDD/3, VOUT VDD/2, VDD/2, CAL/CS VSS.
Frequency Response
Gain Bandwidth Product (MHz) 1.E+3 100k 1.E+4 1.E+5 Frequency (Hz) 1.E+6 1.E+7 -0.5 Common Mode Input Voltage
GBWP
5.5V 2.5V
CMRR, PSRR (dB) 1.E+2
PSRR+ PSRRCMRR
FIGURE 2-24: Frequency.
CMRR PSRR
FIGURE 2-27: Gain Bandwidth Product Phase Margin Common Mode Input Voltage.
Gain Bandwidth Product (MHz) Open-Loop Phase Output Voltage
GBWP
Open-Loop Gain (dB)
-120 -150 -180 -210 -240
5.5V 2.5V
1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 100k 1.E+6 100M 1.E+5 1.E+7 1.E+8
Frequency (Hz)
FIGURE 2-25: Frequency.
Gain Bandwidth Product (MHz)
Open-Loop Gain
FIGURE 2-28: Gain Bandwidth Product Phase Margin Output Voltage.
Open-Loop Output Impedance
Phase Margin
5.5V 2.5V
GBWP
Ambient Temperature (°C)
100k 100M 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08 Frequency (Hz)
FIGURE 2-26: Gain Bandwidth Product Phase Margin Ambient Temperature.
FIGURE 2-29: Closed-Loop Output Impedance Frequency.
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Phase Margin
Phase Margin
MCP621/2/5
Note: Unless otherwise indicated, +25°C, +2.5V 5.5V, GND, VDD/3, VOUT VDD/2, VDD/2, CAL/CS VSS.
1.0E-11
Channel-to-Channel Separation (dB)
Gain Peaking (dB)
VDD/2
100p 1.0E-10 1.0E-09 Normalized Capacitive Load; CL/GN
1.E+03
1.E+04
100k 1.E+05 1.E+06 Frequency (Hz)
1.E+07
FIGURE 2-30: Gain Peaking Normalized Capacitive Load.
FIGURE 2-31: Channel-to-Channel Separation Frequency.
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MCP621/2/5
Note: Unless otherwise indicated, +25°C, +2.5V 5.5V, GND, VDD/3, VOUT VDD/2, VDD/2, CAL/CS VSS.
Input Noise Voltage Density (nV/Hz)
1.E+4
Input Noise Distortion
Input Offset Noise; eni(t) (µV) Time (min)
Representative Part Analog NPBW Sample Rate
1.E+3
1.E+2 100n
1.E+1 1.E-1
1.E+0
1.E+1
1.E+2
1.E+5 1.E+3 1.E+4 100k 1.E+6 1.E+7 Frequency (Hz)
FIGURE 2-32: Frequency.
-0.5
Input Noise Voltage Density
FIGURE 2-35: Input Noise plus Offset Time with Filter.
Input Noise Voltage Density (nV/Hz)
Noise
2.5V 5.5V
0.01
0.001
5.0V VOUT VP-P
0.0001 1.E+2
1.E+3
Common Mode Input Voltage
1.E+4 Frequency (Hz)
100k 1.E+5
FIGURE 2-33: Input Noise Voltage Density Input Common Mode Voltage with
-0.5
2.5V 5.5V
FIGURE 2-36:
THD+N Frequency.
Input Noise Voltage Density (nV/Hz)
Common Mode Input Voltage
FIGURE 2-34: Input Noise Voltage Density Input Common Mode Voltage with MHz.
DS22188A-page
2009 Microchip Technology Inc.
MCP621/2/5
Note: Unless otherwise indicated, +25°C, +2.5V 5.5V, GND, VDD/3, VOUT VDD/2, VDD/2, CAL/CS VSS.
Time Response
5.5V
VOUT
Output Voltage mV/div)
Output Voltage
5.5V
VOUT
Time (ns)
Time (µs)
FIGURE 2-37: Step Response.
5.5V
Non-inverting Small Signal
FIGURE 2-40: Response.
Input, Output Voltages
5.5V
Inverting Large Signal Step
VOUT
Output Voltage
VOUT
Time (µs)
Time (ms)
FIGURE 2-38: Step Response.
Non-inverting Large Signal
FIGURE 2-41: MCP621/2/5 Family Shows Input Phase Reversal with Overdrive.
Falling Edge
Output Voltage mV/div)
5.5V
Slew Rate (V/µs)
2.5V
5.5V Rising
VOUT
Time (ns)
Ambient Temperature (°C)
FIGURE 2-39: Response.
Inverting Small Signal Step
FIGURE 2-42: Temperature.
Slew Rate Ambient
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MCP621/2/5
Note: Unless otherwise indicated, +25°C, +2.5V 5.5V, GND, VDD/3, VOUT VDD/2, VDD/2, CAL/CS VSS.
Maximum Output Voltage Swing (VP-P)
5.5V 2.5V
100k 1.E+05
1.E+06 1.E+07 Frequency (Hz)
100M 1.E+08
FIGURE 2-43: Maximum Output Voltage Swing Frequency.
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MCP621/2/5
Note: Unless otherwise indicated, +25°C, +2.5V 5.5V, GND, VDD/3, VOUT VDD/2, VDD/2, CAL/CS VSS.
Calibration Chip Select Response
CAL/CS
0.40 CAL/CS Hysteresis 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 Ambient Temperature (°C)
5.5V 2.5V
CAL/CS Current (µA)
Power Supply Voltage
FIGURE 2-44: Supply Voltage.
CAL/CS,
Calibration starts CAL/CS VOUT
CAL/CS Current Power
FIGURE 2-47: CAL/CS Hysteresis Ambient Temperature.
CAL/CS Turn Time (ms) Ambient Temperature (°C)
2.5V
turns turns
Time (ms)
FIGURE 2-45: CAL/CS Voltage, Output Voltage Supply Current (for Side Time with 2.5V.
Power Supply Current; (mA) CAL/CS, Time (ms)
Calibration starts CAL/CS VOUT turns turns
5.5V
Power Supply Current; (mA)
FIGURE 2-48: CAL/CS Turn Time Ambient Temperature.
CAL/CS Pull-down Resistor
Representative Part
Ambient Temperature (°C)
FIGURE 2-46: CAL/CS Voltage, Output Voltage Supply Current (for Side Time with 5.5V.
FIGURE 2-49: CAL/CS's Pull-down Resistor (RPD) Ambient Temperature.
2009 Microchip Technology Inc.
DS22188A-page
MCP621/2/5
Note: Unless otherwise indicated, +25°C, +2.5V 5.5V, GND, VDD/3, VOUT VDD/2, VDD/2, CAL/CS VSS.
Negative Power Supply Current; (µA) Power Supply Voltage
+125°C +85°C +25°C -40°C
Output Leakage Current
CAL/CS
1.E-06 1.E-07 1.E-08 1.E-09 1.E-10
CAL/CS 5.5V
+125°C +85°C
+25°C
1.E-11 Output Voltage
FIGURE 2-50: Quiescent Current Shutdown Power Supply Voltage.
FIGURE 2-51: Output Voltage.
Output Leakage Current
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MCP621/2/5
DESCRIPTIONS
Descriptions pins listed Table 3-1.
TABLE 3-1:
MCP621 SOIC
FUNCTION TABLE
MCP622 MCP625 MSOP Symbol VOUT, VOUTA VIN-, VINA- VIN+, VINA+ CAL/CS, CALA/CSA CALB/CSB VINB+ VINB- VOUTB VCAL Description Output Inverting Input Non-inverting Input Negative Power Supply Calibrate/Chip Select Digital Input Calibrate/Chip Select Digital Input Non-inverting Input Inverting Input Output Positive Power Supply Calibration Common Mode Voltage Input Internal Connection Exposed Thermal (EP); must connected
SOIC
Analog Outputs
Calibrate/Chip Select Digital Input
analog output pins (VOUT) low-impedance voltage sources.
Analog Inputs
non-inverting inverting inputs (VIN+, VIN-, high-impedance CMOS inputs with bias currents.
This input (CAL/CS, CMOS, Schmitt-triggered input that affects calibration power modes operation. When this goes high, part placed into power mode output high-Z. When this goes low, calibration sequence started (which corrects VOS). calibration sequence, output becomes impedance part resumes normal operation. internal triggers calibration event when part powered when supply voltage drops low. Thus, MCP622 parts calibrated, even though they have CAL/CS pin.
Power Supply Pins
positive power supply (VDD) 2.5V 5.5V higher than negative power supply (VSS). normal operation, other pins between VDD. Typically, these parts used single (positive) supply configuration. this case, connected ground connected supply. will need bypass capacitors.
Exposed Thermal (EP)
Calibration Common Mode Voltage Input
There internal connection between Exposed Thermal (EP) pin; they must connected same potential Printed Circuit Board (PCB). This connected ground plane provide larger heat sink. This improves package thermal resistance (JA).
impedance voltage placed this input (VCAL) analog input will amps' common mode input voltage during calibration. this left open, common mode input voltage during calibration approximately VDD/3. internal resistor divider disconnected from supplies whenever part calibration.
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NOTES:
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MCP621/2/5
APPLICATIONS
4.1.3 INTERNAL
MCP621/2/5 family self-zeroed amps manufactured using Microchip's state CMOS process. designed cost, power high precision applications. supply voltage, quiescent current wide bandwidth makes MCP621/2/5 ideal battery-powered applications. This part includes internal Power Reset (POR) protect internal calibration memory cells. monitors power supply voltage (VDD). When detects event, places part into power mode operation. When detects normal event, starts delay counter, then triggers calibration event. additional delay gives total turn time (typical); this also power time (since triggered power up).
Calibration Chip Select
These amps include circuitry dynamic calibration offset voltage (VOS).
4.1.4
PARITY DETECTOR
4.1.1
mCal CALIBRATION CIRCUITRY
internal mCal circuitry, when activated, starts delay timer wait settle bias point), then calibrates input offset voltage (VOS). mCal circuitry triggered power-up (and after some power brown events) internal POR, memory's Parity Detector. power time, when mCal circuitry triggers calibration sequence, (typical).
parity error detector monitors memory contents corruption. rare event that parity error detected (e.g., corruption from alpha particle), event automatically triggered. This will cause input offset voltage re-corrected, will return normal operation period time (the turn time, tPON).
4.1.5
CALIBRATION INPUT
4.1.2
CAL/CS
CAL/CS gives user means externally demand power mode operation, then calibrate VOS. Using CAL/CS makes possible correct drifts over time (1/f noise aging; Figure 2-35) across temperature. CAL/CS performs functions: places amp(s) power mode when held high, starts calibration event (correction VOS) after rising edge. While power mode, quiescent current quite small (ISS typical). output also High-Z state. During calibration event, quiescent current near, smaller than, specified quiescent current typical). output continues High-Z state, inputs disconnected from external circuit, prevent internal signals from affecting circuit operation. inputs internally connected common mode voltage buffer feedback resistors. offset corrected (using digital state machine, logic memory), calibration constants stored memory. Once calibration event completed, amplifier reconnected external circuitry. turn time, when calibration started with CAL/CS pin, (typical). There internal pull-down resistor tied CAL/CS pin. CAL/CS left floating, amplifier operates normally.
VCAL available some options (e.g., single MCP621) those applications that need calibration occur internally driven common mode voltage other than VDD/3. Figure shows reference circuit that internally sets amp's common mode reference voltage (VCM_INT) during calibration (the resistors disconnected from supplies other times). resistor provides over-current protection buffer. VCAL during calibration BUFFER VCM_INT
FIGURE 4-1: Input Circuitry.
Common-Mode Reference's
When VCAL left open, internal resistor divider generates VCM_INT approximately VDD/3, which near center input common mode voltage range. recommended that external capacitor from VCAL ground added improve noise immunity.
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When VCAL driven external voltage source, which within specified range, will have input offset voltage calibrated that common mode input voltage. Make sure that VCAL within specified range. possible external resistor voltage divider modify VCM_INT; Figure 4-2. internal circuitry VCAL looks like tied VDD/3. parallel equivalent should much smaller than minimize differences matching temperature drift between internal external resistors. Again, make sure that VCAL within specified range. MCP62X VCAL Bond
VIN+ Bond
Input Stage
Bond
Bond
FIGURE 4-3: Structures.
Simplified Analog Input
FIGURE 4-2: Resistors.
Setting with External
order prevent damage and/or improper operation these amplifiers, circuit must limit currents (and voltages) input pins (see Section "Absolute Maximum Ratings Figure shows recommended approach protecting these inputs. internal diodes prevent input pins (VIN+ VIN-) from going below ground, resistors limit possible current drawn input pins. Diodes prevent input pins (VIN+ VIN-) from going above VDD, dump currents onto VDD. When implemented shown, resistors also limit current through MCP62X VOUT (minimum expected (minimum expected
instance, design goal VCM_INT 0.1V when 2.5V could with: 24.3 1.00 This will keep VCAL within range VDD, should close enough ground based applications.
4.2.1
Input
PHASE REVERSAL
input devices designed exhibit phase inversion when input pins exceed supply voltages. Figure 2-41 shows input voltage exceeding both supplies with phase inversion.
4.2.2
INPUT VOLTAGE CURRENT LIMITS
FIGURE 4-4: Inputs.
Protecting Analog
protection inputs depicted shown Figure 4-3. This structure chosen protect input transistors, minimize input bias current (IB). input diodes clamp inputs when they more than diode drop below VSS. They also clamp voltages that above VDD; their breakdown voltage high enough allow normal operation, enough bypass quick events within specified limits.
also possible connect diodes left resistor this case, currents through diodes need limited some other mechanism. resistors then serve in-rush current limiters; current into input pins (VIN+ VIN-) should very small. significant amount current flow inputs (through diodes) when common mode voltage (VCM) below ground (VSS); Figure 2-15. Applications that high impedance need limit usable voltage range.
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4.2.3 NORMAL OPERATION 4.3.2.1 Power Dissipation
input stage MCP621/2/5 amps uses differential PMOS input stage. operates common mode input voltage (VCM), with 1.3V down 0.3V. input offset voltage (VOS) measured 0.3V 1.3V ensure proper operation. Figure Figure temperature effects. When operating very non-inverting gains, output voltage limited range 1.3V); Figure 4-5. MCP62X VOUT MCP62X Since output short circuit current (ISC) specified (typical), these amps capable both delivering dissipating significant power. common loads, their impact amp's power dissipation, will discussed. Figure shows resistive load (RL) with output voltage (VOUT). RL's ground point, usually ground (0V) IOUT output current. input currents assumed negligible. IOUT VOUT
1.3V
FIGURE 4-5: Unity Gain Voltage Limitations Linear Operation.
FIGURE 4-7: Diagram Resistive Load Power Calculations.
currents are:
4.3.1
Rail-to-Rail Output
MAXIMUM OUTPUT VOLTAGE
Maximum Output Voltage (see Figure 2-16 Figure 2-17) describes output range given load. instance, output voltage swings within negative rail with load tied VDD/2.
EQUATION 4-1:
Where: Quiescent supply current (mA/amplifier) VOUT value power
4.3.2
OUTPUT CURRENT
Figure shows possible combinations output voltage (VOUT) output current (IOUT). IOUT positive when flows into external circuit.
-0.5
Limited (VDD 5.5V)
EQUATION 4-2:
+ISC Limited
VOUT
-ISC Limited
maximum power, resistive loads occurs when VOUT halfway between halfway between
Limited
IOUT (mA)
EQUATION 4-3:
FIGURE 4-6:
Output Current.
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Figure shows capacitive load (CL), which driven sine wave with offset. capacitive load causes output higher currents higher frequencies. Because output rectifies IOUT, amp's dissipated power increases (even though capacitor does dissipate power). MCP62X IOUT VOUT power dissipated package depends powers dissipated each that package:
EQUATION 4-7:
Where:
Number amps package maximum ambient junction temperature rise (TJA) junction temperature (TJ) calculated using maximum expected package power (PPKG), ambient temperature (TA) package thermal resistance (JA) found Section "Temperature Specifications":
FIGURE 4-8: Diagram Capacitive Load Power Calculations.
output voltage assumed
EQUATION 4-8:
worst case power de-rating amps particular package easily calculated:
EQUATION 4-4:
Where: offset Peak output swing (VPK)
EQUATION 4-9:
Jmax
Radian frequency (rad/s)
amp's currents are: Where:
EQUATION 4-5:
Where: Quiescent supply current (mA/amplifier) amp's instantaneous power, average power peak power are:
TJmax Absolute maximum junction temperature (°C) Ambient temperature (°C) Several techniques available reduce given package: Reduce another package Improve layout (ground plane, etc.) heat sinks flow Reduce max(PPKG) Increase Decrease Limit IOUT using RISO (see Figure 4-9) Decrease
EQUATION 4-6:
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4.4.1
Improving Stability
CAPACITIVE LOADS
4.4.2
GAIN PEAKING
Driving large capacitive loads cause stability problems voltage feedback amps. load capacitance increases, feedback loop's phase margin decreases closed-loop bandwidth reduced. This produces gain peaking frequency response, with overshoot ringing step response. Figure 2-30. unity gain buffer most sensitive capacitive loads, though gains show same general behavior. When driving large capacitive loads with these amps (e.g., when +1), small series resistor output (RISO Figure 4-9) improves feedback loop's phase margin (stability) making output load resistive higher frequencies. bandwidth will generally lower than bandwidth with capacitive load. RISO VOUT MCP62X
Figure 4-11 shows circuit that represents non-inverting amplifiers voltage input) inverting amplifiers voltage input). capacitances represent total capacitance input pins; they include amp's common mode input capacitance (CCM), board parasitic capacitance capacitor placed parallel.
MCP62X VOUT
FIGURE 4-11: Capacitance.
Amplifier with Parasitic
acts parallel with (except gain V/V), which causes increase gain high frequencies. also reduces phase margin feedback loop, which becomes less stable. This effect reduced either reducing form low-pass filter that affects signal This filter single real pole 1/(2RNCN). largest value that should used depends noise gain (see Section 4.4.1 "Capacitive Loads") Figure 4-12 shows maximum recommended several values.
1.E+05 100k Maximum Recommended
FIGURE 4-9: Output Resistor, RISO Stabilizes Large Capacitive Loads.
Figure 4-10 gives recommended RISO values different capacitive loads gains. x-axis normalized load capacitance (CL/GN), where circuit's noise gain. non-inverting gains, Signal Gain equal. inverting gains, 1+|Signal Gain| (e.g., gives V/V).
1,000 Recommended RISO
1.E+04
1.E+03
1.E+02 Noise Gain; (V/V)
1.E-12
100p 1.E-11 1.E-10 1.E-09 Normalized Capacitance; CL/GN
1.E-08
FIGURE 4-12: Gain.
Maximum Recommended
FIGURE 4-10: Recommended RISO Values Capacitive Loads.
After selecting RISO your circuit, double check resulting frequency response peaking step response overshoot. Modify RISO's value until response reasonable. Bench evaluation simulations with MCP621/2/5 SPICE macro model helpful.
Figure 2-37 Figure 2-38 show small signal large signal step responses V/V. unity gain buffer usually open. Figure 2-39 Figure 2-40 show small signal large signal step responses V/V. Since noise gain resistors were chosen 500.
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also possible capacitor (CF) parallel with compensate de-stabilizing effect This makes possible larger values conditions stability summarized Equation 4-10. coax cables, inductance wiring, route signal power from PCB. Mutual self inductance power wires often cause crosstalk unusual behavior.
EQUATION 4-10:
Given:
4.7.1
Typical Applications
POWER DRIVER WITH HIGH GAIN
need: GBWP GBWP
Figure 4-13 shows power driver with high gain R2/R1). MCP621/2/5 amp's short circuit current makes possible drive significant loads. calibrated input offset voltage supports accurate response high gains. should small, equal R1||R2, order minimize bias current induced offset. MCP62X
VDD/2
VOUT
Power Supply
With this family operational amplifiers, power supply (VDD single supply) should have local bypass capacitor (i.e., 0.01 within good high frequency performance. Surface mount, multilayer ceramic capacitors, their equivalent, should used. These amps require bulk capacitor (i.e., larger) within provide large, slow currents. Tantalum capacitors, their equivalent, good choice. This bulk capacitor shared with other nearby analog parts long crosstalk through supplies does prove problem.
FIGURE 4-13: 4.7.2
Power Driver.
OPTICAL DETECTOR AMPLIFIER
High Speed Layout
These amps fast enough that little extra care (Printed Circuit Board) layout make significant difference performance. Good board layout techniques will help achieve performance shown specifications Typical Performance Curves; will also help minimize (Electro-Magnetic Compatibility) issues. solid ground plane. Connect bypass local capacitor(s) this plane with minimal length traces. This cuts down inductive capacitive crosstalk. Separate digital from analog, speed from high speed, power from high power. This will reduce interference. Keep sensitive traces short straight. Separate them from interfering components traces. This especially important high frequency (low rise time) signals. Sometimes, helps place guard traces next victim traces. They should both sides victim trace, close possible. Connect guard traces ground plane both ends, middle long traces.
Figure 4-14 shows transimpedance amplifier, using MCP621 amp, photo detector circuit. photo detector capacitive current source. amp's input common mode capacitance typical) differential mode capacitance typical) parallel with provides enough gain produce VOUT. stabilizes gain limits transimpedance bandwidth about 0.51 MHz. RF's parasitic capacitance (e.g., 0.15 0603 SMD) acts parallel with Photo Detector 30pF MCP621 VDD/2
VOUT
FIGURE 4-14: Transimpedance Amplifier Optical Detector.
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4.7.3 H-BRIDGE DRIVER
Figure 4-15 shows MCP622 dual used H-bridge driver. load could speaker motor. MCP622
VDD/2
MCP622
FIGURE 4-15:
H-Bridge Driver.
This circuit automatically makes noise gains (GN) equal, when gains properly, that frequency responses match well magnitude phase). Equation 4-11 shows calculate that both amps have same gains; needs selected first.
EQUATION 4-11:
Equation 4-12 gives resulting common mode differential mode output voltages.
EQUATION 4-12:
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DESIGN AIDS
Microchip provides basic design aids needed MCP621/2/5 family amps.
Analog Demonstration Evaluation Boards
SPICE Macro Model
latest SPICE macro model MCP621/2/5 amps available Microchip site www.microchip.com. This model intended initial design tool that works well amp's linear region operation over temperature range. model file information capabilities. Bench testing very important part design cannot replaced with simulations. Also, simulation results using this macro model need validated comparing them data sheet specifications characteristic curves.
Microchip offers broad spectrum Analog Demonstration Evaluation Boards that designed help customers achieve faster time market. complete listing these boards their corresponding user's guides technical information, visit Microchip site www.microchip.com/analog tools. Some boards that especially useful are: MCP6XXX Amplifier Evaluation Board MCP6XXX Amplifier Evaluation Board MCP6XXX Amplifier Evaluation Board MCP6XXX Amplifier Evaluation Board Active Filter Demo Board 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board, SOIC8EV
FilterLab® Software
Microchip's FilterLab® software innovative software tool that simplifies analog active filter (using amps) design. Available cost from Microchip site www.microchip.com/filterlab, Filter-Lab design tool provides full schematic diagrams filter circuit with component values. also outputs filter circuit SPICE format, which used with macro model simulate actual filter performance.
Application Notes
following Microchip Application Notes available Microchip site www.microchip. com/appnotes recommended supplemental reference resources. ADN003: "Select Right Operational Amplifier your Filtering Circuits", DS21821 AN722: "Operational Amplifier Topologies Specifications", DS00722 AN723: "Operational Amplifier Specifications Applications", DS00723 AN884: "Driving Capacitive Loads With Amps", DS00884 AN990: "Analog Sensor Conditioning Circuits Overview", DS00990 AN1177: Precision Design: Errors", DS01177 AN1228: Precision Design: Random Noise", DS01228 Some these application notes, others, listed design guide: "Signal Chain Design Guide", DS21825
MindiCircuit Designer Simulator
Microchip's MindiCircuit Designer Simulator aids design various circuits useful active filter, amplifier power management applications. free online circuit designer simulator available from Microchip site www.microchip.com/mindi. This interactive circuit designer simulator enables designers quickly generate circuit diagrams, simulate circuits. Circuits developed using Mindi Circuit Designer Simulator downloaded personal computer workstation.
Microchip Advanced Part Selector (MAPS)
MAPS software tool that helps efficiently identify Microchip devices that particular design requirement. Available cost from Microchip website www.microchip.com/maps, MAPS overall selection tool Microchip's product portfolio that includes Analog, Memory, MCUs DSCs. Using this tool, customer define filter sort features parametric search devices export side-by-side technical comparison reports. Helpful links also provided Data sheets, Purchase Sampling Microchip parts.
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PACKAGING INFORMATION
Package Marking Information
8-Lead (3x3) (MCP622)
Device MCP622 Code DABL
Example:
XXXX YYWW
Note: Applies 8-Lead
DABL 0921
8-Lead SOIC (150 mil) (MCP621, MCP622) XXXXXXXX XXXXYYWW
Example:
MCP621E 0921
10-Lead (3x3) (MCP625)
Example:
Code BAFA
XXXX YYWW
Device MCP625
Note: Applies 10-Lead
BAFA 0921
10-Lead MSOP (MCP625)
Example:
XXXXXX YWWNNN
625EUN 921256
Legend: XX.X Note:
Customer-specific information Year code (last digit calendar year) Year code (last digits calendar year) Week code (week January week `01') Alphanumeric traceability code Pb-free JEDEC designator Matte (Sn) This package Pb-free. Pb-free JEDEC designator found outer packaging this package.
event full Microchip part number cannot marked line, will carried over next line, thus limiting number available characters customer-specific information.
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APPENDIX REVISION HISTORY
Revision (June 2009)
Original Release this Document.
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PRODUCT IDENTIFICATION SYSTEM
order obtain information, e.g., pricing delivery, refer factory listed sales office. PART Device Temperature Range
MCP621: MCP621T: MCP622: MCP622T: MCP625: MCP625T:
Package
Examples:
MCP621T-E/SN: Tape Reel, Extended Temperature, SOIC package. Tape Reel, Extended Temperature, package. Tape Reel, Extended Temperature, SOIC package. Tape Reel, Extended Temperature, 10LD package. Tape Reel, Extended Temperature, 10LD MSOP package.
Device:
Single Single (Tape Reel) (SOIC) Dual Dual (Tape Reel) (DFN SOIC) Dual Dual (Tape Reel) (DFN MSOP)
MCP622T-E/MF: MCP622T-E/SN:
MCP625T-E/MF: MCP625T-E/UN:
Temperature Range: Package:
-40°C +125°C
Plastic Dual Flat, Lead (3x3 DFN), 8-lead, 10-lead Plastic Small Outline, (3.90 mm), 8-lead Plastic Micro Small Outline, (MSOP), 10-lead
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Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
Code protection constantly evolving. Microchip committed continuously improving code protection features products. Attempts break Microchip's code protection feature violation Digital Millennium Copyright Act. such acts allow unauthorized access your software other copyrighted work, have right relief under that Act.
Information contained this publication regarding device applications like provided only your convenience superseded updates. your responsibility ensure that your application meets with your specifications. MICROCHIP MAKES REPRESENTATIONS WARRANTIES KIND WHETHER EXPRESS IMPLIED, WRITTEN ORAL, STATUTORY OTHERWISE, RELATED INFORMATION, INCLUDING LIMITED CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY FITNESS PURPOSE. Microchip disclaims liability arising from this information use. Microchip devices life support and/or safety applications entirely buyer's risk, buyer agrees defend, indemnify hold harmless Microchip from damages, claims, suits, expenses resulting from such use. licenses conveyed, implicitly otherwise, under Microchip intellectual property rights.
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Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
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AMERICAS
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ASIA/PACIFIC
India Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4080 India Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 82-2-558-5934 Malaysia Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan Hsin Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
03/26/09
DS22188A-page
2009 Microchip Technology Inc.
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