min. Recording Playback Voice Multi-level analog storage High qua

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

min. Recording Playback Voice Multi-level analog storage High qua

Datasheet Thumbnail

Top Searches for this datasheet

INTEGRATED CIRCUITS INC.-APR6016
min. Recording Playback Voice
Multi-level analog storage High quality audio recording playback Dual mode storage analog and/or digital Data Eliminates need separate digital memory Advanced, non-volatile Flash memory technology battery backup required interface Allows commercial micro-controller control device Programmable Sampling Clock Allows user choose quality duration leve Single power supply power consumption Playback operating current: 15mA typical Standby current: maximum Automatic power-down Multiple package options available CSP, TSOP, PDIP, Bare On-board clock prescaler Eliminates need external clock dividers Automatic squelch circuit Reduces background noise during quiet passages
General Description
APR6016 offers non-volatile storage voice and/or data advanced Multi-Level Flash memory. minutes audio recording playback accommodated. maximum bits digital data stored. APR6016 devices cascaded longer duration recording greater digital storage. Device control accomplished through industry standard interface that allows microcontroller manage message recording playback. This flexible arrangement allows widest variety messaging options. APR6016 ideal cellular cordless phones, telephone answering devices, personal digital assistants, personal voice ecorders,and voice pagers. APLUS achieves this high level storage capability using proprietary analog multi-level storage technology implemented advanced on-volatile Flash memory process. Each memory cell Typically store voltage levels. This allows APR6016 device reproduce audio signals their natural form,eliminating need encoding compression,which introduce distortion.
Figure APR6016 Pinout Diagrams
http://www.aplusinc.com.tw
886-2-2782-9266
ver1.2
INTEGRATED CIRCUITS INC.-APR6016
Functional Description
EXTCLK allows external sampling clock. This input accept wide range frequencies depending divider ratio programmed into divider that follows clock. Alternatively, programmable internal oscillator used supply sampling clock. following both signals automatically selects EXTCLK signal clock present, otherwise internal oscillator source chosen. Detailed information program divider internal oscillator found explanation PWRUP command, which appears OpCode Command Description section. Guidance choose appropriate sample clock frequency found Sampling Rate Voice Quality section. audio signal containing content wish record should into differential inputs ANAIN-,and ANAIN+. After pre-amplification signal routed into anti-aliasing filter. anti-aliasing filter automatically adapts response based sample rate being used. external anti-aliasing filter therefore required. After passing through anti-alias filter, signal into sample hold circuit which works conjunction with Analog Write Circuit store each analog sample flash memory cell. When read operation desired Analog Read Circuit extracts analog data from memory array feeds signal Internal Pass Filter. pass filter converts individual samples into continuous output. output signal then goes squelch control circuit differential output driver. differential output driver feeds ANAOUT+ ANAOUT- pins. Both differential output pins swing around 1.23V potential.The squelch control circuit automatically reduces output signal during quiet passages. copy squelch control signal present SQLOUT facilitate reducing gain external amplifier well. more information, refer Squelch section. After passing through squelch circuit output signal goes output amplifier. output amplifier drives single ended output AUDOUT pin. single ended output swings around 1.23V potential.All control hand shaking signals routed Master Control Circuit. This circuit decodes signals generates internal control signals. also contains status register used examining current status APR6016.
Figure APR6016 Block Diagram
http://www.aplusinc.com.tw
886-2-2782-9266
ver1.2
INTEGRATED CIRCUITS INC.-APR6016
Memory Organization
APR6016 memory array organized allow greatest flexibility message management digital storage. smallest addressable memory unit called "sector". APR6016 contains 1280 sectors.
Interface
memory management handled external host processor. host processor communicates with APR6016 through simple Serial Peripheral Interface (SPI) Port. port little three wires many seven depending amount control necessary. This section will describe manage memory using APR6016 Port associated OpCode commands. This topic broken down into following sections: Sending Commands Device OpCode Command Description Receiving Device Information Current Device Status (CDS) Reading Silicon Identification (SID) Writing Digital Data Reading Digital Data Recording Audio Data Playing Back Audio Data Handshaking Signals
Figure Memory Map.
Sending Commands Device
Sectors through 1279 used analog storage.During audio recording memory cell used sample clock cycle. When recording stopped data (EOD) programmed into memory. This prevents playback silence when partial sectors used. Unused memory that exists between sector cannot used.Sectors through tested guaranteed digital storage. Other sectors, with exception sector 1279, store data have been tested, thus guaranteed provide 100% good bits.This managed with error correction forward check-before-store methods. Once write cycle initiated previously written data chosen sector lost. Mixing audio signals digital data within same sector possible. Note. There total 15bits reserved addressing.The APR6016 only requires bits. additional bits used larger devices within later APRXXfamily. This section describes process sending OpCodes APR6016. OpCodes sent same with exception DIG_ WRITE DIG_READ commands DIG_ WRITE DIG_READ commands described Writing Digital Data Reading Digital Data sections that follow. minimum configuration needed send commands uses /CS, SCLK pins. device will accept inputs whenever low. OpCode commands clocked rising edge clock. Figure shows timing diagram shifting OpCode commands into device. Figure description OpCode stream. must wait command finish executing before sending command. This accomplished monitoring /BUSY pin. substitute monitoring busy inserting fixed delay between commands. required delay specified Tnext1,Tnext2, Tnext3 Tnext4. Figure shows timing diagram sending consecutive commands. Table describes which Tnext specification use.
http://www.aplusinc.com.tw
886-2-2782-9266
ver1.2
INTEGRATED CIRCUITS INC.-APR6016
http://www.aplusinc.com.tw
886-2-2782-9266
ver1.2
INTEGRATED CIRCUITS INC.-APR6016
Table Sequential Command Timing
Command Next command Timing Symbol
PWRUP STOP_PWDN SET_REC SET_PLAY PLAY SET_FWD DIG_WRITE DIG_READ DIG_ERASE STOP
Command Command PWRUP STOP, STOP_PWDN, SET_REC, REC, STOP, STOP_PWDN, SET_FWD, FWD, SET_PLAY, PLAY, SET_FWD, FWD, STOP, STOP_PWDN Digital Command, STOP, STOP_PWDN
Note: partial DIG_READ Tnext2 measured from extra clock that follows rise /CS, from rise
Tnext1 Tnext2 Tnext2 Within Time
Tnext3 Tnext4
Command
OpCode Command Description
Designers have access total OpCodes. These OpCodes listed Table name OpCode appears left hand column. following columns represent actual binary information contained data stream. Some commands have limits which command follow them. These limits shown "Allowable Follow Commands" column. last column summarizes each command. Combinations OpCodes used accommodate almost memory management scheme.
Table APR6016 Operational Codes
Instruction OpCode Name (5bit)
[op4-op0]
Opcode Parameters (15bit)
[Address Address LSB] [Address Address
Allowable Follow
Commands
Summary
SET_FWD PWPUP STOP
[00000] [00001] [00010] [00011]
[Don't care] [Don't care] Sector Address [A14 [Don't care] [A14-A10]: zeros
Commands Commands SET_FWD, FWD, STOP, STOP_PWDN SET_FWD,
STOP,STOP_PWDN
Operation Causes silicon read. Starts fast forward operation from sector address specified. Starts fast forward operation from current sector address. Resets device initial conditions. Sets sample frequency divider ratios. Stops current operation. Stops current operation. Causes device enter power down mode.
[A9-A2]:EXTCLK divider ratio [00100] [Al-A0]: Sample Rate Frequency
Commands Commands PWRUP
[00110]
[Don't care] [Don't care]
STOP_PWDN [00111]
http://www.aplusinc.com.tw
886-2-2782-9266
ver1.2
INTEGRATED CIRCUITS INC.-APR6016
Instruction OpCode Name (5bit) SET_REC
[01000]
Opcode Parameters (15bit)
Sector Address [A14
Allowable Follow
Commands STOP, STOP_PWDN
SET_REC, REC, STOP, STOP_PWDN, SET_REC, REC,
Summary
Starts record operation from sector address specified. Starts record operation from current sector address. Erases data contained specified sector. must erase sector before recording voice signals into must erase sector before storing digital data This command writes data bits -D3003 starting specified address. 3004 bits must written. This command reads data bits D3003 starting specified address
[01001]
[Don't care]
DIG_ERASE [01010]
Sector Address [A14
Commands
DIG_ WRITE [01011]
[A14 A0][XXXX] D3004][XXXX]
Commands
DIG_READ
[01111]
Sector Address [A14 Commands
PLAY
[01100]
Sector Address [A14
PLAY
[01101]
[Don't care]
STOP, STOP_PWDN, Starts play operation from SET_FWD, FWD, current sector address specified. SET_PLAY, PLAY, STOP, STOP_PWDN, Starts play operation from SET_FWD, FWD, current sector address. SET_PLAY, PLAY,
command performs operation device.It most often used when reading current Device status. more information reading device Status Current Device Status section. operation instructs device return contents silicon register. more Information Reading section. SET_FWD command instructs device fast forward from beginning sector specified OpCode parameter field.The device will fast forward until either sector reached. forthcoming command been received when sector reached,the device will loop back beginning same sector begin same process again. found device will stop generate interrupt /INT pin. output amplifiers muted during this operation.
command instructs device fast forward from start current sector next marker. marker found within current sector device will increment next sequential sector continue looking. device will continue fast forward this manner until either reached, command sent, memory array reached. When reached device will stop generate interrupt /INT pin. output amplifiers muted during this operation. PWRUP command causes device enter power mode internal clock frequency EXTCLK divider ratio. select Internal oscillator frequency bits according following binary values: Sample rate
http://www.aplusinc.com.tw
886-2-2782-9266
ver1.2
INTEGRATED CIRCUITS INC.-APR6016
using external sample clock signal must also EXTCLK divider ratio. This divider ratio equal where integer between 256, excluding 2.The value should selected satisfy following equation closely possible:
EXTCLK freq =(N)*(128)*(selected sampling frequency)
DIG_ERASE command erases data Contained sector specified. Erase should done before recording voice signals into sector. Erase must done before storing digital data sector.
Example: Suppose that sampling desired. Assume that frequency signal present EXTCLK 8MHz.
Rounding Code Parameter stream, composed Bits A2][A1 A0], therefore becomes binary [00001000][10]. STOP Command causes device stop current operation. STOP_PWDN command causes device Stop current command enter power down mode.During power down device consumes significantly less power. PWRUP command must used force device into power mode before commands executed. SET_REC command instructs device Begin recording sector address specified. device will continue record until current sector reached. forthcoming command been received when sector reached device will loop back beginning same sector overwrite previously recorded material. next command another SET_REC command device will execute command immediately following current sector that audio information lost. more information section entitled Recording Audio Data. command instructs device begin recording current sector. command received before device reaches sector device will automatically increment next sequential sector continue recording. device will continue record this manner until memory exhausted STOP STOP_PWDN command received. more information section entitled Recording Audio Data.
DIG_WRITE command stores bits digital Data specified sector. bits must written; partial usage sector possible. memory acts FIFO, first data shifted will first data shifted out. sector must erased using DIG_ERASE command EFORE data written sector. more information storing digital data,see section entitled Writing Digital Data. DIG_READ command instructs device retrieve digital data that previously written specified sector. first shifted first that written. last shifted last that written. more information reading digital data section entitled Reading Digital Data. SET_PLAY command instructs device Begin playback specified sector. Forthcoming command received, encountered, before sector reached device will loop back beginning same sector continue playback with noticeable audio output. next command another SET_PLAY PLAYcommand device will execute commandimmediately following current sector sothat playback present. more information section entitled Playing Back Audio Data. PLAY command instructs device begin playback current sector. forthcoming command received, encountered, before device reaches sector device will automatically increment next sequential sector continue playing. device will continue play this manner until memory exhausted STOP STOP_PWDN command received. more information section entitled Playing Back Audio Data.
http://www.aplusinc.com.tw
886-2-2782-9266
ver1.2
INTEGRATED CIRCUITS INC.-APR6016
Receiving Device Information
device communicates data user Shifting data pin. device will shift data according timing parameters given Figure 7.The device shift three different types data streams: Device status, Silicon user stored data.Device status silicon described next sections. Retrieval user data described Reading Digital Data section
Current Device Status (CDS)
described previous section, three different types data streams shifted data shifted pin. these steams current device status. will shifted unless previous command command. Figure shows format stream. first shifted out, Overflow flag. Overflow flag binary attempt made record beyond available memory. Overflow flag overflow occurred. This flag cleared
after been read. Data flag. flag when device stops playing, fast forwarding result memory. flag cleared after been read.The Illegal Address flag. Illegal Address flag whenever illegal address sent device. battery (Lbat) flag. Thisflag when device senses supply voltage below specification. used should ignored. last fifteen bits represent address current last active sector.
http://www.aplusinc.com.tw
886-2-2782-9266
ver1.2
INTEGRATED CIRCUITS INC.-APR6016
Reading
Each device APRXX series family contains embedded Silicon Identification (SID). read host processor identify which family/family member being used. Reading device requires issuing OpCode commands; command followed other command,usually command. device will clock data command that follows command clocked Figure diagram that describes process necessary reading information.
information follows format given Figure first shifted Overflow bit. Overflow binary attempt made record beyond available memory. Overflow overflow occurred. This cleared after been read. Data (EOD) bit. when device stops playing fast-forwarding result memory. cleared after been read. Illegal Address bit. Illegal Address
whenever illegal address sent device. LBAT bit. This when device senses supply voltage below specification. following five bits represent product family. APRXX product family code binary 01000 shown Figure next four bits represent device code. APR6016 device code binary 0010 shown Figure last seven bits random data should ignored.
http://www.aplusinc.com.tw
886-2-2782-9266
ver1.2
INTEGRATED CIRCUITS INC.-APR6016
Writing Digital Data
Digital data written into device using DIG_WRITE command. mixing analog data digital data within sector possible. Sectors through tested guaranteed Immediately following four buffer bits should data that wish store. 3004 bits must stored.Four additional buffer bits must clocked into device following stored data. These bits will stored array must considered don't care bits.Ending digital write command early will permanently damage sector. will clock normal followed five don't care bits, copy 3004 data bits, finally three don't care bits. Figure shows timing diagram, which describes digital storage process. timing with exception TpSCLK should adhere specifications given Figure Figure TpSCLK specification replaced DTpSCLK when storing digital data.
digital storage.Other sectors, with exception sector 1279, store data have been tested thus guaranteed provide 100% good bits. This managed with error correction forward check-before-store methods. Issuing
DIG_ERASE command sector 1279 will cause data throughout sectors lost. sector must erased, using DIG_ERASE command, before digital data written This requirement necessary whether analog data digital data previously stored sector. sector should erased more than once between analog digital write operations. Executing multiple erase operations sector will permanently damage sector. sector reallocated either analog storage digital storage time. process storing digital data begins sending DIG_WRITE command. DIG_WRITE command followed immediately four buffer bits. These bits will stored array must considered don't care bits.
Note: DIG_ERASE command should used before storing analog data. device will perform internal erase before analog storage. Figure does show DIG_ERASE command,which must executed sector before digital data stored.
http://www.aplusinc.com.tw
886-2-2782-9266
ver1.2
INTEGRATED CIRCUITS INC.-APR6016
Reading Digital Data
Digital data read from device using DIG_READ command. read data must send DIG_READ command immediately followed 3012 don't care bits during same cycle. data previously stored specified sector will begin appear after current device status four buffer bits. next 3004 bits previously stored data. first shifted first that written. last shifted last that written. There four random don't care bits following 3004 bits user data. incomplete read sector allowed. incomplete read defined read with less than 3032 clock cycles. incomplete read cycles require extra SCLK cycle after signal returns high. Figure shows timing diagram, which describes entire process complete sector read. timing with exception TpSCLK should adhere specifications given Figure Figure TpSCLK specification replaced pSCLK when reading digital data.
http://www.aplusinc.com.tw
886-2-2782-9266
ver1.2
INTEGRATED CIRCUITS INC.-APR6016
Recording Audio Data
When SET_REC command issued device will begin sampling storing data present ANAIN+ ANAIN- specified sector. After half sector used will drop indicate that command accepted. device will accept commands long remains low. command received after return high will queued executed during cycle. Figure shows typical timing diagram OpCode sequence recording operation. this example SET_REC command begins recording specified memory location after Tarac time passed. Some time later going edge alerts host processor that first sector nearly full. host processor responds issuing command before returns high. command instructs APR6016 continue recording sector immediately following current sector. When first sector full device automatically jumps next sector returns signal high state indicate that second sector being used. this point host processor decides issue STOP command during next cycle. device follows STOP command terminates recording after TSarec. /BUSY indicates when actual recording taking place.
http://www.aplusinc.com.tw
886-2-2782-9266
ver1.2
INTEGRATED CIRCUITS INC.-APR6016
Playing Back Audio Data
When SET_PLAY PLAY command issued device will begin sampling data specified sector produce resultant output AUDOUT,ANAOUT-, ANAOUT+ pins. After half sector used will drop indicate that command accepted. device will accept commands long remains low. command received after returns high will queued executed during next cycle. Figure shows typical timing diagram OpCode sequence playback operation. SET_PLAY command begins playback specified memory location after Taplay time passed. Some time later going edge alerts host processor that half first sector been played back. host processor responds issuing PLAY command during time. PLAY command instructs APR6016 continue playback sector immediately following current sector. When first sector been played back device jumps next sector returns signal high state indicate that second sector being played. this point host processor decides issue STOP command during next available time. device follows STOP command terminates playback after TSaplay /BUSY indicates when actual playback taking place.
Handshaking signals
Several signals included device that allow handshaking. These signals simplify message management significantly depending message management scheme used.The /INT signal used generate interrupts processor when attention required APR6016 This normally high goes when interrupt requested. interrupt generated
whenever Overflow occurs. interrupt also generated after PWRUP command battery sensed. signal used determine when device nearing current memory segment during record, play forward operation. signal normally high state. signal goes after half currently active segment been played recorded.
http://www.aplusinc.com.tw
886-2-2782-9266
ver1.2
INTEGRATED CIRCUITS INC.-APR6016
signal returns high state after entire segment been played recorded. microprocessor should sense edge signal indicator that next segment needs selected, before signal returns high. Failing specify next command before current segment exhausted (either during recording playback) will result noticeable during playback. /BUSY indicates when device performing either play, record fast-forward function. host microprocessor monitor busy confirm status these commands. Busy normally high goes while device busy. time governed length recording playback specified user. internal clock divider provided that external clock signals divided down desired sampling rate. This allows high frequency signals into EXTCLK pin. Using this feature simplifies designs allowing clock already present system, opposed having generate externally divide down custom clock. Details programming clock divider described interface section under PWRUP paragraph. default power condition APR6016 internal oscillator sampling frequency 6.4kHz.
Storage Technology
APR6016 stores voice signals sampling incoming voice data storing sampled signals directly into FLASH memory cells. Each FLASH cell support voltage ranges from levels. These discrete voltage levels equivalent eight (28=256) binary encoded values. During playback stored signals retrieved from memory, smoothed form continuous signal finally amplified before being external speaker amplifier.
Sampling Rate Voice Quality
Nyquist Sampling Theorem requires that highest frequency component sampling system accommodate without introduction aliasing errors equal half sampling frequency. APR6016 automatically filters input, based selected sampling frequency, meet this requirement. Higher sampling rates increase recording bandwidth,and hence voice quality, also more memory cells same amount recording time.The APR6016 accommodates sampling rates high 8kHz.Lower sampling rates less memory cells effectively increase duration capabilities device, also reduce recording bandwidth.The APR6016 allows sampling rates 4kHz. Designers thus control quality/duration trade-off controlling sampling frequency. Sampling frequency controlled PWRUP command. This command change sampling frequency regardless whether internal oscillator used external clock used. APR6016 derives sampling clock from sources: internal external. clocking signal present EXTCLK input device would automatically this signal sampling clock source. input present EXTCLK input device automatically defaults internal clock source. When EXTCLK used should tied GND.
Squelch
APR6016 equipped with internal squelch feature. Squelch circuit automatically attenuates output signal during quiet passages playback material. Muting output signal during quiet passages help eliminate background noise.Background noise enter system number ways including: present original signal, natural noise present some power amplifier designs, induced through poorly filtered power supply.The response time squelch circuit controlled time constant capacitor connected SQLCAP pin. recommended value this capacitor squelch feature disabled connection SQLCAP VCC.The active output /SQL goes whenever internal squelch activates. This signal used squelch output power amplifier. Squelching output amplifier results further reduction noise;especially when power amplifier high gain loud volumes.
http://www.aplusinc.com.tw
886-2-2782-9266
ver1.2
INTEGRATED CIRCUITS INC.-APR6016
Sample Application
Figure shows sample application utilizing generic microcontroller interface message management. microcontroller uses three general-purpose inputs play, record skip buttons. Five general purpose signals utilized interface. /RESET /BUSY signal used this design. output signal must amplified order drive Speaker. Several vendors supply integrated speaker amplifiers that used this purpose. microphone amplifier recommended. Both blocks optional. Several vendors supply integrated microphone/AGC amplifiers that used this purpose. Note that circuit simplified using SQLCAP signal peak detector Signal.
Figure Sample Schematic using PDIP package
http://www.aplusinc.com.tw
886-2-2782-9266
ver1.2
INTEGRATED CIRCUITS INC.-APR6016
Descriptions
Table three shows descriptions APR6016 device. pins listed numerical order with exception VCC, pins, which listed Table.
Table APR6016 Number Description Functionality Name (Die) Sector Address Control Output: This active output indicates when device nearing current segment. Interrupt Output: This active open drain output goes whenever device reaches message device overflows.When /INT connected interrupt input host microcontroller this output used implement powerful message management options. External Clock Input: This input used feed device external EXTCLK sample clock instead using internal sampling clock. This should connected VSSA when use. Clock Input: Data clocked into device through upon SCLK rising edge this clock. Data clocked part through falling edge Chip Select Input: This active input selects device currently active slave interface. When this high device tri-states ignores data pin. Data Input: input receives digital data input from bus. Data clocked rising edge SCLK input. Data Output: Data available after falling edge SCLK input. Negative Audio Output: This negative audio output playback prerecorded messages. This output usually negative input ANAOUTdifferential input power amplifier. power amplifier drives external speaker. Positive Audio Output: This positive audio output playback prerecorded messages. This output usually positive input ANAOUT+ differential input power amplifier. power amplifier drives external speaker. Reset Input: This active input clears internal address registers /RESET restores device power defaults. Single Ended Audio Output: This audio output playback AUDOUT pre-recorded messages. This output usually input power amplifier driving external speaker. Squelch Capacitor I/O: This controls attack time squelch circuitry. Connect through capacitor enable SQLCAP squelch feature. capacitor's time constant will affect quickly squelch circuitry reacts. Connect this VCCA disable squelch feature. Squelch Output: This active output indicates when internal squelch circuitry activated. This signal used automatically squelch /SQLOUT external power amplifier. Squelching external power amplifier result even greater reduction background noise. Inverting Analog Input: This input inverting input analog signal that user wishes record. When device used differential input configuration this should receive peak-to-peak input coupled ANAINthrough capacitor. When device used single ended input onfiguration this input should tied VSSA through capacitor Non-Inverting Analog Input: This input non-inverting input analog signal that user wishes record. When device used differential input configuration this should receive peak-to-peak ANAIN+ input coupled through capacitor. When device used single ended input configuration this should receive peak-to-peak input coupled through 0.1uF capacitor.
http://www.aplusinc.com.tw
886-2-2782-9266
ver1.2
INTEGRATED CIRCUITS INC.-APR6016
Name (Die)
Functionality
/BUSY
VCCD
VCCA
VSSA VSSD
12,23 5,6,7, 10,19, 20,22
Busy Output: This active output during either record playback fast forward operation. tri-stated otherwise. This connected indicate playback/record operation user. This also connected external microcontroller indication status playback record forward digital operation. Digital Power Supply: This connection supplies power chip digital circuitry. This should connected power plane through via. 31,32,33 This should also connected bypass close possible. Analog Power Supply: This connection supplies power on-chip analog circuitry. This should connected power plane through via. 19,20 This should also connected bypass close possible 11,12,13, Analog Ground: These pins should connected ground plane through 24,25 via. connection should made close possible. Digital Ground: This should connected ground plane through via. connection should made close possible. Connect: These pins should connected anything board. 6,7,21, Connection these pins signal result incorrect 27,28 device behavior cause damage device.
Electrical Characteristics
following tables list Absolute Maximum Ratings,recommended Characteristics, recommend Characteristics APR6016 device. Operation device these other conditions above those specified recommended Characteristics recommended Characteristics this specification implied. Maximum condition extended periods affect reliability.
Absolute Maximum Ratings
Stresses greater than those listed Table cause permanent damage device. These specifications represent stress rating only.
Table Absolute Maximum Ratings.
Item
Power Supply voltage Input Voltage Storage Temperature Temperature Under Bias Lead Temperature
Symbol
TSTG
Condition
25°C 25°C Device
Unit
http://www.aplusinc.com.tw
886-2-2782-9266
ver1.2
INTEGRATED CIRCUITS INC.-APR6016
Table Characteristics
Item
Operating Voltage Operating Temperature Input High Voltage Input Voltage Output High Voltage Output Voltage Input Leakage Current Input Leakage Current Output Tri-state Leakage Current Operating Current Consumption Standby Current Consumption
Symbol
VCCA, VCCD
Condition
Unit
ICCS
2.7V 3.3V 2.7V IOH=-1.6mA 2.7V IOL=1.0mA 3.3V VIH=VCC 3.3V VIL= 3.3V VOUT=VCC VOUT=VSS 3.3V Recording Playback Idle 3.3V After
0.3V VCCD 0.5V
Table Characteristics
Item
ANAIN+ ANAINinput voltage ANAIN+ input resistance ANAIN+/ANAIN- Gain ANAOUT output voltage Total Harmonic Distortion ready fall /RESET time Rise /RESET fall fall clock edge Data set-up time Period clock data hold time dock time clock high time Clock rising edge Fall output Fall SCLK data valid Rise high Period clock Digital read write First SET_REC command start recording
Symbol
RANAIN GANAIN VANAOUT Tpwrup TloRST TRdone TfCS TsuDI TpSCLK ThDI TloSCLK ThiSCLK TrCS SCLK TfSCLK ThzDO DTpSCLK
Condition
Unit
mVP-P mVp-p
1kHz 45mVP-P. input min. specification
1000 1000
Tarec
@4kHz Internal sample clock @8kHz Internal sample clock External sample clock equation1 @4kHz Internal sample clock @8kHz Internal sample clock equation2 External sample clock
http://www.aplusinc.com.tw
886-2-2782-9266
ver1.2
INTEGRATED CIRCUITS INC.-APR6016
Item
Rise after STOP Command recording First SET_PLAY command audio output STOP after SET_PLAY PLAY audio output
Symbol
TSarec
Condition
@4kHz Internal sample clock @8kHz Internal sample clock External sample clock @4kHz Internal sample clock @8kHz Internal sample clock External sample clock @4kHz Internal sample clock @8kHz Internal sample clock External sample clock REC, PLAY @4kHz REC, PLAY @8kHz REC, PLAY @EXTCLK @4kHz @8kHz @EXTCLK REC, PLAY @4kHz REC, PLAY @8kHz REC, PLAY @EXTCLK @4kHz @8kHz @EXTCLK
equation2 equation2 equation2 equation3 equation4 equation5 0.25 0.125
equation
Unit
Taplay
TSaplay
period
TpSAC
time
TloSAC
Figure Table Figure Table
Tnext1 Tnext2 @4kHz Internal sample clock @8kHz Internal sample clock External sample clock Previous command SET_REC, REC, SET_PLAY, PLAY @4kHz Internal sample clock @8kHz Internal sample clock External sample clock Previous command SET_FWD, @4kHz Internal sample clock @8kHz Internal sample clock External sample clock Previous command Others @4kHz Internal sample clock @8kHz Internal sample clock External sample clock
equation
Figure Table
Tnext3
Figure Table
Tnext4
1.25 0.625
http://www.aplusinc.com.tw
886-2-2782-9266
ver1.2
INTEGRATED CIRCUITS INC.-APR6016
http://www.aplusinc.com.tw
886-2-2782-9266
ver1.2
INTEGRATED CIRCUITS INC.-APR6016
http://www.aplusinc.com.tw
886-2-2782-9266
ver1.2
INTEGRATED CIRCUITS INC.-APR6016
http://www.aplusinc.com.tw
886-2-2782-9266
ver1.2
INTEGRATED CIRCUITS INC.-APR6016
REVISION HISTORY Date MAY. 30.2008 Revision Description Figure-8 Format stream,the change MSB, change Page
http://www.aplusinc.com.tw
886-2-2782-9266
ver1.2

min. Recording Playback Voice Multi-level analog storage High qua

Top Searches for this datasheet

Other recent searches