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Very Power, 16-bit 20-Bit Converters Very Power, 16-Bit and20-bit Conv


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CS5505/6/7/8 CS5505/6/7/8
Very Power, 16-bit 20-Bit Converters Very Power, 16-Bit and20-bit Converters
Very
Description
CS5505/6/7/8 family power CMOS converters which ideal measuring low-frequency signals representing physical, chemical, biological processes. 5507/8 have single-channel differential analog reference inputs while CS5505/6 have four pseudo-differential analog input channels. CS5505/7 have 16-bit output word. CS5506/8 have 20-bit output word.The CS5505/6/7/8 sample upon command Sps. on-chip digital filter offers superior line rejection when device operated from 32.768 clock (output word rate Sps). 5505/6/7/8 include on-chip self-calibration circuitry which initiated time temperature ensure minimum offset full-scale errors. CS5505/6/7/8 serial port offers general-purpose modes direct terface shift egisters synchronous serial ports industry-standard microcontrollers. ORDERING INFORMATION page
Power Consumption
Single supply operation: Dual supply operation:
Offers
superior performance VFCs multi-slope integrating ADCs Differential Inputs
Single-channel (CS5507/8) Four-channel (CS5505/6) pseudo-differential versions
Digital Interface Linearity Error:
±0.0015% (16-bit CS5505/7) ±0.0007% (20-bit CS5506/8)
Either
update rates Flexible Serial Port Pin-Selectable Unipolar/Bipolar Ranges
Output
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06/3 %383
Cirrus Logic, Inc. Crystal Semiconductor Products Division http://www.cirrus.com P.O. 17847, Austin, Texas 78760 (512) 7222 FAX: (512) 7581 http://www.crystal.com
Copyright Cirrus Copyright Cirrus Logic, Inc. 2009 Logic, Inc. 1997 (All Rights Reserved) (All Rights Reserved)
DS59F4 DS59F7
CS5505/6/7/8
CS5505/6/7/8
ANALOG CHARACTERISTICS TMAX; 10%; 10%; 3.3V VREF+ 2.5V(external); VREF- 32.768kHz; Bipolar Mode; Rsource with 10nF AGND AIN; Anal input channel AIN1+; AIN- AGND; unless otherwise specified.) (Notes
CS5505/7-A Parameter* Specified Temperature Range (Note (Note (Note (Note (Note (Note 0.0015 ±0.25 ±0.25 ±0.5 ±0.5 ±0.5 ±0.25 ±0.25 0.16 0.003 ±0.5 CS5507-S +125 0.0015 ±0.25 ±0.5 ±0.5 ±0.5 0.16 0.003 ±0.5 Units ±%FS LSB16 LSB16 LSB16 LSB16 LSB16 LSB16 LSB16 LSBrms16
Accuracy
Linearity Error Differential Nonlinearity Full Scale Error Full Scale Drift Unipolar Offset Unipolar Offset Drift Bipolar Offset Bipolar Offset Drift Noise (Referred Output)
Notes: presents very high input resistance minor dynamic load which scales master clock frequency. Both sour resistance shunt capacitance therefore critical determining CS5505/6/7/8's source impedance requirements. more information refer text section Analog Input Impedance Consi derations. Specifications guaranteed desi characterization and/or test. Applies after calibration temperature interest. Total drift over specified temperature range since calibration power-up 25°C. Recalibration temperature will remove these errors.
LSB's 0.26 0.50 1.00 2.00 4.00
Unipolar Mode 0.0004 0.0008 0.0015 0.0030 0.0061
LSB's 0.13 0.26 0.50 1.00 2.00 VREF 2.5V
Bipolar Mode 0.0002 0.0004 0.0008 0.0015 0.0030
CS5505/7; 16-Bit Unit Conversion Factors
Refer Specification Definitions immediately following Description Section. Specifications subject change without notice. DS59F7
CS5505/6/7/8
CS5505/6/7/8
ANALOG CHARACTERISTICS TMAX; 10%; 10%; 3.3V VREF+ 2.5V (external); VREF- fCLK 32.768kHz Bipolar Mode; Rsource with 10nF AGND AIN; Analog input channel AIN1+; AIN- AGND; unless otherwise specified.) (Notes
CS5506/8-B Parameter* Specified Temperature Range (Note (Note (Note (Note (Note (Note 0.0007 0.0015 CS5508-S +125 0.0015 0.003 LSB20 LSB20 LSB20 LSB20 LSB20 LSB20 LSBrms20 Units ±%FS Bits
Accuracy
Linearity Error Differential Nonlinearity Missing Codes) Full Scale Error Full Scale Drift Unipolar Offset Unipolar Offset Drift Bipolar Offset Bipolar Offset Drift Noise (Referred Output)
0.596 1.192 2.384 4.768 9.537
LSB's 0.25 0.50 1.00 2.00 4.00
Unipolar Mode 0.0000238 0.0000477 0.0000954 0.0001907 0.0003814
LSB's 0.24 0.13 0.47 0.26 0.95 0.50 1.91 1.00 3.81 2.00 VREF 2.5V
Bipolar Mode 0.0000119 0.0000238 0.0000477 0.0000954 0.0001907
0.12 0.24 0.47 0.95 1.91
CS5506/8; 20-Bit Unit Conversion Factors
DYNAMIC CHARACTERISTICS
Parameter Modulator Sampling Frequency Output Update Rate (CONV Filter Corner Frequency Settling Time Step) Symbol fout f-3dB Ratio fclk/2 fclk/1622 fclk/1928 1/fout Units
DS59F7
CS5505/6/7/8
CS5505/6/7/8
ANALOG CHARACTERISTICS TMAX;
CS5505/7 CS5506/8 Parameter* Specified Temperature Range +2.5 ±2.5 (Note (VA+)-2.5
10%; 10%; 3.3V VREF+ 2.5V (external); VREF- fCLK 32.768kHz Bipolar Mode; source with 10nF AGND AIN; Analog input channel AIN1+; AIN- AGND; unless otherwise specified.) (Notes CS5507/8-S +125 +2.5 ±2.5 (VA+)-2.5 Units Volts Volts Volts ppm/°C mV/Volt µVp-p
Analog Input
Analog Input Range: (VAIN+)-(VAIN-) Unipolar polar (Note
Common Mode Rejection: (Note Channel Isolation Input Capacitance Bias Current
Voltage Reference (Output)
VREFOUT Voltage VREFOUT Voltage Tolerance VREFOUT Voltage Temperature Coefficient VREFOUT Line Regulation VREFOUT Output Voltage Noise VREFOUT: Sour Current Sink Current
Power Supplies
Power Supply Currents: ITotal IAnalog IDigital
Power Dissipation:
(Note SLEEP inactive SLEEP active
Power Supply Rejection: Positive Supplies Negative Supplies
Notes: Common mode voltage value long AIN+ AIN- remain within supply voltages. 32.768 kHz. Guaranteed design characterization. outputs unloaded. inputs CMOS levels. SLEEP mode controlled M/SLP pin. SLEEP active M/SLP (VD+)/2 input level.
DS59F7
CS5505/6/7/8
CS5505/6/7/8
DIGITAL CHARACTERISTICS TMAX;
Parameter High-Level Input Voltage: M/SLP Pins Except M/SLP M/SLP Pins Except M/SLP (Note (Note Iout
VA+VD+ 10%; VA-= 10%; DGND measurements below performed under static conditions. (Note Symbol VSLP Cout 0.9VD+ 0.45VD+ (VD+)-1.0 0.5VD+ 0.1VD+ 0.55VD+ Units
Low-Level Input Voltage:
M/SLP SLEEP Active Threshold High-Level Output Voltage Level Output tage Input Leakage Current 3-State Leakage Current Digital Output Capacitance
Notes: Under normal operation this should tied DGND. Anytime voltage M/SLP enters SLEEP active threshold range device will enter power down condition. Returning active state equires elapse power-on reset period, oscillator start-up, elapse wake-up period. Iout -100 This guarantees ability drive load. (VOH 2.4V µA).
3.3V DIGITAL CHARACTERISTICS
Parameter High-Level Input Voltage:
TMAX; 10%; 3.3V VA-= 10%; DGND measurements below performed under static conditions. (Note Symbol
0.7VD+ 0.9VD+ 0.6VD+ (VD+)-0.3
0.3VD+ 0.1VD+ 0.16VD+
Units
M/SLP Pins Except M/SLP M/SLP Pins Except M/SLP (Note Iout -400 Iout
Low-Level Input Voltage:
VSLP Cout
M/SLP SLEEP Active Threshold High-Level Output Voltage Level Output tage Input Leakage Current 3-State Leakage Current Digital Output Capacitance
0.43VD+ 0.45VD+ 0.47VD+
DS59F7
CS5505/6/7/8
CS5505/6/7/8
SWITCHING CHARACTERISTICS TMAX;
Parameter Master Clock Frequency: Internal Oscillator: External Clock: Master Clock Duty Cycle Rise Times: Fall Times: Digital Input Digital Output Digital Input Digital Output (Note (Note trise tfall -A,B Symbol fclk
VA+, 10%; 10%; Input Levels: Logic Logic VD+; pF.) (Note 30.0 30.0 82/fclk 32.768 32.768 1800/fclk 3246/fclk 1624/fclk 53.0 34.0 2/fclk+200 2/fclk+200 Units
Start-Up
Power-On Reset Period Oscillator Start-up Time Wake-up Period XTAL=32.768 (Note (Note (Note (Note tres tosu twup tccw tscl tcal tsac thca tcpw tscn tbus tbuh tcon BP/UP stable prior DRDY ling BP/UP stable after DRDY (Note
Calibration
CONV Pulse Width (CAL CONV High Start Calibration Start Calibration Calibration
Conversion
Time Hold Time CONV Pulse Width CONV High Start Conversion Time Hold Time CONV High after CONV High
Start Conversion Conversion
Notes: Specified using points waveform interest. internal power-on-reset activated whenever power applied device, when coming SLEEP state. Oscillator start-up time with crystal parameters. This specification does apply when using external clock source. wake-up period begins once oscillator starts; when using external clk, after power-on reset time elapses. Calibration also initiated pulsing high while CONV=1. Conversion time will 1622/fclk CONV remains high continuously.
DS59F7
CS5505/6/7/8
CS5505/6/7/8
10%; 3.3V 10%; Input Levels: Logic Logic pF.) (Note Parameter Master Clock Frequency: Internal Oscillator: External Clock: Master Clock Duty Cycle Rise Times: Fall Times: Digital Input Digital Output Digital Input Digital Output (Note (Note trise tfall -A,B Symbol fclk 30.0 30.0 82/fclk 32.768 32.768 1800/fclk 3246/fclk 1624/fclk 53.0 34.0 2/fclk+200 2/fclk+200 Units
3.3V SWITCHING CHARACTERISTICS TMAX
Start-Up
Power-On Reset Period Oscillator Start-up Time Wake-up Period XTAL=32.768 (Note (Note (Note (Note tres tosu twup tccw tscl tcal tsac thca tcpw tscn tbus tbuh tcon BP/UP stable prior DRDY ling BP/UP stable after DRDY (Note
Calibration
CONV Pulse Width (CAL CONV High Start Calibration Start Calibration Calibration
Conversion
Time Hold Time CONV Pulse Width CONV High Start Conversion Time Hold Time CONV High after CONV High
Start Conversion Conversion
DS59F4 DS59F7
CS5505/6/7/8
CS5505/6/7/8
XIN/2 CONV STATE Standby Calibration Standby
Figure Calibration Timing (Not Scale)
XIN/2 CONV DRDY BP/UP STATE Standby Conversion
Standby
Figure Conversion Timing (Not Scale)
DS59F4 DS59F7
CS5505/6/7/8
CS5505/6/7/8
SWITCHING CHARACTERISTICS TMAX;
Parameter Symbol tcsd1 tdfd tdd1 tcd1 tph1 tpl1 tfd1 tfd2 fsclk Pulse Width High Pulse Width data valid (Note (Note SCLK falling SDATA high output Hi-Z (Note SCLK falling SDATA Hi-Z tph2 tpl2 tcsd2 tdd2 tfd3 tfd4
VA+, 10%; 10%; Input Levels: Logic Logic VD+; pF.) (Note 2/fclk 1/fclk 1/fclk 1/fclk 1/fclk 2/fclk 3/fclk 2/fclk Units
Mode (M/SLP VD+)
Access Time: SDATA Delay Time: SCLK Delay Time Serial Clock (Out) Output Float Delay: SDATA (DRDY low) DRDY falling low) SCLK falling next SDATA SDATA SCLK rising Pulse Width High Pulse Width high output Hi-Z (Note SCLK rising SDATA Hi-Z
Mode (M/SLP DGND)
Serial Clock (In) Serial Clock (In) Access Time: Maximum Delay time: Output Float Delay:
Notes: returned high before data bits output, SDATA SCLK outputs will complete current data then high impedance. activated asynchronously DRDY, will recognized when DRDY high clock cycles. propagation delay time great cycles plus guarantee proper clocking SDATA when using asynchronous SCLK(i) should taken high sooner than after goes low. SDATA transitions falling edge SCLK. Note that rising SCLK must occur enable serial port shifting mechanism before falling edges recognized.
DS59F7
CS5505/6/7/8
CS5505/6/7/8
10%; 3.3V 10%; Input Levels: Logic Logic VD+; pF.) (Note Parameter Symbol tcsd1 tdfd tdd1 tcd1 tph1 tpl1 tfd1 tfd2 fsclk Pulse Width High Pulse Width data valid (Note (Note SCLK falling SDATA high output Hi-Z (Note SCLK falling SDATA Hi-Z tph2 tpl2 tcsd2 tdd2 tfd3 tfd4 2/fclk 1/fclk 1/fclk 1/fclk 1/fclk 2/fclk 3/fclk 2/fclk 1.25 Units
3.3V SWITCHING CHARACTERISTICS TMAX
Mode (M/SLP VD+)
Access Time: SDATA Delay Time: SCLK Delay Time Serial Clock (Out) Output Float Delay: SDATA (DRDY low) DRDY falling low) SCLK falling next SDATA SDATA SCLK rising Pulse Width High Pulse Width high output Hi-Z (Note SCLK rising SDATA Hi-Z
Mode (M/SLP DGND)
Serial Clock (In) Serial Clock (In) Access Time: Maximum Delay time: Output Float Delay:
DS59F4 DS59F7
CS5505/6/7/8
CS5505/6/7/8
XIN/2 CONV STATE DRDY tph1 SCLK(o) Hi-Z tcd1 SDATA(o) Hi-Z
Standby Conversion
tcsd1
Standby Conversion
Hi-Z tdd1
MSB-1
tpl1
LSB+1
tfd2
Hi-Z
STATE (CONV held high)
Conversion1
Conversion2
Figure Timing Relationships; Mode (Not Scale)
DRDY
SDATA(o) Hi-Z SCLK(i) csd2
MSB-1 MSB-2
DRDY SDATA(o) Hi-Z csd2
MSB-1 LSB+2 LSB+1
SCLK(i)
Figure Timing Relationships; Mode (Not Scale)
DS59F4 DS59F7
CS5505/6/7/8
CS5505/6/7/8
RECOMMENDED OPERATING CONDITIONS (DGND
Parameter Power Supplies: Positive Digital (VA+)-(VA-) Positive Analog Negative Analog Analog Input Voltage: (Note Unipolar Bipolar Symbol Vdiff VAMin 3.15 4.75 -((VREF+)-(VREF-))
(Note -5.0 -5.5 (VREF+)-(VREF-) +((VREF+)-(VREF-)) Units
Analog Reference Voltage (Note (VREF+)-(VREF-) VAIN VAIN
Notes: voltages with espect ground. CS5505/6/7/8 operated with reference voltage with corresponding reduction nois e-free resolution. common mode voltage voltage reference value long -VREF remain inside supply values VA-. CS5505/6/7/8 input voltages analog suppl (VA+ VA-). unipolar mode CS5505/6/7/8 output input magnitude (AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) will output input becomes more negative than Volts. bipolar mode CS5505/6/7/8 will output input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) will output input becomes more negative magnitude than -((VREF+)-(VREF-)).
ABSOLUTE MAXIMUM RATINGS*
Parameter Power Supplies: Digital Ground Positive Digital Positive Analog Negative Analog (VA+)-(VA-) (VA+)-(VD+) VREF pins (Note (Note Symbol DGND VAVdiff1 Vdiff2 VINA VIND -0.3 -0.3 -0.3 +0.3 -0.3 -0.3 (VA-)-0.3 -0.3 (VD+)-0.3 12.0 -6.0 12.0 12.0 (VA+)+0.3 (VD+)+0.3 Units
Input Current, Except Supplies Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature Notes:
(Notes
should more positive than (VA+)+0.3V. must always less than (VA+)+0.3 V,and never exceed 6.0V. Applies pins including continuous overvoltage conditions analog input (AIN) pin. Transient currents 100mA will cause latch-up. Maximum input current power supply
WARNING: Operation beyond these limits esult manent damage device. Normal operation guaranteed these extremes.
DS59F4 DS59F7
CS5505/6/7/8
CS5505/6/7/8
GENERAL DESCRIPTION CS5505/6/7/8 very power monolith nverters designed specifically measurement signals. CS5505/7 16-bit converters four channel single channel version). CS5506/8 20-bit converters four channel single channel version). Each devices includes delta-sigma charge-balance converter, voltage reference, calibration microcontroller with SRAM, digital filter serial interface. CS5505 CS5506 include four channel pseudo-differential (all four channels have same reference measurement node) multiplexer. CS5505/6/7/8 include on-chip reference also utilize off-chip reference precision applications. CS5505/6/7/8 used measure either unipolar bipolar signals. devices self-calibration insure excellent offset gain accuracy. CS5505/6/7/8 optimized operate from 32.768 crystal driven external clock whose frequency between kHz. When digital filter operated with 32.768 clock, filter zeros precisely line frequencies multiples thereof. CS5505/6/7/8 "start convert" command latch input channel selection start convolution cycle digital filter. Once filter cycle completed, output port updated. When operated with 32.768 clock converts updates output port samples/sec. throughput rate channel output update rate divided number channels being multiplexed. output port includes serial interface with modes operation. CS5505/6/7/8 operate from dual polarity power supplies -5), from single volt supply, with volts analog
DS59F4 DS59F7
digital. They also operate with dual polarity -5), from single volt supply analog digital.
THEORY OPERATION CS5505/6/7/8 front page this data sheet illustrates block diagram CS5505/6. Basic Converter Operation CS5505/6/7/8 converters have four operating states. These start-up, calibration, conversion sleep. When power first applied, device enters start-up state. first step power-on reset delay about which resets logic device. proceed with start-up, oscillator must then begin oscillating. After power-on reset device enters wake-up period 1800 clock cycles after clock present. This allows delta-sigma modulator other circuitry (which operating with very currents) reach stable bias condition prior entering into either calibration conversion states. During 1800 cycle wake-up period, device accept input command. Execution this command will occur until complete wake-up period elapses. command given, device enters standby mode. Calibration After initial application power, CS5505/6/7/8 must enter calibration state prior performing accurate conversions. During calibration, chip executes two-step process. device first performs offset calibration then follows this with gain calibration. calibration steps determine zero reference point full scale reference point converter's transfer function. From these points calibrates zero point gain
CS5505/6/7/8
CS5505/6/7/8
slope used properly scale output digital codes when doing conversions. calibration state entered whenever CONV pins high same time. state CONV pins poweron when coming sleep recognized commands, will executed until 1800 clock cycle wake-up period. Note that time CONV transitions from high, multiplexer inputs latched internal CS5505 CS5506 devices. These latched inputs select analog input channel which will used once conversion commences. CONV become active (high) during 1800 clock cycle wake-up time, converter will wait until wake-up period elapses before executing calibration. wake-up time elapsed, converter will standby mode waiting instruction will enter calibration cycle immediately. calibration lasts 3246 clock cycles. Calibration coefficients then retained SRAM (static RAM) during conversion. calibration cycle, on-chip microcontroller checks logic state CONV signal. CONV input device will enter standby mode where waits further instruction. CONV signal high calibration cycle, converter will enter conversion state perform conversion input channel which selected when CONV transitioned from high. signal returned time after calibration initiated. CONV also returned low, should never taken then taken back high until calibration period ended converter standby state. CONV taken then high again with high while converter calibrating, device will interrupt current calibration cycle start one. taken CONV taken
then high during calibration, calibration cycle will continue conversion command disregarded. states BP/UP important during calibrations. "end calibration" signal desired, pulse signal high while leaving CONV signal high continuously. Once calibration completed, conversion will performed. conversion, DRDY will fall indicate first valid conversion after calibration been completed. Understanding Converter Calibration details converter calibrates transfer function. Conversion conversion state entered calibration cycle, whenever converter idle standby mode. CONV taken high initiate calibration cycle also high), remains high until calibration cycle completed (CAL taken after CONV transitions high), converter will begin conversion upon completion calibration period. device will perform conversion input channel selected inputs when CONV transitioned high. Table indicates multiplexer channel selection truth table
Channel addressed AIN1 AIN2 AIN3 AIN4
Table Multiplexer Truth Table
inputs latched internal 4-channel devices (CS5505/6) when CONV rises. have internal pull-down circuits which default multiplexer channel
DS59F4 DS59F7
CS5505/6/7/8
CS5505/6/7/8
AIN1. BP/UP latched input. BP/UP controls output word from digital filter processed. bipolar mode output word computed digital filter offset 8000H 16-bit CS5505/7 80000H 20-bit CS5506/8 (see Understanding Converter Calibration). BP/UP changed after conversion started long stable clock cycles conversion period prior DRDY falling. wishes intermix measurement bipolar unipolar signals various input channels, best switch BP/UP immediately after DRDY falls leave BP/UP stable until DRDY falls again. converter beginning conversion starting from standby state, BP/UP changed same time digital filter CS5505/6/7/8 Finite Impulse Response designed settle full accuracy conversion time. Therefore, multiplexer changed conversion rate. CONV left high, CS5505/6/7/8 will perform continuous conversions channel. conversion time will 1622 clock cycles. conversion initiated from standby state, there clock cycles uncertainty when conversion actually begins. This because internal logic operates half external clock rate exact phase internal clock 180° phase relative clock. When conversion initiated from standby state, will take clock cycles begin. Actual conversion will 1624 clock cycles before DRDY goes indicate that serial port been updated. Serial Interface Logic section data sheet information reading data from serial port. event conversion command (CONV going positive) issued during conversion state, current conversion will
DS59F7
terminated conversion will initiated. Voltage Reference CS5505/6/7/8 uses differential voltage reference input. positive input VREF+ negative input VREF-. voltage between VREF+ VREF- range from volt minimum volts maximum. gain slope will track changes reference without recalibration, accommodating ratiometric applications. CS5505/6/7/8 include on-chip voltage reference which outputs volts VREFOUT pin. This voltage referenced will track changes relative VA+. VREFOUT output requires capacitor connected between VREFOUT stability. When using internal reference, VREFOUT signal should connected VREF- input VREF+ should connected supply. internal voltage reference capable sourcing maximum sinking maximum. more precise reference voltage required, external voltage reference should used. external voltage reference used, VREFOUT internal reference should connected directly VA-. cannot left open unless capacitor place stability.
CS5505/6/7/8 LT1019, REF43 LM368 2.5V VREF+ VREFVREFOUT
Figure External Reference Connections
CS5505/6/7/8
CS5505/6/7/8
CS5505/6/7/8
VREF+ VREFVREFOUT
ages A/D. differential input voltage also have common mode value long maximum signal magnitude stays within supply voltages. converter intended measure frequency inputs. designed yield accurate conversions even with noise exceeding input voltage range long spectral components this noise will filtered digital filter. example, with volt reference unipolar mode, converter will accurately convert input signal volts with overrange noise. volt signal could have component which volts above maximum input (3.5 volts peak; volts plus volts peak noise) still accurately convert input signal (XIN 32.768 kHz). This assumes that signal plus noise amplitude stays within supply voltages. CS5505/6/7/8 converters output data binary format when converting unipolar signals offset binary format when converting bipolar signals. Table outlines output coding 16-bit CS5505/7 20-bit CS5506/8 both unipolar bipolar measurement modes.
Figure Internal Reference Connections
External reference voltages range from volt minimum volts maximum. common mode voltage range external reference allow reference voltage between supply rails. Figures illustrate CS5505/6/7/8 converters connected external internal voltage reference use, respectively. Analog Input Range analog input range magnitude voltage between VREF+ VREFpins. unipolar mode input range will equal magnitude voltage reference. bipolar mode input voltage range will equate plus minus magnitude voltage reference. While voltage reference great volts, common mode voltage value long reference inputs VREF+ VREF- stay within supply voltCS5505 CS5507 Bit) Unipolar Input Voltage >(VREF LSB) VREF VREF/2 +0.5 <(+0.5 LSB) Output Codes FFFF FFFF FFFE 8000 7FFF 0001 0000 0000 Bipolar Input Voltage >(VREF LSB) VREF -0.5 -VREF <(-VREF LSB)
CS5506 CS5508 Bit) Unipolar Input Voltage >(VREF LSB) VREF VREF/2 +0.5 <(+0.5 LSB) Output Codes FFFFF FFFFF FFFFE 80000 7FFFF 00001 00000 00000 Bipolar Input Voltage >(VREF LSB) VREF -0.5 -VREF <(-VREF LSB)
Note: VREF (VREF+) (VREF-); Table excludes common mode voltage signal reference inputs. Table Output Coding DS59F7
CS5505/6/7/8
CS5505/6/7/8
Understanding Converter Calibration Calibration performed time. calibration sequence will minimize offset errors gain slope scale factor. deltasigma modulator converter differential modulator. calibrate offset error, converter internally connects modulator differential inputs internal VREF- voltage measures density output from modulator. stores digital code representation this density SRAM remembers this code being zero scale point conversion. converter then connects negative modulator differential input VREF- input positive modulator differential input VREF+ voltage. density output from modulator then reco rded. converter uses digital representation this density along with digital code zero scale point calculates gain scale factor. gain scale factor stored SRAM used calculating proper output codes during conversions. states BP/UP ignored during calibration should remain stable throughout calibration period minimize noise. When conversions performed unipolar mode bipolar mode, converter uses same calibration factors compute digital output code. only difference that bipolar mode on-chip microcontroller offsets computed output word code value
+1/2
8000H (16-bit) 80000H (20-bit) multiplies size two. This means that bipolar measurement range calibrated from full scale positive full scale negative. Instead calibrated from bipolar zero scale point full scale positive. slope factor then extended below bipolar zero accommodate negative input signals. converter used convert both unipolar bipolar signals changing BP/UP pin. Recalibration required when switching between unipolar bipolar modes. Converter Performance CS5505/6/7/8 converters have excellent linearity performance. Calibration minimizes errors offset gain. CS5505/7 devices have missing code performance 16-bits. CS5506/8 devices have missing code performance 20-bits. Figure illustrates 16-bit CS5505. converters achieve Common Mode Rejection (CMR) typical, typical. CS5505/6/7/8 experience some drift temperature changes. CS5505/6/7/8 chopper-stabilized techniques minimize drift. Measurement errors offset gain drift eliminated time recalibrating converter.
(LSB)
-1/2
32,768
65,535
Codes
Figure CS5505 Differential Nonlinearity plot. DS59F4 DS59F7
CS5505/6/7/8
CS5505/6/7/8
Analog Input Impedance Considerations analog input CS5505/6/7/8 modeled illustrated Figure (the model ignores multiplexer switch resistance). Capacitors each) used dynamically sample each inputs (AIN+ AIN-). Every half cycle switch alternately connects capacitor output buffer then directly pin. Whenever sample capacitor switched from output buffer pin, small packet charge dynamic demand current) required from input source settle voltage sample capacitor final value. voltage output buffer differ from actual input voltage offset voltage buffer. Timing allows half clock cycle voltage sample capacitor settle final value. equation which defines settling time
Vmax
Vmax occurs instant sample capacitor switched from buffer output pin. Prior switching, error estimated being less than equal Vmax equal prior error (Ve) plus additional error from buffer offset. estimate Vmax
Vmax 100mV
15pF (15pF CEXT
Where CEXT combination external stray capacitance. From settling time equation, equation maximum acceptable source resistance derived.
Rsmax 2XIN (15pF CEXT 15pF(100mv) (15pF CEXT
Where final settled value, Vmax maximum error voltage value input signal, value input source resistance, sample capacitor plus value stray additional capacitance input pin. value equal 1/(2XIN).
This equation assumes that offset voltage buffer which worst case. value maximum error voltage which acceptable. maximum error voltage (Ve) CS5505 (1/4LSB 16-bits) CS5506 (1/4LSB 20-bits), above equation indicates that when operating from 32.768 XIN, source resistances CS5505 CS5506 acceptable absence external capacitance (CEXT higher input source resistances desired master clock rate reduced yield longer settling time. VREF+ VREF- inputs have nearly same structure AIN+ AIN- inputs. Therefore, discussion analog input impedance applies voltage reference inputs well.
AIN+ AINVos
CS5505/6/7/8 Internal Bias Voltage
Figure Analog Input Model DS59F4 DS59F7
CS5505/6/7/8
CS5505/6/7/8
Digital Filter Characteristics digital filter CS5505/6/7/8 combination comb filter pass filter. comb filter zeros transfer function which optimally placed reject line interference frequencies their multiples) when CS5505/6/7/8 clocked 32.768 kHz. Figures illustrate magnitude phase characteristics filter.
32.768kHz 163.00kHz
Figure illustrates filter attenuation from exactly 100, filter provides over rejection. Table indicates filter attenuation each potential line interference frequencies when converter operating with 32.768 clock. converter yields excellent attenuation these interference frequencies even fundamental line frequency should vary from specified frequency. corner frequency filter when operating from 32.768 clock Figure illustrates that phase characteristics filter precisely linear phase.
Frequency (Hz) Notch Depth (dB) 125.6 126.7 145.7 136.0 118.4 132.9 102.5 108.4 Frequency Minimum (Hz) Attenuation (dB) 55.5 50±1% 58.4 60±1% 62.2 100±1% 68.4 120±1% 74.9 150±1% 87.9 180±1% 94.0 200±1% 104.4 240±1%
Attenuation (dB)
-100
-120 -140
-160 32.768 198.97 397.95 596.92 795.10 993.87 1193.85 Frequency (Hz)
Figure Filter Magnitude Plot
Flatness Frequency -0.010
-0.093
Table Filter Notch Attenuation (XIN 32.768 kHz)
Phase (Degrees) 32.768 -135 -180
Attenuation (dB)
-0.041
-0.166 -0.259 -0.374 -0.510 -0.667 -0.846 -1.047 -3.093
-100 -120
-140
32.768
Frequency (Hz)
Frequency (Hz)
Figure Filter Magnitude Plot DS59F4 DS59F7
Figure Filter Phase Plot
CS5505/6/7/8
CS5505/6/7/8
CS5505/6/7/8 operated clock rate other than 32.768 kHz, filter characteristics, including comb filter zeros, will scale with operating clock frequency. Therefore, optimum rejection line frequency interference will occur with CS5505/6/7/8 running 32.768 kHz. CS5505/6/7/8 used with external clock rates from kHz. Anti-Alias Considerations Spectral Measurement Applications Input frequencies greater than half output word rate (CONV aliased converter. prevent this, input signals should limited frequency greater than half output word rate converter (when CONV =1). Frequencies close modulator sample rate (XIN/2) multiples thereof also aliased. signal source includes spectral components above half output word rate (when CONV these com-
ponents should removed means lowpass filtering prior input prevent aliasing. Spectral components greater than half output word rate VREF inputs (VREF+ VREF-) also aliased. Filtering reference voltage remove these spectral components from reference voltage desirable. Crystal Oscillator CS5505/6/7/8 designed operated using 32.768 "tuning fork" type crystal. crystal should connected input. other should attached XOUT. Short lead lengths should used minimize stray capacitance. Figure illustrates gate oscillator, simplified version control logic used chip. Over industrial temperature range (-40 on-chip gate oscillator will oscillate
CS5505/6 CONV 22.5 Modulator Sample Clock Start Conversion Input Decoder Channel
Start Calibration
umho XOUT XTL=32.768
Figure Gate Oscillator Control Logic DS59F4 DS59F7
CS5505/6/7/8
CS5505/6/7/8
with other crystals range kHz. Over military temperature range +125 on-chip gate oscillator designed work only with 32.768 crystal. chip will operate with external clock frequencies from kHz.over temperature ranges. 32.768 crystal normally specified time-keeping crystal with tight specifications both initial frequency drift over temperature. maintain excellent frequency stability, these crystals specified only over limited operating temperature ranges (i.e. manufacturers. Applications these crystals with CS5505/6/7/8 require tight initial tolerance tempco drift. Therefore, lower cost crystal with looser initial tolerance tempco will generally adequate with CS5505/6/7/8 converters. Also check with manufacturer about wide temperature range application their standard crystals. Generally, even those crystals specified limited temperature range will operate over much larger ranges frequency stability over temperature requirement. frequency stability ±3000 over operating temperature range still typically better than line frequency stability over cycle cycle during course day. There crystals available operation over military temperature range (-55 +125 °C). Appendix suppliers 32.768 crystals. Serial Interface Logic digital filter CS5505/6/7/8 takes 1624 clock cycles compute output word once conversion begins. conversion cycle, filter will attempt update serial port. clock cycles prior update DRDY will high. When DRDY goes high just prior port update checks port either empty unselected port empty unselected, digital filter will update port with output word.
DS59F4 DS59F7
When data into port DRDY will low. Data read from serial port either modes. M/SLP determines which serial mode selected. Serial port mode selection follows: (Synchronous Self-Clocking) mode; M/SLP VD+, (Synchronous External Clocking) mode; M/SLP DGND. Timing diagrams which illustrate timing tables section this data sheet. Synchronous Self-Clocking Mode serial port operates mode when M/SLP connected part. mode CS5505/6/7/8 furnishes both serial output data (SDATA) serial clock (SCLK). When serial port updated conversion, DRDY falls. low, SDATA SCLK pins will come high impedance state clock cycles after DRDY falls. data will presented cycles clock. SCLK signal will rise middle data bit. When SCLK then returns (MSB will appear. Subsequent data bits will output each falling edge SCLK until data output. After data output, SCLK will fall which time both SDATA SCLK outputs will return high impedance output state. DRDY will return high this time. taken after DRDY falls, data will appear within clock cycles after taken low. need held entire data output. returned high during data port will complete output that then into Hi-Z state. port reselected time prior completion next conversion (DRDY falling) allow remaining data bits output.
CS5505/6/7/8
CS5505/6/7/8
Synchronous External-Clocking Mode serial port operates mode when M/SLP connected DGND pin. SDATA output serial data. When goes after data becomes available (DRDY goes low), SDATA comes Hi-Z with data present. SCLK input serial clock mode. data SDATA pin, first rising edge SCLK enables shifting mechanism. This allows falling edges SCLK shift subsequent data bits port. Note that data output SCLK signal high, first falling edge SCLK will ignored because shifting mechanism become activated. After first rising edge SCLK, each subsequent falling edge will shift serial data. Once present, falling edge SCLK will cause SDATA output Hi-Z DRDY return high. serial port register will updated with data word upon completion another conversion serial port been emptied, inactive (high). operated asynchronously DRDY signal. DRDY signal need monitored long signal taken least clock cycles plus prior SCLK being toggled. This ensures that gained control over serial port. Sleep Mode CS5505/6/7/8 devices offer methods putting device into SLEEP condition conserve power. Calibration words will retained SRAM during either sleep condition. M/SLP into SLEEP threshold lower operating power used device about nominal. Alternately, clock into stopped. This will lower power consumed converter about nominal. both cases,
converter must through wake-up sequence prior conversions being initiated. This wakeup sequence includes msec. (typ.) power-on-reset delay, start-up oscillator (unless external clock used), 1800 clock cycle wake-up delay after clock begins. When coming sleep condition, converter will latch inputs. Figure illustrates gate resistors bias M/SLP into SLEEP threshold region when using converter mode. mode return resistor DGND instead supply. When mode configuration CS5505/6/7/8 will enter SLEEP threshold when logic control input logic (VD+). Note that large resistors used conserve power while sleep. input leakage typically less than even although worst case specification tables indicate leakage
M/SLP 499k 0.01µF
CS5505/6/7/8
Control Input Mode SLEEP
DGND mode; control input logic inverts. 499k, 590k, 3.3V
Figure Sleep Threshold Control
maximum. Power Supplies Grounding analog digital supply pins CS5505/6/7/8 brought separate pins minimize noise coupling between analog digital sections chip. Note that there
DS59F7
CS5505/6/7/8
CS5505/6/7/8
analog ground pin. analog ground required because inputs measurement voltage reference differential require ground. digital section chip supply current flows into DGND pin. CMOS device, CS5505/6/7/8 requires that supply voltage always more positive than voltage other device. this requirement met, device latch-up damaged. circumstances voltage must remain more positive than
DGND pins; must remain more positive than DGND pin. following power supply options possible:
+10V, +5V, -5V, -5V, +3.3V
CS5505/6/7/8 cannot operated with 3.3V digital supply greater than +5.5V.
Analog Supply
Calibration Control Bipolar/ Unipolar Input Select XOUT M/SLP
Optional Clock Source 32.768 Sleep Mode Control Output Mode Select Serial Data Interface
BP/UP
CS5505/6
Analog* Signal Sources Signal Ground *Unused analog inputs should tied AIN14 AIN1+ AIN2+ AIN3+ AIN4+ AINVREF+ VREF-
SCLK SDATA DRDY CONV
Voltage Reference
Control Logic
VREFOUT DGND VA18
Unused Logic inputs must connected DGND.
Note: internal volt reference Figure
Figure CS5505/6 System Connection Diagram Using External Reference, Single Supply DS59F7
CS5505/6/7/8
CS5505/6/7/8
Figure illustrates System Connection Diagram CS5505/6 using single supply. Note that supply pins bypassed with capacitors that digital supply derived from supply. Figure illustrates CS5505/6 using dual supplies -5V.
Figure illustrates CS5505/6 using dual supplies +10V analog digital. When using separate supplies VD+, must established first. should never become more positive than under operating condition. Remember investigate transient power-up conditions, when power supply have faster rise time.
Analog Supply
Calibration Control Bipolar/ Unipolar Input Select XOUT M/SLP
Optional Clock Source 32.768 Sleep Mode Control Output Mode Select Serial Data Interface
BP/UP
CS5505/6
Analog* Signal Sources Signal Ground *Unused analog inputs should tied AIN14 AIN1+ AIN2+ AIN3+ AIN4+ AINVREF+ VREF-
SCLK SDATA DRDY CONV
Voltage Reference
Control Logic
Analog Supply
VREFOUT DGND VA18
Unused Logic inputs must connected DGND.
Note: internal volt reference Figure
Figure CS5505/6 System Connection Diagram Using External Reference, Dual Supplies
DS59F7
CS5505/6/7/8
CS5505/6/7/8
+10V Analog Supply
Analog Supply Optional Clock Source
Calibration Control Bipolar/ Unipolar Input Select
XOUT M/SLP
32.768 Sleep Mode Control Output Mode Select Serial Data Interface
BP/UP
CS5505/6 Analog* Signal Sources Signal Ground AIN1+ AIN2+ AIN3+ AIN4+ AINVREF+ VREF-
SCLK SDATA DRDY CONV
*Unused analog inputs should tied AIN14 Voltage Reference
Control Logic
VREFOUT DGND VA18
Unused Logic inputs must connected DGND.
Note: internal volt reference Figure must never exceed VA+. Examine power-up conditions.
Figure CS5505/6 System Connection Diagram Using External Reference, Dual Supply, +10V Analog, Digital
Schematic Layout Review Service
Confirm Optimum Schematic Layout Before Building Your Board. Free Review Service Call Applications Engineering.
DS59F4 DS59F7
CS5505/6/7/8
CS5505/6/7/8
CONNECTIONS*
CS5505/6
MULTIPLEXER SELECTION INPUT CHIP SELECT CONVERT CALIBRATE CRYSTAL CRYSTAL RIAL MODE/ SLEEP BIPOLAR/UNIPOLAR DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG RETURN DIFFERENTIAL ANALOG INPUT
CONV XOUT M/SLP BP/UP AIN1+ AIN2+ AINAIN3+
DRDY SDATA SCLK DGND VAVA+
MULTIPLEXER SELECTION INPUT DATA READY SERIAL DATA UTPUT SERIAL CLOCK INPUT/OUTPUT POSITIVE DIGITAL POWER DIGITAL GROUND NEGATIVE ANALOG POWER POSITIVE ANALOG POWER
VREFOUT VOLTAGE REFERENCE OUTPUT VREFVREF+ AIN4+ VOLTAGE REFERENCE INPUT VOLTAGE REFERENCE INPUT DIFFERENTIAL ANALOG INPUT
CS5507/8
CHIP SELECT CONVERT CALIBRATE CRYSTAL CRYSTAL SERIAL MODE/ SLEEP BIPOLAR/UNIPOLAR DIFFERENTIAL ANALOG INPUT CONNECTION DIFFERENTIAL ANALOG INPUT *Pinout applies both SOIC
CONV XOUT M/SLP BP/UP AIN+ AIN-
DRDY SDATA SCLK DGND VAVA+ VREFVREF+
DATA READY SERIAL DATA UTPUT SERIAL CLOCK INPUT/OUTPUT POSITIVE DIGITAL POWER DIGITAL GROUND NEGATIVE ANALOG POWER POSITIVE ANALOG POWER VOLTAGE REFERENCE INPUT VOLTAGE REFERENCE INPUT
VREFOUT VOLTAGE REFERENCE OUTPUT
DS59F4 DS59F7
CS5505/6/7/8
CS5505/6/7/8
DESCRIPTIONS numbers four channel devices parentheses.
Clock Generator XIN; XOUT Crystal Crystal Out, Pins (6). gate inside chip connected these pins used with crystal provide master clock device. Alternatively, external (CMOS compatible) clock supplied into provide master clock device. Loss clock will device into lower powered state (approximately power reduction). Serial Output M/SLP Serial Interface Mode Select/ Sleep, (7). Dual function which selects operating mode serial port provides very power sleep function. When M/SLP tied serial port will operate Synchronous Self-Clocking (SSC) mode. When M/SLP tied DGND serial port will operate Synchronous External Clocking (SEC) mode. When M/SLP tied half between DGND chip will enter into very powered sleep mode which calibration data will maintained. Chip Select, (2). This input allows external device access serial port. DRDY Data Ready, (23) Data Ready goes digital filter convolution cycle indicate that output word been placed into serial port. DRDY will return high after data bits shifted serial port master clock cycles before data becomes available inactive (high). SDATA Serial Data Output, (22). SDATA output serial output port. Data from this will output rate determined SCLK format determined M/SLP pin. Data output first advances next data falling edges SCLK. SDATA will high impedance state when transmitting data. SCLK Serial Clock Input/Output, (21). clock signal this determines output rate data from SDATA pin. M/SLP determines whether SCLK input output. When used input, must allowed float.
DS59F7
CS5505/6/7/8
CS5505/6/7/8
Control Input Pins Calibrate, (4). When taken high same time that CONV taken high converter will perform self-calibration which includes calibration offset gain scale factors converter. CONV Convert, (3). CONV initiates calibration cycle taken from high while high, initiates conversion taken from high with low. CONV latches multiplexer selection when transitions from high multiple channel devices. CONV held high (CAL low) converter will continuous conversions. Multiplexer Selection Inputs, Pins 24). select input channel conversion multi-channel input devices. latched when CONV transitions from high. These inputs have pull-down resistors internal chip. BP/UP Bipolar/Unipolar, (8). BP/UP selects conversion mode converter. When high converter will convert bipolar input signals; when will convert unipolar input signals. Measurement Reference Inputs AIN+, AIN-, (AIN1+, AIN2+, AIN3+, AIN4+, AIN-) Differential Analog Inputs, Pins 11). AIN- CS5505/6 common measurement node AIN1+, AIN2+, AIN3+ AIN4+. VREF+, VREF- Differential Voltage Reference Inputs, Pins (14, 15). differential voltage reference these pins operates voltage reference converter. voltage between these pins voltage between volts. Voltage Reference VREFOUT Voltage Reference Output, (16). on-chip voltage reference output from this pin. voltage reference nominal magnitude volts referenced converter. Power Supply Connections Positive Analog Power, (17). Positive analog supply voltage. Nominally volts. Negative Analog Power, (18). Negative analog supply voltage. Nominally volts when using dual polarity supplies; volts (tied system analog ground) when using single supply operation.
DS59F4 DS59F7
CS5505/6/7/8
CS5505/6/7/8
Positive Digital Power, (20). Positive digital supply voltage. Nominally volts volts. DGND Digital Ground, (19). Digital Ground. Other Connection, should left floating.
SPECIFICATION DEFINITIONS
Linearity Error deviation code from straight line which connects endpoints Converter transfer function. endpoint located below first code transition other endpoint located beyond code transition ones. Units percent full-scale. Differential Nonlinearity deviation code's width from ideal width. Units LSBs. Full Scale Error deviation last code transition from ideal [{(VREF+) (VREF-)} LSB]. Units LSBs. Unipolar Offset deviation first code transition from ideal (1/2 above voltage AINpin.) when unipolar mode (BP/UP low). Units LSBs. Bipolar Offset deviation mid-scale transition (011.111 100.000) from ideal (1/2 below voltage AIN- pin.) when bipolar mode (BP/UP high). Units LSBs
DS59F7
CS5505/6/7/8
ORDERING INFORMATION
Model Resolution Liearity Error Channels Package Temperature
CS5505-ASZ (lead free) CS5506-BSZ (lead free) CS5507-ASZ (lead free) CS5508-BSZ (lead free)
Bits Bits Bits Bits
0.0030% 0.0015% 0.0030% 0.0015%
24-pin SOIC 20-pin SOIC
ENVIRONMENTAL, MANUFACTURING, HANDLING INFORMATION
Model Number Peak Reflow Temp Rating* Floor Life
CS5505-ASZ (lead free) CS5506-BSZ (lead free) CS5507-ASZ (lead free) CS5508-BSZ (lead free)
Days
(Moisture Sensitivity Level) specified IPC/JEDEC J-STD-020.
DS59F7
CS5505/6/7/8
REVISION HISTORY
Revision Date 1995 2005 2009 First Final Release Updated device ordering info. Updated legal notice. Added data. Increased minimum Vdiff voltage from 4.75 Changes
Contacting Cirrus Logic Support
product questions inquiries contact Cirrus Logic Sales Representative. find nearest www.cirrus.com
IMPORTANT NOTICE Cirrus Logic, Inc. subsidiaries ("Cirrus") believe that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). Customers advised obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, indemnification, limitation liability. responsibility assumed Cirrus this information, including this information basis manufacture sale items, infringement patents other rights third parties. This document property Cirrus furnishing this information, Cirrus grants license, express implied under patents, mask work rights, copyrights, trademarks, trade secrets other intellectual property rights. Cirrus owns copyrights associated with information contained herein gives consent copies made information only within your organization with respect Cirrus integrated circuits other products Cirrus. This consent does extend other copying such copying general distribution, advertising promotional purposes, creating work resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS DESIGNED, AUTHORIZED WARRANTED PRODUCTS SURGICALLY IMPLANTED INTO BODY, AUTOMOTIVE SAFETY SECURITY DEVICES, LIFE SUPPORT PRODUCTS OTHER CRITICAL APPLICATIONS. INCLUSION CIRRUS PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK CIRRUS DISCLAIMS MAKES WARRANTY, EXPRESS, STATUTORY IMPLIED, INCLUDING IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE, WITH REGARD CIRRUS PRODUCT THAT USED SUCH MANNER. CUSTOMER CUSTOMER'S CUSTOMER USES PERMITS CIRRUS PRODUCTS CRITICAL APPLICATIONS, CUSTOMER AGREES, SUCH USE, FULLY INDEMNIFY CIRRUS, OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS OTHER AGENTS FROM LIABILITY, INCLUDING ATTORNEYS' FEES COSTS, THAT RESULT FROM ARISE CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, Cirrus Logic logo designs trademarks Cirrus Logic, Inc. other brand product names this document trademarks service marks their respective owners.
DS59F7
CS5505/6/7/8
NOTES
DS59F7
CDB5505/6/7/8 CDB5505/6/7/8 Evaluation Board CS5505/6/7/8 Series ADCs Evaluation Board CS5505/6/7/8 Series ADC's
Features Description
CDB5505/ 5506/5507/5508 rcuit esigned provide quick evaluation CS5505/6/7/8 series converters. board configured evaluate CS5505/6/7/8 either (Synchronous Self-Clocking) (Synchronous External-Clocking) serial port mode. board allows access digital interface pins CS5505/6/7/8 chip. ORDERING INFORMATION CDB5505 CDB5506 CDB5507 CDB5508 Evaluation Board Evaluation Board Evaluation Board Evaluation Board
off-board clock source Jumper selectable:
Operation with on-board 32.768 crystal
mode; mode; Sleep
Switch Selectable:
On-board precision voltage reference Access digital control pins On-board patch area
BP/UP mode; channel selection
AIN4+
AIN3+ AIN2+
AIN1+
CS5505/6/7/8
AIN-
CLKIN
VREF
Cirrus Logic, Inc. Crystal Semiconductor Products Division http://www.cirrus.com P.O. 17847, Austin, Texas 78760 (512) 7222 FAX: (512) 7581 http://www.crystal.com
Copyright Cirrus Copyright Cirrus Logic, Inc. 2009 Logic, Inc. 1998 (All Rights Reserved) (All Rights Reserved)
DS59DB4 DS59DB2
CDB5505/6/7/8
CS5505/6/7/8
Introduction CDB5505/6/7/8 evaluation board provides quick means testing CS5505/6/7/8 series converters. CS5505/6/7/8 converters require minimal amount external circuitry. evaluation board comes configured with converter chip operating from 32.768 crystal with off-chip precision volt reference. board provides access digital interface pins CS5505/6/7/8 chip. board configured operation from volt power supplies, operated from single volt supply binding post shorted binding post. off-board reference connections bandgap cut. Note that pin-out CS5505/6/7/8 series chips allows 20-pin single channel devices plugged into 24-pin, four channel footprint. Figure which illustrates footprint compatibility. Prior powering board, select serial port operating mode with appropriate jumper M/SLP header. device operated either (Synchronous Self-Clocking) (Synchronous External Clocking) mode. device data sheet explanation these modes. control pins CS5505/6/7/8 available header connector. Buffer used buffer converter interface off-board circuits. buffers used evaluation board only because exact loading off-board circuitry unknown. Most applications will require buffer proper operation. board operation, select either bipolar unipolar mode with switch Then press pushbutton after board powered This initiates calibration converter which required before measurements taken. select input channel four channel devices, switch select inputs
Channel addressed AIN1 AIN2 AIN3 AIN4
Evaluation Board Overview board provides complete means making CS5505/6/7/8 converter chip function. user must provide means taking output data from board serial format using system. Figure illustrates schematic board. board comes configured converter chip operate from 32.768 watch crystal. connector external clock provided board. connect external source converter chip, circuit trace must cut. Then jumper must inserted proper holes connect converter input line from BNC. input terminated with resistor. Remove this resistor driving from logic gate. schematic Figure board comes with converter VREF+ VREF- pins hard-wired volt bandgap voltage reference board. VREF+ VREF- pins connected either chip reference
Table Multiplexer Truth Table
DS59DB2 DS59DB4
DRDY SCLK SDATA CONV AGND 0.01 100k DGND VREFOUT TP10 10nF VREF+ CONV VREFCS
DS59DB2 DS59DB4
10nF
6.8V
6.8V
CS5505
DRDY
LT1019 -2.5
CS5506
CS5507
100k 100k
TP11
External VREF
DRDY
CS5508
AIN4+ AIN3+ SCLK TP13
AIN4+
SDATA
TP12
100k
SDATA SCLKO SCLKI BP/UP
100k
100k
AIN3+ AIN2+
100k
AIN2+ AIN1+
100k
AIN1+ TP15 AIN-
100k 100k TP14 100k BP/UP M/SLP
100k 0.01 0.01 0.01 0.01
AIN-
100k
100k
100k
74HC4050 74HC125 CONV
XOUT DGND
CLKIN
32.768 SLEEP BP/UP
CDB5505/6/7/8
CS5505/6/7/8
Figure Connections
CDB5505/6/7/8
CS5505/6/7/8
CONV XOUT
CS5505/6
DRDY SDATA SCLK VADGND
20/23 CS5507/8 19/22 18/21 17/20 16/19 15/18 14/17 13/16 12/15 11/14
M/SLP BU/UP AIN1+ VREFOUT AIN2+/NC AIN3+
10/9
VREFAIN4+
AIN-
11/10
VREF+
Figure CS5505/6 CS5507/8 Layouts
(see Table Once selected, CONV switch (S2-3) must switched (closed) then open cause CONV signal transition high. This latches channel selection into converter. With CONV high (S2-3 open) converter will convert continuously.
Figures illustrate evaluation board layout while Figure illustrates component placement (silkscreen) evaluation board.
DS59DB2 DS59DB4
CDB5505/6/7/8
CS5505/6/7/8
Figure Ground Plane Layer (NOT SCALE) DS59DB2 DS59DB4
CDB5505/6/7/8
CS5505/6/7/8
Figure Bottom Trace Layer (NOT SCALE) DS59DB2 DS59DB4
CDB5505/6/7/8
CS5505/6/7/8
Figure Silk Screen Layer (NOT SCALE) DS59DB2 DS59DB4
CDB5505/6/7/8
REVISION HISTORY
Revision Date 1995 2005 2009 First Release Updated legal notice. Removed references part numbers devices containing lead (Pb). Changes
Contacting Cirrus Logic Support
product questions inquiries contact Cirrus Logic Sales Representative. find nearest www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. subsidiaries ("Cirrus") believe that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). Customers advised obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, indemnification, limitation liability. responsibility assumed Cirrus this information, including this information basis manufacture sale items, infringement patents other rights third parties. This document property Cirrus furnishing this information, Cirrus grants license, express implied under patents, mask work rights, copyrights, trademarks, trade secrets other intellectual property rights. Cirrus owns copyrights associated with information contained herein gives consent copies made information only within your organization with respect Cirrus integrated circuits other products Cirrus. This consent does extend other copying such copying general distribution, advertising promotional purposes, creating work resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS DESIGNED, AUTHORIZED WARRANTED PRODUCTS SURGICALLY IMPLANTED INTO BODY, AUTOMOTIVE SAFETY SECURITY DEVICES, LIFE SUPPORT PRODUCTS OTHER CRITICAL APPLICATIONS. INCLUSION CIRRUS PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK CIRRUS DISCLAIMS MAKES WARRANTY, EXPRESS, STATUTORY IMPLIED, INCLUDING IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE, WITH REGARD CIRRUS PRODUCT THAT USED SUCH MANNER. CUSTOMER CUSTOMER'S CUSTOMER USES PERMITS CIRRUS PRODUCTS CRITICAL APPLICATIONS, CUSTOMER AGREES, SUCH USE, FULLY INDEMNIFY CIRRUS, OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS OTHER AGENTS FROM LIABILITY, INCLUDING ATTORNEYS' FEES COSTS, THAT RESULT FROM ARISE CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, Cirrus Logic logo designs trademarks Cirrus Logic, Inc. other brand product names this document trademarks service marks their respective owners.
DS59DB4

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