Features Description Energy Linearity: ±0.1% Reading over 1000:1

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Features Description Energy Linearity: ±0.1% Reading over 1000:1

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CS5467 Four-channel Power Energy
Features Description
Energy Linearity: ±0.1% Reading over 1000:1 Dynamic Range On-chip Functions:
Voltage Current Measurement Active, Reactive, Apparent Power/Energy Voltage Current Calculations Current Fault Voltage Detection Calibration Phase Compensation Temperature Sensor Energy Pulse Outputs
Description
CS5467 watt-hour meter chip. measures line voltage current calculates active, reactive, apparent power, energy, power factor, voltage current. internal voltage reference used voltage measurement disabled tampering. Four analog-to-digital converters used measure voltages currents. Optionally, voltage2 channel used temperature measurement. CS5467 designed interface variety voltage current sensors. Additional features include system-level calibration, voltage current fault detection, peak detection, phase compensation, energy pulse outputs.
ORDERING INFORMATION
Page
Meets Accuracy Spec IEC, ANSI, Power Consumption Voltage Tamper Correction Ground-referenced Inputs with Single Supply On-chip Reference typ.) Power Supply Monitor Function Three-wire Serial Interface Microcontroller E2PROM Power Supply Configurations
GND: VA+: VD+: +3.3
RESET
IIN1+ IIN1-
Order Modulator
Digital Filter
Option
MODE
VIN1+ VIIN1-
Order Modulator
Digital Filter
Option Power Calculation Engine
Serial Interface
SCLK
IIN2+ IIN2-
Order Modulator
Digital Filter
Option
E-to-F
VIN2+ VIN2-
Order Modulator
Digital Filter
Option
Calibration
VREFIN
Voltage Reference AGND Power Monitor Temperature Sensor System Clock Clock Generator
VREFOUT
PFMON
XOUT CPUCLK
DGND
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2007 (All Rights Reserved)
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CS5467
TABLE CONTENTS
Overview Description
Clock Generator Control Pins Serial Data Analog Inputs/Outputs Power Supply Connections
Characteristics Specifications Recommended Operating Conditions Analog Characteristics
Accuracy Analog Inputs (All Inputs) Analog Inputs (Current Inputs) Analog Inputs (Voltage Inputs) Temperature Power Supplies
Voltage Reference
Reference Output Reference Input
Digital Characteristics
Master Clock Characteristics Filter Characteristics Input/Output Characteristics
Switching Characteristics
Start-up Serial Port Timing Timing Timing E2PROM mode Timing Timing
Absolute Maximum Ratings Signal Path Description Analog-to-Digital Converters Decimation Filters Phase Compensation Offset Gain Correction High-pass Filters Low-Rate Calculations Results Power Energy Results Peak Voltage Current 4.10 Power Offset Descriptions Analog Pins 5.1.1 Voltage1 Voltage2 Inputs 5.1.2 Current1 Current2 Inputs 5.1.3 Power Fail Monitor Input
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5.1.4 Voltage Reference Input 5.1.5 Voltage Reference Output 5.1.6 Crystal Oscillator Digital Pins 5.2.1 Reset Input 5.2.2 Clock Output 5.2.3 Interrupt Output 5.2.4 Energy Pulse Outputs 5.2.5 Serial Interface Setting CS5467 Clock Divider Clock Inversion Interrupt Behavior Current Input Gain Ranges High-pass Filters Cycle Count Energy Pulse Outputs Load Threshold Energy Pulse Width 6.10 Energy Pulse Rate 6.11 Voltage Sag/Current Fault Detection 6.12 Epsilon 6.13 Temperature Measurement Using CS5467 Initialization Power-down States Voltage Tamper Correction Command Interface Register Paging Commands Register Descriptions Page Register Page Registers Page Registers Page Registers Page Register System Calibration Calibration 9.1.1 Offset Calibration 9.1.1.1 Offset Calibration 9.1.1.2 Offset Calibration 9.1.2 Gain Calibration 9.1.2.1 Gain Calibration 9.1.2.2 Gain Calibration
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9.1.3 Calibration Order 9.1.4 Temperature Sensor Calibration 9.1.4.1 Temperature Offset Calibration 9.1.4.2 Temperature Gain Calibration E2PROM Operation 10.1 E2PROM Configuration 10.2 E2PROM Code 10.3 Which E2PROMs Used? Basic Application Circuits Package Dimensions Ordering Information Environmental, Manufacturing, Handling Information Revision History
LIST FIGURES
Figure CS5467 Read Write Timing Diagrams Figure Timing Diagram Figure Signal Flow Measurements Figure Signal Flow Measurements Figure Low-rate Calculations Figure Two-channel Power Summation. Figure Oscillator Connections. Figure Fault Detect. Figure Fixed Voltage Selection. Figure Calibration Data Flow Figure System Calibration Offset. Figure System Calibration Gain. Figure Typical Interface E2PROM CS5467 Figure Typical Connection Diagram
LIST TABLES
Table Interrupt Configuration Table Current Input Gain Ranges Table High-pass Filter Configuration Table Configuration Table Configuration Table Modes Table with E1MODE enabled
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OVERVIEW
CS5467 CMOS power measurement integrated circuit utilizing four analog-to-digital converters measure line voltages currents. Optionally, voltage2 channel used temperature measurement. calculates active, reactive, apparent power well peak voltage current. handles other system-related functions, such pulse output conversion, voltage sag, current fault, voltage zero crossing, line frequency, voltage tamper correction. CS5467 optimized interface current transformers shunt resistors current measurement, resistive dividers voltage transformers voltage measurement. full-scale ranges provided current inputs accommodate both types current sensors. CS5467's four differential inputs have common-mode input range from analog ground (AGND) positive analog supply (VA+). additional analog input (PFMON) provided allow application determine when power failure progress. monitoring unregulated power supply, application take required action when power loss occurs. on-chip voltage reference (nominally volts) generated provided analog output, VREFOUT. This reference supplied chip connecting reference voltage input, VREFIN. Alternatively, external voltage reference supplied reference input. Three digital outputs (E1, provide variety output signals and, depending mode selected, provide energy pulses, power failure indication, other choices. CS5467 includes three-wire serial host interface external microcontroller serial E2PROM. Signals include serial data input (SDI), serial data output (SDO), serial clock (SCLK), optionally chip select (CS), which allows CS5467 share signal with other devices. MODE input used control whether E2PROM will used instead host microcontroller.
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DESCRIPTION
Crystal Clock Output Positive Digital Supply Digital Ground Serial Clock Serial Data Ouput Chip Select Mode Select Differential Voltage Input Differential Voltage Input Voltage Reference Output Voltage Reference Input Differential Voltage Input Differential Voltage Input XOUT CPUCLK DGND SCLK MODE VIN1+ VIN1VREFOUT VREFIN VIN2+ VIN21 RESET PFMON IIN1+ IIN1VA+ AGND IIN2+ IIN2Crystal Serial Data Input Energy Output Energy Output Interrupt Reset Energy Output Power Fail Monitor Differential Current Input Differential Current Input Positive Analog Supply Analog Ground Differential Current Input Differential Current Input
Clock Generator Crystal Crystal Clock Output Control Pins Serial Data Serial Clock Serial Data Output Chip Select Mode Select Energy Output Reset Interrupt Serial Data Input Analog Inputs/Outputs Differential Voltage Inputs Differential Current Inputs Voltage Reference Output Voltage Reference Input Power Supply Connections Positive Digital Supply Digital Ground Positive Analog Supply Analog Ground Power Fail Monitor
positive digital supply. DGND Digital ground. positive analog supply. AGND Analog ground. PFMON Used monitor unregulated power supply resistive divider. PFMON voltage drops below limit, low-supply detect (LSD) Status register.
1,28
XOUT, Connect external quartz crystal. Alternatively, external clock supplied provide system clock device. CPUCLK Logic-level output from crystal oscillator. used clock external CPU.
SCLK Clocks serial data from when low. SCLK Schmitt-trigger input when MODE driven output when MODE high. Serial data output. Data clocked SCLK. input that enables serial interface when MODE driven output when MODE high. MODE High selects external E2PROM, selects external microcontroller. MODE includes weak internal pull-down therefore selects microcontroller mode connected.
Primarily active-low energy pulse outputs. These programmed output other conditions.
RESET active-low Schmitt-trigger input used reset chip. Active-low output, indicates that enabled condition occurred. Serial data input. Data clocked SCLK.
9,10 VIN1+, VIN1-, VIN2+, VIN2- Differential analog inputs voltage channels. 20,19, IIN1+, IIN1-, IIN2+, IIN2- Differential analog inputs current channels. 16,15
VREFOUT on-chip voltage reference output. Nominally referenced AGND. VREFIN voltage reference input. connected VREFOUT external reference.
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CHARACTERISTICS SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter Positive Digital Power Supply Positive Analog Power Supply Voltage Reference Specified Temperature Range Symbol VREFIN 3.135 4.75 5.25 5.25 Unit
ANALOG CHARACTERISTICS
characteristics specifications guaranteed over Recommended Operating Conditions. Typical characteristics specifications measured nominal supply voltages ±5%; AGND DGND VREFIN +2.5 voltages with respect DCLK 4.096 MHz.
Parameter Accuracy Active Power
(Note Gain Ranges Input Range 0.1% 100% Gain Ranges Input Range 0.1% 100% Gain Ranges Input Range 1.0% 100% Input Range 0.1% 1.0% Gain Ranges Input Range 1.0% 100% Input Range 0.1% 1.0% Gain Ranges Input Range 100%
Symbol PACTIVE QAVG
Unit
-0.25
±0.1 ±0.2 ±0.2 ±0.27 ±0.1 ±0.17 ±0.1 -115 ±0.4
22.5
mVP-P mVP-P µVrms µVrms µV/°C
Reactive Power
(Note
Power Factor
(Note
Current
(Note
IRMS VRMS CMRR
Voltage
(Note
Analog Inputs (All Inputs) Common Mode Rejection Common Mode Signal Analog Inputs (Current Inputs) Differential Input Range
[(IIN+) (IIN-)]
(DC,
(Gain (Gain (Gain (50,
Total Harmonic Distortion Crosstalk from Voltage input Full Scale Input Capacitance Effective Input Impedance Noise (Referred Input) Offset Drift (Without High-pass Filter) Gain Error
(Gain (Gain
(Note
Notes: Applies when option enabled. Applies when line frequency equal product output word rate (OWR) value Epsilon.
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ANALOG CHARACTERISTICS (Continued)
Parameter Analog Inputs (Voltage Inputs) Differential Input Range Symbol
[(VIN+) (VIN-)]
16.0 ±3.0 2.45 2.55
Unit mVP-P µVrms µV/°C
Total Harmonic Distortion Crosstalk from Current inputs Full Scale (50, Input Capacitance Gain Ranges Effective Input Impedance Noise (Referred Input) Offset Drift (Without High-pass Filter) Gain Error Temperature Temperature Accuracy Power Supplies Power Supply Currents (Active State)
(Note
(VA+ (VA+
PSCA PSCD PSCD
Power Consumption
(Note
Active State (VA+ Active State (VA+ Stand-by State Sleep State
Power Supply Rejection Ratio (50,
(Note
Voltage Current (Gain 50x) Current (Gain 10x)
(Note (Note
PSRR PMLO PMHI
PFMON Low-voltage Trigger Threshold PFMON High-voltage Power-on Trip Point Notes: Applies before system calibration.
outputs unloaded. inputs CMOS level. Measurement method PSRR: VREFIN tied VREFOUT, (zero-to-peak) sinewave imposed onto supply voltage pins. input pins both input channels shorted AGND. CS5467 then commanded continuous conversion acquisition mode, digital output data collected channel under test. (zero-to-peak) value digital sinusoidal output signal determined, this value converted into (zero-to-peak) value sinusoidal voltage (measured that would need applied channel's inputs, order cause same digital sinusoidal output. This voltage then defined Veq. PSRR dB):
PSRR
When voltage level PFMON sagging this voltage which been (because PFMON voltage fell below PMLO), this voltage level PFMON which permanently reset back
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VOLTAGE REFERENCE
Parameter Reference Output Output Voltage Temperature Coefficient Load Regulation Reference Input Input Voltage Range Input Capacitance Input Current VREFIN +2.4 +2.5 +2.6
(Note (Note
Symbol VREFOUT TCVREF
+2.4
+2.5
+2.6
Unit ppm/°C
Notes: voltage VREFOUT measured across temperature range. From these measurements following formula used calculate VREFOUT temperature coefficient.
TCVREF
(VREFOUT VREFOUT VREFOUT
MIN)
AMAX
TAMIN
Specified maximum recommended output source sink.
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DIGITAL CHARACTERISTICS
characteristics specifications guaranteed over Recommended Operating Conditions. Typical characteristics specifications measured nominal supply voltages ±5%; AGND DGND voltages with respect DCLK 4.096 MHz.
Parameter Symbol Master Clock Characteristics Master Clock Frequency Internal Gate Oscillator (Note DCLK Master Clock Duty Cycle CPUCLK Duty Cycle (Note Filter Characteristics Phase Compensation Range 4000 Input Sampling Rate DCLK MCLK/K Digital Filter Output Word Rate (Both channels) High-pass Filter Corner Frequency Full-scale Calibration Range (Referred Input) (Note FSCR Channel-to-channel Time-shift Error (Note Input/Output Characteristics High-level Input Voltage
Pins Except SCLK RESET SCLK RESET
-5.4
4.096 DCLK/8 DCLK/1024
+5.4
Unit
(VD+) (VD+)
0.48
Low-level Input Voltage
Pins Except SCLK RESET SCLK RESET
Low-level Input Voltage
Pins Except SCLK RESET SCLK RESET
Cout
High-level Output Voltage Low-level Output Voltage
Iout Iout +5V) Iout -2.5 +3.3V)
Input Leakage Current 3-state Leakage Current Digital Output Capacitance
(Note
Notes: measurements performed under static conditions. crystal used, frequency must remain between MHz. external oscillator used, frequency range MHz, must that MCLK between MHz. external MCLK used, duty cycle must between maintain this specification. frequency CPUCLK equal MCLK. minimum FSCR limited maximum allowed gain register value. maximum FSCR limited full-scale signal applied input. Configuration register (Config) bits PC[6:0] "0000000".
MODE pulled internal resistor.
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SWITCHING CHARACTERISTICS
characteristics specifications guaranteed over Recommended Operating Conditions. Typical characteristics specifications measured nominal supply voltages ±5%; AGND DGND voltages with respect Logic Levels: Logic Logic VD+.
Parameter Rise Times (Note Fall Times (Note Start-up Oscillator Start-up Time Serial Port Timing Serial Clock Frequency Serial Clock Timing Falling SCLK Rising Data Set-up Time Prior SCLK Rising Data Hold Time After SCLK Rising Timing Falling Driving SCLK Falling Data (hold time) Rising Hi-Z E2PROM mode Timing Serial Clock MODE setup time RESET Rising RESET rising falling falling SCLK rising SCLK falling rising rising driving MODE setup time SCLK rising
Pulse Width Pulse Width High Pulse Width High Pulse Width XTAL 4.096 (Note Digital Output
Symbol trise tfall
Digital Output
Unit
tost SCLK
DCLK DCLK DCLK
DCLK DCLK
Notes: Specified using points waveform interest. Output loaded with Oscillator start-up time varies with crystal parameters. This specification does apply when using external clock source.
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MSB-1 MSB-1 MSB-1 MSB-1
Write Timing (Not Scale)
MSB-1 MSB-1 MSB-1
STOP Last
UNKNOW
SCLK
MSB-1
Read Timing (Not Scale)
MODE
RESET
SCLK
E2PROM
mode Sequence Timing (Not Scale)
Figure CS5467 Read Write Timing Diagrams DS714F1
CS5467
SWITCHING CHARACTERISTICS (Continued)
Parameter Timing Period Pulse Width Rising Edge Falling Edge Setup and/or Falling Edge Falling Edge Falling Edge
(Note
Symbol tperiod
Unit
Notes: Pulse output timing specified DCLK 4.096 MHz, E2MODE E3MODE[1:0] Refer Energy Pulse Outputs page more information pulse output pins. Timing proportional frequency DCLK.
tperiod tperiod
Figure Timing Diagram
ABSOLUTE MAXIMUM RATINGS
WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes. Parameter Power Supplies
(Notes Positive Digital Positive Analog (Notes
Symbol IOUT
(Note Analog Pins Digital Pins
-0.3 -0.3 -0.3
+6.0 +6.0 (VA+) (VD+)
Unit
Input Current, Except Supplies Output Current, Except VREFOUT Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
VINA VIND Tstg
Notes: AGND must satisfy [(VA+) (AGND)] AGND must satisfy [(VD+) (AGND)] Applies pins including continuous over-voltage conditions analog input pins. Transient current will cause latch-up. Maximum input current power supply Total power dissipation, including input currents output currents. DS714F1
CS5467
V1OFF V1GAIN
VHPF1 IHPF1
I1OFF
I1GAIN
Figure Signal Flow Measurements
SIGNAL PATH DESCRIPTION
data flow voltage current measurement other calculations shown Figures "anti-sinc" filters, used compensate amplitude roll-off decimation filters.
Analog-to-Digital Converters
Voltage1 channel voltage2/temperature channel second-order delta-sigma modulators current channels fourth-order delta-sigma modulators convert analog inputs single-bit digital data streams. converters sample rate DCLK/8. This high sampling provides wide dynamic range simplifies anti-alias filter design.
Phase Compensation
Phase compensation changes phase current relative voltage changing sampling time decimation filters. amount phase shift bits PC[7:0] Configuration register (Config) channel bits PC[7:0] Control register (Ctrl) channel Phase compensation, PC[7:0] signed two's complement binary value range -1.0 almost +1.0 output word rate (OWR) samples. sample rate 4000 delay range ±250 phase shift ±4.5° ±5.4° step size would 0.0352° 0.0422° this sample rate.
Decimation Filters
single-bit modulator output data widened bits down-sampled DCLK/1024 with low-pass decimation filters. These decimation filters third-order Sinc. Their outputs passed through third-order
V2OFF
V2GAIN
VHPF2 IHPF2 Control Register
I2OFF I2GAIN
Figure Signal Flow Measurements
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Offset Gain Correction
system chip inherently have gain offset errors which removed using gain offset registers. (See Section System Calibration page 40). Each measurement channel registers. every channel, output filter added offset register multiplied gain register. interest, passes more information, High-pass Filters page filter multiplexers drive result registers.
Low-Rate Calculations
Low-rate results derived from sample-rate results integrated over samples, where value stored Cycle Count register. low-rate interval sample interval multiplied
High-pass Filters
Optional high-pass filters (HPF Figures remove from selected signal paths. Subsequently, will also removed from power, low-rate results. (see Figures Each energy channel current voltage path. enabled only path, phase-matching filter (PMF) applied other path which matches amplitude phase delay band
Results
root mean square (RMS Figure calculations performed instantaneous voltage current samples, using formula:
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V1ACOFF (V2ACOFF)
ACOFF ACOFF)
Figure Low-rate Calculations
Power Energy Results
instantaneous voltage current samples multiplied obtain instantaneous power (P1, (see Figure product then averaged over conversions compute active power (P1AVG, P2AVG). Apparent power (S1, product voltage current shown:
Active
Quadrature power (Q1, sample rate results obtained multiplying instantaneous current (I1, instantaneous quadrature voltage (V1Q, V2Q) which created phase shifting instantaneous voltage (V1, degrees using first-order integrators. (See Figure gain these integrators inversely related line frequency, their gain corrected Epsilon register, which based line frequency. Reactive power (Q1Avg, Q2AvG) generated integrating instantaneous quadrature power over samples. Active power (P1AVG, P2AVG), apparent power (S1, S2), reactive power (Q1AVG, Q2AVG) channels summed then divided calculation results placed EPULSE, SPULSE, QPULSE registers which configured drive energy pulse outputs. (See Figure
OVF=
Power factor (PF1, PF2) active power divided apparent power shown below. sign power factor determined active power.
Active
Wideband reactive power (Q1WB, Q2WB) calculated doing vector subtraction active power from apparent power.
P1AVG
P2AVG
EPULSE
EACCM
OVF=
Q1AVG
SPULSE
SACCM
OVF=
Q2AVG
QPULSE
QACCM
PulseRate
Figure Two-channel Power Summation DS714F1
CS5467
Peak Voltage Current
Peak current (I1PEAK, I2PEAK) peak voltage (V1PEAK, V2PEAK) largest current voltage samples detected previous low-rate interval. chip's power supply, from inductance from nearby transformer. These offsets either positive negative, indicating crosstalk coupling either phase phase with applied voltage input. power offset registers compensate either condition. this feature, measure average power load using either Single Continuous Conversion commands. Take measured result (from P1AVG (P2AVG) register), invert (negate) value write associated power offset register, P1OFF (P2OFF).
4.10 Power Offset
power offset registers, P1OFF (P2OFF) used offset erroneous power sources resident system originating from power line. Residual power offsets usually caused crosstalk into current paths from voltage paths from ripple meter
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DESCRIPTIONS
Analog Pins
CS5467 four differential inputs: VIN1±, VIN2±, IIN1±, IIN2± voltage1, voltage2, current1, current2 inputs, respectively. single-ended power fail monitor input, voltage reference input, voltage reference output also available.
5.1.6 Crystal Oscillator
external quartz crystal connected XOUT pins shown Figure reduce system cost, each supplied with on-chip, phase-shifting capacitor ground.
XOUT
5.1.1 Voltage1 Voltage2 Inputs
output line voltage resistive divider transformer connected VIN1+ (VIN2+) VIN1(VIN2-) input pins CS5467. voltage channel equipped with 10x, fixed-gain amplifier. full-scale signal level that applied voltage channel ±250 input signal sine wave, maximum voltage 176.78 mVRMS which approximately 70.7% maximum peak voltage.
Oscillator Circuit
DGND
5.1.2 Current1 Current2 Inputs
output current-sensing resistor transformer connected IIN1+ (IIN2+) IIN1- (IIN2-) input pins CS5467. accommodate different current-sensing elements, current channel incorporates programmable gain amplifier (PGA) with selectable input gains. full-scale signal level current channels ±250 input signal sine wave, maximum voltage 35.35 mVRMS 176.78 mVRMS which approximately 70.7% maximum peak voltage.
Figure Oscillator Connections
Alternatively, external clock source connected pin.
Digital Pins 5.2.1 Reset Input
active-low RESET pin, when asserted, will halt CS5467 operations reset internal hardware registers states. When de-asserted, initialization sequence begins, setting default register values.
5.1.3 Power Fail Monitor Input
analog input (PFMON) provided determine when power loss imminent. connecting resistive divider from unregulated meter power supply PFMON input, interrupt generated, Supply Detected (LSD) Status register monitored indicate low-supply conditions. PFMON input comparator that trips around level voltage reference input (VREFIN).
5.2.2 Clock Output
logic-level clock output (CPUCLK) provided crystal frequency drive external microcontroller clock. phase choices available.
5.2.3 Interrupt Output
indicates enabled Internal Status register (Status) set. Status register bits indicate conditions such data ready, modulator oscillations, supply, voltage sag, current faults, numerical overflows, result updates.
5.1.4 Voltage Reference Input
CS5467 requires stable voltage reference applied VREFIN pin. This reference supplied from external voltage reference from VREFOUT output. bypass capacitor least recommended VREFIN pin.
5.2.4 Energy Pulse Outputs
CS5467 provides three pins (E1, pulse energy outputs. These pins also used output other conditions, such voltage1 sign, power fail monitor, energy sign.
5.1.5 Voltage Reference Output
CS5467 generates reference (VREFOUT). suitable driving VREFIN pin, very little fan-out capacity recommended driving external circuits.
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5.2.5 Serial Interface
CS5467 provides pins, SCLK, SDI, SDO, MODE communication between host microcontroller serial E2PROM CS5467. MODE input that, when high, indicates CS5467 that serial E2PROM being used instead host microcontroller. weak pull-down allowing left unconnected microcontroller mode used. SCLK used shift qualify serial data. Serial data changes result falling edge SCLK valid during rising edge. Schmitt-trigger input host microcontrollers, driven output serial E2PROMs. serial data input CS5467. serial data output from CS5467. It's output drivers disabled whenever de-asserted, allowing other devices drive line. chip select input serial bus. high logic level de-asserts tri-stating clearing serial interface. logic level enables serial port. This tied systems requiring multiple drivers. driven output when interfacing serial E2PROMs.
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SETTING CS5467
Clock Divider
internal clock CS5467 needs operate around MHz. However, using internal clock divider, higher crystal frequency used. This important when driving external microcontroller requiring faster clock using CPUCLK output. divide ratio from crystal input internal clock selected with Configuration register (Config) bits K[3:0]. range value zero results setting path within channel, phase matching filter (PMF) applied other path within that channel. filter matches amplitude phase response band interest, passes
VHPF IHPF Filter Configuration filter Voltage Current Current, Voltage Voltage, Current Current Voltage
Clock Inversion
default, CPUCLK inverted from XIN. Setting Configuration register iCPU removes this inversion. This useful when phase adds more noise system than other.
Table High-pass Filter Configuration
Cycle Count
Low-rate calculations, such average power voltage current integrate over several output word rate (OWR) samples. duration this averaging window Cycle Count register. default, Cycle Count 4000 second output word rate [OWR] 4000 Hz). minimum value Cycle Count
Interrupt Behavior
behavior controlled IMODE IINV bits Configuration register shown.
IMODE IINV
Energy Pulse Outputs
default, outputs total active energy, total reactive energy, sign both active reactive energy. (See Figure Timing Diagram page 13.) Three pairs bits Mode Control (Modes) register control operation these outputs. These bits named E1MODE[1:0], E2MODE[1:0], E3MODE[1:0]. Some combinations these bits override others, read following paragraphs carefully. output energy sign, total apparent energy. Table lists functions controlled E2MODE[1:0] Modes register. Note: E2MODE[1:0]=3 special mode.
E2MODE1 E2MODE0 output
Active-low Level Active-high Level Pulse High Pulse
Table Interrupt Configuration
IMODE duration pulse will DCLK cycles, where DCLK MCLK/K.
Current Input Gain Ranges
Control register bits I1gain (I2gain) select input range current inputs.
I1gain, I2gain Maximum Input Gain
Energy Sign Total Apparent Energy Used Enable E1MODE
±250
Table Current Input Gain Ranges
High-pass Filters
Mode Control (Modes) register bits VHPF IHPF activate voltage current paths, respectively. Each energy channel separate VHPF IHPF bits. When high-pass filter enabled only
Table Configuration
output total reactive energy, power fail monitor status, voltage1 sign, total apparent energy. Table lists functions controlled
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E3MODE[1:0] Modes register when E1MODE enabled.
E3MODE1 E3MODE0 output
Load Threshold
Load Threshold register (LoadMIN) used zero contents EPULSE QPULSE registers their magnitude less than LoadMIN register value.
Total Reactive Energy Power Fail Monitor Voltage1 Sign Total Apparent Energy
Energy Pulse Width
Note: Energy Pulse Width (PulseWidth) only applies pins that configured output pulses. When configured output steady-state signals, such voltage1 sign, power fail monitor, energy sign, pulse widths output rates apply. pulse width time (tpw) Figure value PulseWidth register which integer multiple sample output word rate (OWR). 4000 period PulseWidth default, PulseWidth
Table Configuration
When both E2MODE bits high, E1MODE bits enabled, allowing active, apparent, reactive, wide band reactive energy both energy channels output Table lists functions with E1MODE enabled.
E1MODE1 E1MODE0 outputs
6.10 Energy Pulse Rate
Active Energy Apparent Energy Reactive Energy Wideband Reactive full-scale pulse frequency enabled pins value PulseRate output word rate (OWR)/2. actual pulse frequency full-scale pulse frequency multiplied pulse register's (EPULSE, SPULSE, QPULSE) value. Example: output word rate (OWR) 4000 PulseRate register 0.05, full-rate pulse frequency 0.05 4000 EPULSE register, driving 0.4567, pulse output rate will 0.4567 45.67
Table Modes
When E1MODE bits enabled, outputs either power fail monitor status, sign outputs. Table list functions using E3MODE[1:0] Modes register when E1MODE enabled
E3MODE1 E3MODE0 output
6.11 Voltage Sag/Current Fault Detection
Voltage detection used determine when averaged voltage falls below predetermined level specified interval time. Current fault detection determines when averaged current falls below predetermined level specified interval time. specified interval time (duration) value V1SagDUR (V2SagDUR) I1FaultDUR (I2FaultDUR) registers. Setting these zero (default) disables detect feature given channel. value output word rate (OWR) samples. predetermined level values V1SagLEVEL (V2SagLEVEL) I1FaultLEVEL (I2FaultLEVEL) registers.
Power Fail Monitor Energy Sign used used
Table with E1MODE enabled
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each enabled input channel, measured value rectified compared associated level register. Over duration window, number samples above below level counted. number samples below level exceeds number samples above, Status register V1SAG (V2SAG), I1FAULT (I2FAULT) set, indicating fault condition. (see Figure updated. Voltage2 register (V2) will update during temperature measurement, resume measurement afterwards. Temperature measurements stored Temperature register which, default, configured range ±128 degrees Celsius (°C) scale. application program change both scale range Temperature changing Temperature Gain (TGAIN) Temperature Offset (TOFF) registers. values must known transistor's degree, transistor's degrees. time this publication, these values are:
(per degree) 0.2769523 mV/°C
VBE0 79.2604368 determine values write TGAIN TOFF, following formulae:
TGAIN ADFS TOFF -VBE0 ADFS Figure Fault Detect
6.12 Epsilon
Epsilon register used gain phase shift used quadrature power calculation. value Epsilon register ratio line frequency output word rate (OWR). default, 50/4000 (0.0125), line 4000 sample (OWR) frequencies. line frequency, 60/4000 (0.015). Other output word rates (OWR) used.
Epsilon also calculated automatically CS5467 setting Mode Control (Modes) register. Frequency Update (FUP) Status register every time Epsilon register been automatically updated.
above equations, ADFS full-scale input range temperature converter 833.333 desired full-scale range Temperature register. binary exponents positions binary point these registers. Celsius scale (°C) cover chip's operating temperature range -40°C +85°C, Temperature register range needs ±128 degrees. should degrees.
TGAIN 833.333 0.2769523 131072
3081155 (0x2F03C3)
TOFF -79.2604368 833.333 8388608 -797862 (0xF3D35A)
These actual default values these registers.
TGAIN TOFF also used calibrate gain and/or offset temperature sensor converter. (See Section System Calibration page 40).
6.13 Temperature Measurement
on-chip temperature sensor designed measure temperature optionally compensate temperature drift voltage reference. uses transistor determine temperature. CS5467, voltage2 temperature multiplexed channel. initiate temperature measurement, write Temperature Measurement (TMEAS) register. TMEAS will through counts back Wait TMEAS return When done, Temperature updated. Status register also indicates when Temperature register
Kelvin (°K) scale, simply times ADFS TOFF since 273°K,. will also need more range. Since -40°C +85°C 233°K 358°K, degrees should used TGAIN calculation. Fahrenheit (°F) scale, multiply times ADFS TOFF since 32°F. will also want degrees cover -40°C +85°C range.
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USING CS5467
Initialization
CS5467 uses power-on-reset circuit (POR) provide internal reset until analog voltage reaches RESET input also used application circuit reset part. After RESET removed oscillator stable, initialization program executed default register values. Software Reset command also provided allow application initialization program without removing power asserting RESET. application should avoid sending commands during initialization. DRDY Status register indicates when initialization program completed. entering stand-by state. When returning from sleep mode, complete initialization occurs.
Voltage Tamper Correction
CSS5467 provides compensation meter tampering voltage channels. application detects that voltage input been impaired choose fixed internal voltage reference setting VFIX Modes register. value this reference (VFRMS) default 0.707107 (full-scale RMS) changed application program. (See figure
Power-down States
CS5467 power-down states, stand-by sleep. stand-by state, circuitry except voltage reference crystal oscillator powered off. sleep state, circuitry except instruction decoder powered off. return device active state, send Wakeup/Halt command device. When returning from stand-by mode, registers will retain their contents prior
Figure Fixed Voltage Selection
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Command Interface
Commands data transferred most-significant (MSB) first. Figure page defines serial port timing. Commands clocked using SCLK. They single byte bits) long fall into four basic types: Register Read Register Write Synchronizing Instructions Register reads will cause four bytes register data clocked out, first SCLK. During this time, other commands clocked pin. Other commands will interrupt read data, except another register read, which will cause read data appear SDO. Synchronizing sent while read data being clocked other commands need sent. Synchronizing commands also used synchronize serial port byte boundary. RESET pins will also synchronize serial port. Register writes require three bytes write data follow, clocked pin, first SCLK. Instructions commands that will interrupt instruction currently executing begin instruction. These include conversions, calibrations, power control, soft reset. (See Section Commands page 25).
Register Paging
Read Write commands access registers within specified page. Register Page Select register's (Page) default value access registers another page, write desired page number Page register. Page register always address accessible from within page.
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Commands
commands byte bits) long. Many command values unused should written application program. commands except register reads, register writes, synchronizing commands will abort conversion, calibration, initialization sequence currently executing. This includes reset. commands other than reads synchronizing should executed until reset sequence completes.
7.6.1 Conversion
Executes conversion (measurement) program. Continuous/Single Conversion Perform Single Conversion (0xE0) Perform Continuous Conversion (0xE8)
7.6.2 Synchronization (SYNC0 SYNC1)
SYNC
serial interface bidirectional. While reading data output, input must receiving commands. command needed during read, SYNC0 SYNC1 commands sent while read data received SDO. serial port normally initialized de-asserting alternative method initialization send more SYNC1 commands followed SYNC0. This useful systems where used tied low.
7.6.3 Power Control (Stand-by, Sleep, Wake-up/Halt Software Reset)
CS5467 power-down states, stand-by sleep. stand-by, circuitry except voltage reference clocks turned off. sleep mode, circuitry except command decoder turned off. Wake-up/Halt command restores full-power operation after stand-by issues hardware reset after sleep. Software Reset command program that emulates reset power control function. S[1:0] Software Reset Sleep Wake-up/Halt Stand-by
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7.6.4 Calibration
CAL5 CAL4 CAL3 CAL2 CAL1 CAL0
CS5467 perform gain offset calibrations using either signals. Proper input levels must applied current inputs voltage input before performing calibrations. CAL[5:4]* Offset Gain Offset Gain 0001 Current Channel 0010 Voltage Channel 0100 Current Channel 1000 Voltage Channel Anywhere from channels calibrated simultaneously.
CAL[3:0]
Note:
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7.6.5 Register Read Write
Read Write commands provide access on-chip registers. After Read command, addressed data clocked SCLK. After Write command, bits write data must follow. data transferred addressed register after 24th data received. Registers organized into pages addresses each. access desired page, write number Page register address Write/Read control Read Write Register address.
RA[4:0]
Page Registers Address RA[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 11111 Name Config P1AVG I1RMS V1RMS P2AVG I2RMS V2RMS Q1AVG Status Q2AVG I1PEAK V1PEAK I2PEAK V2PEAK Mask Ctrl EPULSE SPULSE QPULSE Page Description Configuration Instantaneous Current Channel Instantaneous Voltage Channel Instantaneous Power Channel Active Power Channel Current Channel Voltage Channel Instantaneous Current Channel Instantaneous Voltage Channel Instantaneous Power Channel Active Power Channel Current Channel Voltage Channel Reactive Power Channel Instantaneous Quadrature Power Channel Internal Status Reactive Power Channel Instantaneous Quadrature Power Channel Peak Current Channel Peak Voltage Channel Apparent Power Channel Power Factor Channel Peak Current Channel Peak Voltage Channel Apparent Power Channel Power Factor Channel Interrupt Mask Temperature Control Active Energy Pulse Output Apparent Energy Pulse Output Reactive Energy Pulse Output Register Page Select
Warning: write unpublished register locations.
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Page1 Registers Address RA[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10011 10100 10101 10110 10111 11001 11010 11011 11100 11101 11111 Name I1OFF I1GAIN V1OFF V1GAIN P1OFF I1ACOFF V1ACOFF I2OFF I2GAIN V2OFF V2GAIN P2OFF I2ACOFF V2ACOFF PulseWidth PulseRate Modes Epsilon Q1WB Q2WB TGAIN TOFF TSETTLE LoadMIN VFRMS Time Page Description Current Offset Channel Current Gain Channel Voltage Offset Channel Voltage Gain Channel Power Offset Channel Current (RMS) Offset Channel Voltage (RMS) Offset Channel Current Offset Channel Current Gain Channel Voltage Offset Channel Voltage Gain Channel Power Offset Channel Current (RMS) Offset Channel Voltage (RMS) Offset Channel Pulse Output Width Pulse Output Rate (frequency) Mode Control Ratio Line Sample Frequency Cycle Count (Number Samples Low-rate Interval) Wideband Reactive Power from Power Triangle Channel Wideband Reactive Power from Power Triangle Channel Temperature Sensor Gain Temperature Sensor Offset Filter Settling Time Conversion Startup Load Threshold Voltage Fixed Reference System Gain System Time samples) Register Page Select
Page2 Registers Address Page5 Register Address RA[4:0] 11010 11111 Name TMEAS Page Description Temperature Measurement Register Page Select RA[4:0] 00000 00001 00100 00101 01000 01001 01100 01101 11111 Name V1SagDUR V1SagLEVEL I1FaultDUR I1FaultLEVEL V2SagDUR V2SagLEVEL I2FaultDUR I2FaultLEVEL Page Description Duration Channel Level Channel Fault Duration Channel Fault Level Channel Duration Channel Level Channel Fault Duration Channel Fault Level Channel Register Page Select
Warning: write unpublished register locations.
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REGISTER DESCRIPTIONS
"Default" states after power-on reset write unpublished register bit. write unpublished register address.
Page Register
8.1.1 Page Address: Write-only, written from page.
Default Register Read Write commands contain only address bits. internal address CS5467 bits wide. Therefore, registers organized into "Pages". There pages registers each. Page register provides high-order address bits selects register pages. pages used,
Page write-only integer containing bits.
Page Registers
8.2.1 Configuration (Config) Address:
IMODE iCPU IINV
Default (K=1) PC[7:0] Phase compensation channel Sets delay voltage, relative current. Phase signed range -1.0 value sample (OWR) intervals. Allows pins configured open-drain outputs. Normal Outputs Open-drain Outputs Interrupt configuration. Selects behavior. Logic Level When Asserted High Logic Level When Asserted Low-going Pulse Interrupt High-going Pulse Interrupt Inverts CPUCLK output. Default Invert CPUCLK. Clock divider. Divides MCLK generate internal clock DCLK. (DCLK MCLK/K). unsigned range When zero, reset,
IMODE, IINV
iCPU
K[3:0]
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8.2.2 Instantaneous Current (I1, I2), Voltage (V1, V2), Power (P1,
Address: (I1), (V1), (P2), (I2), (V2), (P2)
2-17
2-23
(I2) (V2) contain instantaneous current voltage, respectively, which multiplied yield instantaneous power, (P2). These two's complement values range -1.0 value 1.0, with binary point right MSB.
8.2.3 Active Power (P1AVG P2AVG
Address: (P1AVG (P2AVG
-(20) 2-17 2-18 2-19 2-20 2-21 2-22 2-23
Instantaneous power averaged over each low-rate interval samples) compute active power, P1AVG (P2AVG). These two's complement values range -1.0 value 1.0, with binary point right MSB.
8.2.4 Current (I1RMS I2RMS Voltage (V1RMS V2RMS
Address: (I1RMS), (V1RMS), (I2RMS), (V2RMS)
2-18 2-19 2-20 2-21 2-22 2-23 2-24
I1RMS (I2RMS) V1RMS (V2RMS) contain root mean square (RMS) values (I2) (V2), calculated each low-rate interval. These unsigned values range value 1.0, with binary point left MSB.
8.2.5 Instantaneous Quadrature Power (Q1,
Address: (Q1), (Q2)
2-17 2-18 2-19 2-20 2-21 2-22 2-23
Instantaneous quadrature power, (Q2), product voltage1 (voltage2) shifted degrees current1 (current2). These two's complement values range -1.0 value 1.0, with binary point right MSB.
8.2.6 Reactive Power (Q1Avg Q2AVG
Address: (Q1AVG), (Q2AVG)
-(20) 2-17 2-18 2-19 2-20 2-21 2-22 2-23
Reactive power Q1AVG (Q2AVG) (Q2) averaged over every samples. These two's complement values range -1.0 value 1.0, with binary point right MSB.
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8.2.7 Peak Current (I1PEAK, I2PEAK Peak Voltage (V1PEAK, V2PEAK
Address: (I1PEAK), (V1PEAK), (I2PEAK), (V2PEAK)
-(20) 2-17 2-18 2-19 2-20 2-21 2-22 2-23
Peak current, I1PEAK (I2PEAK) peak voltage, V1PEAK (V2PEAK) instantaneous current voltage samples with greatest magnitude detected during last low-rate interval. These two's complement values range -1.0 value 1.0, with binary point right MSB.
8.2.8 Apparent Power (S1,
Address: (S1), (S2)
-(20) 2-17 2-18 2-19 2-20 2-21 2-22 2-23
Apparent power (S2) product V1RMS I1RMS (V2RMS I2RMS), These two's complement values range value 1.0, with binary point right MSB.
8.2.9 Power Factor (PF1, PF2)
Address: (PF1), (PF2)
-(20) 2-17 2-18 2-19 2-20 2-21 2-22 2-23
Power factor calculated dividing active power apparent power. sign determined active power sign. These two's complement values range -1.0 value 1.0, with binary point right MSB.
8.2.10 Temperature Address:
-(27) 2-10 2-11 2-12 2-13 2-14 2-15 2-16
contains results from on-chip temperature measurement. default, uses Celsius scale, two's complement value range -128.0 value 128.0 (oC), with binary point right rescaled application using TGAIN TOFF registers.
8.2.11 Active, Apparent, Reactive Energy Pulse Outputs (EPULSE SPULSE QPULSE
Address: (EPULSE), (SPULSE), (QPULSE)
-(20
2-17
2-23
These drive pulse outputs when configured These two's complement values range -1.0 value 1.0, with binary point right MSB. Refer Power Energy Results page
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8.2.12 Internal Status (Status) Interrupt Mask (Mask)
Address: (Status); (Mask)
DRDY E2OR I2OR I1ROR V2OD V2OR V1ROR I2OD CRDY E1OR V1OD I2ROR I1FAULT I1OD V2ROR V1SAG I1OR I2FAULT V1OR V2SAG
Default
(Status), (Mask)
Status register indicates variety conditions within chip. Writing Status register will clear that condition that been removed. Writing effect. Mask register used control activation pin. Writing Mask register will allow corresponding Status register activate when set. DRDY I1OR (I2OR) V1OR (V2OR) CRDY I1ROR (I2ROR) Data Ready. During conversion, this indicates that low-rate results have been updated. indicates completion other commands reset sequence. Current Range. when measured current would cause (I2) register overflow. Voltage Range. when measured voltage would cause (V2) register overflow. Conversion Ready. Indicates that sample rate (output word rate) results have been updated. Current Range. when current would cause I1RMS (I2RMS) register overflow.
V1ROR (V2ROR) Voltage Range. when voltage would cause V1RMS (V2RMS) register overflow. E1OR (E2OR) Energy Range. when average power would cause P1AVG (P2AVG) overflow.
I1FAULT (I2FAULT)Indicates when current fault condition occurred. V1SAG (V2SAG) V1OD (V2OD) I1OD (I2OD) Indicates when voltage condition occurred. Indicates when Temperature register been updated. Modulator oscillation been detected voltage1 (voltage2) A/D. Modulator oscillation been detected current1 (current2) A/D. Supply Detect. when voltage PFMON falls below specified level. cannot reset until voltage rises above specified high level. Frequency Updated. Indicates Epsilon register been updated. Invalid Command. Normally logic when invalid command received. also indicate loss serial command synchronization part need re-initialized.
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8.2.13 Control (Ctrl) Address:
I1gain I2gain INTOD NOCPU NOOSC STOP
Default PC[7:0] I1gain (I2gain) Phase compensation channel Sets delay voltage relative current. Phase signed range -1.0 value sample (OWR) intervals. Sets gain current1 (current2) input. Gain ±250mV range. Gain ±50mV range. Terminates E2PROM command sequence used). Action Stop E2PROM Commands. Converts output open drain output. Normal Output Open-drain Output Saves power disabling CPUCLK output pin. CPUCLK Enabled CPUCLK Disabled Disables crystal oscillator, making logic-level input. Crystal Oscillator Enabled Crystal Oscillator Disabled
STOP
INTOD
NOCPU
NOOSC
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Page Registers
8.3.1 Offset Current (I1OFF I2OFF Voltage (V1OFF V2OFF
Address: (I1OFF (V1OFF (I2OFF (V2OFF
-(20) 2-17 2-18 2-19 2-20 2-21 2-22 2-23
Default offset registers I1OFF V1OFF (I2OFF V2OFF initialized zero reset. During offset calibration, selected registers written with inverse offset measured. application program also write offset register values. These two's complement values range -1.0 value 1.0, with binary point right MSB.
8.3.2 Gain Current (I1GAIN I2GAIN Voltage (V1GAIN V2GAIN
Address: (I1GAIN (V1GAIN (I2GAIN (V2GAIN
2-16 2-17 2-18 2-19 2-20 2-21 2-22
Default Gain registers I1GAIN V1GAIN (I2GAIN V2GAIN) initialized reset. During gain calibration, selected register written with multiplicative inverse gain measured. These unsigned fixed-point values range value 4.0, with binary point right second MSB.
8.3.3 Power Offset (P1OFF P2OFF Address: (P1OFF (P2OFF
-(20) 2-17 2-18 2-19 2-20 2-21 2-22 2-23
Default Power offset P1OFF (P2OFF added instantaneous power averaged over low-rate interval yield P1AVG (P2AVG register results. used reduce systematic energy errors. These two's complement values range -1.0 value 1.0, with binary point right MSB.
8.3.4 Offset Current (I1ACOFF I2ACOFF Voltage (V1ACOFF V2ACOFF
Address: (I1ACOFF (V1ACOFF (I2ACOFF (V2ACOFF
-(20) 2-17 2-18 2-19 2-20 2-21 2-22 2-23
Default offset registers I1ACOFF V1ACOFF (VACOFF V2ACOFF initialized zero reset. These added results before being stored result registers. They used reduce systematic errors results. These two's complement values range -1.0 value 1.0, with binary point right MSB.
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8.3.5 Mode Control (Modes) Address:
IHPF2 VFIX E1MODE1 VHPF1 E1MODE0 IHPF1 E3MODE1 E2MODE1 E3MODE0 E2MODE0 VHPF2
Default VFIX internal voltage reference instead voltage input average active power. voltage input. internal voltage reference, VFRMS. alternate output mode (when enabled E2MODE). P1AVG, P2AVG Q1AVG, Q2AVG Q1WB, Q2WB Output Mode Energy Sign Total Apparent Energy Used Enable E1MODE High-pass Filter Enable Energy Channel Filter Current, Voltage Voltage, Current both Voltage Current High-pass Filter Enable Energy Channel Filter Current, Voltage Voltage, Current both Voltage Current Output Mode (with E1MODE disabled) Total Reactive Energy (default) Power Fail Monitor Voltage1 Sign Total Apparent Energy Output Mode (with E1MODE enabled) Power Fail Monitor Energy Sign Used Used Positive Energy Only. Suppresses negative values P1AVG P2AVG. negative value calculated, zero will stored instead. Enables automatic line frequency measurement which sets Epsilon every time line frequency measurement completes. Epsilon used control gain degree phase shift integrator used quadrature power calculations.
E1MODE[1:0]
E2MODE[1:0]
VHPF2:IHPF2
VHPF1:IHPF1
E3MODE[1:0]
E3MODE[1:0]
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8.3.6 Line Sample Frequency Ratio (Epsilon) Address:
2-17
2-23
Default 0.0125 (4.0 0.0125
Epsilon ratio input line frequency output word rate (OWR). either written application program calculated automatically from line frequency (from voltage input) using Modes register. two's complement value range -1.0 value 1.0, with binary point right MSB. Negative values used.
8.3.7 Pulse Output Width (PulseWidth) Address:
Default (250 kHz)
PulseWidth sets duration energy pulses. actual pulse duration contents PulseWidth divided output word rate (OWR). PulseWidth integer range 8,388,607.
8.3.8 Pulse Output Rate (PulseRate) Address:
-(20) 2-17 2-18 2-19 2-20 2-21 2-22 2-23
Default=
PulseRate sets full-scale frequency pulse outputs. sample rate, maximum pulse rate kHz. This two's complement value range value with binary point left MSB.
Refer 6.10 Energy Pulse Rate page more information.
8.3.9 Cycle Count Address:
Default 4000 Determines number output word rate (OWR) samples calculating low-rate results. Cycle Count integer range 8,388,607. Values less than should used.
8.3.10 Wideband Reactive Power (Q1WB Q2WB
Address: (Q1WB (Q2WB
2-17 2-18 2-19 2-20 2-21 2-22 2-23
Wideband reactive power calculated using vector subtraction. (See Section Power Energy Results page 16). value signed, range value 1.0. binary point right MSB.
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8.3.11 Temperature Gain (TGAIN Address:
2-11
2-17
Default 0x2F02C3 Refer 6.13 Temperature Measurement page more information.
8.3.12 Temperature Offset (TOFF Address:
-(20
2-17
2-23
Default 0xF3D35A Refer 6.13 Temperature Measurement page more information.
8.3.13 Filter Settling Time Conversion Startup (TSETTLE Address:
Default Sets number output word rate (OWR) samples that will used allow filters settle beginning Conversion Calibration commands. This integer range 8,388,607 samples.
8.3.14 Load Threshold (LoadMIN Address:
-(20) 2-17 2-18 2-19 2-20 2-21 2-22 2-23
Default
LoadMIN used load threshold. When magnitude EPULSE register less than LoadMIN, EPULSE will zeroed. magnitude QPULSE register less than LoadMIN, Qpulse will zeroed. LoadMIN two's compliment value range -1.0 value 1.0, with binary point right MSB. Negative values used.
8.3.15 Voltage Fixed Reference (VFRMS Address
-(20) 2-17 2-18 2-19 2-20 2-21 2-22 2-23
Default 0.7071068 (full scale RMS) application program detects that meter possibly been tampered with such manner that voltage input longer working, choose this internal reference instead disabled voltage input setting VFIX Modes register. This two's complement value range value 1.0, with binary point right MSB. Negative values used.
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8.3.16 System Gain Address:
2-16
2-22
Default 1.25 System Gain applied channels. default, 1.25, finely adjusted compensate voltage reference error. two's complement value range -2.0 value 2.0, with binary point right second MSB. Values should kept within 1.25.
8.3.17 System Time (Time) Address:
Default System Time (Time) measured output word rate (OWR) samples. This unsigned integer range 16,777,215 samples. kHz, will overflow every hour, minutes, seconds. Time used application manage real-time events.
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Page Registers
8.4.1 Voltage Current Fault Duration (V1SagDUR V2SagDUR I1FaultDUR I2FaultDUR
Address: (V1SagDUR (V2SagDUR (I1FaultDUR (I2FaultDUR
Default Voltage duration, V1SagDUR (V2SagDUR) current fault duration, I1FaultDUR (I2FaultDUR) determine count output word rate (OWR) samples utilized determine fault event. These integers range 8,388,607 samples. value zero disables feature.
8.4.2 Voltage Current Fault Level (V1SagLEVEL V2SagLEVEL I1FaultLEVEL I2FaultLEVEL
Address: (V1SagLEVEL (V2SagLEVEL (I1FaultLEVEL (I2FaultLEVEL
-(20) 2-17 2-18 2-19 2-20 2-21 2-22 2-23
Default Voltage level, V1SagLEVEL (V2SagLEVEL current fault level, I1FaultLEVEL (I2FaultLEVEL establish input level below which fault triggered. These two's complement values range -1.0 value 1.0, with binary point right MSB. Negative values used.
Page Register
8.5.1 Temperature Measurement (TMEAS Address:
Default Temperature Measurement (TMEAS) register used cycle-steal voltage channel2 temperature measurement. Writing causes temperature measured Temperature register updated. Refer 6.13 Temperature Measurement page more information.
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SYSTEM CALIBRATION
Calibration
CS5467 provides offset gain calibration that applied voltage current measurements, offset calibration which applied voltage current calculations. Since voltage current channels have independent offset gain registers, offset gain calibration performed channel independently. data flow calibration shown Figure CS5467 must operating active state ready accept valid commands. Refer Commands page value Cycle Count register determines number output word rate (OWR) samples that averaged during calibration. offset gain calibrations take least TSETTLE samples. offset calibrations take least 6(N) TSETTLE samples. increased, accuracy calibration results tends also increase. DRDY Status register will completion Calibration commands. overflow occurs during calibration, other Status register bits well.
Figure System Calibration Offset
External Connections AIN+ AINXGAIN
9.1.1.1 Offset Calibration
Offset Calibration command measures averages values read specified voltage current channels zero input stores inverse result associated offset registers. This will added instantaneous measurements subsequent conversions, removing offset. Gain registers channels being calibrated should prior performing offset calibration.
9.1.1.2 Offset Calibration
Offset Calibration command measures residual values read specified voltage current channels zero input stores inverse result associated offset registers. This will added measurements subsequent conversions, removing offset. offset registers channels being calibrated should first cleared prior performing calibration.
9.1.1 Offset Calibration
During offset calibrations, line voltage current should applied meter. zero-volt differential signal also applied voltage inputs VIN1± (VIN2±) current inputs IIN1± (IIN2±) CS5467. (see Figure 11.)
Modulator
Filter
I1RMS, V1RMS, I2RMS, V2RMS
I1DCOFF, V1DCOFF, I1GAIN, V1GAIN, I2DCOFF, V2DCOFF I2GAIN, V2GAIN
I1ACOFF, V1ACOFF, I2ACOFF, V2ACOFF
Offset
Offset Gain
Gain DCAVG Negate
Negate READABLE/WRITABLE REGISTERS.
Figure Calibration Data Flow
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9.1.2 Gain Calibration
During gain calibration, full-scale reference signal must applied meter optionally, scaled VIN1± (VIN2±), IIN1± (IIN2±) pins CS5467. reference must used gain calibration. Either reference used calibrations. used, associated high-pass filter (HPF) must off. Figure shows basic setup gain calibration.
External Connections
eference Signal
During gain calibration level applied reference measured with preset gain, then divided into quotient stored back into corresponding gain register.
9.1.2.2 Gain Calibration
With reference applied, Gain Calibration command measures averages values read specified voltage current channels stores reciprocal result associated gain registers, converting measured voltage into needed gain. Subsequent conversions will gain value.
9.1.3 Calibration Order
offset. gain. offset needed). both gain offset calibrations were performed, possible repeat both obtain additional accuracy gain offset interact.
Figure System Calibration Gain.
Using reference that large small cause over-range condition during calibration. Either condition Status register bits I1OR (I2OR) V1OR (V2OR) I1ROR (I2ROR) V1ROR (V2ROR) calibration. Full scale (FS) voltage input ±250 peak current inputs ±250 peak depending selected gain range. normal peak voltage applied these pins should exceed these levels during calibration normal operation. range gain registers limits gain calibration range subsequently range reference level that applied. reference should exceed lower than FS/4.
9.1.4 Temperature Sensor Calibration
Temperature sensor calibration involves adjustment parameters VBE0. These values must known order calibrate temperature sensor. Section 6.13 Temperature Measurement page explanation VBE0 calculate TGAIN TOFF register values from them.
9.1.4.1 Temperature Offset Calibration
Offset calibration done temperature, should done mid-scale gain error exists. Subtract measured register temperature from actual temperature determine offset error. Multiply this error VBE0 yield VBE0 value. Recalculate TOFF using this value.
9.1.2.1 Gain Calibration
Full scale gain calibrations input's full-scale range, which either depending gain range selected. That's again depending range. normal reference input level should either mVRMS, Prior executing Gain Calibration command, gain registers channel calibrated should reference level mentioned above used, that level divided actual reference level used.
9.1.4.2 Temperature Gain Calibration
temperature points enough apart give reasonable accuracy, example 25°C 85°C, required calibrate temperature gain. Divide actual temperature difference measured register) difference temperatures. This gives gain correction factor. Update TGAIN register multiplying it's value this correction factor. Update dividing value gain correction factor. will needed subsequent offset calibrations.
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E2PROM OPERATION
CS5467 accept commands from serial E2PROM connected serial interface instead host microcontroller. high level (logic MODE input indicates that E2PROM connected. This makes SCLK pins become driven outputs. After reset after running initialization program, CS5467 begins reading commands from connected E2PROM.
10.2 E2PROM Code
EEPROM code should following: Configuration Control register bits, such enables phase compensation settings. Write calibration data gain offset registers. energy output pulse width, rate, formats. Execute Continuous Conversion command. STOP Control register (last). Below example E2PROM code set.
Change page Write Modes Register, turn high-pass filters Write value 0x7FC4A9 I1GAIN register. Write value 0xFFB253 V1GAIN register. Write value 0x7FC4A9 I2GAIN register. Write value 0xFFB253 V2GAIN register. Change page Mask register. Start continuous conversions Write STOP Control register (Ctrl) terminate E2PROM command sequence.
10.1 E2PROM Configuration
typical connection between CS5467 E2PROM shown Figure CS5467 asserts (logic clocks SCLK, sends Read commands E2PROM SDO. Command format identical microcontroller mode, except CS5467 will attempt write EEPROM device. command sequence stops when STOP Control register (Ctrl) written command sequence.
Pulse Output Counter
CS5467
SCLK MODE
EEPROM
Connector Calibrator
Figure Typical Interface E2PROM CS5467
Figure also shows external connections that would made calibration device, such notebook computer, handheld calibrator, tester during meter assembly, calibrator tester used control CS5467 during calibration program required values into E2PROM.
10.3 Which E2PROMs Used?
Several industry-standard serial E2PROMs used with CS5467. Some listed below:
Atmel AT25010, AT25020 AT25040 National Semiconductor NM25C040M8 NM25020M8 Xicor X25040SI
These serial E2PROMs expect specific 8-bit command (00000011) order perform memory read. CS5467 been hardware programmed transmit this 8-bit command E2PROM after reset.
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BASIC APPLICATION CIRCUITS
Figure shows CS5467 configured measure power single-phase, 3-wire system while operating single-supply configuration. this diagram, current transformers (CT) used sense line currents voltage dividers used sense line voltages.
VIN2+
CVdiff VCV14
CS5467
VIN2VIN1+ PFMON CPUCLK XOUT 4.096 Optional Clock Source
CVdiff VCV10 RBurden
VIN1-
Idiff
IIN1RESET
ISOLATION (Optional) Serial Data Interface
RBurden RBurden
IIN1+
Idiff
IIN2-
SCLK
RBurden
LOAD LOAD
IIN2+ VREFIN VREFOUT AGND DGND
Pulse Output Counter
Figure Typical Connection Diagram (Single-phase, 3-wire Direct Connect Power Line)
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PACKAGE DIMENSIONS
SSOP PACKAGE DRAWING
SIDE VIEW
VIEW
SEATING PLANE
VIEW
-0.002 0.064 0.009 0.390 0.291 0.197 0.022 0.025
INCHES -0.006 0.069 -0.4015 0.307 0.209 0.026 0.0354
0.084 0.010 0.074 0.015 0.413 0.323 0.220 0.030 0.041
-0.05 1.62 0.22 9.90 7.40 5.00 0.55 0.63
MILLIMETERS -0.15 1.75 -10.20 7.80 5.30 0.65 0.90
NOTE 2.13 0.25 1.88 0.38 10.50 8.20 5.60 0.75 1.03
JEDEC MO-150 Controlling Dimension Millimeters
Notes: "E1" reference datums included mold flash protrusions, include mold mismatch
measured parting line, mold flash protrusions shall exceed 0.20 side. Dimension does include dambar protrusion/intrusion. Allowable dambar protrusion shall 0.13 total excess dimension maximum material condition. Dambar intrusion shall reduce dimension more than 0.07 least material condition. These dimensions apply flat section lead between 0.10 0.25 from lead tips.
DS714F1
CS5467
ORDERING INFORMATION
Model Temperature Package
CS5467-IS CS5467-ISZ (lead free)
28-pin SSOP
ENVIRONMENTAL, MANUFACTURING, HANDLING INFORMATION
Model Number Peak Reflow Temp Rating* Floor Life Days Days
CS5467-IS CS5467-ISZ (lead free)
(Moisture Sensitivity Level) specified IPC/JEDEC J-STD-020.
DS714F1
CS5467
REVISION HISTORY
Revision Date Changes
2007 2007
Initial release. Corrections implicitly state that temperature measurement secondary function voltage2 channel. Updated typical connection diagram. Changed Phase Compensation Range from ±2.8° ±5.4°. Updated quality process level (QPL).
2007
Contacting Cirrus Logic Support
product questions inquiries contact Cirrus Logic Sales Representative. find nearest www.cirrus.com
IMPORTANT NOTICE "Preliminary" product information describes products that production, which full characterization data available. Cirrus Logic, Inc. subsidiaries ("Cirrus") believe that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). Customers advised obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, indemnification, limitation liability. responsibility assumed Cirrus this information, including this information basis manufacture sale items, infringement patents other rights third parties. This document property Cirrus furnishing this information, Cirrus grants license, express implied under patents, mask work rights, copyrights, trademarks, trade secrets other intellectual property rights. Cirrus owns copyrights associated with information contained herein gives consent copies made information only within your organization with respect Cirrus integrated circuits other products Cirrus. This consent does extend other copying such copying general distribution, advertising promotional purposes, creating work resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS DESIGNED, AUTHORIZED WARRANTED AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO BODY, AUTOMOTIVE SAFETY SECURITY DEVICES, LIFE SUPPORT PRODUCTS OTHER CRITICAL APPLICATIONS. INCLUSION CIRRUS PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK CIRRUS DISCLAIMS MAKES WARRANTY, EXPRESS, STATUTORY IMPLIED, INCLUDING IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE, WITH REGARD CIRRUS PRODUCT THAT USED SUCH MANNER. CUSTOMER CUSTOMER'S CUSTOMER USES PERMITS CIRRUS PRODUCTS CRITICAL APPLICATIONS, CUSTOMER AGREES, SUCH USE, FULLY INDEMNIFY CIRRUS, OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS OTHER AGENTS FROM LIABILITY, INCLUDING ATTORNEYS' FEES COSTS, THAT RESULT FROM ARISE CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, Cirrus Logic logo designs trademarks Cirrus Logic, Inc. other brand product names this document trademarks service marks their respective owners.
DS714F1

Features Description Energy Linearity: ±0.1% Reading over 1000:1

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