Single-chip multiband transceiver 3GPP 25.104 release WCDMA/HSPA compa
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Single-Chip, Multiband Femtocell Transceiver ADF4602
Single-chip multiband transceiver 3GPP 25.104 release WCDMA/HSPA compatible UMTS band coverage Local area Class Band Band Band Band Direct conversion transmitter receiver Minimal external components Integrated multiband multimode monitoring interstage filters Integrated power management (3.1 supply) Integrated synthesizers including loop filters Integrated bias control DACs/GPOs WCDMA receive baseband filter options Easy with minimal calibration Automatic offset control Simple gain, frequency, mode programming supply current typical current current (varies with output power) 40-pin LFCSP package
GPO[4:1] DAC1 DAC2
DAC1
DAC2
ADF4602
Tx_PWR_CONTROL TXBBIB TXBBI
TXLBRF Tx_PWR_ CONTROL TXHBRF Tx_PWR_ CONTROL GENERATOR LOOP FILTER FRAC SYNTHESIZER VSUP7 TXBBQ TXBBQB Tx_PWR_CONTROL
GENERATOR LOOP FILTER FRAC SYNTHESIZER
VSUP6
Rx_LO_LB SELECTABLE BANDWIDTH BASEBAND FILTERS RXHB1RF CHANNEL RXBBI RXBBIB OFFSET CORRECTION RXBBQ CHANNEL Rx_LO_LB REFIN 26MHz 19.2MHz SERIAL INTERFACE VSUP8 RXBBQB OFFSET CORRECTION
APPLICATIONS
home basestations (femtocells) repeaters
RXHB2RF
RXLBRF
LDO1 LDO2 LDO3 LDO4 LDO5
VINT REFCLK
SCLK SDATA
VSUP1
VSUP2
VSUP3
VSUP4
VSUP5
CHIPCLK
Figure
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. rights reserved.
07092-001
ADF4602 TABLE CONTENTS
Features Applications Functional Block Diagram Revision History General Description Specifications. Timing Characteristics. Absolute Maximum Ratings. Caution Configuration Function Descriptions Typical Performance Characteristics Theory Operation Transmitter Description DACs General Purpose Outputs Receiver Description Power Management Frequency Synthesis Serial Port Interface (SPI) Operation Timing Registers Register Register Description Software Initialization Procedure Initialization Sequence Applications Information Interfacing ADF4602 AD9863 Outline Dimensions Ordering Guide
REVISION HISTORY
10/09-Revision Initial Version
Rev. Page
ADF4602 GENERAL DESCRIPTION
ADF4602 transceiver integrated circuit (IC) offering unparalleled integration feature set. ideally suited high performance femtocells providing cellular fixed mobile converged (FMC) services. With only handful external components, full multiband transceiver implemented. UMTS Band through Band Band through Band supported single device. receiver based direct conversion architecture. This architecture ideal choice highly integrated wideband CDMA (WCDMA) receivers, reducing bill materials fully integrating interstage filtering. front includes three high performance, single-ended noise amplifiers (LNAs), allowing device support tri-band applications. single-ended input structure eases interface reduces matching components required small footprint singleended duplexers. excellent device linearity achieves good performance with large range ceramic filter duplexers. integrated receive baseband filters offer selectable bandwidth, enabling device receive both WCDMA GSM-EDGE radio signals. selectable bandwidth filter, coupled with multiband input structure, allows GSM-EDGE signals monitored part UMTS home basestation. transmitter uses innovative direct conversion modulator that achieves high modulation accuracy with exceptionally noise, eliminating need external transmit filters. fully integrated phase lock loops (PLLs) provide high performance power fractional-N frequency synthesis both receive transmit sections. Special precautions have been taken provide isolation demanded frequency division duplex (FDD) systems. loop filter components fully integrated. ADF4602 also contains on-chip dropout voltage regulators (LDOs) deliver regulated supply voltages functions chip, with input voltage between controlled standard 3-wire serial interface with advanced internal features allowing simple software programming. Comprehensive power-down modes included minimize power consumption normal use.
Rev. Page
ADF4602 SPECIFICATIONS
TMIN TMAX, unless otherwise noted. Typical specifications 25°C, reference input level p-p. Table
Parameter REFERENCE SECTION Reference Input Reference Input Frequency Reference Input Amplitude REFCLK Output MHz) Output Load Capacitance Output Swing Output Slew Rate Output Duty Cycle Variation CHIPCLK Output (19.2 MHz) Output Load Capacitance Frequency Multiplication Ratio Output Swing Output Duty Cycle Variation Output Jitter Lock Time TRANSMIT SECTION Input Input Resistance Input Capacitance Differential Peak Input Voltage Input Common-Mode Voltage Baseband Filter Bandwidth Gain Control Maximum Gain Gain Control Range Gain Control Resolution Gain Control Accuracy Gain Settling Time Specifications (High Band) Carrier Frequency Output Impedance Output Power (POUT) Output Noise Spectral Density Unit Test Conditions
Single-ended operation, dc-coupled
load load Input duty cycle
48/65
48/65
load Input duty cycle
1.05
1/32
Single-ended Single-ended
differential baseband input Average steps step step POUT within final value
1710 -155 -161 -161 -163
2170
Carrier Leakage ACLR
dBc/Hz dBc/Hz dBc/Hz dBc/Hz
signal DPCH offset offset offset offset POUT POUT MHz, POUT MHz, POUT
Rev. Page
ADF4602
Parameter Specifications (Low Band) Carrier Frequency Output Impedance Output Power (POUT) Output Noise Spectral Density Carrier Leakage ACLR RECEIVE SECTION Baseband Output Output Common Mode Voltage Differential Output Range Output Offset Quadrature Gain Error Quadrature Phase Error In-Band Gain Ripple Low-Pass Filter Rejection WCDMA (Seventh Order) -158 Unit dBc/Hz Test Conditions
signal DPCH offset POUT POUT MHz, POUT MHz, POUT
1.15 1.35
±100
1.35 1.55
°rms
Mode Mode WCDMA mode servo loop mode
WCDMA (Fifth Order)
@2.7 @3.5 @5.9 @2.7 @3.5 @5.9 @200 @400 @800 1.92 band band WCDMA mode
Differential Group Delay WCDMA Receiver Gain Control Maximum Voltage Gain Gain Control Range Gain Control Resolution Gain Control Step Error Specifications (High Band) Input Frequency Input Impedance Input Return Loss Noise Figure Maximum Input Power Input Input
step step
1710
2170
Rev. Page
power dBm, spur-free measurement Maximum gain Minimum gain Offset, gain Offset, gain offset offset input
ADF4602
Parameter Specifications (Low Band) Input Frequency Input Impedance Input Return Loss Noise Figure Maximum Input Power3 Input Input Synthesizer Section Channel Resolution Lock Time3 DAC/GPO CONTROL DAC1 Resolution Output Range Absolute Accuracy Output Step Output Capacitive Load Output Current Output Impedance DAC2 Resolution Output Range Output Capacitive Load Output Current Output Impedance GPO1 GPO4 Output Current Output High Voltage Output Voltage Switching Time LOGIC INPUTS Input High Voltage, VINH Input High Voltage, VINH Input Voltage, VINL Input Current, IINH/IINL Input Capacitance, LOGIC OUTPUTS (SDATA) Output High Voltage, Output Voltage, CLKOUT Rise/Fall CLKOUT Load TEMPERATURE RANGE (TA) Unit Test Conditions
gain, power Maximum gain Minimum gain offset, gain offset, gain offset input
±0.5 ±1.0 2.85 3.15
bits bits
3.15 code,
load load
GPO1, GPO2, GPO3 GPO4 Maximum output current Maximum output current load readback mode readback mode4
0.45 0.45
VINT VSUP8,
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ADF4602
Parameter POWER SUPPLIES Voltage Supply VSUP1 VSUP2 Unit Test Conditions
VSUP3 VSUP4 VSUP5
VSUP6 VSUP7 VSUP8 VINT CURRENT CONSUMPTION Transmit Current Consumption Output Level Output Level Receive Current Consumption
Main supply input Output from internal LDO1, rating, supply Output from Internal LDO2, rating, supply baseband downconverter Output from internal LDO3, rating, supply LNAs Output from internal LDO4, rating, supply Output from internal LDO5, rating, supply modulator, baseband, control DACs Supply input synthesizer, connect VSUP3 Supply input synthesizer, connect VSUP3 Supply input reference section, connect VSUP2 Supply input serial interface control logic output matched into 2170 2170
reference frequency should coupled REFIN pin. ac-coupled internally. noise figure measurement does include spurious harmonics reference frequency. Spurs appear integer multiples reference frequency (every MHz), degrading receive sensitivity about Guaranteed design, production tested. sif_vsup8 Register controls whether readback mode readback mode selected. Serial Port Interface (SPI) section more details.
Rev. Page
ADF4602 TIMING CHARACTERISTICS
VGND 25°C, unless otherwise noted. Guaranteed design production tested. Table
Parameter Limit TMIN TMAX Unit Test Conditions/Comments high write time SCLK setup time SDATA SCLK setup time SDATA SCLK hold time SCLK high duration SCLK duration SCLK hold time SDATA valid delay SCLK SDATA valid delay SDATA disabled delay
WRITE
SCLK
SDATA W[25]
W[1] W[0]
W[24]
Figure Serial Interface Write Diagram
READ REQUEST
READ
SCLK
SDATA Q[25] Q[24] Q[1] Q[0] R[25] R[24] R[1] R[0]
07092-002
more MORE SYSCLK periods SCLK PERIODS
ADF4602 selected device DRIVES RSDATA drives SDATA
releases HOST RELEASES RSDATA SDATA
Figure Serial Interface Read/Write Diagram
Rev. Page
07092-003
ADF4602 ABSOLUTE MAXIMUM RATINGS
25°C, unless otherwise noted. Table
Parameter VSUP1, VSUP2 VSUP4, VSUP5, VSUP6, VSUP7, VSUP8, VSUP9 VSUP3 VINT Analog Voltage Digital Voltage Operating Temperature Range Commercial Version) Storage Temperature Range Maximum Junction Temperature LFCSP Thermal Impedance Reflow Soldering Peak Temperature Time Peak Temperature Rating -0.3 -0.3 +3.6 -0.3 +3.6 -0.3 +2.0 -0.3 +2.0 -0.3 -0.3 +85°C -65°C +125°C 150°C 32°C/W 240°C
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. This device high performance integrated circuit with rating sensitive. Proper precautions should taken handling assembly.
CAUTION
Rev. Page
ADF4602 CONFIGURATION FUNCTION DESCRIPTIONS
GPO2 GPO1 VSUP6 REFIN REFCLK VSUP8 CHIPCLK GPO4
GPO3 VSUP1 VSUP3 RXLBRF RXHB2RF RXHB1RF RXBBI RXBBIB RXBBQ
ADF4602
VIEW (Not Scale)
DAC1 DAC2 VSUP5 TXRFGND TXHBRF TXRFGND TXLBRF TXBBQB TXBBQ VSUP4
NOTES CONNECT. EXPOSED PADDLE MUST CONNECTED GROUND CORRECT CHIP OPERATION. PROVIDES BOTH THERMAL ELECTRICAL CONNECTION PCB.
RXBBQB VSUP2 VINT SDATA SCLK VSUP7 TXBBI TXBBIB
Figure Configuration
Table Function Descriptions
Mnemonic GPO3 VSUP11 VSUP31 RXLBRF RXHB2RF RXHB1RF RXBBI RXBBIB RXBBQ RXBBQB VSUP21 VINT SDATA SCLK VSUP71 TXBBI TXBBIB VSUP41 TXBBQ TXBBQB TXLBRF TXRFGND TXHBRF TXRFGND VSUP51 DAC2 DAC1 Function General Purpose Output Digital output. This used external switch control. Output from Supply receive VCO. Nominal value decoupling ground required. Output from Supply receive LNA. Nominal value decoupling ground required. Receive Band Input. Connect. connect this pin. Receive Second High Band Input. Should used Band Receive First High Band Input. Should used Band Receive Baseband Output. Complementary Receive Baseband Output. Receive Baseband Output. Complementary Receive Baseband Output. Output from Supply receive downconverter baseband. Nominal value decoupling ground required. Serial Port Supply Input. should applied this pin. Serial Port Data Pin. This input output. Serial Clock Input. Serial Port Enable Input. Connect. connect this pin. Transmit Synthesizer Supply Input. Connect VSUP3 decouple with ground. Transmit Baseband Input. Complementary Baseband Input. Output from LDO4. Supply transmit VCO. Nominal value decoupling required. Transmit Baseband Input. Complementary Baseband Input. Band Transmit Output. This output range MHz. Transmit Ground. Connect this ground. High Band Transmit Output. This output range 1710 2170 MHz. Transmit Ground. Connect this ground. Output from Supply transmit modulator, baseband, power detector, DACs. Nominal value decoupling ground required. Output from DAC2. Output from DAC1.
Rev. Page
07092-004
ADF4602
Mnemonic GPO4 CHIPCLK VSUP81 REFCLK REFIN VSUP61 GPO1 GPO2 EPAD Function Main Supply Input. Digital Output. This used switch control. Chip Clock Output. Reference Clock Supply Input. Connect VSUP2, decouple ground with Reference Clock Output. Reference Clock Input. reference ac-coupled internally. Connect. connect this pin. Receive Synthesizer Supply Input. Connect VSUP3 decouple ground with Digital Output. This used switch control. Digital Output. This used switch control. Exposed Paddle Under Chip. This must connected ground correct chip operation. provides both thermal electrical connection PCB.
capacitors recommended with these pins. X7R, X5R, similar type capacitor should used.
Rev. Page
ADF4602 TYPICAL PERFORMANCE CHARACTERISTICS
START: CH/DIV 881.5 Result Summary CPICH Slot STOP: ksps Chan Code Chan Slot 881.5 Code Relative CPICH Slot ksps Chan Code Chan Slot
+5MHz -5MHz +10MHz -10MHz
ACLR (dB)
07092-005
OUTPUT POWER (dBm/3.84MHz)
Figure UMTS Band Transmit EVM, Test Model DPCH,
Code Power Relative 2.1399994 3.90 Att* VIEW CPICH Slot ksps Chan Code Chan Slot
Figure TXHBRF Transmit ACLR Output Power, Test Model Signal, 10.54 PAR,
+5MHz -5MHz +10MHz -10MHz
Start Result Summary 2.1399994 CPICH Slot -8.03 0.95 1.83 2.54 ksps Chan Code Chan Slot Carrier Freq Error Trigger Frame Imbalance ksps) Active Chan Timing Offset Channel Slot Modulation Type Channel Power Symbol 65.98 9.642977 0.23 -50.12 Stop
ACLR (dB)
07092-009
3.90 Att*
GLOBAL RESULTS FRAME Total Power Chip Rate Error Offset Composite CPICH Slot CHANNEL RESULTS Symbol Rate Channel Code Pilot Bits Channel Power Symbol
07092-006
CLRWR
240.00 ksps -0.04 2.43
0.99936 Chips 16QAM -19.05 7.02
OUTPUT POWER (dBm/3.84MHz)
Figure UMTS Band Transmit EVM, Test Model 2.5%
Figure TXLBRF Transmit ACLR Output Power, Test Model Signal, 10.54 PAR,
*RBW 30kHz *VBW 300kHz *SWT 100ms ALT1 ALT1
COMPOSITE
-12.7dBm
*ATT
-12.698dBm
-8.08dBm -57.05dBm -57.09dBm -70.92dBm -71.41dBm
30dB DYNAMIC RANGE
-100
07092-007
TXPWR_SET (dBm)
-110 CENTER 2.14GHz 2.55MHz/DIV SPAN 25.5MHz
Figure 7.Transmit TXPWR_SET (dBm), Measured Across DUTS, Four Calibration Points Applied
Figure TXHBR Transmit ACLR, 2140
Rev. Page
07092-010
07092-008
GLOBAL RESULTS Total Chip Rate Offset Composite CPICH Slot Number CHANNEL RESULTS Symb Rate Channel Code Modulation Type Chan rel. Symbol
-4.57 1.04 0.79 2.04 QPSK 0.00 0.74
RESULT SUMMARY Carr Freq -92.42 Frame 22.62 Imbalance 0.36 Code -49.96 ksps) Timing Offset ksps Chips Chan Slot Number Pilot Bits Chan abs. -14.60 Symbol 1.21
ADF4602
MARKER (T1) *RBW 30kHz -23.01dBm *VBW 300kHz 880.877403846MHz -10.9dBm *ATT *SWT 100ms -4.39dBm -10.895dBm -60.63dBm -58.52dBm ALT1 -72.07dBm -72.13dBm ALT1
5MHz HIGH 25°C 5MHZ HIGH 85°C 5MHz HIGH 5MHz 25°C 5MHz 85°C 5MHz
5MHz ACLR (dB)
07092-011
07092-014
07092-016
-100 -110 CENTER 881MHz 2.55MHz/DIV SPAN 25.5MHz
FREQUENCY (MHz)
Figure TXLBRF Transmit ACLR,
Figure Transmit ACLR Frequency Temperature (Band Transmit Output Power
5MHz HIGH 25°C 5MHZ HIGH 85°C 5MHz HIGH 5MHz 25°C 5MHz 85°C 5MHz
MAGNITUDE (dBm)
07092-015
5MHz ACLR (dB)
07092-012
2110
2120
2130 2140 2150 FREQUENCY (MHz)
2160
2170
FREQUENCY (MHz)
Figure Transmit ACLR Frequency Temperature (Band Transmit Output Power
5MHz HIGH 25°C 5MHZ HIGH 85°C 5MHz HIGH 5MHz 25°C 5MHz 85°C 5MHz
PHASE NOISE (dBc/Hz)
Figure Transmit Baseband Filter Response
-100 -110 -120 -130 -140 -150
5MHz ACLR (dB)
-160 -170
1940
1950 1960 1970 FREQUENCY (MHz)
1980
1990
07092-013
1930
100k OFFSET FREQUENCY (Hz)
100M
Figure Transmit ACLR Frequency Temperature (Band Transmit Output Power
Figure Transmit Synthesizer Phase Noise
Rev. Page
ADF4602
0.14
MIXSTEP LNASTEP GAINCAL
0.12
CURRENT CONSUMPTION
0.10 0.08
07092-017
0.06 0.04
0.02
07092-020 07092-022 07092-021
OUTPUT POWER (dBm/3.84MHz)
RECEIVE GAIN SETTING (dB)
Figure Current Consumption Transmit Output Power; Frequency 2170 MHz, Test Model Signal, Receiver Disabled
Figure Receive Gain; 2.84 QPSK Modulated Input Signal, WCDMA Receive Baseband Filter
MIXSTEP LNASTEP GAINCAL
MAGNITUDE (dB)
GAIN STEP (dB)
07092-018
-100 0.01 FREQUENCY (MHz)
RECEIVE GAIN SETTING (dB)
Figure Receive WCDMA Baseband Filter Response
Figure Receive Gain Step Error Gain Setting, Steps, Measurement taken injecting known signal level measuring gain through device. gain then stepped through settings steps, gain step change measured each case.
MIXSTEP LNASTEP GAINCAL
MAGNITUDE (dBm)
NOISE FIGURE (dB)
07092-019
-100 FREQUENCY (kHz) 1000
RECEIVE GAIN SETTING (dB)
Figure Receive Baseband Filter Response
Figure Receiver Noise Figure Gain. Frequency 1955
Rev. Page
ADF4602
GAIN 80dB NOISE FIGURE (dB)
07092-023
-100 25°C 85°C GAIN 80dB -102 -104 SENSITIVITY (dBm) -106 -108 -110 -112 -114 -116 -118
07092-046
07092-027 07092-026
TS25.104 LIMIT
1920
1930
1940 1950 1960 FREQUENCY (MHz)
1970
1980
-120 1918
1928
1938 1948 1958 FREQUENCY (MHz)
1968
1978
Figure Receive Noise Figure Frequency
Figure Receive Sensitivity Frequency (See Receive Sensitivity Section More Details)
GAIN 80dB
NOISE FIGURE (dB)
25°C 85°C
10MHz 19.8MHz (dBm)
25°C 85°C
07092-024
1850
1860
1870 1880 1890 FREQUENCY (MHz)
1900
1910
RECEIVE GAIN SETTING (dB)
Figure Receive Noise Figure Frequency
Figure Receive IP3, 19.8 Gain Setting
GAIN 80dB NOISE FIGURE (dB)
07092-025
25°C 85°C
85MHz 190MHz (dBm)
RECEIVE GAIN SETTING (dB)
25°C 85°C
FREQUENCY (MHz)
Figure Receive Noise Figure Frequency
Figure Receive IP3, Gain Setting
Rev. Page
ADF4602
25°C 85°C RECEIVE GAIN SETTING (dB) RECEIVE GAIN SETTING (dB)
07092-031 07092-033 07092-032 07092-028
190MHz (dBm)
10MHz 19.8MHz (dBm)
25°C 85°C
Figure Receive IP2, Gain Setting
25°C 85°C
Figure Receive IP3, 19.8 Gain Setting
25°C 85°C
07092-029
45MHz 22.5MHz (dBm)
80MHz 40MHz (dBm)
RECEIVE GAIN SETTING (dB)
RECEIVE GAIN SETTING (dB)
Figure Receive IP3, Gain Setting
25°C 85°C
Figure Receive IP3, 22.5 Gain Setting
25°C 85°C
80MHz (dBm)
45MHz (dBm)
07092-030
RECEIVE GAIN SETTING (dB)
RECEIVE GAIN SETTING (dB)
Figure Receive IP2, Gain Setting
Figure Receive IP2, Gain Setting
Rev. Page
ADF4602 THEORY OPERATION
TRANSMITTER DESCRIPTION
TESTI, SWAP_I
TXBBI TXBBIB INTEGRATED BALUN
ONLY DIVIDER DIVIDER QUAD DEGREES TXBs
OUTPUT
TXBBQ TXBBQB
TESTQ, SWAP_Q
GAIN CONTROL
07092-034
TXPWR_SET[11:0]
Figure Transmitter Block Diagram
ADF4602 contains highly innovative noise variable gain direct conversion transmitter architecture, that removes need external transmit filters. direct conversion architecture significantly reduces risk transmit harmonics across bands simplified nature frequency plan. Figure block diagram.
VOLTS
Baseband
baseband interface channels differential, dc-coupled input, supporting wide range input commonmode voltages (VCM). allowable input common-mode range 1.05 maximum signal swing allowed peak differential. This corresponds peak-to-peak differential either channel. Figure shows graphical definition peak differential voltage VCM. baseband input signals pass through second order Butterworth filter prior quadrature modulator. cutoff frequency MHz. This gives some rejection images. filter also helps suppress spurious signals that might coupled baseband terminals PCB. ease routing between ADF4602 transmit DAC, differential inputs internally swapped. user test purposes, inputs also internally shorted together offset applied. This produces large carrier output, which useful signal path integrity testing.
PEAK
07092-035
TIME
Figure Transmit Baseband Input Signals
Rev. Page
ADF4602
Modulator
modulator converts transmit baseband input signals Calibration techniques used maintain accurate balance phase across frequency environmental conditions, thus ensuring that 3GPP carrier leakage ACLR requirements with good margin under conditions. on-chip calibrations carried during transmit lock time specified self-contained, requiring additional input from user. modulator gain control range, programmable 1/32 decibel step. 12-bit word txpwr_set[11:0] Register controls transmit output power. setting referenced full-scale (500 peak differential) sine wave signal applied transmit baseband inputs. calculate output power when WCDMA modulated signal with certain peak-to-average ratio applied, Equation should used. Output Power (dBm/3.84 MHz) txpwr(dBm) PAR(dB) where txpwr(dBm) txpwr_set[11:0] value converted dBm, peak-to-average ratio WCDMA signal. example, output power required WCDMA signal with peak-to-average ratio txpwr(dBm) current consumption modulator scales with output power. When power backed from maximum, transceiver benefits from lower power dissipation. user because most power amplifiers (PAs) singled-ended. This situation would normally require additional external matching components differential single-ended filter structure. With ADF4602, filter necessary, required loss balun fully integrated, converting differential internal signals single-ended output, thus allowing easy interfacing high band output available TXHBRF pin, band output available TXLBRF pin. These directly connected load, necessary, require ac-coupling.
DACS
ADF4602 integrates DACs that designed interface external control reference bias nodes within this function required, DACs used general purpose powered down required. DAC1 5-bit voltage output DAC. output range from 3.15 (for 3.15 DAC1 output stage supplied directly from VDD, with capability supply current within VDD. high accuracy, reference supplied from LDO5, which internally trimmed accuracy. DAC1 output PADAC1[4:0] word. DAC2 6-bit voltage output with range from LDO5 supplies both reference voltage full-scale output voltage DAC2. output voltage padac2_ow[5:0] word. dacgpo_owen must also high control DAC2 required. Both DACS powered down writing code, 0x0, respective control register.
Output
output tuned buffer stage then quadrature generation circuitry. tuned buffer ensures that minimum current related noise generated transport. This action transparent user. quadrature generator creates highly accurate phased signals required drive modulator also acts divide-by-2. band, additional divide-by-2 used transport path, which bypassed high band. This done minimize tuning range required cover bands. phase accuracy signals important ensuring good modulation quality accurate output power. on-chip calibration ensures that phased signals exactly phase. This calibration runs each time frequency changed txpwr_set[11:0] word written temperature device changes, this calibration should updated. calibration, user should simply write txpwr_set[11:0] word each five degree change temperature, update value regularly (every seconds) between WCDMA frames timeslots. This ensures that good accurate output power maintained temperature device changes.
GENERAL PURPOSE OUTPUTS
Four general-purpose outputs (GPOs) provided ADF4602. These used control bias modes more commonly, GPOs used control external front-end switches transmit/receive path. GPOs simple digital output drivers. GPO1 GPO3 capable supplying maximum current whereas GPO4 supply operation GPOs, dacgpo_owen must GPOs then controlled gpo_ow[3:0] word.
RECEIVER DESCRIPTION
ADF4602 contains fully integrated direct conversion receiver designed multiband WCDMA femtocell applications. High performance, power consumption, minimal external components features design. Figure shows block diagram receiver, which consists three blocks multiband operation, high linearity mixers, advanced baseband channel filtering, offset compensation circuit.
Output Baluns
baseband input, modulator, associated circuitry fully differential maintain high signal integrity noise immunity. However, differential output optimal
Rev. Page
ADF4602
18dB STEPS RxEN[1:0] MIXER TRANSCONDUCTANCE 18dB 30dB (WCDMA) 27dB 39dB (CDMA) STEPS ACTIVE FILTER CHANGES 18dB 18dB STEPS STEPS -6dB +18dB STEPS
RXBBI RXHB2RF HIGH BAND RXHB1RF HIGH BAND RXLBRF BAND VCMSEL GAIN CONTROL RXBW_TOGGLE
07092-036
PROGRAMMABLE OFFSET CONTROL
RXBBIB
RXBBQ RXBBQB
RxGAIN[6:0]
Figure Receiver Block Diagram
LNAs
ADF4602 contains three tunable front ends suitable major 3GPP frequency bands. suitable high band operation region 1700 2170 MHz. suitable operation from MHz. Thus, three integrated LNAs offer designer opportunity create multiband regional specific variants with additional components. power control internal band switching fully controlled serial interface. ADF4602 LNAs designed single-ended inputs, thus further simplifying front-end design providing easy matching with minimal components. Typically, twocomponent match required: series shunt inductor. Within LNA, signal converted differential path signal processing subsequent blocks within receive signal chain. Interstage filtering fully integrated, ensuring that external out-of-band blockers suitably attenuated prior mixer stages. characteristic designed provide additional filtering transmitter frequency offset. LNAs enabled programming bits rxbs[1:0] Register input should used UMTS Band operation, should used UMTS Band operation.
Quadrature drive provided mixers from receiver synthesizer section transport system, which includes programmable divider, that same used both high bands. Excellent quadrature phase amplitude match achieved careful design layout mixers transport circuits.
Baseband Section
ADF4602 baseband section distributed gain filter function designed provide maximum gain with gain control range. Through careful design, pass band ripple, group delay, signal loss, power consumption kept minimum. Filter calibration performed during manufacturing process, resulting high degree accuracy ease use. Three baseband filters available ADF4602, shown Table Bits rxbw_toggle[2:0] used select mode operation. seventh order WCDMA filter with 1.92 cutoff ensures that good attenuation adjacent channel should used meet blocking/adjacent channel selection specifications femtocell applications. filter cut-off intended monitoring receiver home base station. fifth order WCDMA filter provides less attenuation adjacent channel, should used femtocell applications. channels internally swapped, thus allowing optimum routing between radio analog baseband. This achieved using swapi swapq bits. Table Receive Baseband Filter Modes
Mode Seventh Order WCDMA Fifth Order WCDMA Filter Cutoff Frequency (fC) 1.92 1.92
Mixers
High linearity quadrature mixer circuits used convert signal baseband in-phase quadrature components. Although shown Figure mixer sections exist: optimized high band outputs optimized band. high band band mixer outputs combined then driven directly into first stage baseband low-pass filter, which also acts reduce level largest blocking signals, prior baseband amplification.
Rev. Page
ADF4602
receive baseband outputs have programmable common mode voltage selectable vcmsel Register
BLOCK GAIN (dB)
REQUESTED GAIN (dB) GAIN BASEBAND GAIN CHIP GAIN
07092-037 07092-038
MIXSTEP LNASTEP GAINCAL
Gain Control
Gain control distributed throughout receive signal chain shown Figure front contains control range: mixer transconductance stage. baseband active filter stages each provide gain control range steps. Filter characteristics (ripple group delay) best conserved active filter stages have equal gain. This results total gain control steps filter stage. variable gain amplifier (VGA) implements gain controllable steps. base gain mixer base gain This gives total gain with gain control range. base gain mixer stage WCDMA mode mode.
Figure Gain Distribution Between Baseband Blocks Default Setting
BLOCK GAIN (dB)
MIXSTEP LNASTEP GAINCAL
GAIN MIXER GAIN FILTER GAIN GAIN
Table Receive Gain Control WCDMA mode
Stage Mixer Filter Gain Control (WCDMA) (GSM) Control Steps steps steps steps steps
REQUESTED GAIN (dB)
simplify programming ensure optimum receiver performance dynamic range, user simply programs total desired receive gain rx_gain[6:0] bits Register ADF4602 then decodes gain setting automatically distributes gain between various blocks. allow some flexibility, predefined user inputs control gain threshold points which mixer gain steps occur. settings mixstep[3:0] lnastep[3:0] control mixer gain threshold steps, respectively. Excel spreadsheet detailing receive gain decode system available from Analog Devices, Inc., request. Figure shows example gain distribution profile.
Figure More Detailed Gain Distribution Profile
addition, gain calibration setting Register (gaincal[4:0]) used account losses front end. total gain ADF4602 given ReceiveGain rxgain[6:0] gaincal[4:0] where WCDMA filter mode, filter mode. Rxgain[6:0] receive gain programmed Register Gaincal[4:0] gain calibration setting Register calculated using following formula: gaincal[4:0] front_end_losses where front_end_losses loss receive path duplexers/switches. This useful referencing programmed gain antenna accounting losses path. example, total receive front-end loss user should program gaincal[4:0] user then requestes gain programming rxgain[6:0] ADF4602 uses Equation give ReceiveGain receive gain used internally ADF4602.
Rev. Page
ADF4602
Offset Compensation
very high proportion total system gain assigned analog baseband function, compensating offsets inherent part direct conversion solution. offsets characterized falling into categories: static slow varying time varying ADF4602 architecture been designed reduce amount time varying offsets. device also includes offset control system. control system consists ADCs baseband output digitize offsets: digital signal processing block where characteristics loop programmed customization loops transfer function, trim DACs that used introduce error term back into signal path. offset control transfer function either programmed servo loop that automatically triggered gain change high-pass filter (HPF) with automatic fast settling mode that also triggered gain change. Parameters servo loop, high-pass filter, fast settling mode initial ADF4602 programming. operation, offset control system fully automatic does require external programming. Recommended default programming conditions offset compensation loop shown Register Description section.
SERIAL INTERFACE 1.8V BASEBAND MIXERS LNAs DACs PATH (SER READ) 2.8V
VINT
VBAT
VSUP1
VSUP2
VSUP3
VSUP4
VSUP5
VSUP6
VSUP7
VSUP8
DIGITAL 1.8V SUPPLY
1.9V
ANALOG VSUP2
07092-039
Figure Power Management Block
VINT supplies serial interface enabling register data preservation with minimum current consumption during power-down. This should supplied with externally. five LDOs individually powered up/down bits ldoen[4:0] Register Table summarizes supply strategy. Note that reference path (VSUP8) supply supplied from external source internal VSUP2. external supply option convenient that entire reference path shut down collapsing single supply. VSUP8 also programmed supply voltage used serial interface readback. Serial Port Interface (SPI) section more information. Table Power Management Strategy
VINT VSUP1 VSUP2 VSUP3 VSUP4 VSUP5 Connection External External Internal LDO1 Internal LDO2 Internal LDO3 Internal LDO4 Internal LDO5 Usage Serial interface control logic Main device supply, DAC1 Receive Receive baseband down-converter Receive LNAs Transmit Transmit baseband, modulator, DAC2, GPOs Receive synthesizer Transmit synthesizer Reference path, reference buffer outputs; Optional: serial interface readback Volts
POWER MANAGEMENT
ADF4602 contains integrated power management requiring external power supplies: VINT. Figure shows block diagram. supplies five integrated drop-out regulators (LDOs), VSUP1 VSUP5, that used supply vast majority internal circuitry. VSUP6, VSUP7, VSUP8 supply receive PLL, transmit PLL, reference block, respectively. These nodes require external connections ensure good supply isolation ensure minimum level interference between PLL/reference blocks rest transceiver. VSUP6 VSUP7 should connected VSUP3, whereas VSUP8 should connected VSUP2. Each node, VSUP1 VSUP8, should externally decoupled ground with capacitor. capacitors recommended here. X7R, X5R, C0G, similar type capacitor should used.
VSUP6 VSUP7 VSUP8
Connect VSUP3 Connect VSUP3 VSUP2 external
Rev. Page
ADF4602
FREQUENCY SYNTHESIS
ADF4602 contains fully integrated programmable frequency synthesizers generation transmit receive local oscillator (LO) signals. design uses fractional-N architecture noise fast lock-time. fractional-N functionality implemented with third order modulator. Figure shows block diagram synthesizer architecture.
LOOP FILTER FREF FVCO 3.4GHz 4.4GHz RANGE
When high band enabled, programmed frequency equal frequency. band operation, programmed frequency should desired frequency. transmit receive synthesizers enabled setting txsynthen rxsynthen Register respectively.
Reference Path
ADF4602 requires reference frequency input. VCTCXO used provide this. reference input accoupled internally, external coupling necessary. reference internally buffered distributed respective blocks, such synthesizer inputs. Figure shows block diagram.
PHASE FREQUENCY DETECTOR CHARGE PUMP 50kHz STEP DIVIDERS FREQ AMPLITUDE CONTROL
DIGITAL DECODE
07092-040
RxFREQ[15:0]
Figure Frequency Synthesizer Block Diagram
ADF4602 provides buffered outputs: buffered version reference REFCLK 19.2 WCDMA chip clock CHIPCLK. 19.2 chip clock multiple 3.84 chip rate used WCDMA. Thus, used clock ADCs/DACs elsewhere system. chip clock generated integrated contains user settings. Both outputs slew rate limited produce swing digital outputs. buffers contain their regulator circuits improve isolation minimize unwanted supply noise. 19.2 buffer outputs enabled disabled programming refclken chipclken (Register
26MHz CLOCK DISTRIBUTION VSUP8 REFIN (26MHz)
necessary components fully integrated both transmit receive synthesizers, including loop filters, VCOs, tank components. VCOs high band frequency band frequency. dividers external synthesizer loop. This minimizes leakage power desired frequency tuning range requirements VCO. VCOs multiband structure cover wide frequency range required. design incorporates both frequency amplitude calibration ensure that oscillator always operating with optimum performance. calibrations occur during lock time fully self contained, requiring user inputs. charge pump loop filter internally trimmed remove variations associated with manufacture frequency. This process fully automated. simplified programming, ADF4602 contains frequency decode table synthesizers, meaning programmer concerned with internal operation counters fractional-N system. Frequency step sizes possible with both transmit receive synthesizers. programming words rxfreq[15:0] txfreq[15:0] frequency steps from 3276.75 MHz. Note that synthesizers cover this full range. frequency range each synthesizer high bands given Specifications section.
REFCLK 1.5V REFCLKEN 1.5V VSUP8 CHIPCLKEN VSUP8 VSUP8
07092-041
CHIPCLK
Figure Reference Path Block Diagram
reference sections powered from VSUP8, which safely removed from chip isolation, enter current power-down mode. Calibration data lost, reference frequency ceases exist. soon VSUP8 reapplied, oscillation begins. This visible buffer outputs, long they were previously enabled.
Rev. Page
ADF4602 SERIAL PORT INTERFACE (SPI)
ADF4602 contains internal registers that used configure device. three-wire serial port interface provides read write access internal registers. write, read requests, read operations, 26-bit transfers used. words transferred first. read request format same address structure write format does contain data field. Padding used maintain 26-bit word length. readback format same word format during write. Again, padding used maintain 26-bit word length. Table Chip Select Code
CS[2] CS[1] other permutations CS[0] Device ADF4602 Reserved
Format
Figure shows format register write. This consists 5-bit address 16-bit data words. exception register 00000, where lower data byte used 8-bit subaddress. total, this creates 16-bit registers 8-bit registers. registers referred text "Register example, while 8-bit registers referred "Register 0.144". 2-bit code specifying type operation being performed (see Table more information). chip select code, 3-bit field indicating which device being programmed. ADF4602, should (D2, D0). Table Operation Code
OP[1] OP[0] Operation Write Description Normal register write. Register bits corresponding data word set. Other bits modified. Register bits corresponding data word cleared. Other bits modified. Register read request.
OPERATION TIMING
SCLK, SDATA, used transfer data into ADF4602 registers. Data clocked into register, MSB, first rising edge each SCLK. data transferred selected register address rising edge SEN. Figure Figure timing information.
Read
Figure shows read operation. First, read request written host ADF4602. must remain high least three SCLK periods between read request operation following read operation. host must release SDATA line during this period. ADF4602 takes control SDATA, read operation commences when host device drives low. SDATA output voltage during readback sif_vsup8 (Register controls this. this configures device VINT supply, whereas configures VSUP8 supply. After power-up after soft reset, ADF4602 defaults readback mode.
Clear
Read
OPERATION WRITE REGISTER W[25:0] WRITE REGISTER W[25:0] READ REQUEST REGISTER Q[25:0] READ REQUEST REGISTER Q[25:0] READ REGISTER Q[25:0] READ REGISTER Q[25:0]
POSITION DATA D[15:0] DATA D[7:0] SUBADDRESS A2[7:0] RANDOM PADDING P[15:0] RANDOM PADDING P[7:0] DATA D[15:0] DATA D[7:0] SUBADDRESS A2[7:0] SUBADDRESS A2[7:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0]
07092-042
ADDRESS A1[4:0] ADDRESS 00000 ADDRESS A1[4:0] ADDRESS A1[4:0] ADDRESS A1[4:0] ADDRESS 00000
[1:0] [1:0] [1:0] [1:0]
Figure Register Write Format
Rev. Page
ADF4602 REGISTERS
REGISTER
GENERAL USER REGISTERS rxen refclk chipclk ldoen[4:0] txen txbs txsynth rxsynth reset_ soft DEFAULT1 0x2FFD 0x0002
rxbs[1:0] sif_ vsup8
RECEIVER USER REGISTERS rfskip[3:0] osadc2x[3:0] nint3[3:0] vcmsel sdmen[3:0] nper2[3:0] nint2[3:0] swapq swapi rxbw[2:0] mixstep[3:0] nper1[3:0] nint1[3:0] gaincal[4:0] DEFAULT1 0x9858 rxgain[6:0] lnastep[3:0] nper0[3:0] nint0[3:0] sdmosr 0x0000 0x0FA6 0x103E 0xEE53 0x0890
rxfreq[15:0]
TRANSMITTER USER REGISTERS dacgpo _owen cmmod DEFAULT1 0x001F 0x8000 0x0000 cntrl_ mode nvmld 0x0001 0x0000
test_I/swap_I gpo_ow[3:0]
test_Q/swap_Q
gain_blanksel [1:0] padac2_ow[5:0]
vcm_sat_thres[5:0] padac1[4:0]
txfreq[15:0] txpwr_set[11:0]
SUB-ADDRESS REGISTERS buff_value[7:0] reserved[7:0] en_mix[3:0] buffstate vsup2[7:0] reserved[7:0] reserved[7:0] reserved[7:0] DEFAULT1 0x06 0x6F 0x85 0x78 0x20 0xF0 0x04 0x5F 0x14
reserved[1:0]
NOTES 1THESE RECOMMENDED DEFAULT SETTINGS THAT SHOULD PROGRAMMED INTO REGISTERS. 2DEFAULT SHOWN BAND OPERATION. 0x00 TRANSMIT FREQUENCY 21100MHz. 3DEFAULT SHOWN BAND OPERATION. 0x50 TRANSMIT FREQUENCY 21100MHz.
Figure Register
Rev. Page
07092-043
ADF4602
REGISTER DESCRIPTION
Table General User Registers
Register [10:6] Name rxen refclken chipclken ldoen Description this high enable receiver. here disables receiver. Setting this high enables reference output buffer. Setting this high enables the19.2 chip clock output buffer. on-chip LDOs powered down individually. normal operation LDOs should enabled (Bits[10 [11111]) Mode ldoen[10:6] XXXX1 VSUP1 enable XXX1X VSUP2 enable XX1XX VSUP3 enable X1XXX VSUP4 enable 1XXXX VSUP5 enable Setting this high enables transmitter. This controls which transmit outputs use. band (TXLBRF), high band (TXHBRF). Setting this high enables transmit synthesizer. These bits control receiver band select. rxbs[2:1] Operation Reserved band enable (RXLB) High Band enable (RXHB1) (default) High Band enable (RXHB2) Setting this high enables receive synthesizer serial port readback (SDATA) output voltage changed from with this bit. VINT supply, VSUP8 supply. After power-up after soft reset, ADF4602 defaults readback mode. rising edge this starts reset pulse full chip. This self clearing. recommended that soft reset performed after power-up.
[2:1]
txen txbs txsynthen rxbs
rxsynthen sif_vsup8
reset_soft
don't care.
Rev. Page
ADF4602
Table Receiver User Registers
Register [15:0] Name rxfreq Description These bits receive synthesizer frequency steps from 3276.75 MHz. high bands this equal channel frequency, bands channel frequency. example: (Hex) HB1, Synthesizer Frequency Synthesizer Frequency 0x9470 1900 0x9858 1950 These bits receiver gain conjunction with gaincal[4:0] setting register 0x00 0dB, 0x7F Gain rxgain gaincal where WCDMA mode mode. mode selected rxbw bits Register With mixstep lnastep valid range rxgain from Settings outside these clipped Figure example. Skip offset control state when gain step occurred State State Default modulator enable State State Default Gain decode threshold mixer gain reduction step. steps. Default Gain decode threshold gain reduction step. steps. Default Offset measurement range State State Default State duration State Default State duration State Default State duration State Default Integrator time constant State Default Integrator time constant State Default =0xE Integrator time constant State Default Integrator time constant State Default This sets receive baseband output common-mode voltage. Setting this high swaps differential outputs, RXBBQ RXBBQB. Setting this high swaps differential outputs, RXBBI RXBBIB. This controls receive baseband filter bandwidth. rxbw [8:6] Filter Mode Fifth order WCDMA filter (not recommended femtocells) Seventh order WCDMA filter (recommended WCDMA filter femtocells) filter Else Reserved These bits used calibration front-end loss. 0x00 0x1F used calculation receive gain. rxgain Register used calibration, this should WCDMA mode mode. Offset loop modulator over sampling ratio. (default)
[6:0]
rxgain
[15:12] [11:8] [7:4] [3:0] [15:12] [11:8] [7:4] [3:0] [15:12] [11:8] [7:4] [3:0] [8:6]
rfskip sdmen mixstep lnastep osadc2x nper2 nper1 nper0 nint3 nint2 nint1 nint0 vcmsel swapq swapi rxbw
[5:1]
gaincal
sdmosr
Rev. Page
ADF4602
Table Transmitter User Registers
Register [12:11] Name test_I/swap_I Description These bits allow various options inputs detailed following table: Bits Function Normal operation Swap differential inputs ease routing Zero input inputs offset applied inputs; creates large carrier These bits allow various options inputs detailed table below: Bits Function Normal operation Swap differential inputs ease routing Zero input inputs offset applied inputs: creates large carrier During transmit gain change, some spectral splatter occur output transmitter. These bits allow input baseband signal input low-pass filter blanked short period, reduce spectral splatter observed during gain change. gain_blanksel[8:7] Operation Default setting; blanking blanking blanking blanking This adjusts internal modulator common-mode setting. should Setting this results reduced power consumption degrades transmit linearity. This should 0x1F normal operation. Setting this high allows user have manual control over DAC2 GPO1 GPO4. These bits allow manual control dacgpo_owen must allow this mode operation. Each controls GPOs following table. This allows possible permutations output combinations. gpo_ow[14 :11] Mode XXX1 GPO1 high XX1X GPO2 high X1XX GPO3 high 1XXX GPO4 high These bits allow manual control DAC2. dacgpo_owen must allow this mode operation. These bits control DAC1. These bits transmitter synthesizer frequency steps from 3276.75 MHz. high bands, this equal channel frequency, bands channel frequency. example: (Hex) Synthesizer Frequency synthesizer Frequency 0xA730 2140 1070 0xA988 2170 1085
[10:9]
test_Q/swap_Q
[8:7]
gain_blanksel
[5:0] [14:11]
cmmod vcm_sat_thres dacgpo_owen gpo_ow
[10:5] [4:0] [15:0]
padac2_ow padac1 txfreq
Write
Rev. Page
ADF4602
Register Write [15:4] Name txpwr_set Description Requested transmit power antenna. 1/32 dBm, 0x000 dBm, 0xFFF 47.96875 dBm. output power referenced full scale sine wave applied transmit baseband inputs. WCDMA modulated signals, output power measured 3.84 bandwidth reduced peak average ratio signal. Modulator section more details. valid range transmit output power setting dBm. Output clipping occur sooner, depending applied signal. txpwr_set register should updated periodically, with every change temperature ensure accurate output power. Output section more details. this control output power from txpwr_set bits. Setting this triggers manual load nonvolatile memory contents. Software Initialization Procedure section more details.
Write
nvmld
don't care.
Table Sub-Address Registers
Register 0.144, Write 0.151, Write [2:1] [7:0] Name reserved[1:0] vsup2[7:0] Description These bits should normal operation. These bits control VSUP2 regulator voltage should 0x6F normal operation. During initialization sequence, VSUP2 voltage temporarily Software Initialization Procedure section more details. These bits should 0x85 normal operation. These bits should 0x78 normal operation. These bits should 0x20 normal operation. These bits enable channels modulator separately. these bits enable modulator normal operation. This controls transmit buffer state. transmit synthesizer frequencies 2100 (Band buffer state should corresponding buffer value R0.174 should 0x5F. This ensures correct device operation frequencies 2100 MHz. operation below 2100 (Band buffer state should corresponding buffer value R0.174 should 0x50. This ensures correct device operation frequencies 2100 MHz. These bits should 0x5F transmit frequencies >2100 MHz, 0x50 transmit frequencies <2100 MHz. description Register 0.171 more. These bits should 0x14 normal operation.
0.153, Write 0.155, Write 0.165, Write 0.170, Write 0.171, Write
[7:0] [7:0] [7:0] [7:4]
reserved[7:0] reserved[7:0] reserved[7:0] en_mix[3:0] buffstate
0.174, Write 0.175, Write
[7:0] [7:0]
buff_value[7:0] reserved[7:0]
Rev. Page
ADF4602 SOFTWARE INITIALIZATION PROCEDURE
INITIALIZATION SEQUENCE
Table shows initialization sequence that should used after power-up. Note that reference clock must applied REFIN before programming begins. default settings described comments section, some settings, such output frequency, gain, settings, vary from those required application user. user substitute settings these instances. Table Initialization Sequence
Step Register Data 0x0003 Comment Performs soft reset ADF4602. reset takes registers should written during this period. After programming continue normal. This self clearing. using logic levels, this register should programmed 0x0001 instead 0x0003. VSUP2 Nonvolatile Memory (NVM) Initialization section more details. Transfers non-volatile memory (NVM) contents registers. Wait before next programming step. Negate last programming step. VSUP2 back Enables receiver disables transmit output. Selects TXHBRF transmit output RXHB1 receive input. Enables on-chip regulators. 19.2 output clock enabled, output clock disabled. desired disable 19.2 output clock, this register programmed 0x27DD. Default settings mixer gain reduction steps. Default settings. Default settings. Sets received gain calibration, WCDMA filter mode, output common-mode voltage Default settings. Enables manual control. Default settings. Default settings. Default settings. Default settings. Default settings. transmit synthesizer frequency >2100 transmit synthesizer frequency <2100 transmit synthesizer frequency >2100 transmit synthesizer frequency <2100 Default settings. Receiver gain Receiver synthesizer frequency 1950 MHz. takes lock. Registers should written during this period. Transmit synthesizer frequency 2140 MHz. takes lock. Registers should written during this period. Enables transmit output. Enables control output power sets txpwr_set field dBm. Control output power txpwr_set bits.
0.151 0.151
0xE0 0x0010 0x0000 0x6F 0x2FDD
0.144 0.155 0.153 0.165 0.170 0.171 0.174 0.175
0x0FA6 0x103E 0xEE53 0x0890 0x001F 0x8000 0x06 0x78 0x85 0x20 0xF0 0x04 0x00 0x5F 0x50 0x14 0x0050 0x9858 0xA730 0x2FFD 0xA001
Register numbers 0.xxx 8-bit registers described Interface section ADF4602-x datasheet.
Rev. Page
ADF4602
Nonvolatile Memory (NVM) Initialization
ADF4602 on-chip non-volatile memory (NVM) that contains chip factory calibration coefficients. soft reset device transfers contents internal registers; however, this been found unreliable performed temperatures below 0°C. software work-around outlined Step Step Table ensures that data transferred reliably under operating conditions. involves setting VSUP2 on-chip regulator manually transferring data setting nvmld Register then resetting VSUP2 regulator Device programming then continue normal. matically turned prevent unwanted transmissions locks. user should wait (time taken lock), then output power desired value writing Register user disables transmit synthesizer, transmit output power must turned before reenabling transmit synthesizer. This achieved means: setting Register setting output power Register minimum. After reenabling synthesizer, then locking synthesizer frequency programming frequency word Register user reenable output power. change receive frequency, simply program frequency Register wait before using device transceiver. receive gain time (apart from during locking transient).
Programming Transmit Receive frequencies
After initialization, transmit/receive synthesizer frequencies need changed. change transmit frequency, write frequency word Register When transmit frequency programmed, transmit output power auto-
Rev. Page
ADF4602 APPLICATIONS INFORMATION
INTERFACING ADF4602 AD9863
AD9863 mixed signal front-end processor recommended with ADF4602. AD9863 contains dual 12-bit ADCs dual 12-bit DACs sampling ADF4602 receive signal providing transmit baseband signal ADF4602. This section discusses connections necessary between devices.
optimum ADF4602. With gain permanently maximum, transmit output power controlled ADF4602 power setting.
AD9863
IOUT+A DACA IOUT-A TXBBIB TXBBQ TXBBQB INPUT
07092-044
ADF4602
TXBBI INPUT
Transmit Interface
AD9863 TxDAC core provides dual, differential current output DACs generated from 12-bit data. full scale output current, IOUTFSMAX, means external resistor, RSET. relationship between IOUTFSMAX RSET follows:
OUTFSMAX
IOUT+B DACB IOUT-B
1.23
Figure AD9863 TxDAC ADF4602 Baseband Input Interface
Receive Interface
AD9863 input consists differential input resistance switched capacitor circuit with differential full scale input level. input self biased mid-supply, alternatively, programmed accept external bias. ADF4602 receive baseband outputs provide this external bias (1.4 this preferred interface between devices. vcmsel Register should give common-mode voltage from ADF4602, AD9863 input bias should disabled. direct connection then made between ADF4602 receive baseband outputs AD9863 inputs. sampling action sample hold capacitor introduce kick-back effect onto input signal. This lead spurs receive signal integer multiples sampling frequency. These spurs degrade sensitivity receiver channels containing these spurs. reduce these spurs improve sensitivity, filtering capacitors ground should placed each receive baseband output. Figure shows interface between devices.
Setting RSET gives optimal dynamic setting TxDACs results full scale output current ADF4602 transmit baseband inputs accept commonmode input signal with differential swing. configuration Figure used provide this from AD9863 TxDACs. Resistor common-mode voltage, whereas load Resistor sets differential swing. differential swing, VDIFF, function load resistor, full scale current, IOUTFSMAX, according
VDIFF OUTFSMAX OUTFSMAX
common-mode voltage
OUTFSMAX
Using these equations, give commonmode voltage, give differential input swing. AD9863 transmit programmable gain amplifier (TxPGA) provides simultaneous gain range both DACs controlled port. gain range 100% IOUTFSMAX. Coarse gain controls also available each output. Maximum settings (255) both TxPGA gain coarse gain controls (full gain) recommended. This because output common-mode voltage designed with specific IOUTFSMAX. Varying gain results different IOUTFSMAX consequently, different VCM, which
Receive Sensitivity
Figure shows ADF4602 receive sensitivity vs.frequency. sensitivity degradation 63rd 64th harmonics 30.72 sampling frequency seen near 1935 1966 MHz. filtering capacitors ground were used inputs this plot. Note also sensitivity degradation reference frequency harmonics 1924 MHz, 1950 MHz, 1976 MHz. degradation sensitivity less than these harmonics. Overall, solution exceeds 3GPP sensitivity specifications across frequency range.
Rev. Page
ADF4602
AD9863
IOUT+A ADCA IOUT-A 100pF IOUT+B ADCB IOUT-B 100pF RXBBQ 100pF RXBBQB QOUTPUT
07092-045
ADF4602
RXBBI 100pF RXBBIB OUTPUT
Figure ADF4602 Receive Baseband Output AD9863 Interface
Rev. Page
ADF4602 OUTLINE DIMENSIONS
6.00 0.60
0.60 INDICATOR
INDICATOR
VIEW
5.75
0.50 0.50 0.40 0.30
EXPOSED
(BOT VIEW)
4.25 4.10 3.95
0.25 4.50
0.80 0.65 0.05 0.02
1.00 0.85 0.80
COMPLIANT JEDEC STANDARDS MO-220-VJJD-2
Figure 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Body, Very Thin Quad (CP-40-1) Dimensions shown millimeters
ORDERING GUIDE
Model1 ADF4602BCPZ ADF4602BCPZ-RL
Temperature Range +85°C +85°C
Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
072108-A
SEATING PLANE
0.30 0.23 0.18
0.20
COPLANARITY 0.08
PROPER CONNECTION EXPOSED PAD, REFER CONFIGURATION FUNCTION DESCRIPTIONS SECTION THIS DATA SHEET.
Package Option CP-40-1 CP-40-1
RoHS Compliant Part.
Rev. Page
ADF4602 NOTES
Rev. Page
ADF4602 NOTES
Rev. Page
ADF4602 NOTES
©2009 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. D07092-0-10/09(0)
Rev. Page
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