Complete monolithic 12-bit ADCs with track-and-hold amplifier On-chip
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LC2MOS Complete, 12-Bit, kHz, Sampling ADCs AD7870/AD7875/AD7876
Complete monolithic 12-bit ADCs with track-and-hold amplifier On-chip reference Laser-trimmed clock Parallel, byte, serial digital interface input frequency (AD7870, AD7875) data access time power: typical Variety input ranges AD7870 AD7875 AD7876
AGND
INPUT SCALING
AD7870/AD7875/ AD7876
TRACK-AND-HOLD
COMP REFERENCE 12-BIT
CLOCK COUNTER
12/8/CLK CONTROL LOGIC CONVST PARALLEL SERIAL INTERFACE
07730-001
BUSY/INT
DB11
DGND
Figure
GENERAL DESCRIPTION
AD7870/AD7875/AD7876 fast, complete, 12-bit analog-to-digital converters (ADCs). These converters consist track-and-hold amplifier, successive approximation ADC, buried Zener reference, versatile interface logic. ADCs feature self-contained internal clock which laser trimmed guarantee accurate control conversion time. external clock timing components required; on-chip clock overridden external clock required. parts offer choice three data output formats: single, parallel, 12-bit word; 8-bit bytes serial data. Fast access times standard control inputs ensure easy interfacing modern microprocessors digital signal processors. parts operate from power supplies. AD7870 AD7876 accept input signal ranges respectively, while AD7875 accepts unipolar input range. parts convert full power signals kHz. AD7870/AD7875/AD7876 feature accuracy specifications, such linearity, full-scale offset error. addition, AD7870 AD7875 fully specified dynamic performance parameters including distortion signal-tonoise ratio. parts available 24-pin, inch-wide, plastic hermetic dual-in-line package (DIP). AD7870 AD7875 available 28-pin plastic leaded chip carrier (PLCC), while AD7876 available 24-pin small outline (SOIC) package.
PRODUCT HIGHLIGHTS
Complete 12-bit chip. AD7870/AD7875/AD7876 provide functions necessary analog-to-digital conversion combine 12-bit with internal clock, track-and-hold amplifier reference single chip. Dynamic specifications users. AD7870 AD7875 fully specified tested parameters, including signal-to-noise ratio, harmonic distortion intermodulation distortion. Fast microprocessor interface. Data access times make parts compatible with modern 8-bit 16-bit microprocessors digital signal processors. digital timing parameters tested guaranteed over full operating temperature range.
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
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AD7870/AD7875/AD7876 TABLE CONTENTS
Features Functional Block Diagram General Description Product Highlights Revision History Specifications. AD7870 Specifications AD7875/AD7876 Specifications. Timing Characteristics Absolute Maximum Ratings. Caution Configurations Function Descriptions Load Circuits Converter Details Internal Reference Track-and-Hold Amplifier Analog Input Offset Full-Scale Adjustment-AD7870 Offset Full-Scale Adjustment-AD7876 Offset Full-Scale Adjustment-AD7875 Timing Control Data Output Formats Mode Interface. Mode Interface. Dynamic Specifications Microprocessor Interface. Parallel Read Interfacing Two-Byte Read Interfacing Serial Interfacing Standalone Operation Applications Information Layout Hints Noise Outline Dimensions Ordering Guide
REVISION HISTORY
2/09-Rev. Rev. Updated Format Universal Reorganized Layout Universal Deleted Version Universal Changes Internal Clock Parameter, Table Added Endnote Table Changes Internal Clock Parameter, Table Changes Mode Interface Section Deleted Data Acquisition Board Interface Connections Sections Figure Deleted Figure Power Supply Connections, Shorting Plug Options Components List Sections Deleted Figure Figure Deleted Figure Figure Updated Outline Dimensions Changes Ordering Guide
Rev. Page
AD7870/AD7875/AD7876 SPECIFICATIONS
AGND DGND fCLK external, unless otherwise stated. Specifications Tmin Tmax, unless otherwise noted.
AD7870 SPECIFICATIONS
Table
Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) +25°C TMIN TMAX Total Harmonic Distortion (THD) Peak Harmonic Spurious Noise Intermodulation Distortion (IMD) Second Order Terms Third Order Terms Track-and-Hold Acquisition Time ACCURACY Resolution Minimum Resolution which Missing Codes Guaranteed Integral Nonlinearity Integral Nonlinearity Differential Nonlinearity Bipolar Zero Error Positive Full-Scale Error Negative Full-Scale Error4 ANALOG INPUT Input Voltage Range Input Current REFERENCE OUTPUT +25°C Tempco Reference Load Sensitivity (REF OUT/I) LOGIC INPUTS Input High Voltage, VINH Input Voltage, VINL Input Current, Input Current (12/8/CLK Input Only) Input Capacitance, LOGIC OUTPUTS Output High Voltage, Output Voltage, DB11 Floating-State Leakage Current Floating-State Output Capacitance5 ADN7870 Units Test Conditions/Comments
sine wave, fSAMPLE Typically 71.5 sine wave, fSAMPLE Typically kHz, fSAMPLE Typically kHz, kHz, fSAMPLE kHz, kHz, fSAMPLE
±1/2
±1/2 ±500 2.99 3.01
±1/4 ±1/2 ±500 2.99 3.01
±1/2 ±500 2.99 3.01
Bits Bits ppm/°C
±500 2.99 3.01
Reference load current change Reference load should changed during conversion.
ISOURCE ISINK
Rev. Page
AD7870/AD7875/AD7876
Parameter CONVERSION TIME External Clock (fCLK MHz) Internal Clock POWER REQUIREMENTS Power Dissipation 6.5/9 ADN7870 6.5/9 6.5/9 6.5/9 Units min/ specified performance specified performance Typically Typically Typically Test Conditions/Comments
temperature range versions from +70°C; versions is-40°C +85°C; version -55°C +125°C. (p-p) calculation includes distortion noise components. Measured with respect internal reference includes bipolar offset error. Sample tested +25°C ensure compliance. Conversion time specification AD7870A device with internal clock used s/10 minimum/maximum.
AD7875/AD7876 SPECIFICATIONS
Table
Parameter ACCURACY Resolution Resolution which Missing Codes Guaranteed Integral Nonlinearity +25°C TMIN TMAX (AD7875 Only) TMIN TMAX (AD7876 Only) Differential Nonlinearity Unipolar Offset Error (AD7875 Only) Bipolar Zero Error (AD7876 Only) Full-Scale Error +25°C Full-Scale Track-and-Hold Acquisition Time DYNAMIC PERFORMANCE (AD7875 ONLY) Signal-to-Noise Ratio (SNR) +25°C TMIN TMAX Total Harmonic Distortion (THD) Peak Harmonic Spurious Noise Intermodulation Distortion (IMD) Second Order Terms Third Order Terms AD7875/AD7876 ±1/2 ±1/2 ±1.5/-1.0 Units Bits Bits ppm/°C Test Conditions/Comments
Typical full-scale error Typical ppm/°C
sine wave, fSAMPLE Typically 71.5 sine wave, fSAMPLE Typically kHz, fSAMPLE Typically kHz, kHz, fSAMPLE kHz, kHz, fSAMPLE
Rev. Page
AD7870/AD7875/AD7876
Parameter ANALOG INPUT AD7875 Input Voltage Range AD7875 Input Current AD7876 Input Voltage Range AD7876 Input Current REFERENCE OUTPUT +25°C Tempco Reference Load Sensitivity (REF OUT/I) LOGIC INPUTS Input High Voltage, VINH Input Voltage, VINL Input Current, Input Current (12/8/CLK Input Only) Input Capacitance, LOGIC OUTPUTS Output High Voltage, Output Voltage, DB11-DB0 Floating-State Leakage Current Floating-State Output Capacitance5 CONVERSION TIME External Clock (fCLK MHz) Internal Clock POWER REQUIREMENTS
AD7875/AD7876 ±600 2.99 3.01 ±600 2.99 3.01 ±600 2.99 3.01
Units ppm/°C
Test Conditions/Comments
Typical tempco ppm/°C Reference load current change Reference load should changed during conversion.
ISOURCE ISINK
6.5/9
6.5/9
6.5/9
min/s Refer power requirements Table
AD7870
AD7875, temperature range versions from +70°C; versions is-40°C +85°C; version -55°C +125°C. AD7876, temperature range versions from -40°C +85°C version is-55°C +125°C. Includes internal reference error calculated after unipolar offset error (AD7875) bipolar zero error (AD7876) been adjusted out. Full-scale error refers both positive negative full-scale error AD7876. Dynamic performance parameters tested AD7876, these typically same AD7875. calculation includes distortion noise components. Sample tested +25°C ensure compliance.
Rev. Page
AD7870/AD7875/AD7876
TIMING CHARACTERISTICS
AGND DGND Figure Figure Figure Figure Timing specifications sample tested 25°C ensure compliance, unless otherwise noted. input signals specified with (10% timed from voltage level Table
Parameter t62, t72,
Limit TMIN, TMAX Versions)
Limit TMIN, TMAX Version)
Units
Conditions/Comments CONVST pulse width setup time (Mode pulse width hold time (Mode delay Data access time after relinquish time after HBEN setup time HBEN hold time SSTRB SCLK falling edge setup time SCLK cycle time SCLK valid data delay. SCLK rising edge SSTRB relinquish time after SCLK setup time (Mode BUSY propagation delay Data setup time prior BUSY hold time (Mode HBEN setup time HBEN hold time
Serial timing measured with pull-up resistor SDATA SSTRB pull-up SCLK. capacitance three outputs Timing specifications maximum limit 100% production tested. measured with load circuits Figure defined time required output cross defined time required data lines change when loaded with circuits Figure SCLK mark/space ratio (measured from voltage level 40/60 60/40. SDATA will drive higher capacitive loads this will since increases external time constant (4.7 k||CL) thus time reach
Rev. Page
AD7870/AD7875/AD7876 ABSOLUTE MAXIMUM RATINGS
Table
Parameter AGND AGND AGND DGND AGND AGND Digital Inputs DGND Digital Outputs DGND Operating Temperature Range Commercial Versions-AD7870) Commercial Versions-AD7875) Industrial Versions-AD7870) Industrial Versions-AD7875/ AD7876) Extended Version) Storage Temperature Range Lead Temperature (Soldering, sec) Power Dissipation (Any Package) +75°C Derates above +75°C Rating -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 +70°C +70°C -25°C +85°C -40°C +85°C -55°C +125°C -65°C +150°C +300°C mW/°C
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
CAUTION
Rev. Page
AD7870/AD7875/AD7876 CONFIGURATIONS FUNCTION DESCRIPTIONS
BUSY/INT
BUSY/INT DB11/HBEN DB10/SSTRB DB9/SCLK
AD7870/ AD7875/ AD7876
12/8/CLK
DB11/HBEN DB10/SSTRB DB9/SCLK DB8/SDATA
07730-004
CONVST
VIEW DB8/SDATA (Not Scale) AGND DB7/LOW
INDENTFIER
12/8/CLK
CONVST
AGND DB0/DB8
DB6/LOW DB5/LOW DB4/LOW DGND
DB0/DB8 DB1/DB9 DB2/DB10 DB3/DB11
AD7870/AD7875/ AD7876
VIEW (Not Scale)
DB7/LOW DB6/LOW
DB3/DB11
DB5/LOW
DB4/LOW
DGND
DB2/DB10
DB1/DB9
CONNECT
Figure SOIC Configuration
Figure PLCC Configuration
Table Function Descriptions
SOIC PLCC Mnemonic BUSY/INT DB11/HBEN Function Connect. Read. Active logic input. This input used conjunction with enable data outputs. Busy/Interrupt. Active logic output indicating converter status. Figure Figure Figure Figure Clock Input. external TTL-compatible clock applied this input pin. Alternatively, tying this enables internal laser-trimmed clock oscillator. Data (MSB)/High Byte Enable. function this dependent state 12/8/CLK input. When 12-bit parallel data selected, this provides DB11 output. When byte data selected, this becomes HBEN logic input. HBEN used 8-bit interfacing. When HBEN low, DB7/LOW DB0/DB8 become DB0. With HBEN high, DB7/LOW DB0/DB8 used upper byte data (see Table Data 10/Serial Strobe. When 12-bit parallel data selected, this provides DB10 output. SSTRB active open-drain output that provides strobe framing pulse serial data. external pull-up resistor required SSTRB. Data 9/Serial Clock. When 12-bit parallel data selected, this provides output. SCLK gated serial clock output derived from internal external clock. 12/8/CLK input then SCLK runs continuously. 12/8/CLK then SCLK gated after serial transmission complete. SCLK open-drain output requires external pull-up resistor. Data 8/Serial Data. When 12-bit parallel data selected, this provides output. SDATA open-drain serial data output which used with SCLK SSTRB serial data transfer. Serial data valid falling edge SCLK while SSTRB low. external pull-up resistor required SDATA. Three-state data outputs controlled Their function depends 12/8/CLK HBEN inputs. With 12/8/CLK high, they always DB7-DB4. With 12/8/CLK their function controlled HBEN (see Table Digital Ground. Ground reference digital circuitry. Three-state data outputs which controlled Their function depends 12/8/CLK HBEN inputs. With 12/8/CLK high, they always DB3-DB0. With 12/8/CLK their function controlled HBEN (see Table Positive Supply,
DB10/SSTRB
DB9/SCLK
DB8/SDATA
to11
DB7/LOW- DB4/LOW DGND DB3/DB11- DB0/DB8
Rev. Page
07730-005
AD7870/AD7875/AD7876
SOIC PLCC Mnemonic AGND 12/8/CLK Function Analog Ground. Ground reference track-and-hold, reference DAC. Voltage Reference Output. internal reference provided this pin. external load capability Analog Input. analog input range AD7870, AD7876, AD7875. Negative Supply, Three Function Input. Defines data format serial clock format. With this output data for-mat 12-bit parallel only. With this either byte serial data available SCLK continuous. With this either byte serial data again available SCLK continuous. Convert Start. high transition this input puts track-and-hold into hold mode starts conversion. This input asynchronous input. Chip Select. Active logic input. device selected when this input active. With CONVST tied low, conversion initiated when goes low.
CONVST
Table Output Data Byte Interfacing
HBEN High DB7/Low DB6/Low DB5/Low DB4/Low DB3/DB11 DB11(MSB) DB2/DB10 DB10 DB1/DB9 DB0/DB8 (LSB)
Rev. Page
AD7870/AD7875/AD7876 LOAD CIRCUITS
DGND HIGH-Z 50pF 50pF
07730-002
DGND HIGH-Z 10pF 10pF
07730-003
DGND HIGH-Z
DGND HIGH-Z
Figure Load Circuits Access Time
Figure Load Circuits Output Float Delay
Rev. Page
AD7870/AD7875/AD7876 CONVERTER DETAILS
AD7870/AD7875/AD7876 complete 12-bit ADC, requiring external components apart from power supply decoupling capacitors. comprised 12-bit successive approximation based fast settling voltage output DAC, high speed comparator SAR, track-and-hold amplifier, buried Zener reference, clock oscillator, control logic.
TRACK-AND-HOLD AMPLIFIER
track-and-hold amplifier analog input AD7870/AD7875/AD7876 allows accurately convert input frequencies 12-bit accuracy. input bandwidth track-and-hold amplifier much greater than Nyquist rate even when operated maximum throughput rate. cutoff frequency occurs typically kHz. track-and-hold amplifier acquires input signal 12-bit accuracy less than overall throughput rate equal conversion time plus track-and-hold amplifier acquisition time. input clock throughput rate max. operation track-and-hold essentially transparent user. track-and-hold amplifier goes from tracking mode hold mode start conversion. CONVST input used start conversion then track hold transition occurs rising edge CONVST. starts conversion, this transition occurs falling edge
INTERNAL REFERENCE
AD7870/AD7875/AD7876 have on-chip temperature compensated buried Zener reference that factory trimmed Internally provides both reference bias required bipolar operation (AD7870 AD7876). reference output available (REF OUT) capable providing external load. maximum recommended capacitance normal operation reference required external ADC, should decoupled with resistor series with parallel combination tantalum capacitor ceramic capacitor. These decoupling components required remove voltage spikes caused ADC's internal operation.
ANALOG INPUT
three parts differ from each other analog input voltage range that they handle. AD7870 accepts input signals, AD7876 accepts input range, while input range AD7875 Figure shows AD7870 analog input. analog input range into input resistance typically designed code transitions occur midway between successive integer values (that LSB, LSBs, LSBs FS-3/2 LSBs). output code twos complement binary with FS/4096 V/4096 1.46 ideal input/output transfer function shown Figure
AD7870
TRACK-AND-HOLD AMPLIFIER INTERNAL COMPARATOR
AD7870/AD7875/AD7876
TEMPERATURE COMPENSATION
Figure Reference Circuit
reference output voltage applications using AD7875 AD7876, reference required. Figure shows scale voltage provide either external reference.
AD7870/AD7875/AD7876
07730-006
INTERNAL REFERENCE
VOUT (10V)
Figure AD7970 Analog Input
(9.1k)
07730-007
(3.9k)
Figure Generating Reference
AD7876 analog input structure shown Figure analog input range into input resistance typically before, designed code transitions occur midway between successive integer values. output code twos complement with FS/4096 V/4096 4.88 ideal input/output transfer function shown Figure
Rev. Page
07730-008
INTERNAL REFERENCE
AD7870/AD7875/AD7876
AD7876
TRACK-AND-HOLD AMPLIFIER INTERNAL COMPARATOR INTERNAL REFERENCE
OUTPUT CODE 111.111 111.110 111.101 111.100
2.1R
AGND
07730-009
INTERNAL AGND
000.011 000.010 000.001
1LSB 4096
07730-012
Figure AD7876 Analog Input
Figure shows analog input AD7875. input range into input resistance typically Once again, designed code transitions occur midway between successive integer values. output code straight binary with FS/4096 V/4096 1.22 ideal input/output transfer function shown Figure
AD7875
TRACK-AND-HOLD AMPLIFIER AGND INTERNAL AGND
07730-010
000.000
INPUT VOLTAGE
1LSB
Figure AD7875 Transfer Function
OFFSET FULL-SCALE ADJUSTMENT- AD7870
most digital signal processing (DSP) applications, offset full-scale errors have little effect system performance. Offset error always eliminated analog domain coupling. Full-scale error effect linear does cause problems long input signal within full dynamic range ADC. Some applications will require that input signal span full analog input dynamic range. such applications, offset full-scale error have adjusted zero. Where adjustment required, offset error must adjusted before full-scale error. This achieved trimming offset driving analog input AD7870 while input voltage below ground. trim procedure follows: apply voltage -0.73 mV(-1/2 LSB) Figure adjust offset voltage until output code flickers between 1111 1111 1111 0000 0000 0000. Gain error adjusted either first code transition (ADC negative full-scale) last code transition (ADC positive full scale). trim procedures both cases follows (see Figure 13).
INTERNAL COMPARATOR
Figure AD7875 Analog Input
OUTPUT CODE 011.111 011.110
AD7870 (AD7876)
000.010 000.001 000.000 111.111 111.110 (20V) 100.001 100.000 INPUT VOLTAGE 1LSB 4096
07730-011
1LSB
Figure AD7870/AD7876 Transfer Function
Rev. Page
AD7870/AD7875/AD7876
Positive Full-Scale Adjust
Apply voltage 9.9927 (FS/2 LSBs) Adjust until output code flickers between 0111 1111 1110 0111 1111 1111.
AD7870/ AD7875/ AD78761
AGND
07730-013
Negative Full-Scale Adjust
Apply voltage -9.9976 (FS/2 LSB) adjust until output code flickers between 1000 0000 0000 1000 0000 0001.
1ADDITIONAL PINS OMITTED CLARITY.
Figure Offset Full-Scale Adjust Circuit
OFFSET FULL-SCALE ADJUSTMENT- AD7875
Similar AD7870, most applications which AD7875 used require offset full-scale adjustment. applications that require adjustment, offset error must adjusted before full-scale (gain) error. This achieved applying input voltage 0.61 (1/2 LSB) Figure adjusting offset voltage until output code flickers between 0000 0000 0000 0000 0000 0001. full-scale adjustment, apply input voltage 4.9982 LSBs) adjust until output code flickers between 1111 1111 1110 1111 1111 1111.
Positive Full-Scale Adjust
Apply voltage 2.9978 (FS/2 LSBs) Adjust until output code flickers between 0111 1111 1110 0111 1111 1111.
Negative Full-Scale Adjust
Apply voltage -2.9993 (-FS/2 LSB) adjust until output code flickers between 1000 0000 0000 1000 0000 0001.
OFFSET FULL-SCALE ADJUSTMENT- AD7876
offset full-scale adjustment AD7876 similar that just outlined AD7870. trim procedure, those applications that require adjustment, follows: apply voltage -2.44 (-1/2 LSB) adjust offset voltage until output code flickers between 1111 1111 1111 0000 0000 0000. Full-scale error adjusted either first code transition (ADC negative full scale) last code transition (ADC positive full scale). trim procedure both case described following sections (see Figure 13).
Rev. Page
AD7870/AD7875/AD7876 TIMING CONTROL
AD7870/AD7875/AD7876 capable basic operating modes. first mode (Mode CONVST line used start conversion drive track-and-hold into hold mode. conversion, track-and-hold returns tracking mode. intended principally digital signal processing other applications where precise sampling time required. these applications, important that signal sampling occur exactly equal intervals minimize errors sampling uncertainty jitter. these cases, CONVST line driven timer some precise clock source. second mode achieved hardwiring CONVST line low. This mode (Mode intended systems where microprocessor total control ADC, both initiating conversion reading data. starts conversion microprocessor normally driven into WAIT state duration conversion BUSY/INT. nized serial clock output (SCLK) framed serial strobe (SSTRB). Data clocked high transition serial clock valid falling edge this clock while SSTRB output low. SSTRB goes within three clock cycles after CONVST, first serial data (the first leading zero) valid first falling edge SCLK. three serial lines open-drain outputs require external pull-up resistors. serial clock derived from clock source, which internal external. Normally, SCLK required during serial transmission only. these cases, shut down conversion allow multiple ADCs share common serial bus. However, some serial systems (such TMS32020) require serial clock that runs continuously. Both options available AD7870/AD7875/AD7876 using 12/8/CLK input. With this input serial clock (SCLK) runs continuously; when 12/8/CLK SCLK turned transmission.
DATA OUTPUT FORMATS
addition operating modes, AD7870/AD7875/ AD7876 also offers choice three data output formats, serial parallel. parallel data formats single, 12-bit parallel word 16-bit data buses two-byte format 8-bit data buses. data format controlled 12/8/ input. logic high this selects 12-bit parallel output format only. logic applied this allows user access either serial byte formatted data. Three pins previously assigned four MSBs parallel form used serial communications while fourth becomes control input byte-formatted data. three possible data output formats selected either modes operation.
MODE INTERFACE
Conversion initiated going pulse CONVST input. rising edge this CONVST pulse starts conversion drives track-and-hold amplifier into hold mode (AD7870/AD7875/AD7876). falling edge CONVST pulse starts conversion drives track-and-hold amplifier into hold mode (AD7870A). Conversion initiated low. BUSY/INT status output assumes function this mode. normally high goes conversion. This line used interrupt microprocessor. read operation accesses data line reset high falling edge CONVST input must high when brought operate correctly this mode. input should hardwired this mode. Data cannot read from part during conversion because onchip latches disabled when conversion progress. applications where precise sampling critical, CONVST pulse generated from microprocessor line OR-gated with decoded address. some applications, depending power supply turn-on time, AD7870/AD7875/AD7876 perform conversion power-up. this case, line powers-up dummy read AD7870/AD7875/AD7876 required reset line before starting conversion. Figure shows Mode timing diagram 12-bit parallel data output format (12/8/CLK read conversion accesses bits data same time. Serial data available this data output format.
Parallel Output Format
parallel formats available part 12-bit wide data word two-byte data word. first format, bits data available same time DB11 (MSB) through (LSB). second, reads required access data. When this data format selected, DB11/ HBEN assumes HBEN function. HBEN selects which byte data read from ADC. When HBEN low, lower eight bits data placed data during read operation; with HBEN high, upper four bits 12bit word placed data bus. These four bits right justified thereby occupy lower nibble data while upper nibble contains four zeros.
Serial Output Format
Serial data available AD7870/AD7875/AD7876 when 12/8/CLK input this case DB10/ SSTRB, DB9/SCLK DB8/SDATA pins assume their serial functions. Serial data available during conversion with word length bits; four leading zeros, followed 12-bit conversion result starting with MSB. data synchro-
Rev. Page
AD7870/AD7875/AD7876
CONVST TRACK-AND-HOLD GOES INTO HOLD
TRACK-AND-HOLD RETURNS TRACK ACQUISITION TIME BEGINS
07730-014
tCONVERT
THREE-STATE
DATA
VALID DATA DB11
Figure Mode Timing Diagram, 12-Bit Parallel Read
CONVST TRACK-AND-HOLD GOES INTO HOLD
HBEN1
TRACK-AND-HOLD RETURNS TRACK ACQUISITION TIME BEGINS
VALID DATA VALID DATA DB11
tCONVERT
DATA THREE-STATE
SSTRB2
SCLK3
DB11 DB10 SERIAL DATA
SDATA2
LEADING ZEROS
1TIMES
SAME 2EXTERNAL 4.7k PULL-UP RESISTOR.
3EXTERNAL
HIGH BYTE READ BYTE READ.
07730-015
PULL-UP RESISTOR; CONTINUOUS SCLK (DASHED LINE) WHEN 12/8/CLK -5V; NONCONTINUOUS WHEN 12/8/CLK
Figure Mode Timing Diagram, Byte Serial Read
Mode timing diagram byte serial data shown Figure goes conversion reset high first falling edge This first read conversion either access byte high byte data depending status HBEN (Figure shows byte only example). diagram shows both noncontinuously continuously running clock (dashed line).
conversion, stays during conversion returns high when conversion complete. normally used parallel interfaces drive microprocessor into WAIT state duration conversion. Mode relevant AD7870A device. Figure shows Mode timing diagram 12-bit parallel data output format (12/8/CLK this case, behaves like slow memory. major advantage this interface that allows microprocessor start conversion, WAIT then read data with single READ instruction. user does have worry about servicing interrupts ensuring that software delays long enough avoid reading during conversion.
MODE INTERFACE
second interface mode achieved hard wiring CONVST conversion initiated taking while HBEN low. track-and-hold amplifier goes into hold mode falling edge this mode, BUSY /INT assumes BUSY function. BUSY goes start
Rev. Page
AD7870/AD7875/AD7876
TRACK-AND-HOLD GOES INTO HOLD
tCONVERT
BUSY TRACK-AND-HOLD RETURNS TRACK ACQUISITION TIME BEGINS
07730-016
DATA
THREE-STATE
VALID DATA DB11
Figure Mode Timing Diagram, 12-Bit Parallel Read
HBEN1
TRACK-AND-HOLD GOES INTO HOLD
tCONVERT
TRACK-AND-HOLD RETURNS TRACK ACQUISITION TIME BEGINS
BUSY THREE-STATE DATA SSTRB2
VALID DATA DB11
VALID DATA
SCLK3
DB11 DB10 SERIAL DATA
SDATA2
LEADING ZEROS
1TIMES
t15, t16, SAME HIGH BYTE READ BYTE READ. 2EXTERNAL 4.7k PULL-UP RESISTOR.
3EXTERNAL PULL-UP RESISTOR;
07730-017
CONTINUOUS SCLK (DASHED LINE) WHEN 12/8/CLK -5V; NONCONTINUOUS WHEN 12/8/CLK
Figure Mode Timing Diagram, Byte Serial Read
Mode timing diagram byte serial data shown Figure two-byte data read, lower byte (DB0 DB7) accessed first since HBEN must start conversion. behaves like slow memory this first read, second read access upper byte data normal read. Operation serial functions identical between Mode Mode timing diagram Figure shows both noncontinuously continuously running SCLK (dashed line).
input signal. Thus, parameters which AD7870 AD7875 specified include SNR, harmonic distortion, intermodulation distortion peak harmonics. These terms discussed more detail following sections.
Signal-to-Noise Ratio (SNR)
measured signal-to-noise ratio output ADC. signal magnitude fundamental. Noise nonfundamental signals half sampling frequency (FS/2) excluding dependent upon number quantization levels used digitization process; more levels, smaller quantization noise. theoretical signal-to-noise ratio sine wave input given (6.02N 1.76) where number bits. Thus ideal 12-bit converter, Note that sine wave signal very distortion input which sampled sampling rate. fast
DYNAMIC SPECIFICATIONS
AD7870 AD7875 specified 100% tested dynamic performance specifications well traditional specifications such integral differential nonlinearity. Although AD7876 production tested parameters, dynamic performance similar AD7870 AD7875. specifications required signal processing applications such speech recognition, spectrum analysis high speed modems. These applications require information ADC's effect spectral content
Rev. Page
AD7870/AD7875/AD7876
Fourier transform (FFT) plot generated from which data obtained. Figure shows typical 2048 point plot AD7870KN/AD7875KN with input signal sampling frequency kHz. obtained from this graph 72.6 should noted that harmonics taken into account when calculating SNR.
INPUT FREQUENCY 25kHz SAMPLE FREQUENCY 100kHz 72.6dB 25°C
Total Harmonic Distortion (THD)
ratio harmonics value fundamental. AD7870/AD7875, defined
SIGNAL AMPLITUDE (dB)
where amplitude fundamental amplitudes second through sixth harmonic. also derived from plot output spectrum.
Intermodulation Distortion
-140
FREQUENCY (kHz)
Figure Plot
Effective Number Bits
formula given Equation relates number bits. Rewriting formula, Equation possible measure performance expressed effective number bits (N).
07730-018
-120
With inputs consisting sine waves frequencies, active device with nonlinearities creates distortion products difference frequencies where Intermodulation terms those which neither equal zero. example, second order terms include fb), while third order terms include (2fa fb), (2fa fb), 2fb) 2fb). Using CCIF standard, where input frequencies near input bandwidth used, second third order terms different significance. second order terms usually distanced frequency from original sine waves while third order terms usually frequency close input frequencies. result, second third order terms specified separately. calculation intermodulation distortion specification where ratio individual distortion products amplitude fundamental expressed dBs. this case, input consists two, equal amplitude, distortion sine waves. Figure shows typical plot AD7870/AD7875.
1.76 6.02
effective number bits device calculated directly from measured SNR. Figure shows typical plot effective number bits frequency AD7870KN/AD7875KN with sampling frequency kHz. effective number bits typically falls between 11.7 11.85 corresponding figures 72.2 73.1
12.0
Peak Harmonic Spurious Noise
Peak harmonic spurious noise defined ratio value next largest component output spectrum FS/2 excluding value fundamental. Normally, value this specification determined largest harmonic spectrum, parts where harmonics buried noise floor peak noise peak.
EFFECTIVE NUMBER BITS
11.5
11.0
10.5
07730-019
SAMPLE FREQUENCY 100kHz 25°C 10.0 6.25 12.5 18.75 25.0 31.25 37.5 43.75
50.0
INPUT FREQUENCY (kHz)
Figure Effective Number Bits Frequency
Rev. Page
AD7870/AD7875/AD7876
INPUT FREQUENCIES 9.05kHz 9.55kHz SAMPLING FREQUENCY 100kHz 25°C TERMS 90.06dB SECOND ORDER TERMS 92.73dB THIRD ORDER TERSM 93.45dB
V(i), estimated code transition point, derived follows:
SIGNAL AMPLITUDE (dB)
where: peak signal amplitude. number histogram samples. cum(i)
occurrences.
INPUT FREQUENCY 25kHz SAMPLE FREQUENCY 100kHz 25°C
07730-020
-120
RELATIVE ACCURACY (LSB)
FREQUENCY (kHz)
0.25
Figure Plot
Linearity Plot
When sine wave specified frequency applied input AD7870/AD7875 several million samples taken, histogram showing frequency occurrence each 4096 codes generated. From this histogram data possible generate integral linearity plot shown Figure This shows very good integral linearity performance from AD7870/AD7875 input frequency kHz. absence large spikes plot shows good differential linearity. Simplified versions formulae used outlined below.
-0.25
07730-021
-0.50 1023 1535 2047 CODE 2559 3071 3583
4095
Figure Plot
4096
where: INL(i) integral linearity code V(fs) V(o) estimated full-scale offset transitions. V(i) estimated transition code.
Rev. Page
AD7870/AD7875/AD7876 MICROPROCESSOR INTERFACE
AD7870/AD7875/AD7876 have wide variety interfacing options. They offer operating modes three data-output formats. Fast data access times allow direct interfacing most microprocessors including processors.
TIMER ADDRESS
TMS32010
AD7870/ AD7875/ AD78761
CONVST ADDR DECODE 12/8/CLK BUSY/INT DB11
PARALLEL READ INTERFACING
Figure Figure Figure show interfaces ADSP-2100, TMS32010 TMS32020 processors. operating Mode parallel read three interfaces. external timer controls conversion start asynchronously microprocessor. each conversion BUSY/INT interrupts microprocessor. conversion result read from with following instruction: ADSP-2100: DM(ADC) TMS32010: D,ADC TMS32020: D,ADC ADSP-2100 Register Data Memory Address AD7870/AD7875/AD7876 Address Some applications require that conversions initiated microprocessor rather than external timer. option decode CONVST signal from address that write operation starts conversion. Data read conversion described earlier. Note: read operation must attempted during conversion.
TIMER DMA13 DMA0 ADDRESS
1ADDITIONAL PINS OMITTED CLARITY.
Figure TMS32010 Parallel Interface
TIMER ADDRESS
TMS32020
AD7870/ AD7875/ AD78761
CONVST ADDR DECODE 12/8/CLK BUSY/INT DB11
07730-024
INTn STRB
ADSP-2100
AD7870/ AD7875/ AD78761
CONVST ADDR DECODE 12/8/CLK BUSY/INT DB11
DATA
1ADDITIONAL PINS OMITTED CLARITY.
Figure TMS32020 Parallel Interface
TWO-BYTE READ INTERFACING
68008 Interface
Figure shows 8-bit interface MC68008 microprocessor. this interface, 12/8/CLK input tied DB11/HBEN driven from microprocessor least significant address bit. Conversion start control provided microprocessor. this interface example, Move instruction from address both starts conversion reads conversion result. MOVEW ADC,DO AD7870/AD7875/AD7876 address 68008 register
IRQn DMRD
DMD15 DMD0
1ADDITIONAL PINS OMITTED CLARITY.
Figure ADSP-2100 Parallel Interface
07730-022
DATA
Rev. Page
07730-023
DATA
AD7870/AD7875/AD7876
This two-byte read instruction. During first read operation BUSY, conjunction with forces microprocessor WAIT conversion. conversion byte (DB7 DB0) loaded into register high byte (DB15 DB7) loaded into Bits register. following rotate instruction register swaps high bytes correct format. Note that while executing two-byte read instruction above, WAIT states inserted during first read operation only second.
ADDRESS
1ADDITIONAL
conversion. During conversion, data valid SDATA output clocked into receive data shift register DSP56000. When this register received bits data, generates internal interrupt DSP56000 read data from register.
AD7870/ AD7875/ AD78761
TIMER CONVST 12/8/CLK
DSP56000
4.7k
SCLK
07730-026
07730-027
SDATA
PINS OMITTED CLARITY.
MC68008
ADDR DECODE DTACK STRB
HBEN
AD7870/ AD7875/ AD78761
Figure DSP56000 Serial Interface
BUSY/INT 12/8/CLK CONVST
DSP56000 AD7870/AD7875/AD7876 also configured continuous clock operation (12/8/CLK this case, strobe pulse required DSP56000 indicate when data valid. SSTRB output inverted applied input DSP56000 provide this strobe pulse. other conditions connections same gated clock operation.
NEC7720/77230 Serial Interface
serial interface between AD7870/AD7875/AD7876 NEC7720 shown Figure interface shown, configured continuous clock operation. This changed noncontinuous clock simply tying 12/8/CLK input with other connections remaining same. NEC7720 expects valid data rising edge input therefore inverter required SCLK output ADC. NEC7720 configured 16-bit data word. Once bits data have been received register NEC7720, internal interrupt generated read contents register. NEC77230 interface similar that just outlined NEC7720. However, clock input NEC77230 SICLK. Additionally, inverter required between SCLK output this SICLK input since NEC77230 assumes data valid falling edge SICLK.
AD7870/ AD7875/ AD78761
TIMER CONVST 12/8/CLK 4.7k SIEN SCLK 4.7k SSTRB SCLK SDATA
DATA
07730-025
1ADDITIONAL PINS OMITTED CLARITY. 2RESISTOR CAPACITOR REQUIRED GUARANTEE
Figure MC68008 Byte Interface
SERIAL INTERFACING
Figure Figure Figure Figure show AD7870/AD7875/AD7876 configured serial interfacing. four interfaces, configured Mode operation. interfaces show timer driving CONVST input, this could generated from decoded address required. SCLK, SDAT SSTRB open-drain outputs. these required drive capacitive loads excess buffering recommended.
DSP56000 Serial Interface
Figure shows serial interface between AD7870/AD7875/ AD7876, DSP56000. interface arrangement two-wire with configured noncontinuous clock operation (12/8/CLK DSP56000 configured normal mode asynchronous operation with gated clock. also 16-bit word with inputs control this configuration, DSP56000 assumes valid data first falling edge SCK. Since provides valid data this first edge, there need strobe framing pulse data. SCLK SDATA gated when performing
µPD7720
1ADDITIONAL PINS OMITTED CLARITY.
Figure NEC7720 Serial Interface
Rev. Page
AD7870/AD7875/AD7876
TMS32020 Serial Interface
Figure shows serial interface between AD7870/ AD7875/AD7876 TMS32020. AD7870/AD7875/ AD7876 configured continuous clock operation. Note that will interface correctly TMS32020 configured noncontinuous clock. Data clocked into data receive register (DRR) TMS32020 during conversion. with previous interfaces, when 16-bit word received TMS32020 generates internal interrupt read data from DRR.
AD7870/ AD7875/ AD78761
TIMER CONVST 12/8/CLK 4.7k CLKR 4.7k SSTRB SCLK
07730-028
AD7870/ AD7875/ AD78761
TIMER CONVST 12/8/CLK 4.7k 4.7k SSTRB SCLK
07730-029
ADSP-2101/ ADSP-2102
CLKR
SDATA
1ADDITIONAL PINS OMITTED CLARITY.
Figure ADSP-2101/ADSP-2102 Serial Interface
STANDALONE OPERATION
AD7870/AD7875/AD7876 used Mode parallel interface mode standalone operation. this case, conversion initiated with pulse input. This pulse must longer than conversion time ADC. BUSY output used drive input. Data latched from DB0-DB11 outputs external latch rising edge BUSY.
tCS1
TMS32020
SDATA
1ADDITIONAL PINS OMITTED CLARITY.
Figure TMS32020 Serial Interface
ADSP-2101/ADSP-2102 Serial Interface
Figure shows serial interface between AD7870/ AD7875/AD7876 ADSP-2101/ADSP-2102. configured continuous clock operation. Data clocked into serial port register ADSP-2101/ADSP-2102 during conversion. with previous interfaces, when 16bit data word received ADSP-2101/ADSP-2102 internal microprocessor interrupt generated data read from serial port register.
AD7870/ AD7875/ AD78762
BUSY
LATCH
DB11
tCONVERT 2ADDITIONAL PINS OMITTED CLARITY.
07730-030
Figure Stand-Alone Operation
Rev. Page
AD7870/AD7875/AD7876 APPLICATIONS INFORMATION
Good printed circuit board (PCB) layout important overall circuit design itself achieving high speed analogto-digital performance. designer conscious noise both itself preceding analog circuitry. Switching mode power supplies recommended because switching spikes feed through comparator causing noisy code transitions. Other causes concern ground loops digital feedthrough from microprocessors. These factors which influence ADC, proper layout which minimizes these effects essential best performance. AD7870/AD7875/AD7876 DGND this single analog ground point. connect other digital grounds this analog ground point. impedance analog digital power supply common returns essential noise operation ADC, make foil width these tracks wide possible. ground planes minimizes impedance paths also guards analog circuitry from digital noise. circuit layout both analog digital ground planes which kept separated only joined together AD7870/ AD7875/AD7876 AGND pin.
LAYOUT HINTS
Ensure that layout printed circuit board digital analog signal lines separated much possible. Take care digital track alongside analog signal track. Guard (screen) analog input with AGND. Establish single point analog ground (star ground) separate from logic system ground AGND close possible ADC. Connect other grounds
NOISE
Keep input signal leads signal return leads from AGND short possible minimize input noise coupling. applications where this possible, shielded cable between source ADC. Reduce ground circuit impedance much possible since potential difference grounds between signal source appears error voltage series with input signal.
Rev. Page
AD7870/AD7875/AD7876 OUTLINE DIMENSIONS
1.280 (32.51) 1.250 (31.75) 1.230 (31.24)
0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) 0.015 (0.38) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92)
0.100 (2.54) 0.210 (5.33) 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36)
0.015 (0.38) GAUGE PLANE SEATING PLANE 0.430 (10.92)
0.005 (0.13) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14)
0.014 (0.36) 0.010 (0.25) 0.008 (0.20)
COMPLIANT JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS INCHES; MILLIMETER DIMENSIONS PARENTHESES) ROUNDED-OFF INCH EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN. CORNER LEADS CONFIGURED WHOLE HALF LEADS.
Figure 24-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-24-1) Dimensions shown inches (millimeters)
0.005 (0.13)
0.098 (2.49)
0.310 (7.87) 0.220 (5.59)
0.200 (5.08) 1.280 (32.51)
0.060 (1.52) 0.015 (0.38) 0.150 (3.81)
0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20)
0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36)
0.100 (2.54)
0.070 (1.78) SEATING 0.030 (0.76) PLANE
CONTROLLING DIMENSIONS INCHES; MILLIMETER DIMENSIONS PARENTHESES) ROUNDED-OFF INCH EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN.
Figure 24-Lead Ceramic Dual In-Line Package [CERDIP] Narrow Body (Q-24-1) Dimensions shown inches (millimeters)
Rev. Page
100808-A
071006-A
AD7870/AD7875/AD7876
0.048 (1.22) 0.042 (1.07)
IDENTIFIER
0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07) 0.020 (0.51) 0.021 (0.53) 0.013 (0.33) 0.032 (0.81) 0.026 (0.66)
0.048 (1.22) 0.042 (1.07)
VIEW
(PINS DOWN)
0.050 (1.27)
0.430 (10.92) 0.390 (9.91)
BOTTOM VIEW (PINS
0.456 (11.582) 0.450 (11.430) 0.495 (12.57) 0.485 (12.32)
0.120 (3.04) 0.090 (2.29)
0.045 (1.14) 0.025 (0.64)
COMPLIANT JEDEC STANDARDS MO-047-AB CONTROLLING DIMENSIONS INCHES; MILLIMETER DIMENSIONS PARENTHESES) ROUNDED-OFF INCH EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN.
Figure 28-Lead Plastic Leaded Chip Carrier [PLCC] (P-28) Dimensions shown inches (millimeters)
15.60 (0.6142) 15.20 (0.5984)
7.60 (0.2992) 7.40 (0.2913)
10.65 (0.4193) 10.00 (0.3937)
0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 1.27 (0.0500) 0.51 (0.0201) 0.31 (0.0122)
2.65 (0.1043) 2.35 (0.0925)
0.75 (0.0295) 0.25 (0.0098)
SEATING PLANE
0.33 (0.0130) 0.20 (0.0079)
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT JEDEC STANDARDS MS-013-AD CONTROLLING DIMENSIONS MILLIMETERS; INCH DIMENSIONS PARENTHESES) ROUNDED-OFF MILLIMETER EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN.
Figure 24-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-24) Dimensions shown millimeters (inches)
Rev. Page
060706-A
042508-A
AD7870/AD7875/AD7876
ORDERING GUIDE
Table
Model AD7870JN AD7870JNZ AD7870KN AD7870KNZ1 AD7870LN AD7870LNZ1 AD7870JP AD7870JP-REEL AD7870JPZ1 AD7870JPZ-REEL1 AD7870KP AD7870KP-REEL AD7870KPZ1 AD7870KPZ-REEL1 AD7870LP AD7870LP-REEL AD7870LPZ1 AD7870AQ AD7870BQ AD7870CQ AD7870TQ AD7875KN AD7875KNZ1 AD7875LN AD7875LNZ1 AD7875KP AD7875KPZ1 AD7875KPZ-REEL1 AD7875LP-REEL AD7875LPZ1 AD7875LPZ-REEL1 AD7875BQ AD7875CQ AD7875TQ AD7876BN AD7876BNZ1 AD7876CN AD7876CNZ1 AD7876BR AD7876BR-REEL AD7876BR-REEL7 AD7876BRZ1 AD7876BRZ-REEL1 AD7876BRZ-REEL71 AD7876CR AD7876CR-REEL AD7876CRZ1 AD7876BQ AD7876TQ
Temperature Range +70°C +70°C +70°C +70°C +70°C +70°C +70°C +70°C +70°C +70°C +70°C +70°C +70°C +70°C +70°C +70°C +70°C -25°C +85°C -25°C +85°C -25°C +85°C -55°C +125°C +70°C +70°C +70°C +70°C +70°C +70°C +70°C +70°C +70°C +70°C -40°C +85°C -40°C +85°C -55°C +125°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C
Voltage Range
(dBs)
Integral Nonlinearity (LSB) ±1/2 ±1/2 ±1/2 ±1/2 ±1/2 ±1/2 ±1/2 ±1/2 ±1/2 ±1/2 ±1/2 ±1/2 ±1/2 ±1/2 ±1/2 ±1/2 ±1/2 ±1/2 ±1/2 ±1/2 ±1/2 ±1/2 ±1/2 ±1/2
Package Description 24-Lead PDIP 24-Lead PDIP 24-Lead PDIP 24-Lead PDIP 24-Lead PDIP 24-Lead PDIP 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 24-Lead CERDIP 24-Lead CERDIP 24-Lead CERDIP 24-Lead CERDIP 24-Lead PDIP 24-Lead PDIP 24-Lead PDIP 24-Lead PDIP 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 24-Lead CERDIP 24-Lead CERDIP 24-Lead CERDIP 24-Lead PDIP 24-Lead PDIP 24-Lead PDIP 24-Lead PDIP 24-Lead SOIC_W 24-Lead SOIC_W 24-Lead SOIC_W 24-Lead SOIC_W 24-Lead SOIC_W 24-Lead SOIC_W 24-Lead SOIC_W 24-Lead SOIC_W 24-Lead SOIC_W 24-Lead CERDIP 24-Lead CERDIP
Package Option N-24-1 N-24-1 N-24-1 N-24-1 N-24-1 N-24-1 P-28 P-28 P-28 P-28 P-28 P-28 P-28 P-28 P-28 P-28 P-28 Q-24-1 Q-24-1 Q-24-1 Q-24-1 N-24-1 N-24-1 N-24-1 N-24-1 P-28 P-28 P-28 P-28 P-28 P-28 Q-24-1 Q-24-1 Q-24-1 N-24-1 N-24-1 N-24-1 N-24-1 RW-24 RW-24 RW-24 RW-24 RW-24 RW-24 RW-24 RW-24 RW-24 Q-24-1 Q-24-1
RoHS Compliant Part.
Rev. Page
AD7870/AD7875/AD7876 NOTES
Rev. Page
AD7870/AD7875/AD7876 NOTES
Rev. Page
AD7870/AD7875/AD7876 NOTES
©1997-2009 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. D07730-0-2/09(C)
Rev. Page
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