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Nonvolatile Memory, Dual 256-Position Digital Potentiometer AD5232
Dual-channel, 256-position resolution nominal terminal resistance Nonvolatile memory maintenance wiper settings Predefined linear increment/decrement instructions Predefined step taper increment/decrement instructions SPI-compatible serial interface Wiper settings EEMEM readback single-supply operation ±2.5 dual-supply operation bytes general-purpose user EEMEM Permanent memory write protection 100-year typical data retention 55°C)
SERIAL INTERFACE EEMEM1 RDAC1
FUNCTIONAL BLOCK DIAGRAM
ADDR DECODE
AD5232
RDAC1 REGISTER
POWER-ON RESET
RDAC2 REGISTER EEMEM2 RDAC2
EEMEM CONTROL
APPLICATIONS
Mechanical potentiometer replacement Instrumentation: gain offset adjustment Programmable voltage-to-current conversion Programmable filters, delays, time constants Programmable power supply resolution replacement Sensor calibration
BYTES USER EEMEM
02618-001
Figure
GENERAL DESCRIPTION
AD5232 device provides nonvolatile, dual-channel, digitally controlled variable resistor (VR) with 256-position resolution. This device performs same electronic adjustment function mechanical potentiometer with enhanced resolution, solid state reliability, superior temperature coefficient performance. versatile programming AD5232, perormed microcontroller, allows multiple modes operation adjustment. direct program mode, predetermined setting RDAC registers (RDAC1 RDAC2) loaded directly from microcontroller. Another important mode operation allows RDACx register refreshed with setting previously stored corresponding EEMEM register (EEMEM1 EEMEM2). When changes made RDACx register establish wiper position, value setting saved into EEMEMx register executing EEMEM save operation. After settings saved EEMEMx register, these values automatically transferred RDACx register wiper position system power-on. Such operation enabled internal preset strobe. preset strobe also accessed externally.
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
internal register contents read serial data output (SDO). This includes RDAC1 RDAC2 registers, corresponding nonvolatile EEMEM1 EEMEM2 registers, spare USER EEMEM registers that available constant storage. basic mode adjustment increment decrement command instructions that control wiper position setting register (RDACx). internal scratch RDACx register moved down step nominal resistance between Terminal Terminal This step adjustment linearly changes wiper Terminal resistance (RWB) position segment device's end-to-end resistance (RAB). exponential/ logarithmic changes wiper setting, left/right shift command instruction adjusts levels steps, which useful audio light alarm applications. AD5232 available thin, 16-lead TSSOP package. parts guaranteed operate over extended industrial temperature range -40°C +85°C. evaluation board, EVAL-AD5232-10EBZ, available.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2001-2009 Analog Devices, Inc. rights reserved.
AD5232 TABLE CONTENTS
Features Applications Functional Block Diagram General Description Revision History Specifications. Electrical Characteristics-10 Versions Interface Timing Characteristics Absolute Maximum Ratings. Thermal Resistance Caution Configuration Function Descriptions Typical Performance Characteristics Test Circuits Theory Operation Scratch EEMEM Programming. Basic Operation EEMEM Protection Digital Input/Output Configuration. Serial Data Interface Daisy-Chaining Operation. Advanced Control Modes Using Additional Internal, Nonvolatile EEMEM Terminal Voltage Operating Range Detailed Potentiometer Operation Programming Variable Resistor Programming Potentiometer Divider Operation from Dual Supplies Application Programming Examples Equipment Customer Start-up Sequence Calibrated Unit with Protected Settings Flash/EEMEM Reliability. Evaluation Board Outline Dimensions Ordering Guide
REVISION HISTORY
10/09-Rev. Rev. Updated Format Universal Changes Data Sheet Title Changes Features Section. Changes Applications Section Change Wiper Resistance Parameter, Table Changes Rise Fall Time Parameter, Table Changes Figure Figure Changes Figure Added Figure Changes Serial Data Interface Section Changes Programming Variable Resistor Section Changes Ordering Guide 10/01-Revision Initial Version
Rev. Page
AD5232 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS-10 VERSIONS
+VDD, -40°C +85°C, unless otherwise noted. Table
Parameter CHARACTERISTICS, RHEOSTAT MODE Resistor Differential Nonlinearity2 Resistor Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient Wiper Resistance POTENTIOMETER DIVIDER MODES Resolution Differential Nonlinearity3 Integral Nonlinearity3 Voltage Divider Temperature Coefficient Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Terminal Voltage Range4 Capacitance Capacitance Common-Mode Leakage Current5, DIGITAL INPUTS OUTPUTS Input Logic High Input Logic Input Logic High Input Logic Input Logic High Input Logic Output Logic High (SDO RDY) Output Logic Input Current Input Capacitance5 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Programming Mode Current Read Mode Current7 Negative Supply Current Power Dissipation8 Power Supply Sensitivity5 Symbol Conditions Specifications apply RWB, RWB, Typ1 Unit
R-DNL R-INL RAB/T
-0.4
±1/2
+0.4
code 0x1E code 0x1E -0.4 Code half scale Code full scale Code zero scale MHz, measured GND, code half-scale MHz, measured GND, code half scale VDD/2 With respect GND, With respect GND, With respect GND, VDD= With respect GND, With respect GND, +2.5 -2.5 With respect GND, +2.5 -2.5 RPULL-UP VLOGIC
ppm/°C Bits ppm/°C
VW/T VWFSE VWZSE VDD/VSS IDD(PG) IDD(XFR) PDISS
±1/2
+0.4
0.01
±2.5
GND, +2.5 -2.5
±2.25 0.018 0.002
±2.75 0.05 0.01
Rev. Page
AD5232
Parameter DYNAMIC CHARACTERISTICS5, Bandwidth Total Harmonic Distortion Settling Time Symbol Conditions BW_10k, rms, kHz, rms, kHz, VDD, 0.50% error band, Code 0x00 Code 0x80 k/50 k/100 VDD, measure with adjacent making full-scale code change VDD, measure with kHz; Code1 0x80; Code2 0xFF 0.022 0.045 0.65/3/6 Unit
THDw
Resistor Noise Voltage Crosstalk (CW1/CW2) Analog Crosstalk (CW1/CW2) FLASH/EE MEMORY RELIABILITY Endurance Data Retention
eN_WB
mV/Hz nV-sec
kCycles Years
Typical parameters represent average readings 25°C Resistor position nonlinearity (R-INL) error deviation from ideal value measured between maximum resistance minimum resistance wiper positions. R-DNL measures relative step change from ideal between successive positions. Parts guaranteed monotonic. version, version, version (see Figure 22). measured with RDACx configured potentiometer divider similar voltage output digital-to-analog converter. VSS. specification limits maximum guaranteed monotonic operating conditions (see Figure 23). resistor terminals have limitations polarity with respect each other. Dual supply operation enables ground-referenced bipolar signal adjustment. Guaranteed design; subject production test. Common-mode leakage current measure leakage from terminal common-mode bias level VDD/2. Transfer (XFR) mode current continuous. Current consumed while EEMEMx locations read transferred RDACx register (see Figure 13). PDISS calculated from (IDD VDD) (ISS VSS). dynamic characteristics +2.5 -2.5 unless otherwise noted. Endurance qualified 100,000 cycles JEDEC Std. Method A117 measured -40°C, +25°C, +85°C. Typical endurance +25°C 700,000 cycles. retention lifetime equivalent junction temperature (TJ) 55°C, JEDEC Std. Method A117. Retention lifetime, based activation energy derates with junction temperature shown Figure Flash/EEMEM Reliability section. AD5232 contains 9,646 transistors. size mil, 7,993 mil.
Rev. Page
AD5232
INTERFACE TIMING CHARACTERISTICS
input control voltages specified with (10% timed from voltage level Switching characteristics measured using both Table
Parameter1, Clock Cycle Time (tCYC) Setup Time Shutdown Time Rise Input Clock Pulse Width Data Setup Time Data Hold Time SDO-SPI Line Acquire SDO-SPI Line Release Propagation Delay4 Data Hold Time High Pulse Width5 High High5 Rise Fall Rise Fall Time Store/Read EEMEM Time6 Rise Clock Rise/Fall Setup Preset Pulse Width (Asynchronous) Preset Response Time High
Symbol tPRW tPRESP
Conditions
Clock level high From positive transition From positive transition
Typ3
0.15
Applies Command Instruction Command Instruction Command Instruction shown timing diagram pulsed refresh wiper positions
Unit tCYC tCYC
Guaranteed design; subject production test. Timing Diagrams section location measured values. Typicals represent average readings 25°C Propagation delay depends value VDD, RPULL-UP, Valid commands that activate pin. only Command Instruction Command Instruction Command Instruction Command Instruction Command Instruction hardware pulse: CMD_8 CMD_9 CMD_10 0.12 CMD_2 CMD_3 Device operation -40°C extends save time
Rev. Page
AD5232
Timing Diagrams
CPHA
CPOL
HIGH
(MSB) (LSB)
HIGH
B16* (MSB)
(LSB)
NOTES EXTRA THAT DEFINED, USUALLY CHARACTER THAT PREVIOUSLY TRANSMITTED. CPOL MICROCONTROLLER COMMAND ALIGNS INCOMING DATA POSITIVE EDGE CLOCK.
Figure CPHA
CPHA (MSB)
(LSB)
CPOL
HIGH HIGH
(MSB
(LSB)
(MSB OUT)
(LSB)
NOTES THIS EXTRA DEFINED, USUALLY CHARACTER THAT JUST RECEIVED. CPOL MICROCONTROLLER COMMAND ALIGNS INCOMING DATA POSITIVE EDGE CLOCK.
Figure CPHA
Rev. Page
02618-003
02618-002
AD5232 ABSOLUTE MAXIMUM RATINGS
25°C, unless otherwise noted. Table
Parameter Intermittent1 Continuous Digital Inputs Output Voltage Operating Temperature Range2 Maximum Junction Temperature max) Storage Temperature Range Lead Temperature, Soldering Vapor Phase sec) Infrared sec) Package Power Dissipation
Rating -0.3 +0.3 -0.3 -40°C +85°C 150°C -65°C +150°C 215°C 220°C TA)/JA
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
THERMAL RESISTANCE
specified worst-case conditions, that device soldered circuit board surface-mount packages. Table Thermal Resistance
Package Type 16-Lead TSSOP (RU-16) Unit °C/W
CAUTION
Maximum terminal current bounded maximum current handling switches, maximum power dissipation package, maximum applied voltage across terminals given resistance. Includes programming nonvolatile memory.
Rev. Page
AD5232 CONFIGURATION FUNCTION DESCRIPTIONS
02618-004
AD5232
VIEW (Not Scale)
Figure Configuration
Table Function Descriptions
Mnemonic Description Serial Input Register Clock. Shifts time positive clock edges. Serial Data Input. loaded first. Serial Data Output. This open-drain output requires external pull-up resistor. Command Instruction Command Instruction activate output (see Table Other commands shift previously loaded pattern delayed clock pulses, allowing daisy-chain operation multiple packages. Ground, Logic Ground Reference. Negative Power Supply. Connect single-supply applications. Terminal RDAC1. Wiper Terminal RDAC1, ADDR (RDAC1) 0x0. Terminal RDAC1. Terminal RDAC2. Wiper Terminal RDAC2, ADDR (RDAC2) 0x1. Terminal RDAC2. Positive Power Supply. Write Protect. When active low, prevents changes present register contents, except Command Instruction Command Instruction which refresh RDACx register from EEMEM. Execute instruction (Command Instruction before returning logic high. Hardware Override Preset. Refreshes scratch register with current contents EEMEMx register. Factory default loads Midscale 0x80 until EEMEMx loaded with value user activated logic high transition). Serial Register Chip Select, Active Low. Serial register operation takes place when returns logic high. Ready. This active-high, open-drain output requires pull-up resistor. Identifies completion Command Instruction Command Instruction Command Instruction Command Instruction Command Instruction
Rev. Page
AD5232 TYPICAL PERFORMANCE CHARACTERISTICS
2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 -0.25 -0.50 -0.75 -1.00 -1.25 -1.50 -1.75
02618-005
2000
2.7V
RHEOSTAT MODE TEMPCO (ppm/°C)
-40°C
1500
-40°C/+85°C CONNECT MEASURED
ERROR (LSB)
+25°C
1000
+85°C
DIGITAL CODE
CODE (Decimal)
Figure Code; -40°C, +25°C, +85°C Overlay
2.00 1.50 1.25 1.00 0.75 0.50 0.25 -0.25 -0.50 -0.75 -1.00 -1.25 -1.50 -1.75
02618-006
Figure RWB/T Code;
POTENTIOMETER MODE TEMPCO (ppm/°C)
1.75
2.7V
-40°C/+85°C
ERROR (LSB)
-40°C +25°C
+85°C
DIGITAL CODE
CODE (Decimal)
Figure Code; -40°C, +25°C, +85°C Overlay
0.20 0.15 0.10
R-DNL (LSB)
Figure VWB/T Code;
5.5V 25°C
+2.5V -2.5V
0.05 -0.05
(µA)
0.01
-0.10 -0.15
02618-007
CODE (Decimal)
TEMPERATURE (°C)
Figure R-DNL Code; Overlay
Figure Temperature (See Figure
Rev. Page
02618-010
-0.20
0.001
02618-009
-2.00
02618-008
-2.00
AD5232
5.5V
f-3dB 500kHz,
GAIN (dB)
f-3dB 45kHz, 100k f-3dB 95kHz,
(µA)
100mV +2.5V -2.5V +25°C
2.7V
02618-011
TEMPERATURE (°C)
100k FREQUENCY (Hz)
Figure Temperature
Figure Bandwidth Resistance
25°C FILTER 22kHz
NOISE
0.01
50k, 100k
2mA/DIV 5.00V 5.00V 5.00V 10.00V 2.00ms
02618-015
02618-012
0.001
FREQUENCY (Hz)
100k
Figure Time (Save) Program Mode
Figure Total Harmonic Distortion Noise Frequency
2.7V 25°C
IDD* 2mA/DIV
CODE (Decimal)
02618-016
5.00V 5.00V
5.00V 10.00V
2.00ms
02618-013
*SUPPLY CURRENT RETURNS MINIMUM POWER CONSUMPTION COMMAND INSTRUCTION (NOP) EXECUTED IMMEDIATELY AFTER COMMAND INSTRUCTION (READ EEMEM).
Figure Time Read Mode
Figure Wiper Resistance Code
Rev. Page
02618-014
AD5232
GAIN (dB) 0x08 0x04 0x02 +2.7V -2.7V 100mV 25°C
0x80 0x40 100k
PSRR REJECTION (dB)
0x20 0x10
0x01
02618-017
5.5V 100mV MEASURE WITH CODE 0x80 25°C 100k FREQUENCY (Hz)
02618-020 02618-021
100k FREQUENCY (Hz)
Figure Gain Frequency Code,
GAIN (dB) +2.7V -2.7V 100mV 25°C
Figure PSRR Frequency
0x40 0x20 0x10 0x08 0x04 0x02 0x01
02618-018
ANALOG CROSSTALK REJECTION (dB)
0x80
100k
+2.75V -2.75V 25°C FREQUENCY (kHz)
100k FREQUENCY (Hz)
Figure Gain Frequency Code,
GAIN (dB) +2.7V -2.7V 100mV 25°C
Figure Analog Crosstalk Frequency (See Figure
0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 100k
02618-019
100k FREQUENCY (Hz)
Figure Gain Frequency Code,
Rev. Page
AD5232 TEST CIRCUITS
Figure Figure define test conditions that used Specifications section.
02618-022
OFFSET
OP279 OFFSET BIAS
VOUT
02618-026
CONNECT
Figure Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
Figure Inverting Gain
1LSB V+/2N
02618-023
OP279
VOUT
OFFSET
02618-027
OFFSET BIAS
Figure Potentiometer Divider Nonlinearity Error (INL, DNL)
VMS2
Figure Noninverting Gain
+15V 2.5V OP42
VOUT
02618-028
VDD/RNOMINAL
VMS1
02618-024
[VMS1 VMS2]/IW
OFFSET
-15V
Figure Wiper Resistance
PSRR (dB) (%/%) VMS% VDD%
02618-025
Figure Gain Frequency
0.1V 0.1V
CODE 0x00
Figure Power Supply Sensitivity (PSS, PSRR)
Figure Incremental Resistance
Rev. Page
02618-029
AD5232
200µA
OUTPUT
02618-030
50pF 200µA
(MIN) (MAX)
CONNECT
NOTES DIODE BRIDGE TEST CIRCUIT EQUIVALENT APPLICATION CIRCUIT WITH RPULL-UP 2.2k.
Figure Common-Mode Leakage Current
Figure Load Circuit Measuring
RDAC1
RDAC2 VOUT
[VOUT/VIN] CONNECT
Figure Analog Crosstalk
02618-031
Rev. Page
02618-032
AD5232 THEORY OPERATION
AD5232 digital potentiometer designed operate true variable resistor replacement device analog signals that remain within terminal voltage range VTERM VDD. basic voltage range limited |VDD VSS| digital potentiometer wiper position determined RDACx register contents. RDACx register acts scratch register, allowing many value changes necessary place potentiometer wiper correct position. scratch register programmed with position value using standard serial interface mode loading complete representative data-word. When desirable position found, this value saved into corresponding EEMEMx register. Thereafter, wiper position always that position future on-off-on power supply sequence. EEMEM save process takes approximately During this time, shift register locked, preventing changes from taking place. indicates completion this EEMEM save. application programming example shown Table lists digital potentiometers independent data values. wiper positions then saved corresponding nonvolatile EEMEMx registers. Table Application Programming Example
0xB040 0x20XX1 0xB180 0x21XX1
0xXXXX1 0xB040 0x20XX1 0xB180
Action Loads 0x40 data into RDAC1 register; Wiper moves full-scale position. Saves copy RDAC1 register contents into corresponding EEMEM1 register. Loads 0x80 data into RDAC2 register; Wiper moves full-scale position. Saves copy RDAC2 register contents into corresponding EEMEM2 register.
don't care.
SCRATCH EEMEM PROGRAMMING
scratch register (RDACx register) directly controls position digital potentiometer wiper. When scratch register loaded with wiper connected Terminal variable resistor. When scratch register loaded with midscale code (1/2 full-scale position), wiper connected middle variable resistor. When scratch loaded with full-scale code, which wiper connects Terminal Because scratch register standard logic register, there restriction number changes allowed. EEMEMx registers have program erase/write cycle limitation that described Flash/EEMEM Reliability section.
Note that pulse first sets wiper midscale when brought Logic Then, positive transition logic high, reloads wiper register with contents EEMEMx. Many additional advanced programming commands available simplify variable resistor adjustment process. example, wiper position changed, step time, using software controlled increment/decrement command instructions. wiper position also changed, time, using shift left/right command instructions. After increment, decrement, shift command instruction loaded into shift register, subsequent strobes repeat this command instruction. This useful push-button control applications (see Advanced Control Modes section). available daisy chaining readout internal register contents. serial input data register uses 16-bit instruction/address/data-word.
BASIC OPERATION
basic mode setting variable resistor wiper position programming scratch register) accomplished loading serial data input register with Command Instruction which includes desired wiper position data. When desired wiper position found, user loads serial data input register with Command Instruction which copies desired wiper position data into corresponding nonvolatile EEMEMx register. After wiper position permanently stored corresponding nonvolatile EEMEM location. Table provides application programming example listing sequence serial data input (SDI) words corresponding serial data output appearing serial data output (SDO) hexadecimal format. system power-on, scratch register refreshed with last value saved EEMEMx register. factory preset EEMEM value midscale. scratch (wiper) register refreshed with current contents nonvolatile EEMEMx register under hardware control pulsing pin.
EEMEM PROTECTION
write protect (WP) disables changes scratch register contents, regardless software commands, except that EEMEM setting refreshed using Instruction Command Therefore, provides hardware EEMEM protection feature. Execute command (Command Instruction before returning logic high.
DIGITAL INPUT/OUTPUT CONFIGURATION
digital inputs protected, high input impedance that driven directly from most digital sources. pins, which active logic low, must biased they being used. internal pull-up resistors present digital input pins. pins open-drain, digital outputs when pullup resistors needed, only these functions use. resistor value range optimizes power switching speed trade-off.
Rev. Page
AD5232
SERIAL DATA INTERFACE
AD5232 contains 4-wire SPI-compatible digital interface (SDI, SDO, CLK) uses 16-bit serial data-word that loaded first. format SPI-compatible word shown Table chip select (CS) must held until complete data-word loaded into pin. When returns high, serial data-word decoded according instructions Table command bits (Cx) control operation digital potentiometer. address bits (Ax) determine which register activated. data bits (Dx) values that loaded into decoded register. Table provides address EEMEM locations. last command instruction executed prior period programming activity should operation (NOP) command instruction (Command Instruction This instruction places internal logic circuitry minimum power dissipation state.
VALID COMMAND COUNTER
LOGIC PINS
INPUTS
Figure Equivalent Digital Input Protection
INPUTS
COMMAND PROCESSOR ADDRESS DECODE
Figure Equivalent Input Protection
RPULL-UP
DAISY-CHAINING OPERATION
serves purposes: used read back contents wiper setting EEMEM using Command Instruction Command Instruction (see Table used daisy-chaining multiple devices.The remaining command instructions valid daisy-chaining multiple devices simultaneous operations. Daisy chaining minimizes number port pins required from controlling (see Figure 36). contains open-drain N-channel that requires pull-up resistor this function used. shown Figure users must package next package. Users need increase clock period because pull-up resistor capacitive loading SDO-to-SDI interface require additional time delay between subsequent packages. AD5232s daisy-chained, bits data required. first bits second bits with same format bits formatted contain 4-bit instruction, followed 4-bit address, followed eight bits data. should kept until bits locked into their respective serial registers. then pulled high complete operation.
SERIAL REGISTER
AD5232
Figure Equivalent Digital Input/Output Logic
AD5232 internal counter that counts multiple bits (per frame) proper operation. example, AD5232 works with 16-bit 32-bit word, cannot work properly with 15-bit 17-bit word. prevent data from mislocking (due noise, example), counter resets count multiple when goes high, data remains register count multiple addition, AD5232 subtle feature whereby, pulsed without SDI, part repeats previous command (except during powerup). result, care must taken ensure that excessive noise exists line that alter effective number bits pattern. equivalent serial data input output logic shown Figure open-drain disabled whenever logic high. interface used slave modes: CPHA CPOL CPHA CPOL CPHA CPOL refer control bits that dictate timing following microprocessors MicroConverter® devices: ADuC812 ADuC824, M68HC11, MC68HC16R1/916R1. protection digital inputs shown Figure Figure
02618-033
AD5232
2.2k
AD5232
MicroConverter
02618-035
AD5232
02618-034
AD5232
02618-036
Figure Daisy-Chain Configuration Using
Rev. Page
AD5232
Command bits identified address bits data bits command instruction codes defined Table output shifts last eight bits data clocked into serial register daisy-chain operation, with following exception: after Command Instruction Command Instruction selected internal register data present Data Byte command instructions following Command Instruction Command Instruction must full 16-bit Table 16-Bit Serial Data Word
data-words completely clock contents serial register. RDACx register volatile scratch register that refreshed power-on from corresponding nonvolatile EEMEMx register. increment, decrement, shift command instructions ignore contents Data Byte shift register. Execution operation noted Table occurs when strobe returns logic high. Execution instruction minimizes power dissipation.
Table Instruction/Operation Truth Table
Comm. Inst. Instruction Byte Data Byte Operation operation (NOP). nothing. Write contents EEMEM (A0) RDAC (A0) register. This command leaves device read program power state. return part idle state, perform Command Instruction (NOP). Save wiper setting. Write contents RDAC (ADDR) EEMEM (A0). Write contents Serial Register Data Byte EEMEM (ADDR). Decrement right shift contents RDAC (A0). Stops Decrement right shift contents RDAC registers. Stops Decrement contents RDAC (A0) Stops Decrement contents RDAC registers Stops Reset. Load RDACs with their corresponding, previously saved EEMEM values. Write contents EEMEM(ADDR) Serial Register Data Byte Write contents RDAC (A0) Serial Register Data Byte Write contents Serial Register Data Byte RDAC (A0). Increment left shift contents RDAC (A0). Stops Increment left shift contents RDAC registers. Stops Increment contents RDAC (A0) Stops Increment contents RDAC registers Stops
ADDR
ADDR
Rev. Page
AD5232
ADVANCED CONTROL MODES
AD5232 digital potentiometer contains user programming features address wide variety applications available these universal adjustment devices. programming features include following: Independently programmable read write registers Simultaneous refresh RDAC wiper registers from corresponding internal EEMEM registers Increment decrement command instructions each RDAC wiper register Left right shift RDAC wiper registers achieve level changes Nonvolatile storage present scratch RDACx register values into corresponding EEMEMx register Fourteen extra bytes user-addressable, electrical erasable memory tional instruction does change wiper position from full scale (RDACx register code 255). Figure illustrates operation shifting function individual RDACx register data bits 8-bit AD5232 example. Each line going down table represents successive shift operation. Note that Left Shift Left Shift command instructions were modified that data RDACx register equal left shifted, then Code addition, left shift commands were modified that data RDAC register greater than equal midscale left shifted, data then full scale. This makes left shift function close ideally logarithmic possible. Right Shift Right Shift command instructions ideal only (that ideal logarithmic, with error). right shift function generates linear halfLSB error that translates code-dependent logarithmic error codes only, shown Figure plot shows errors codes.
LEFT SHIFT RIGHT SHIFT 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 1111 1111 1111 1111 1111 1111 0111 1111 0011 1111 0001 1111 0000 0111 0000 0011 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000
Increment Decrement Commands
increment decrement command instructions (Command Instruction Command Instruction Command Instruction Command Instruction useful basic servo adjustment application. These commands simplify microcontroller software coding eliminating need perform readback current wiper position then register contents using microcontroller adder. microcontroller sends increment command instruction (Command Instruction digital potentiometer, which automatically moves wiper next resistance segment position. master increment command instruction (Command Instruction moves potentiometer wipers position from their present position next resistor segment position. direction movement referenced Terminal Thus, each Command Instruction moves wiper position farther from Terminal
LEFT SHIFT (+6dB)
RIGHT SHIFT (-6dB)
Figure Detail Left Right Shift Function
Logarithmic Taper Mode Adjustment
Programming instructions allow decrement increment wiper position control individual potentiometer ganged potentiometer arrangement, where both wiper positions changed same time. These settings activated decrement increment command instructions (Command Instruction Command Instruction Command Instruction Command Instruction respectively). example, starting with wiper connected Terminal executing nine increment instructions (Command Instruction moves wiper steps from (Terminal position 100% position AD5232 8-bit potentiometer. increment instruction doubles value RDACx register contents each time command executed. When wiper position greater than midscale, last increment command instruction causes wiper full-scale code position. addi-
Actual conformance logarithmic curve between data contents RDACx register wiper position each Right Shift Right Shift command execution contains error only codes. even codes ideal, with exception zero right shift greater than half-scale left shift. Figure shows plots Log_Error, that log10 (error/code). example, Code Log_Error log10 (0.5/3) -15.56 which worst case. plot Log_Error more significant lower codes.
GAIN (dB)
LOG_ERROR (CODE) 8-BIT
CODE, FROM
Figure Plot Log_Error Conformance Codes Only (Even Codes Ideal)
Rev. Page
02618-038
02618-037
AD5232
USING ADDITIONAL INTERNAL, NONVOLATILE EEMEM
AD5232 contains additional internal user storage registers (EEMEM) saving constants other 8-bit data. Table provides address internal nonvolatile storage registers, which shown functional block diagram EEMEM1, EEMEM2, bytes USER EEMEM. Note following about EEMEM function: RDAC data stored EEMEM locations transferred their corresponding RDACx register power-on when Command Instruction Command Instruction executed. USERx refers internal nonvolatile EEMEM registers that available store retrieve constants using Command Instruction Command Instruction respectively. EEMEM locations byte each (eight bits). Execution Command Instruction leaves device read mode power consumption state. When final Command Instruction executed, user should perform (Command Instruction return device power idle state.
Figure Maximum Terminal Voltages
Table RDAC Digital Register Address
Register Address (ADDR) 0000 0001
Name Register1 RDAC1 RDAC2
RDACx registers contain data that determines position variable resistor wiper.
DETAILED POTENTIOMETER OPERATION
actual structure RDACx designed emulate performance mechanical potentiometer. RDACx contains multiple strings connected resistor segments, with array analog switches that wiper connection several points along resistor array. number points equal resolution device. example, AD5232 connection points, allowing provide better than 0.5% setability resolution. Figure provides equivalent diagram connections between three terminals that make channel RDACx. switches always whereas only SW(0) SW(2N-1) switches time, depending resistance step decoded from data bits. resistance contributed must accounted output resistance.
Table EEMEM Address
EEMEM Address (ADDR) 0000 0001 0010 0011 0100 0101 1111 EEMEM Contents Each Device EEMEM (ADDR) RDAC1 RDAC2 USER USER USER USER USER
TERMINAL VOLTAGE OPERATING RANGE
positive negative power supply digital potentiometer defines boundary conditions proper 3-terminal programmable resistance operations. Signals present Terminal Terminal Wiper Terminal that exceed clamped forward biased diode (see Figure 39). ground AD5232 device used primarily digital ground reference that needs tied common ground PCB. digital input logic signals AD5232 must referenced ground (GND) device satisfy minimum input logic high level maximum input logic level that defined Specifications section. internal level shift circuit between digital interface wiper switch control ensures that common-mode voltage range three terminals, Terminal Terminal Wiper Terminal extends from VDD.
SW(2N-1) SW(2N-2)
RDAC WIPER REGISTER DECODER
SW(1)
RAB/2N
SW(2)
NOTES DIGITAL CIRCUITRY OMITTED CLARITY
Figure Equivalent RDAC Structure
Rev. Page
02618-040
02618-039
AD5232
Table Nominal Individual Segment Resistor Values
PERCENT NOMINAL END-TO-END RESISTANCE RAB)
Device Resolution 8-Bit
Version 78.10
Segmented Resistor Size End-to-End Values Version Version 390.5 781.0
PROGRAMMING VARIABLE RESISTOR
Rheostat Operation
nominal resistances RDACx between Terminal Terminal available with values final digits part number determine nominal resistance value; example, 100. nominal resistance (RAB) AD5232 contact points accessed Wiper Terminal plus Terminal contact. 8-bit data-word RDACx latch decoded select possible settings. general transfer equation, which determines digitally programmed output resistance between
CODE (Decimal)
02618-041
Figure Symmetrical RDAC Operation
When these terminals used, Terminal should tied wiper. Setting resistance value starts maximum value resistance decreases data loaded latch increased value. general transfer equation this operation
where: decimal equivalent data contained RDACx register. nominal resistance between Terminal Terminal wiper resistance. Table lists output resistance values that RDACx latch codes shown 8-bit, potentiometers.
Table Nominal Resistance Value Selected Codes
(Dec)
where: decimal equivalent data contained RDAC register. nominal resistance between Terminal Terminal wiper resistance. Table lists output resistance values that RDACx latch codes shown 8-bit, potentiometers.
Table Nominal Resistance Value Selected Codes
(Dec) 5050 10011 10050 Output State Full scale Midscale Zero scale
10011 5050
Output State Full scale Midscale Zero scale1 (wiper contact resistance)
Note that zero-scale condition, finite wiper resistance present. Care should taken limit current flow between this state maximum continuous value avoid degradation possible destruction internal switch metallization. Intermittent current operation allowed.
Like mechanical potentiometer that RDACx replaces, AD5232 parts totally symmetrical. resistance between Wiper Terminal Terminal also produces digitally controlled resistance, RWA. Figure shows symmetrical programmability various terminal connections.
multichannel AD5232 ±0.2% typical distribution internal channel-to-channel match. Device-to-device matching dependent process exhibits -40% +20% variation. change with temperature ppm/°C temperature coefficient.
Rev. Page
AD5232
PROGRAMMING POTENTIOMETER DIVIDER
Voltage Output Operation
digital potentiometer easily generates output voltage proportional input voltage applied given terminal. example, connecting Terminal Terminal produces output voltage wiper that value from Each voltage equal voltage applied across Terminal Terminal divided position resolution potentiometer divider. general equation defining output voltage with respect ground given input voltage applied Terminal Terminal
RDAC 45pF 45pF
60pF
Figure RDAC Circuit Simulation Model RDACx
following code provides macro model list RDAC:
.PARAM DW=255, RDAC=10E3 .SUBCKT DPOT (A,W,B) {45E-12} {(1-DW/256)*RDAC+50} 60E-12 {DW/256*RDAC+50} {45E-12} .ENDS DPOT
where RWB(D) obtained from Equation RWA(D) obtained from Equation Operation digital potentiometer divider mode results more accurate operation over temperature. Here output voltage dependent ratio internal resistors, absolute value; therefore, drift improves ppm/°C. There voltage polarity restriction between Terminal Terminal Wiper Terminal long terminal voltage (VTERM) stays within VTERM VDD.
APPLICATION PROGRAMMING EXAMPLES
command sequence examples shown Table Table have been developed illustrate typical sequence events various features AD5232 nonvolatile digital potentiometer. Table illustrates setting digital potentiometers independent data values.
Table
OPERATION FROM DUAL SUPPLIES
AD5232 operated from dual supplies, enabling control ground-referenced signals (see Figure typical circuit connection).
+2.5V
MicroConverter SCLK MOSI
0xB140 0xB080
0xXXXX 0xB140
Action Loads 0x40 data into RDAC2 register; Wiper moves full-scale position. Loads 0x80 data into RDAC1 register; Wiper moves full-scale position.
AD5232
02618-042
Table illustrates active trimming potentiometer, followed save nonvolatile memory (PCB calibrate).
Table
0xB040 0xE0XX 0xXXXX 0xB040 Action Loads 0x40 data into RDAC1 register; Wiper moves full-scale position. Increments RDAC1 register 0x41; Wiper moves resistor segment away from Terminal Increments RDAC1 register 0x42; Wiper moves more resistor segment away from Terminal Continue until desired wiper position reached. Saves RDAC1 register data into corresponding nonvolatile EEMEM1 memory: ADDR 0x0.
-2.5V
Figure Operation from Dual Supplies
internal parasitic capacitances external capacitive loads dominate characteristics RDACs. When configured potentiometer divider, bandwidth AD5232BRU10 resistor) measures half scale. Figure provides large signal BODE plot characteristics three resistor versions: (see Figure parasitic simulation model RDAC circuit).
0xE0XX
0xE0XX
0x20XX
0xE0XX
Rev. Page
02618-043
AD5232
Table illustrates using left shift-by-one change circuit gain steps. Table
0xC1XX 0xXXXX Action Moves Wiper double present data value contained RDAC2 register direction Terminal Moves Wiper double present data value contained RDAC2 register direction Terminal
During reliability qualification, Flash/EE memory cycled from 0x00 0xFF until first fail recorded, signifying endurance limit on-chip Flash/EE memory. indicated Specifications section, AD5232 Flash/EE memory endurance qualification been carried accordance with JEDEC Std. Method A117 over industrial temperature range -40°C +85°C. results allow specification minimum endurance figure over supply temperature 100,000 cycles, with endurance figure 700,000 cycles being typical operation 25°C. Retention quantifies ability Flash/EE memory retain programmed data over time. Again, AD5232 been qualified accordance with formal JEDEC Retention Lifetime Specification (A117) specific junction temperature 55°C. part this qualification procedure, Flash/EE memory cycled specified endurance limit, described previously, before data retention characterized. This means that Flash/EE memory guaranteed retain data full specified retention lifetime every time Flash/EE memory reprogrammed. should also noted that retention lifetime, based activation energy derates with shown Figure
0xC1XX
0xXXXX
Table illustrates storing additional data nonvolatile memory. Table
0x3280 0x3340 0xXXXX 0xXXXX Action Stores 0x80 data spare EEMEM location, USER1. Stores 0x40 data spare EEMEM location, USER2.
Table illustrates reading back data from various memory locations. Table
0x94XX 0x00XX 0xXXXX 0xXX80 Action Prepares data read from USER3 location. (USER3 already loaded with 0x80.) Instruction (NOP) sends 16-bit word where last eight bits contain contents USER3 location. command ensures that device returns idle power dissipation state.
RETENTION (Years)
TYPICAL PERFORMANCE 55°C
EQUIPMENT CUSTOMER START-UP SEQUENCE CALIBRATED UNIT WITH PROTECTED SETTINGS
setting, prevent changes wiper position. power with respect GND. optional step, strobe ensure full poweron preset wiper register with EEMEM contents unpredictable supply sequencing environments.
JUNCTION TEMPERATURE (°C)
Figure Flash/EE Memory Data Retention
EVALUATION BOARD
Analog Devices, Inc., offers user-friendly EVAL-AD5232-10EBZ evaluation that controlled personal computer through printer port. driving program self-contained; programming languages skills needed.
FLASH/EEMEM RELIABILITY
Flash/EE memory array AD5232 fully qualified Flash/EE memory characteristics: namely, Flash/EE memory cycling endurance Flash/EE memory data retention. Endurance quantifies ability Flash/EE memory cycled through many program, read, erase cycles. real terms, single endurance cycle composed four independent, sequential events. These events defined follows: Initial page erase sequence Read/verify sequence Byte program sequence Second read/verify sequence
Rev. Page
02618-044
AD5232 OUTLINE DIMENSIONS
5.10 5.00 4.90
4.50 4.40 4.30
6.40
1.20 0.20 0.09 0.65 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 0.75 0.60 0.45
0.15 0.05
COMPLIANT JEDEC STANDARDS MO-153-AB
Figure 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown millimeters
ORDERING GUIDE
Model AD5232BRU10 AD5232BRU10-REEL7 AD5232BRUZ102 AD5232BRUZ10-REEL72 AD5232BRU50 AD5232BRU50-REEL7 AD5232BRUZ502 AD5232BRUZ50-REEL72 AD5232BRU100 AD5232BRU100-REEL7 AD5232BRUZ1002 AD5232BRUZ100-REEL72 EVAL-AD5232-10EBZ2
Number Channels
End-to-End
Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C
Package Description 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP Evaluation Board
Package Option RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16
Ordering Quantity 1,000 1,000 1,000 1,000 1,000 1,000
Branding1 5232B10 5232B10 5232B10 5232B10 5232B50 5232B50 5232B50 5232B50 5232BC 5232BC 5232BC 5232BC
Line contains Analog Devices logo, followed date code: YYWW. Line contains model number, followed end-to-end resistance value. (Note that Line contains model number. Line contains Analog Devices logo, followed end-to-end resistance value. Line contains date code: YYWW. RoHS Compliant Part.
Rev. Page
AD5232 NOTES
Rev. Page
AD5232 NOTES
©2001-2009 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. D02618-0-10/09(A)
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