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EE-281
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Hardware Design Checklist Blackfin® Processors
Contributed Robert Kilgore July 2008
Introduction
This engineer-to-engineer note describes most common mistakes avoid when designing with Blackfin® processors. addition this document, designer should read most current data sheet, hardware reference manual, silicon anomaly list (available from Analog Devices site) specific Blackfin processor being used.
Five-Volt Tolerance
General Hardware Problems
following sections address design issues associated with memory interfaces specific peripherals.
Polarity
Applying five volts signals that rated this potential damage device cause malfunction. Blackfin processor outputs should connected inputs five-volt devices. Most Blackfin processor signals cannot tolerate five volts. There exceptions, such some Two-Wire Interface (TWI) signals. Level shifters required other processor signals keep signal voltage below absolute maximum ratings defined specific Blackfin processor data sheet. Level shifters commonly required transceivers ATAPI interface. Currentlimiting resistors provide sufficient protection against high voltage.
Unused Signals
Double-check polarity Non-Maskable Interrupt (NMI) signal processor being used. several Blackfin processors (the ADSPBF531/BF532/BF533/BF535 ADSPBF561), signal active high. other Blackfin processors, signal active order better connect standard Supervisory parts. Also, please remember that signal used, should tied inactive state. signal float, active state.
Check signal list description section data sheet what with unused signals. general, need terminate unused signals been eliminated, signals that require termination found data sheet. Failure connect unused signals such /NMI, cause symptoms that appear power sequence reset problems. Applications requiring high susceptibility immunity terminate unused signals, desired.
Signal Integrity
Rapid rise-time fall-time signals primary cause signal integrity issues such
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intermittent communication failure. edge rates Blackfin processor differ from signal signal. Likewise, some signals have greater sensitivity noise reflections than other signals. simple signal integrity methods prevent transmission-line reflections that cause extraneous clock sync signals. Short trace length series termination critical following signals: signals should have impedancematching series resistance driver
CLKIN
Bypass Capacitors
Appropriate bypass capacitors internal power supply become critical higher operating speeds. Unwanted parasitic inductance capacitors traces reduces effectiveness high frequency. things needed when processors operate above MHz. First, capacitors should physically small their leads should short reduce inductance. Surface mounted capacitors size 0402 will yield better results than larger sizes. Second, lower values capacitance will raise resonant frequency circuit. Although several capacitors work well below MHz, 0.1, 0.01, 0.001 even preferred range VDDINT.
Driving /RESET
SPORT interface signals (TCLK, RCLK, RFS, TFS) should termination signals, such PPI_CLK Sync signals, also benefit from these standard signal integrity techniques SDRAM clocks, control, address, data benefit from series termination that also reduces unwanted cases where signals have multiple sources, will difficult keep traces short, simulation appropriate. IBIS models that assist with signal simulation available from Analog Devices site. Some future Blackfin processor family members will support additional signal integrity features such programmable input hysteresis programmable output drive strength. Consult appropriate hardware reference manual details.
Test Points Signal Access
inputs most Blackfin processors have hysteresis, thus, they require monotonic rise fall. Therefore, even /RESET signal should connected directly time delay because such circuit would noise sensitive. Instead, /RESET should provided through reset supervisory chip.
Board Board Communications
debug process aided adding test points signals such CLKOUT SCLK, bank selects, PPI_CLK, /RESET. selection inputs such Boot Mode (BMODE) connected directly power ground, they will inaccessible under BGA-package chip. debugging, helpful pull-up pulldown resistors instead tying inputs directly power ground.
Some communication standards such have special requirements when unpowered. example, unpowered pull-up resistor cause excessive leakage, thereby disrupting communication between other units bus. This unpowered situation common consideration `hot swap' applications.
JTAG
Blackfin processor JTAG reset pin, /TRST, should pulled down normal operation. application note dedicated entirely considerations JTAG connections. Refer Analog Devices JTAG Emulation Technical Reference (EE-68)[1] details.
Hardware Design Checklist Blackfin® Processors (EE-281)
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GPIO Port Signals Used Inputs Outputs
power-on reset, general purpose signals inputs. During boot process, some these signals change outputs, depending selected boot mode. parts with HWAIT, this signal output boot modes. Output signals should used inputs when driven external device. HWAIT should used output value critical during booting phase operation. GPIO signals used outputs should have pullup pull-down resistors determine their state after reset. Outputs considered here include device enables (such NAND flash) communication handshake signals. Some examples HWAIT, UARTxTX, UARTxRTS, CANxTX, slave-select inputs outputs, serial TWI, chip select signals. Some general-purpose outputs that used like open-drain modes. These listed datasheet require pullups function general-purpose output. Signal capacitance limit output speed these signals.
Using EZ-KIT Lite® Schematics
Asynchronous Considerations
GPIO
Signal
Muxing
Asynchronous signals multiplexed with GPIO functions some Blackfin processors. This require request GPIO programmed request require that GPIO connected pull-up, described above. shown signal description, some processors allow some unused signals used general-purpose input/output signals. However, asynchronous used booting, address signals will driven. Also, some processors, /BGH will driven during boot process used input. This occurs when BMODE parallel memory processors featuring One-Time Programmable (OTP) memory, when asynchronous enabled programming. Other processors share other asynchronous signals with GPIO. Consult booting section hardware reference manual details.
8/16-Bit Memories
EZ-KIT Lite evaluation system schematics good starting reference. Because EZKIT Lite board evaluation development, extra circuitry provided some cases. Read EZ-KIT Lite board schematic carefully because sometimes component populated sometimes extra components have been added make easier modify measure.
Asynchronous Memory
Request
Remember proper addresses connect 8-bit memory ASYNC memory banks. Because there true byte addressing external memory, 8-bit memory addressed same 16-bit memory. (not /ABE0 /ABE1) address. 16-bit memory with byte enable signals accessed bits time. Otherwise, 16-bit memories word wide only. Blackfin devices with 32-bit EBIU programmed connect with 16-bit memory, using /ABE3 least significant address external device. Refer processor's hardware reference manual more information.
ARDY
Request signal (/BR) requires pull-up resistor designs. Erroneous requests will prevent operation this signal pulled driven external device.
used, ARDY terminated. addition, ARDY also programmed ignored
Hardware Design Checklist Blackfin® Processors (EE-281)
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software. ARDY used, consult hardware reference manual. Some Blackfin devices require ARDY input synchronous SCLK (CLKOUT).
Hibernate Considerations
processor address connected memory. Refer "SDRAM Address Mapping" section hardware reference manual details.
Hibernate Considerations
datasheet indicate that external signals tristate during hibernate. This includes strobes. Pull-up resistors required peripheral chip selects such /AMSx.
Other External Interface Control Signals
pull-up resistor recommended /SMS.
Synchronous Memory
Layout
Although required, pull-up resistors should considered active control signals guarantee their state during power power down. Future Blackfin family members have many device control signals multiplexed with GPIO other functions. These require pull-up resistors prevent data corruption contention during reset prior configuration.
SDRAM Memory
SDRAM Bank Addressing
ADDR18 connect BA0. ADDR19 connect BA1.
SDRAM Address SA10
SA10 directly connect SDRAM device. SA10 replaces Blackfin processor's ADDRx, based whether 32bit (for 32-bit-wide external memory interface derivatives) device connected SDRAM interface. example, ADSP-BF561 Blackfin processor, SA10 replaces ADDR11 when 16-bit SDRAM device used, SA10 replaces ADDR12 when 32-bit device used. ADSP-BF533 Blackfin processor, SA10 replaces ADDR11. Note that replaced ADDRx signal used. Therefore, next higher
Proper layout requirement memory design. Review timing specifications listed processor datasheet. Signal timing combination device timing characteristics printed circuit board. Trace length difference, cross-talk, voltage change account timing error. Follow layout recommendations given memory manufacturer. critical importance reduction DQS0 DQ0-7 skew DQS1 DQ8-15 skew. amount allowed skew improved with fast speed grade memory. careful trace length matching increased spacing reduce crosstalk. Serpentine traces should have spacing four times trace width provide sufficient delay. trace length DCLK01, DQS0-1, DQM0-1 DQ0-15 signals should less than inches. DDR_VSSR should connected directly ground processor. DDR_VREF should low-impedance wide connection.
Termination
series termination data, address control signals four memory devices.
Hibernate Considerations
Pull-up resistors recommended /DDRCS chip selects.
Hardware Design Checklist Blackfin® Processors (EE-281)
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Synchronous Memory Burst Flash
MISO MISO MOSI MOSI. peripheral signal names DOUT, connect them
Some Blackfin family members attach directly burst mode page access mode flash devices. Care must taken device functions boot source. Blackfin processor resets itself software reset command watchdog timer event, processor memory then operate incompatible access modes. OTP_RESETOUT_HWAIT feature instruct processor configure flash device before reboot. Consult hardware reference manual datasheet booting, timing connectivity information.
Hibernate Considerations
according their master slave function. Proper schematic signal names will reduce confusion.
Two-Wire Interface
Two-Wire Interface I2C-compatible peripheral. Because open drain outputs, both signals need pull-up resistors just like standard requires them.
SD/SDIO Interface
Secure Digital (SDIO) interface designed such that requires external pull-ups pulldowns most applications. SD/MMC cards require weak pull-up SD_CMD. Other resistor functions provided internal processor. However, impedance-matching series termination resistors should added signals. Consult specification timing numbers datasheet determine maximum frequency supporting both standard high-speed devices. Also consider time flight connector located remotely.
Pull-ups required peripheral chip selects such /AMSx.
Interface
Booting
Master Boot mode requires pull-up resistor GPIO signal used chip-select memory device. name chip-select changes from Blackfin processor another. Check booting section Blackfin processor's data sheet find connection booting. Most current processors require pull-up resistor MISO. systems, SPI_SCK best used with pull-down resistor define initial state reduce noise. Also, refer "SPI Master Booting" section application note ADSP-BF533 Blackfin Booting Process (EE-240)[2].
MOSI MISO
SPORT Interface
SPORTs multi-channel mode that master clocks frame syncs should connect RFS. this mode, frames active transmit channel data role Transmit Data Valid (TDV) signal.
Clock Input Signals
CLKIN
interface requires that MOSI signals tied together MISO signals tied together. prevent contention possible damage device, double-check that these signals have been interchanged. Connect
clock input Blackfin processor should start toggling after power-up continuous while power applied.
Hardware Design Checklist Blackfin® Processors (EE-281)
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XTAL
When using oscillator output instead crystal, XTAL output signal should have capacitor ground. shown this some EZ-KIT Lite board schematics. Note that populated board, should populated design.
Crystal Inputs
data sheet present. Keep VROUT signal trace short, this signal source radiated noise! Refer application note Switching Regulator Design Considerations ADSP-BF533 Blackfin Processors (EE-228)[3] further details component selection. power control functions have been added some Blackfin Processors. VRSEL input selects internal regulator external regulator mode. EXT_WAKE output provided turn external regulator when using hibernate state. high true power-up signal that connected directly true shut down input many regulators. SS/PG signal feature some processors. internal mode, SS/PG used give Soft Start power hibernate. external mode, used true Power-Good signal safely start core processing after wake from hibernate mode.
addition clock source processor core CCLK peripheral clock SCLK, some Blackfin processors have additional clock domains. Examples Real-Time Clock, Ethernet, MXVR. Like CLKIN XTAL, these clock domains crystal external clock drive input signal. external clock square wave sinusoidal. using sine wave, voltage levels must kept within minimum maximum limits found datasheet. Some peripheral XTAL pins also driven CLKBUF output some processors. using external clock instead crystal, corresponding XTAL output signal must left floating. using crystal, check datasheet crystal specifications recommended series parallel resistors. important overdrive small crystals. clock domain used your application, pull input clock high prevent oscillation.
Multiple Power Domains
Does your design require battery continuous time information? not, connect power VDDEXT even used. power ground signals must connected levels described datasheet. This true associated peripheral even true peripheral does exist processor being used design. Failure drive voltage connections result JTAG failures improper initialization operation.
Power Regulator
software controlled internal regulator circuit using external FET, diode inductor offered some Blackfin family processors. core voltage (VDDINT) also powered with standard external regulation. internal voltage regulator attractive option some designs using power management that controls both clock speed core voltage. aware that internal voltage regulator switching regulator circuit (not linear regulation circuit). Ensure that diode shown
Interface
Several members Blackfin family processors allow direct physical interface. This also called Universal Transceiver Macro Interface hardware reference manuals.
Hardware Design Checklist Blackfin® Processors (EE-281)
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Clocking USB_XI
external crystal crystal oscillator required generate internal USB2 highspeed clock. frequency should chosen operate internal clock MHz. External frequency programmed multiplication values combination that gives half speed clock MHz. circuit shown corresponding datasheet CLKIN connections also used example this clock.
USB_ID
USB_ID unique OTG.
termination compliance.
resistance
needed
USB_VBUS Connection
USB_VBUS input processor, except
allows cable determine host (A-Device) peripheral (B-Device) initial status interface. using using interface host (A-Device), this should grounded. using using interface peripheral (B-Device), USB_ID left floating connected weak pull-up.
Connection
when programmed output Session Request pulses. When using host (A-Device) mode, external source more than required drive USB_VBUS cable. This supply needs fully disabled when (B-Device) mode. GPIO signal should used enable/disable. USB_VBUS should connected directly connector. Check datasheet tolerance USB_VBUS. Some processors V-tolerant VDDUSB external power zero volts. applications expect their products experience very long exposure USB_VBUS when processor local power. These applications wish provide power VDDUSB using power from USB_VBUS. example such protection circuit found ADSP-BF548 EZ-Kit lite schematics.
Protection
Blackfin USB_DP USB_DM signals should routed impedance-controlled differential pair directly connector. Traces should have extraneous side traces, sometimes called stubs. Further care should taken isolate this differential pair from high-speed signals other noise sources like VROUT. Blackfin processor provides
Additional protection recommended cable signals USB_DP, USB_DM, USB_ID, USB_VBUS. Protection devices should placed near connector.
Hardware Design Checklist Blackfin® Processors (EE-281)
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References
Analog Devices JTAG Emulation Technical Reference (EE-68). April 2008. Analog Devices, Inc. ADSP-BF533 Blackfin Booting Process (EE-240). January 2005. Analog Devices, Inc. Switching Regulator Design Considerations ADSP-BF533 Blackfin Processors (EE-228). February 2005. Analog Devices, Inc. Estimating Power ADSP-BF531/BF532/BF533 Blackfin Processors (EE-229). December 2007. Analog Devices, Inc.
Document History
Revision October 2005 Robert Kilgore July 2008 Robert Kilgore Description Initial release
Added information cover peripherals features Blackfin processor portfolio
Hardware Design Checklist Blackfin® Processors (EE-281)
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