CS5566 ±2.5 kSps, 24-bit Features Description Different

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CS5566 ±2.5 kSps, 24-bit Features Description Different

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5/4/09
CS5566
±2.5 kSps, 24-bit
Features Description
Differential Analog Input On-chip Buffers High Input Impedance Conversion Time Settles Conversion Linearity Error 0.0005% Signal-to-Noise Bits, Missing Codes Simple three/four-wire serial interface Power Supply Configurations:
Analog: +5V/GND; +1.8V +3.3V Analog: ±2.5V; +1.8V +3.3V
General Description
CS5566 single-channel, 24-bit analog-to-digital converter capable kSps conversion rate. input accepts fully differential analog input signal. On-chip buffers provide high input impedance both inputs VREF+ input. This significantly reduces drive requirements signal sources reduces errors source impedances. CS5566 delta-sigma converter capable switching multiple input channels high rate with loss throughput. uses low-latency digital filter architecture. filter designed fast settling settles full accuracy conversion. converter's 24-bit data output serial form, with serial port acting either master slave. converter designed support bipolar, ground-referenced signals when operated from ±2.5V analog supplies. converter operate from analog supply 0-5V from ±2.5V. digital interface supports standard logic operating from 1.8, 2.5,
Power Consumption: kSps ORDERING INFORMATION: Ordering Information page
CS5566
VREF+ VREFCS SMODE
DIGITAL FILTER LOGIC
SERIAL INTERFACE
SCLK
SLEEP BUFEN
DIGITAL CONTROL
OSC/CLOCK GENERATOR
CONV BP/UP MCLK
VLR2
Preliminary Product Information
http://www.cirrus.com
This document contains information product. Cirrus Logic reserves right modify this product without notice.
Copyright Cirrus Logic, Inc. 2009 (All Rights Reserved)
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CS5566
TABLE CONTENTS
CHARACTERISTICS SPECIFICATIONS ANALOG CHARACTERISTICS SWITCHING CHARACTERISTICS DIGITAL CHARACTERISTICS DIGITAL FILTER CHARACTERISTICS GUARANTEED LOGIC LEVELS RECOMMENDED OPERATING CONDITIONS. ABSOLUTE MAXIMUM RATINGS. OVERVIEW THEORY OPERATION Converter Operation Power Consumption Clock Voltage Reference Analog Input Output Coding Format Typical Connection Diagrams VREF Sampling Structures Converter Performance 3.10 Digital Filter Characteristics 3.11 Serial Port 3.11.1 Mode 3.11.2 Mode 3.12 Power Supplies Grounding 3.13 Using CS5566 Multiplexing Applications 3.14 Synchronizing Multiple Converters DESCRIPTIONS PACKAGE DIMENSIONS ORDERING INFORMATION ENVIRONMENTAL, MANUFACTURING, HANDLING INFORMATION REVISION HISTORY
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CS5566
LIST FIGURES
Figure Converter Status Figure Mode Read Timing, remaining Figure Mode Read Timing, falling after falls Figure Mode Continuous SCLK Read Timing Figure Mode Discontinuous SCLK Read Timing Figure Power Consumption Conversion Rate Figure Voltage Reference Circuit Figure CS5566 Configured Using ±2.5V Analog Supplies Figure CS5566 Configured Using Single Analog Supply Figure CS5566 Plot. Figure Spectral Performance, Figure Spectral Performance, Figure Spectral Performance, Figure Spectral Performance, Figure Spectral Performance, Figure Spectral Performance, -120 Figure Spectral Performance, -130 Figure Noise Histogram (4096 Samples) Figure Spectral Plot Noise with Shorted Input Figure Digital Filter Response kHz)
LIST TABLES
Table Output Coding, Two's Complement Table Output Coding, Offset Binary
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CHARACTERISTICS SPECIFICATIONS
CS5566
characteristics specifications guaranteed over specified operating conditions. Typical characteristics specifications measured nominal supply voltages 25°C. voltages with respect
ANALOG CHARACTERISTICS +2.5 ±5%; -2.5 ±5%; -VLR ±5%; VREF (VREF+) (VREF-) 4.096V; MCLK MHz; SMODE BUFEN unless otherwise stated. Connected Figure Bipolar mode unless otherwise stated.
Parameter Accuracy Linearity Error Differential Linearity Error Positive Full-scale Error Negative Full-scale Error Full-scale Drift Bipolar Offset Bipolar Offset Drift Noise Dynamic Performance Peak Harmonic Spurious Noise Total Harmonic Distortion Signal-to-Noise S/(N Ratio Input Bandwidth Analog Input Analog Input Range (Differential) Input Capacitance Current (Note Buffer (BUFEN Buffer (BUFEN Unipolar Bipolar -100 +VREF ±VREF -110 -0.5 Input, Input, (Note -0.5 Input -0.5 Input -115 -110 -100 (Note (Note (Note (Note 0.0005 ±0.1 ±500 ±%FS LSB24 LSB24 Vrms Unit
Common Mode Rejection Ratio kHz)
missing codes guaranteed bits resolution over specified temperature range. equivalent VREF) 4.096) 16,777,216 Scales with MCLK. Measured using input signal
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CS5566
+2.5 ±5%; -2.5 ±5%; -VLR ±5%; VREF (VREF+) (VREF-) 4.096V; MCLK MHz; SMODE VL.; BUFEN unless otherwise stated. Connected Figure Parameter Voltage Reference Input Voltage Reference Input Range (VREF+) (VREF-) Input Capacitance Current VREF+ Buffer (BUFEN VREF+ Buffer (BUFEN VREFIV1 (Note 4.096 Unit
ANALOG CHARACTERISTICS (CONTINUED)
Power Supplies Average Power Supply Currents (Note
Peak Power Supply Currents
(Note
Average Power Consumption
Normal Operation Buffers (Note Buffers Sleep (SLEEP (Note Supplies V1-, Supplies
Power Supply Rejection
optimum performance, VREF+ should always less than (V+) volts prevent saturation VREF+ input buffer. Specification MCLK 8MHz kSps conversion rate. MCLK frequency conversion rate affect power consumption. Section Power Consumption more details. Tested with mVP-P supply kHz. supplies same voltage potential, supplies same voltage potential.
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SWITCHING CHARACTERISTICS
+2.5 ±5%; -2.5 ±5%; ±5%, ±5%, Input levels: Logic Low; Logic High; Parameter Master Clock Frequency Master Clock Duty Cycle Reset Time rising falling Conversion CONV Pulse Width BP/UP setup CONV falling CONV start conversion Perform Single Conversion (CONV high before falling) Conversion Time Sleep Mode SLEEP low-power state SLEEP high device active (Note
CS5566
Symbol Internal Oscillator External Clock fclk
3084 1182 3083
1186 1604
Unit MCLKs MCLKs MCLKs MCLKs MCLKs MCLKs
tres Internal Oscillator External Clock twup
tcpw (Note tscn tscn tbus tbuh tcon tcon
(Note Start Conversion falling
BP/UP changed coincident CONV falling. BP/UP must remain stable until falls. CONV held continuously, conversions occur every 1600 MCLK cycles. tied CONV, conversions will occur every 1602 MCLKs. CONV operated asynchronously MCLK, conversion take 1604 MCLKs. falls conversion. will fall when device fully operational when coming sleep mode.
tbus CONVERT
Converter Status
IDLE
CONVERT
ACTIVE
IDLE
1182 1186 MCLKs 1600 1604 MCLKs
MCLKs
Figure Converter Status (Not scale) DS806PP2
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CS5566
SWITCHING CHARACTERISTICS (CONTINUED)
+2.5 ±5%; -2.5 ±5%; ±5%, ±5%, Input levels: Logic Low; Logic High; Parameter
Serial Port Timing Mode (SMODE
Symbol Pulse Width (low) Pulse Width (high)
Unit MCLKs MCLKs
falling stable Data hold time after SCLK rising Serial Clock (Out) (Note rising after last SCLK rising
SCLK will high impedance when high. some systems require pull-down resistor. SCLK MCLK/2.
MCLK
SCLK(o)
MSB-1
LSB+1
Figure Mode Read Timing, remaining (Not Scale)
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SWITCHING CHARACTERISTICS (CONTINUED)
+2.5 ±5%; -2.5 ±5%; ±5%, ±5%, Input levels: Logic Low; Logic High; Parameter
Serial Port Timing Mode (SMODE
CS5566
Symbol Pulse Width (low) Pulse Width (high)
Unit MCLKs MCLKs
Data hold time after SCLK rising Serial Clock (Out) (Note rising after last SCLK rising falling stable First SCLK rising after falling hold time (low) after SCLK rising SCLK, tri-state after rising
SCLK will high impedance when high. some systems SCLK require pull-down resistors. SCLK MCLK/2.
MCLK SCLK(o)
MSB-1 LSB+1
Figure Mode Read Timing, falling after falls (Not Scale)
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CS5566
SWITCHING CHARACTERISTICS (CONTINUED)
+2.5 ±5%; -2.5 ±5%; ±5%, ±5%, Input levels: Logic Low; Logic High; Parameter
Serial Port Timing Mode (SMODE VLR)
Symbol
SCLK
Unit
SCLK(in) Pulse Width (High) SCLK(in) Pulse Width (Low) hold time (high) after falling hold time (high) after SCLK rising Hi-Z Data hold time after SCLK rising Data setup time before SCLK rising hold time (low) after SCLK rising rising after SCLK falling
(Note
will high impedance when high. some systems require pull-down resistor.
MCLK SCLK(i)
Figure Mode Continuous SCLK Read Timing (Not Scale)
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CS5566
MCLK
SCLK(i)
Figure Mode Discontinuous SCLK Read Timing (Not Scale)
DIGITAL CHARACTERISTICS
TMIN TMAX; 3.3V, 2.5V, 1.8V, ±5%; Parameter Input Leakage Current Digital Input Capacitance Digital Output Capacitance Symbol Cout Unit
DIGITAL FILTER CHARACTERISTICS
TMIN TMAX; 3.3V, 2.5V, 1.8V, ±5%; Parameter Group Delay
Symbol (Note
Unit MCLKs
Figure understand conversion timing. MCLK group delay occurs during MCLK high-power period conversion cycle. Section Power Consumption more detail.
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CS5566
GUARANTEED LOGIC LEVELS
+2.5 ±5%; -2.5 ±5%; ±5%, ±5%, Input levels: Logic Low; Logic High; Guaranteed Limits Parameter Logic Inputs
Minimum High-level Input Voltage:
Unit
Conditions
0.95
Maximum Low-level Input Voltage:
Logic Outputs
Minimum High-level Output Voltage:
1.65 0.36 0.36 0.44
Maximum Low-level Output Voltage:
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RECOMMENDED OPERATING CONDITIONS
(VLR Note
CS5566
Parameter Single Analog Supply Power Supplies: (Note V1V2-
Symbol
Unit
V2V1+
4.75 4.75
5.25 5.25
Dual Analog Supplies Power Supplies: (Note V1V2(Note [VREF+] [VREF-] V2V1+ V2VREF +2.375 +2.375 -2.375 -2.375 +2.5 +2.5 -2.5 -2.5 4.096 +2.625 +2.625 -2.625 -2.625
Analog Reference Voltage
logic supply value +1.71 +3.465 volts long 3.465 differential voltage reference magnitude constrained supply magnitude.
ABSOLUTE MAXIMUM RATINGS
(VLR
Parameter Power Supplies: [V1+] [V1-] (Note |V1-| (Note Input Current, Except Supplies Analog Input Voltage Digital Input Voltage Storage Temperature Notes: V2+; V220.
Symbol VINA VIND Tstg
(V1-)
(V1+)
Unit
(Note
(AIN VREF pins)
V2Transient currents will cause latch-up.
WARNING: Recommended Operating Conditions indicate limits which device functionally operational. Absolute Maximum Ratings indicate limits beyond which permanent damage device occur. Absolute Maximum Ratings stress ratings only device should operated these limits. Operation conditions beyond Recommended Operating Conditions affect device reliability, functional operation beyond Recommended Operating Conditions implied. Performance specifications intended conditions specified each table Characteristics Specifications section.
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CS5566
OVERVIEW
CS5566 24-bit analog-to-digital converter capable kSps conversion rate. device capable switching multiple input channels high rate with loss throughput. uses low-latency digital filter architecture. filter designed fast settling settles full accuracy conversion. converter serial output device. serial port configured function either master slave. converter operate from analog supply from ±2.5V. digital interface supports standard logic operating from 1.8, 2.5, CS5566 converts kSps when operating from input clock.
THEORY OPERATION
CS5566 converter provides high-performance measurement signals. converter used perform single conversions continuous conversions upon command. Each conversion independent previous conversions settle full specified accuracy, even with full-scale input voltage step. This converter architecture which uses combination high-speed delta-sigma modulator low-latency filter architecture. Once power established converter, reset must performed. reset initializes internal converter logic. CONV held then converter will convert continuously with falling every 1600 MCLKs. This equivalent kSps MCLK MHz. CONV tied RDY, conversion will occur every 1602 MCLKs. CONV operated asynchronously MCLK, take 1604 MCLKs from CONV falling falling. Multiple converters operate synchronously they driven same MCLK source CONV each converter falls same MCLK falling edge. Alternately, CONV held devices reset with rising same falling edge MCLK. output coding conversion word function BP/UP pin. active-low SLEEP signal causes device enter low-power state. When exiting sleep, converter will take 3083 MCLK cycles before conversions performed. should remain inactive (high) when SLEEP asserted (low).
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Converter Operation
converter should reset after power supplies voltage reference stable.
CS5566
CS5566 converts kSps when synchronously operated (CONV VLR) from master clock. Conversion initiated taking CONV low. conversion lasts 1600 master clock cycles, CONV asynchronous MCLK there uncertainty MCLK cycles after CONV falls when conversion actually begins. This extend throughput 1604 MCLKs When conversion completed, output word placed into serial port goes low. convert continuously, CONV should held low. continuous conversion mode with CONV held low, conversion performed 1600 MCLK cycles. Alternately tied CONV conversion will occur every 1602 MCLK cycles. perform only conversion, CONV should return high least master clock cycles before falls. Once conversion completed falls, will return high when bits data word emptied from serial port conversion data read held low, will high MCLK cycles before conversion. will fall next conversion when data into port register. Section 3.11 Serial Port information about reading conversion data. Conversion performance affected several factors. These include choice clock source chip, timing CONV, choice serial port mode. converter operated from internal oscillator. This clock source greater jitter than external crystal-based clock. Jitter issue when measuring signals, very-low-frequency signals, become issue higher frequency signals. maximum performance when digitizing signals, low-jitter MCLK should used. maximize performance, CONV should held continuous conversion state perform multiple conversions, CONV should occur synchronous MCLK, falling when MCLK falls. converter operated maximum throughput, serial port mode less likely cause interference measurements SCLK output synchronized MCLK. Alternately, interference serial port clocking also minimized data read serial port mode when conversion progress.
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CS5566
Power Consumption
power consumption CS5566 converter function conversion rate. Figure illustrates typical power consumption converter when operating from either MCLK MCLK MHz. rate which conversions performed directly affects power consumption. When converter powered converting, idle state where power consumption about When CONV signal goes start conversion, converter delays actual start conversion 1182 1186 MCLK cycles, depending upon CONV controlled. timing conversion sequence shown Figure page After 1182 1186 MCLK delay from when CONV goes low, converter enters higher-power state MCLK cycles then returns lower-power state MCLK cycles, after which signal falls indicate completion conversion. Since peak operating current converter occurs during MCLK, higher-power state, recommended that large capacitor used supply converter shown Figures 10). This capacitor filters peak current demand from power supply. average power consumption converter will depend upon frequency MCLK rate which conversions performed illustrated Figure page
Power Consumption (mW)
17.5 12.5 2.5k 3.5k 4.5k
Word Rate (Sps)
MCLK 4MHz MCLK 8MHz
Figure Power Consumption Conversion Rate
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Clock
CS5566
CS5566 operated from internal oscillator from external master clock. state MCLK determines which clock source will used. MCLK tied low, internal oscillator will start used clock source converter. external CMOS-compatible clock input into MCLK converter will power down internal oscillator external clock. MCLK held high, internal oscillator will held stopped state. MCLK input held high delete clock cycles operating multiple converters different phase relationships. internal oscillator used signals measured essentially internal oscillator exhibits jitter about picoseconds rms. CS5566 used digitize signals, external low-jitter clock source should used. internal oscillator used clock CS5566, maximum conversion rate will dictated oscillator frequency. driven from external MCLK source, fast rise fall times MCLK signal result clock coupling from internal bond wire analog input. Adding resistor external MCLK source significantly reduces this effect.
Voltage Reference
voltage reference CS5566 range from volts volts. 4.096 volt reference required achieve specified performance. Figure Figure illustrate connection voltage reference with either single analog supply with ±2.5 optimum performance, voltage reference device should that provides capacitor connection provide means noise filtering, output should include some type bandwidth-limiting filter. Some 4.096 volt reference devices need only volts total supply operation connected shown Figure Figure reference should have local bypass capacitor appropriate output capacitor. Some older 4.096 voltage reference designs require more headroom must operate from input voltage volts. this type voltage reference used ensure that when power applied system, voltage reference rise time slower than rise time power supply voltage converter. example circuit slow output startup time reference illustrated Figure
VOUT Refer VREF1 pins.
Figure Voltage Reference Circuit
4.096
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CS5566
Analog Input
analog input converter fully differential with peak-to-peak input 4.096 volts each input. Therefore, differential, peak-to-peak input 8.192 volts. This illustrated Figure Figure These diagrams also illustrate differential buffer amplifier configuration driving CS5566. capacitors outputs amplifiers provide charge reservoir dynamic current from inputs while resistors isolate dynamic current from amplifier. amplifiers powered from higher supplies than those used precautions should taken ensure that opamp output voltage remains within power supply limits A/D, especially under start-up conditions.
Output Coding Format
reference voltage directly defines input voltage range both unipolar bipolar configurations. unipolar configuration (BP/UP low), first code transition occurs above zero, final code transition occurs LSBs below VREF. bipolar configuration (BP/UP high), first code transition occurs above -VREF last transition occurs LSBs below +VREF. Table output coding converter.
Table Output Coding, Two's Complement
Bipolar Input Voltage
>(VREF-1.5 LSB) VREF-1.5 -0.5 -VREF+0.5 <(-VREF+0.5 LSB)
Two's Complement
NOTE: VREF (VREF+) (VREF-) Table Output Coding, Offset Binary
Unipolar Input Voltage
>(VREF-1.5 LSB) VREF-1.5 (VREF/2)-0.5 +0.5 <(+0.5 LSB)
Offset Binary
NOTE: VREF (VREF+) (VREF-)
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Typical Connection Diagrams
CS5566
following figure depicts CS5566 powered from bipolar analog supplies, +2.5
4700pF 49.9
CS5566
AIN+
+2.048 -2.048 +2.048 -2.048
47pF 4.99k 4.99k 49.9 47pF 4.99k 4.99k
SMODE
SCLK
AIN4700pF
(V+) Buffers +2.5 (V-) Buffers +4.096 Voltage Reference (NOTE VREF+
CONV BUFEN BP/UP SLEEP
MCLK VREF-2.5
+2.5
+3.3 +1.8
V20.1
VLR2
V1-2.5
NOTES Section Voltage Reference information required voltage reference performance criteria. 2.Locate capacitors minimize loop length. ±2.5 supplies should also bypassed ground converter. power supply ground ±2.5 should connected same ground plane under chip. SCLK require pull-down resistors some applications. input filter used band limit input reduce noise. Select equal parallel combination feedback feedback resistors 4.99k 4.99k 2.5k0
Figure CS5566 Configured Using ±2.5V Analog Supplies
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CS5566
following figure depicts CS5566 device powered from single analog supply.
4700pF 49.9 47pF 4.99k
2.048
AIN+
4.548 +0.452 +4.548 +0.452
CS5566
SMODE
49.9 47pF 4.99k
SCLK
AIN4.096
4700pF
(V+) Buffers BUFEN (V-) Buffers CONV
BP/UP SLEEP VREF+
+4.096 Voltage Reference (NOTE
MCLK VREFTST
+3.3
V20.1
VLR2
NOTES Section Voltage Reference information required voltage reference performance criteria. Locate capacitors minimize loop length. V1-, V2-, should connected same ground plane under chip. SCLK require pull-down resistors some applications.
Figure CS5566 Configured Using Single Analog Supply
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VREF Sampling Structures
CS5566
CS5566 uses on-chip buffers AIN+, AIN-, VREF+ inputs. Buffers provide much higher input impedance therefore reduce amount drive current required from external source. This helps minimize errors. Buffer Enable (BUFEN) determines on-chip buffers used not. BUFEN connected supply, buffers will enabled. BUFEN connected pin, buffers off. converter will consume about less power when buffers off, input impedances AIN+, AIN- VREF+ will significantly less than with buffers enabled.
Converter Performance
CS5566 achieves excellent differential nonlinearity (DNL). Figure illustrates code widths typical scale zoomed scale ±0.2 LSB.
(Zoom View) Figure CS5566 Plot
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CS5566
Figure through Figure illustrate performance converter with various input signal magnitudes.
-100 -120 -140 -160 -180
Samples kSps
-100 -120 -140 -160 -180 2.5k
Samples kSps
1.5k Frequency (Hz)
1.5k Frequency (Hz)
2.5k
Figure Spectral Performance,
-100 -120 -140 -160 -180
Figure Spectral Performance,
-100 -120 -140 -160 -180
2.5k
Samples kSps
Samples kSps
1.5k Frequency (Hz)
1.5k Frequency (Hz)
2.5k
Figure Spectral Performance,
-100 -120 -140 -160 -180
Figure Spectral Performance,
-100 -120 -140 -160 -180 2.5k
Samples kSps
-120 Samples kSps
1.5k Frequency (Hz)
1.5k Frequency (Hz)
2.5k
Figure Spectral Performance,
Figure Spectral Performance, -120
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CS5566
Figure illustrates device with small signal 1/1,000,000 full scale. signal input Figure about microvolts peak peak, about codes peak peak. Figure illustrates converter with signal about microvolts peak peak, about codes peak peak. CS5566 achieves superb performance with this small signal. Figure illustrates noise floor converter from kHz. plot entirely free spurious frequency content digital activity inside chip. Figure illustrates noise histogram converter constructed from 4096 samples.
-100 -120 -140 -160 -180
-130 Samples kSps
1.5k Frequency (Hz)
2.5k
Figure Spectral Performance, -130
-100 -120 -140 -160 -180
Shorted Input Samples kSps Averages
Frequency (Hz)
2.5k
Figure Spectral Plot Noise with Shorted Input
Number Occurances
4096 Samples Mean 96.32 Std. Dev. 21.3
Output Codes
Figure Noise Histogram (4096 Samples)
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CS5566
3.10 Digital Filter Characteristics
digital filter designed fast settling, therefore exhibits very little in-band attenuation. filter attenuation -0.0414 when sampling kSps.
-0.001646 -0.00663
kSps
-0.0149
-0.0262
-0.0414
Frequency (Hz)
Figure Digital Filter Response kHz)
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3.11 Serial Port
CS5566
serial port CS5566 operate different modes: synchronous self clock (SSC) mode synchronous external clock (SEC) mode. serial port must placed into mode offset gain registers converter read written. converter must idle when reading writing on-chip registers. 3.11.1 Mode SMODE high (SMODE VL), serial port operates (Synchronous Self Clock) mode. mode port shifts conversion data words with SCLK output. SCLK generated inside converter from MCLK. Data output from (Serial Data Output) pin. high, SCLK pins will stay high-impedance state. when falls, conversion data word will output from first. Data output rising edge SCLK should latched into external logic subsequent rising edge SCLK. When bits conversion word output from port signal will return high. 3.11.2 Mode SMODE (SMODE VLR), serial port operates (Synchronous External Clock mode). this mode, user usually monitors RDY. When falls conversion, conversion data word placed into output data register serial port. then activated enable data output. Note that held continuously necessary have output operate high impedance state. When taken (after falls) conversion data word then shifted driving SCLK from system logic external converter. Data bits advanced rising edges SCLK latched subsequent rising edge SCLK. held continuously, signal will fall conversion conversion data will placed into serial port. user starts read, user will maintain control over serial port until port empty. However, SCLK toggled, converter will overwrite conversion data completion next conversion. held read performed, will rise just prior next conversion then fall signal that data been written into serial port.
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CS5566
3.12 Power Supplies Grounding
CS5566 configured operate with analog supply operating from with analog supplies operating from ±2.5V. digital interface supports digital logic operating from either 1.8V, 2.5V, 3.3V. Figure page illustrates device configured operate from ±2.5V analog. Figure page illustrates device configured operate from analog. Note that schematic indicates capacitor between V1-. This capacitor necessary reduce peak current required from power supply during conversion. Power Consumption page more detailed discussion. maximize converter performance, analog ground logic ground converter should connected converter. dual analog supply configuration, analog ground ±2.5V supplies should connected converter with converter placed entirely over analog ground plane. single analog supply configuration (+5V), ground supply should directly tied converter with converter placed entirely over analog ground plane. Refer Figure page
3.13 Using CS5566 Multiplexing Applications
actual conversion process inside CS5566 begins 1182 MCLK cycles after CONV signal taken low. This would over microseconds when MCLK MHz. input channel external multiplexer changed coincident with CONV going low, 1182 MCLK delay should more than adequate time settling. there operational amplifier between multiplexer converter, should certain that amplifier settle within 1182 MCLK delay period. not, multiplexer will need switched some time prior CONV going low.
3.14 Synchronizing Multiple Converters
Many measurement systems have multiple converters that need operate synchronously. converters should driven from same master clock. this configuration, converters will convert synchronously same CONV signal used drive converters, CONV falls falling edge MCLK. CONV held continuously, reset (RST) used synchronize multiple converters released falling edge MCLK.
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DESCRIPTIONS
Chip Select Factory Test Serial Mode Select Differential Analog Input Differential Analog Input Negative Power Positive Power Buffer Enable Voltage Reference Input Voltage Reference Input Bipolar/Unipolar Select Sleep Mode Select SMODE AIN+ AINV1V1+ BUFEN VREF+ VREFBP/UP SLEEP SCLK MCLK V2V2+ CONV VLR2
CS5566
Ready Serial Clock Input/Output Serial Data Output Logic Interface Power Logic Interface Return Master Clock Negative Voltage Positive Voltage Digital Core Regulator Convert Logic Interface Return Reset
Chip Select, Chip Select allows external device access serial port. SMODE (SSC Mode) held high, output SCLK output will held high-impedance output state. Factory Test, Factory test only. Connect VLR. SMODE Serial Mode Select, serial interface mode (SMODE) dictates whether serial port behaves master slave interface. SMODE tied high VL), port will operate Synchronous Self-Clocking (SSC) mode. mode, port acts master which converter outputs both SCLK signals. SMODE tied VLR), port will operate Synchronous External Clocking (SEC) mode. mode, port acts slave which external logic microcontroller generates SCLK used output conversion data word from pin. AIN+, AIN- Differential Analog Input, AIN+ AIN- differential inputs converter. Negative Power pins provide negative supply voltage core circuitry chip. These pins should decoupled shown application block diagrams. should supplied from same source voltage. single-supply operation, these voltages nominally (Ground). dual-supply operation, they nominally -2.5 Positive Power pins provide positive supply voltage core circuitry chip. These pins should decoupled shown application block diagrams. should supplied from same source voltage. single supply-operation, these voltages nominally dual-supply operation, they nominally +2.5 BUFEN Buffer Enable, Buffers input pins AIN+ AIN- enabled BUFEN connected disabled connected V1-. VREF+, VREF- Voltage Reference Input, differential voltage reference input these pins functions voltage reference converter. voltage between these pins range between volts volts, with 4.096 volts being nominal reference voltage value.
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CS5566
BP/UP Bipolar/Unipolar Select, BP/UP determines span output coding converter. When high select (bipolar), input span converter -4.096 volts +4.096 volts fully differential (assuming voltage reference 4.096 volts) output data coded two's complement format. When select (unipolar), input span +4.096 fully differential output data coded binary format. SLEEP Sleep Mode Select, When taken low, SLEEP will cause converter enter into low-power state. SLEEP will stop internal oscillator power down internal analog circuitry. Reset, Reset necessary after power initially applied converter. When input taken low, logic converter will reset. When released high, certain portions analog circuitry started. falls when reset complete. CONV Convert, CONV initiates conversion cycle taken low, unless previous conversion progress. When conversion cycle completed, conversion word output serial port register signal goes low. CONV held remains when falls, another conversion cycle will started. Digital Core Regulator, output on-chip regulator digital logic core. should bypassed with capacitor V2-. designed power external load. Positive Power pins provide positive supply voltage circuitry chip. These pins should decoupled shown application block diagrams. should supplied from same source voltage. single-supply operation, these voltages nominally dual-supply operation, they nominally +2.5 Negative Power pins provide negative supply voltage circuitry chip. These pins should decoupled shown application block diagrams. should supplied from same source voltage. single-supply operation, these voltages nominally (Ground). dual-supply operation, they nominally -2.5 MCLK Master Clock, master clock (MCLK) multi-function pin. tied (MCLK VLR), on-chip oscillator will enabled. tied high (MCLK VL), clocks internal circuitry converter will stop. When MCLK held high internal oscillator will also stopped. MCLK also function input external CMOS-compatible clock that conforms supply voltages pins. VLR2, VLR, Logic Interface Power/Return, Pins supply voltages digital logic interface. configured with wide range common mode voltage. following interface pins function from VL/VLR supply: SMODE, SCLK, SDO, RDY, SLEEP, CONV, RST, BP/UP, MCLK. Serial Data Output, output serial output port. Data from this will output rate determined SCLK format determined BP/UP pin. Data output first advances next data rising edges SCLK. will high impedance state when high.
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CS5566
SCLK Serial Clock Input/Output, SMODE determines whether SCLK signal input output signal. SCLK determines rate which data clocked pin. converter mode, SCLK frequency will determined master clock frequency converter (either MCLK internal oscillator). mode, user determines SCLK frequency. SMODE (SSC Mode), SCLK will high-impedance state when high. Ready, CONV converter will immediately start conversion will remain high until conversion completed. conversion falls indicate that conversion word been placed into serial port. will return high after data bits shifted serial port master clock cycles before data becomes available inactive (high); master clock cycles before data becomes available user holds started reading data from converter when mode.
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5/4/09
CS5566
PACKAGE DIMENSIONS
SSOP PACKAGE DRAWING
SIDE VIEW
VIEW
SEATING PLANE
VIEW
-0.002 0.064 0.009 0.311 0.291 0.197 0.022 0.025
INCHES -0.006 0.068 -0.323 0.307 0.209 0.026 0.03
0.084 0.010 0.074 0.015 0.335 0.323 0.220 0.030 0.041
-0.05 1.62 0.22 7.90 7.40 5.00 0.55 0.63
MILLIMETERS -0.13 1.73 -8.20 7.80 5.30 0.65 0.75
NOTE 2.13 0.25 1.88 0.38 8.50 8.20 5.60 0.75 1.03
JEDEC MO-150
Controlling Dimension Millimeters. Notes:
1."D" "E1" reference datums included mold flash protrusions, include mold mismatch measured parting line, mold flash protrusions shall exceed 0.20 side. 2.Dimension does include dambar protrusion/intrusion. Allowable dambar protrusion shall 0.13 total excess dimension maximum material condition. Dambar intrusion shall reduce dimension more than 0.07 least material condition. 3.These dimensions apply flat section lead between 0.10 0.25 from lead tips.
DS806PP2
5/4/09
ORDERING INFORMATION
Model Linearity Temperature Conversion Time Throughput
CS5566
Package
CS5566-ISZ
0.0005%
kSps
24-pin SSOP
ENVIRONMENTAL, MANUFACTURING, HANDLING INFORMATION
Model Number Peak Reflow Temp Rating* Floor Life Days
CS5566-ISZ
(Moisture Sensitivity Level) specified IPC/JEDEC J-STD-020.
REVISION HISTORY
Revision Date 2008 2009 Changes Preliminary release. Corrected cross reference page
Contacting Cirrus Logic Support
product questions inquiries contact Cirrus Logic Sales Representative. find nearest www.cirrus.com
IMPORTANT NOTICE "Preliminary" product information describes products that production, which full characterization data available. Cirrus Logic, Inc. subsidiaries ("Cirrus") believe that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). Customers advised obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, indemnification, limitation liability. responsibility assumed Cirrus this information, including this information basis manufacture sale items, infringement patents other rights third parties. This document property Cirrus furnishing this information, Cirrus grants license, express implied under patents, mask work rights, copyrights, trademarks, trade secrets other intellectual property rights. Cirrus owns copyrights associated with information contained herein gives consent copies made information only within your organization with respect Cirrus integrated circuits other products Cirrus. This consent does extend other copying such copying general distribution, advertising promotional purposes, creating work resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS DESIGNED, AUTHORIZED WARRANTED PRODUCTS SURGICALLY IMPLANTED INTO BODY, AUTOMOTIVE SAFETY SECURITY DEVICES, LIFE SUPPORT PRODUCTS OTHER CRITICAL APPLICATIONS. INCLUSION CIRRUS PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK CIRRUS DISCLAIMS MAKES WARRANTY, EXPRESS, STATUTORY IMPLIED, INCLUDING IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE, WITH REGARD CIRRUS PRODUCT THAT USED SUCH MANNER. CUSTOMER CUSTOMER'S CUSTOMER USES PERMITS CIRRUS PRODUCTS CRITICAL APPLICATIONS, CUSTOMER AGREES, SUCH USE, FULLY INDEMNIFY CIRRUS, OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS OTHER AGENTS FROM LIABILITY, INCLUDING ATTORNEYS' FEES COSTS, THAT RESULT FROM ARISE CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, Cirrus Logic logo designs trademarks Cirrus Logic, Inc. other brand product names this document trademarks service marks their respective owners.
DS806PP2

CS5566 ±2.5 kSps, 24-bit Features Description Different

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