Features Description Chopper-stabilized CS5530 highly integr

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Features Description Chopper-stabilized CS5530 highly integr

Datasheet Thumbnail

Top Searches for this datasheet

CS5530 24-bit with Ultra-low-noise Amplifier
Features Description
Chopper-stabilized
CS5530 highly integrated Analog-to-Digital Converter (ADC) which uses charge-balance techniques achieve 24-bit performance. optimized measuring low-level unipolar bipolar signals weigh scale, process control, scientific, medical applications. accommodate these applications, includes very-low-noise, chopper-stabilized instrumentation amplifier nV/Hz with gain 64X. This device also includes fourth-order modulator followed digital filter which provides twenty selectable output word rates 6.25, 7.5, 12.5, 100, 120, 200, 240, 400, 480, 800, 960, 1600, 1920, 3200, 3840 (MCLK 4.9152 MHz). ease communication between microcontroller, converter includes simple three-wire serial interface which Microwire compatible with Schmitt-trigger input serial clock (SCLK). High dynamic range, programmable output rates, flexible power supply options make this device ideal solution weigh scale process control applications. ORDERING INFORMATION page
Instrumentation
Amplifier,
nV/Hz noise) 1200 Input Current Digital
Gain Scaling
Delta-sigma Analog-to-digital Converter Linearity Error: 0.0015% Noise Free Resolution: bits Scalable
VREF Input: Analog Supply
Simple Three-wire Serial Interface SPIand MicrowireCompatible Schmitt-trigger Serial Clock (SCLK) Onboard
Offset Gain Calibration Registers Word Rates: 6.25 3,840 Rejection
Selectable Selectable Power
Supply Configurations
+2.5 -2.5
VREF+
VREF-
AIN1+ AIN1-
DIFFERENTIAL ORDER MODULATOR
PROGRAMMABLE SINC FILTER SERIAL INTERFACE SCLK
LATCH
CLOCK GENERATOR
CALIBRATION SRAM/CONTROL LOGIC
OSC1
OSC2
DGND
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2009 (All Rights Reserved)
DS742F3
CS5530
TABLE CONTENTS
CHARACTERISTICS SPECIFICATIONS ANALOG CHARACTERISTICS. TYPICAL NOISE-FREE RESOLUTION (BITS) DIGITAL CHARACTERISTICS DIGITAL CHARACTERISTICS DYNAMIC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS SWITCHING CHARACTERISTICS GENERAL DESCRIPTION 2.1. Analog Input 2.1.1. Analog Input Span 2.1.2. Voltage Noise Density Performance 2.1.3. Offset 2.2. Overview Register Structure Operating Modes 2.2.1. System Initialization 2.2.2. Command Register Descriptions 2.2.3. Serial Port Interface 2.2.4. Reading/Writing On-Chip Registers 2.3. Configuration Register 2.3.1. Power Consumption 2.3.2. System Reset Sequence 2.3.3. Input Short 2.3.4. Voltage Reference Select 2.3.5. Output Latch Pins 2.3.6. Filter Rate Select 2.3.7. Word Rate Select 2.3.8. Unipolar/Bipolar Select 2.3.9. Open Circuit Detect 2.3.10. Configuration Register Description 2.4. Calibration 2.4.1. Calibration Registers 2.4.2. Gain Register 2.4.3. Offset Register 2.4.4. Performing Calibrations 2.4.5. System Calibration 2.4.6. Calibration Tips 2.4.7. Limitations Calibration Range 2.5. Performing Conversions 2.5.1. Single Conversion Mode 2.5.2. Continuous Conversion Mode 2.6. Using Multiple ADCs Synchronously 2.7. Conversion Output Coding 2.7.1. Conversion Data Output Descriptions 2.8. Digital Filter 2.9. Clock Generator 2.10. Power Supply Arrangements 2.11. Getting Started 2.12. Layout DESCRIPTIONS Clock Generator Control Pins Serial Data Measurement Reference Inputs Power Supply Connections SPECIFICATION DEFINITIONS PACKAGE DRAWINGS ORDERING INFORMATION ENVIRONMENTAL, MANUFACTURING, HANDLING INFORMATION
DS742F3
CS5530
LIST FIGURES
Figure Write Timing (Not Scale). Figure Read Timing (Not Scale). Figure Front Configuration. Figure Input Model AIN+ AIN- Pins. Figure Measured Voltage Noise Density. Figure Measured Voltage Noise Density. Figure CS5530 Register Diagram Figure Command Data Word Timing Figure Input Reference Model when Figure Input Reference Model when Figure System Calibration Offset Figure System Calibration Gain Figure Synchronizing Multiple ADCs. Figure Digital Filter Response (Word Rate Sps) Figure Filter Magnitude Plot Figure Filter Phase Plot Figure Z-Transforms Digital Filters. Figure On-chip Oscillator Model. Figure CS5530 Configured with Single Supply Figure CS5530 Configured with ±2.5 Analog Supplies. Figure CS5530 Configured with Analog Supplies.
LIST TABLES
Table Conversion Timing Single Mode Table Conversion Timing Continuous Mode. Table Output Coding
DS742F3
CS5530
CHARACTERISTICS SPECIFICATIONS
ANALOG CHARCTERISTICS
(VA+, ±5%; VREF+ VA-, VREF-, DGND MCLK 4.9152 MHz; (Output Word Rate) Sps; Bipolar Mode) (See Notes
CS5530-CS Parameter Accuracy Linearity Error Missing Codes Bipolar Offset Unipolar Offset Offset Drift Bipolar full-scale Error Unipolar full-scale Error full-scale Drift (Notes ±0.0015 ±0.003 Unit Bits LSB24 LSB24 nV/°C ppm/°C
(Note
Notes: Applies after system calibration temperature within Specifications guaranteed design, characterization, and/or test. bits. This specification applies device only does include effects external parasitic thermocouples. Drift over specified temperature range after calibration power-up
DS742F3
CS5530
ANALOG CHARACTERISTICS
(See Notes Parameter Analog Input Common Mode Signal AIN+ AINBipolar/Unipolar Mode (VA-) Current AIN+ AINInput Current Noise Open Circuit Detect Current Common Mode Rejection Input Capacitance Voltage Reference Input Range (VREF+) (VREF-) Current (Note Common Mode Rejection Input Capacitance System Calibration Specifications Full-scale Calibration Range Bipolar/Unipolar Mode Offset Calibration Range Bipolar Mode -100 Offset Calibration Range Unipolar Mode 1200 Unit (Continued)
(VA+) pA/Hz (VA+)-(VA-)
Notes: section data sheet which discusses input models. Input current VREF+ VREF- increase operated within VA-. This rough charge buffer being saturated under these conditions.
DS742F3
CS5530
ANALOG CHARACTERISTICS
(See Notes CS5530-CS Parameter Power Supplies Power Supply Currents (Normal Mode) Power Consumption IA+, IAID+ Normal Mode Standby Sleep Positive Supplies Negative Supply outputs unloaded. input CMOS levels. Tested with change VA-. (Note Unit (Continued)
Power Supply Rejection
(Note
TYPICAL NOISE-FREE RESOLUTION (BITS) (See Notes
Output Word Rate (Sps) 1,920 3,840 Filter Frequency (Hz) 1.94 3.88 7.75 15.5 Noise-free Bits Noise (nVrms) 1390
Noise Free Resolution listed Bipolar operation, calculated LOG((Input Span)/(6.6xRMS Noise))/LOG(2) rounded nearest bit. Unipolar operation, input span large, lost. input span calculated analog input span section data sheet. Noise Free Resolution table computed with value gain register. Values other than will scale noise, change Noise Free Resolution accordingly. "Noise Free Resolution" same "Effective Resolution". Effective Resolution based noise value, while Noise Free Resolution based peak-to-peak noise value specified times noise value. Effective Resolution calculated LOG((Input Span)/(RMS Noise))/LOG(2).
Specifications subject change without notice. DS742F3
CS5530
DIGITAL CHARACTERISTICS
(VA+, ±5%; VA-, DGND Notes 11.) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage Input Leakage Current 3-State Leakage Current Digital Output Capacitance Pins Except SCLK SCLK Pins Except SCLK SCLK Iout -1.0 SDO, Iout -5.0 Iout SDO, Iout Symbol Cout (VD+) 0.45 (VA+) (VD+) (VA-) Unit
DIGITAL CHARACTERISTICS
±5%; 3.0V±10%; VA-, DGND Notes 11.) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage Input Leakage Current 3-State Leakage Current Digital Output Capacitance Pins Except SCLK SCLK Pins Except SCLK SCLK Iout -1.0 SDO, Iout -5.0 Iout SDO, Iout Symbol Cout (VD+) 0.45 (VA+) (VD+) (VA-) Unit
measurements performed under static conditions.
DS742F3
CS5530
DYNAMIC CHARACTERISTICS
Parameter Modulator Sampling Rate Filter Settling Time (full-scale Step Input) Single Conversion mode (Notes Continuous Conversion mode, 3200 Continuous Conversion mode, 3200 Symbol Ratio MCLK/16 1/OWRSC 5/OWRsinc5 3/OWR 5/OWR Unit
ADCs Sinc5 filter 3200 3840 output word rate (OWR) Sinc5 filter followed Sinc3 filter other OWRs. OWRsinc5 refers 3200 (FRS 3840 (FRS word rate associated with Sinc5 filter. single conversion mode only outputs fully settled conversions. Table more details about single conversion mode timing. OWRSC used here designate different conversion time associated with single conversions. continuous conversion mode outputs every conversion. This means that filter's settling time with full-scale step input continuous conversion mode dictated OWR.
ABSOLUTE MAXIMUM RATINGS
(DGND Note 15.) Parameter Power Supplies (Notes Positive Digital Positive Analog Negative Analog (Notes Symbol VAIIN IOUT (Note VREF pins Pins VINR VINA VIND Tstg -0.3 -0.3 +0.3 (VA-) -0.3 (VA-) -0.3 -0.3 +6.0 +6.0 -3.75 (VA+) (VA+) (VD+) Unit
Input Current, Except Supplies Output Current Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature Notes:
voltages with respect ground. must satisfy {(VA+) (VA-)} +6.6 must satisfy {(VD+) (VA-)} +7.5 Applies pins including continuous overvoltage conditions analog input (AIN) pins. Transient current will cause latch-up. Maximum input current power supply Total power dissipation, including input currents output currents.
WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes. DS742F3
CS5530
SWITCHING CHARACTERISTICS
(VA+ ±5%; -2.5V±5% ±10% ±5%;DGND Levels: Logic Logic VD+; Figures Parameter Master Clock Frequency Master Clock Duty Cycle Rise Times (Note Digital Input Except SCLK SCLK Digital Output (Note Digital Input Except SCLK SCLK Digital Output XTAL 4.9152 (Note trise tfall tost SCLK Pulse Width High Pulse Width (Note External Clock Crystal Oscillator Symbol MCLK 4.9152 Unit
Fall Times
Start-up Oscillator Start-up Time Serial Port Timing Serial Clock Frequency Serial Clock Write Timing Enable Valid Latch Clock Data Set-up Time prior SCLK rising Data Hold Time After SCLK Rising SCLK Falling Prior Disable Read Timing Data Valid SCLK Falling Data Rising Hi-Z
Notes: Device parameters specified with 4.9152 clock. Specified using points waveform interest. Output loaded with Oscillator start-up time varies with crystal parameters. This specification does apply when using external clock source.
DS742F3
CS5530
Figure Write Timing (Not Scale)
Figure Read Timing (Not Scale)
DS742F3
CS5530
GENERAL DESCRIPTION
CS5530 Analog-to-Digital Converter (ADC) which uses charge-balance techniques achieve 24-bit performance. optimized measuring low-level unipolar bipolar signals weigh scale, process control, scientific, medical applications. accommodate these applications, includes very-low-noise, chopper-stabilized instrumentation amplifier nV/Hz with gain 64X. This also includes fourth-order modulator followed digital filter which provides twenty selectable output word rates 6.25, 7.5, 12.5, 100, 120, 200, 240, 400, 480, 800, 960, 1600, 1920, 3200, 3840 samples second (MCLK 4.9152 MHz). ease communication between ADCs micro-controller, converters include simple three-wire serial interface which Microwire compatible with Schmitt-trigger input serial clock (SCLK). Analog Input Figure illustrates block diagram CS5530. front includes chopper-stabilized instrumentation amplifier with gain 64X. amplifier chopper-stabilized operates with chop clock frequency MCLK/128. (sampling) current into instrumentation amplifier typically 1200 over -40°C +85°C (MCLK=4.9152 MHz). common-mode plus signal range instrumentation amplifier (VA-) (VA+) Figure illustrates input model amplifier.
fVos
MCLK
Figure Input Model AIN+ AIN- Pins
Note:
capacitor input current modeling only. physical input capacitance `Input Capacitance' specification under Analog Characteristics.
VREF+ VREFX1
1000
AIN+ AIN1000
Differential Order
Modulator
Sinc Digital Filter
Programmable Sinc Digital Filter
Serial Port
Figure Front Configuration
DS742F3
CS5530
2.1.1 Analog Input Span
full-scale input signal that converter digitize function reference voltage connected between VREF+ VREF- pins. full-scale input span converter ((VREF+) (VREF-))/(64Y), where gain amplifier Voltage Reference Select bit, must according differential voltage applied VREF+ VREF- pins part. section 2.3.4 more details. With reference, full-scale biploar input range equal ±2.5/64, about Note that these input ranges assume calibration registers their default values (i.e. Gain Offset 0.0). gain setting Gain Register altered digital codes converter full scales from
2.1.2 Voltage Noise Density Performance
Overview Register Structure Operating Modes CS5530 on-chip controller, which includes number user-accessible registers. registers used hold offset gain calibration results, configure chip's operating modes, hold conversion instructions, store conversion data words. Figure depicts block diagram on-chip controller's internal registers. converter 32-bit registers function offset gain calibration registers. These registers hold calibration results. contents these registers read written user. This allows calibration data off-loaded into external EEPROM. user also manipulate contents these registers modify offset gain slope converter. converter includes 32-bit configuration register which used setting options such power down modes, resetting converter, shorting analog input, enabling logic outputs, other user options. following pages document initialize converter perform offset gain calibrations. Each bits configuration register described. Also Command Register Quick Reference used decode valid commands (the first 8-bits into serial port).
2.2.1 System Initialization
Figure illustrates measured voltage noise density versus frequency from 0.025 device powered with ±2.5 supplies, using OWR, bipolar mode, with input short enabled.
1000
0.025
0.10
1.00 Frequency (Hz)
10.00
Figure Measured Voltage Noise Density,
2.1.3 Offset
offset included CS5530 because high dynamic range converter eliminates need one. offset register manipulated user mimic function desired.
CS5530 provide power-on-reset function. initialize ADC, user must perform software reset configuration register. Before accessing configuration register, user must insure serial port synchronization using Serial Port Initialization sequence. This sequence resets serial port command mode accomplished transmitting least SYNC1 command bytes (0xFF hexadecimal), followed SYNC0 command (0xFE hexadecimal). Note that this sequence initiated anytime reinitialize serial port. complete system
DS742F3
CS5530
initialization sequence, user must also perform system reset sequence which follows: Write logic into configuration register. This will reset calibration registers other logic (but serial port). valid reset will configuration register logic After writing logic wait master clock cycles, then write back logic Note that other bits configuration register cannot written this write cycle they being held reset until back logic While this involves writing entire word into configuration register casue logic read only bit, therefore write configuration register will overwrite bit. After clearing back logic read configuration register check state this indicates that valid reset occurred. Reading configuration register clears back logic Completing reset cycle initializes on-chip registers following states:
Configuration Register: Offset Register: Gain Register 00000000(H) 00000000(H) 01000000(H)
After configuration register been read clear bit, register then written other function bits other registers written read. Once system initialization reset completed, on-chip controller initialized into command mode where waits valid command (the first 8-bits written into serial port shifted into command register). Once valid command received decoded, byte instructs converter either acquire data from transfer data internal register, perform conversion calibration. Command Register Descriptions section lists valid commands.
Conversion Data Register Data Read Only
Offset Register Offset
Gain Register Gain
Serial Interface
SCLK
Configuration Register
Power Save Select Reset System Input Short Voltage Reference Select Output Latch Filter Rate Select Word Rate Unipolar/Bipolar Open Circuit Detect
Write Only Command Register
Figure CS5530 Register Diagram
DS742F3
CS5530
2.2.2 Command Register Descriptions
READ/WRITE OFFSET REGISTER
D7(MSB)
(Read/Write)
Write offset register. Read offset register.
READ/WRITE GAIN REGISTER
D7(MSB)
(Read/Write)
Write gain register. Read gain register.
READ/WRITE CONFIGURATION REGISTER
D7(MSB)
Function:
These commands used read from write configuration register.
Write configuration register. Read configuration register.
(Read/Write)
PERFORM CONVERSION
D7(MSB)
(Multiple Conversions)
Perform single conversion. Perform continuous conversions.
PERFORM SYSTEM OFFSET CALIBRATION
D7(MSB)
PERFORM SYSTEM GAIN CALIBRATION
D7(MSB)
SYNC1
D7(MSB)
Function:
Part serial port re-initialization sequence.
DS742F3
CS5530
SYNC0
D7(MSB)
Function: NULL
D7(MSB)
serial port re-initialization sequence.
Function:
This command used clear port flag keep converter continuous conversion mode.
DS742F3
CS5530
2.2.3 Serial Port Interface
CS5530's serial interface consists four control lines: SDI, SDO, SCLK. Figure details command data word timing. Chip Select, control line which enables access serial port. tied low, port function three wire interface. SDI, Serial Data data signal used transfer data converters. SDO, Serial Data Out, data signal used transfer output data from converters. output will held high impedance time logic
SCLK, Serial Clock, serial bit-clock which controls shifting data from ADC's serial port. must held (logic before SCLK transitions recognized port logic. accommodate optoisolators SCLK designed with Schmitt-trigger input allow optoisolator with slower rise fall times directly drive pin. Additionally, capable sinking sourcing directly drive optoisolator LED. will have less than loss drive voltage when sinking sourcing
SCLK
Command Time SCLKs
Data Time SCLKs
Write Cycle
SCLK
Command Time SCLKs
Data Time SCLKs
Read Cycle
SCLK
Command Time SCLKs
MCLK /OWR Clock Cycles
SCLKs Clear Flag Data Conversion Cycle
time takes perform conversion. Single Conversion Continuous Conversion sections data sheet more details about conversion timing.
Data Time SCLKs
Figure Command Data Word Timing
DS742F3
CS5530
2.2.4 Reading/Writing On-Chip Registers
CS5530's offset, gain, configuration registers readable writable while conversion data register read only. shown Figure write particular register user must transmit appropriate write command then follow that command bits data. example, write 0x80000000 (hexadecimal) gain register, user would first transmit command byte 0x02 (hexadecimal) followed data 0x80000000 (hexadecimal). Similarly, read particular register user must transmit appropriate read command then acquire bits data. Once register written read from, serial port returns command mode. Configuration Register ease architectural design simplify serial interface, configuration register thirtytwo bits long, however, only fifteen thirty bits used. following sections detail bits configuration register.
2.3.1 Power Consumption
both logic sleep mode entered reducing consumed power around Since this sleep mode disables oscillator, approximately oscillator start-up delay period required before returning normal mode. external clock used, there will delay.
2.3.2 System Reset Sequence
reset system (RS) permits user perform system reset. system reset initiated time writing logic configuration register. After been set, internal logic chip will initialized reset state. reset valid (RV) indicating that internal logic properly reset. cleared after configuration register read. on-chip registers initialized following default states:
Configuration Register: Offset Register: Gain Register 00000000(H) 00000000(H) 01000000(H)
CS5530 accommodates three power consumption modes: normal, standby, sleep. default mode, "normal mode", entered after power applied. this mode, CS5530 typically consumes other modes referred power save modes. They power down most analog portion chip stop filter convolutions. power save modes entered whenever power down (PDW) configuration register logic particular power save mode entered depends state (Power Save Select) bit. logic converter enters standby mode reducing power consumption standby mode leaves oscillator on-chip bias generator analog portion chip active. This allows converter quickly return normal mode once back logic
DS742F3
After reset, should written back logic complete reset cycle. will return command mode where waits valid command. Also, only configuration register that when initiating reset (i.e. second write command needed other bits Configuration Register after been cleared).
2.3.3 Input Short
input short allows user internally ground inputs ADC. This useful function because allows user easily test grounded input performance eliminate noise effects external system components.
2.3.4 Voltage Reference Select
voltage reference select (VRS) selects size sampling capacitor used sample voltage reference. should based upon
CS5530
Fine Coarse 14pF
Fine Coarse
VREF
VREF
MCLK VREF
MCLK VREF
Figure Input Reference Model when
Figure Input Reference Model when
magnitude reference voltage achieve optimal performance. Figures model effects reference's input impedance input current each setting. models show, reference includes coarse/fine charge buffer which reduces dynamic current demand external reference. reference's input buffer designed accommodate rail-to-rail (common-mode plus signal) input voltages. differential voltage between VREF+ VREF- voltage from analog supply (depending configured), however, VREF+ cannot above VREF- below VA-. Note that power supplies chip should established before reference voltage.
2.3.5 Output Latch Pins
2.3.6 Filter Rate Select
Filter Rate Select (FRS) modifies output word rates converter allow either rejection when operating from 4.9152 crystal. cleared logic word rates corresponding filter characteristics selected using Configuration Register. Rates 7.5, 120, 240, 480, 960, 1920, 3840 when using 4.9152 clock. logic word rates corresponding filter characteristics scale factor 5/6, making selectable word rates 6.25, 12.5, 100, 200, 400, 800, 1600, 3200 when using 4.9152 clock. When using other clock frequencies, these selectable word rates will scale linearly with clock frequency that used.
2.3.7 Word Rate Select
A1-A0 pins mimic D24-D23 bits configuration register. A1-A0 used control external multiplexers other logic functions outside converter. A1-A0 outputs sink source least recommended limit drive currents less than reduce self-heating chip. These outputs powered from VA-. Their output voltage will limited voltage logic logic Note that latch bits used modify analog input signal user should delay performing conversion until knows effects A0/A1 bits fully settled.
Word Rate Select bits (WR3-WR0) allow slection output word rate converter depicted Configuration Register Descriptions. word rate chosen WR3-WR0 bits modified setting presented previous paragraph.
2.3.8 Unipolar/Bipolar Select
UP/BP Select sets converter measure either unipolar bipolar input span.
2.3.9 Open Circuit Detect
When activates current source means test open thermocouples.
DS742F3
CS5530
2.3.10 Configuration Register Description
D31(MSB) UP/BP
(Power Save Select)[31]
Standby Mode (Oscillator active, allows quick power-up). Sleep Mode (Oscillator inactive). Normal Mode Activate power save select mode. Normal Operation. Activate Reset cycle. System Reset Sequence datasheet text. Normal Operation System reset. This read only. cleared logic zero after configuration register read. Normal Input signal input pairs each channel disconnected from pins shorted internally. Must always logic Reserved future upgrades. VREF [(VA+) (VA-)] VREF 2.5V latch bits will logic state these bits when Configuration register written. Note that these logic outputs powered from VA-. Must always logic Reserved future upgrades. default output word rates. Scale output word rates their corresponding filter characteristics factor 5/6. Must always logic Reserved future upgrades.
(Power Down Mode)[30]
(Reset System)[29]
(Reset Valid)[28]
(Input Short)[27]
(Not Used)[26] (Voltage Reference Select)[25]
A1-A0 (Output Latch bits)[24:23]
(Not Used)[22:20] Filter Rate Select, FRS[19]
(Not Used)[18:15]
DS742F3
CS5530
WR3-WR0 (Word Rate) [14:11]
listed Word Rates continuous conversion mode using 4.9152 clock. word rates will scale linearly with clock frequency used. very first conversion using continuous conversion mode will last longer, will conversions done with single conversion mode. section Performing Conversions Tables more details. 0000 0001 0010 0011 0100 1000 1001 1010 1011 (FRS 3840 1920 (FRS 12.5 6.25 3200 1600
1100 other combinations used.
(Unipolar Bipolar) [10]
Select Bipolar mode. Select Unipolar mode. When set, this activates current source input channel (AIN+) selected channel select bits. Note that 300nA current source rated 25°C. This feature particularly useful thermocouple applications when user wants drive suspected open thermocouple lead supply rail. Normal mode. Activate current source. Must always logic Reserved future upgrades.
(Open Circuit Detect Bit)
(Not Used) [8:0]
DS742F3
CS5530
Calibration Calibration used zero gain slope ADC's transfer function. CS5530 provides system calibration.
Note: After reset, functional perform measurements without being calibrated (remember that configuration register must properly configured). converter operated without calibraton, converter will utilize initialized values on-chip registers (Offset 0.0; Gain 1.0) calculate output words. initial offset gain errors internal circuitry chip will remain.
unipolar span, gain register 1.000.000 decimal). offset register determines offset trimmed positive negative positive, negative). Note that magnitude offset that trimmed from input mapped through gain register. converter typically trim ±100 percent input span. shown Gain Register section, gain register spans from 2-24). decimal equivalent meaning gain register
+.+b
2.4.1 Calibration Registers
CS5530 converter offset register that used zero point converter's transfer function. shown Offset Register section, offset register 1.835007966 2-24 proportion input span (bipolar span times 2.4.2 Gain Register
where binary numbers have value either zero (bD29 binary value D29). While gain register settings 2-24 available, gain register should never values above
Decimal Point 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-23 2-24
gain register span from (64-2-24). After Reset other bits `0'.
2.4.3 Offset Register
Sign 2-17
2-16
2-18
2-19
2-20
2-21
2-22
2-23
2-24
represents 1.835007966 2-24 proportion input span (bipolar span times unipolar span). Offset data word bits align MSB. After reset, bits `0'. offset register stored 32-bit, two's complement number, where last bits
DS742F3
CS5530
2.4.4 Performing Calibrations
perform calibration, user must send command byte with MSB=1, appropriate calibration bits (CC2-CC0) choose type calibration performed. calibration will performed using filter rate, siganl span (unipolar bipolar) configuration register. length time takes calibration slightly less than amount time takes single conversion (see Table single conversion timing). Offset calibration takes clock cycles less than single conversion when clock cycles less when Gain calibration takes clock cycles less than single conversion when clock cycles less when Once calibration cycle complete, falls results automatically stored either gain offset register. will remain until next command word begun. additional calibrations performed while referencing same calibration registers, last calibration results will replace effects from previous calibration. Only calibration performed with each command byte.
2.4.5 System Calibration
represent ground full-scale. When system offset calibration performed, ground referenced signal must applied converter. Figure illustrates system offset calibration. shown Figure user must input signal representing positive full-scale point perform system gain calibration. either case, calibration signals must within specified calibration limits each specific calibration step (refer System Calibration Specifications).
2.4.6 Calibration Tips
system calibration functions, user must supply converter input calibration signals which
Calibration steps performed output word rate selected WR3-WR0 bits configuration register. minimize effects peak-topeak noise accuracy calibration converter should calibrated using slowest word rate that acceptable. recommended that word rates higher used calibration.) minimize digital noise near device, user should wait each calibration step completed before reading writing serial port. Reading calibration registers averaging multiple calibrations together produce more accurate calibration result. Note that accessing ADC's serial port before calibration finished result loss synchronization between microcontroller ADC, prematurely halt calibration cycle.
Figure System Calibration Offset
Figure System Calibration Gain
DS742F3
CS5530
maximum accuracy, calibrations should performed both offset gain. When device used without calibration, uncalibrated gain accuracy about percent. Note that gain from offset register output 1.83007966 decimal, user wants adjust calibration coefficients externally, they will need divide information written offset register scale factor 1.83007966. (This discussion assumes that gain register 1.000.000 decimal. offset register also multiplied gain register before being applied output conversion words).
2.4.7 Limitations Calibration Range
FSCR, margin again incorporated accommodate intrinsic gain error. Performing Conversions CS5530 offers distinctly different conversion modes. paragraphs that follow detail differences conversion modes.
2.5.1 Single Conversion Mode
System calibration limited signal headroom analog signal path inside chip discussed under Analog Input section this data sheet. gain calibration, full-scale input signal reduced nominal fullscale value. this point, gain register approximately equal 33.33 (decimal). While gain register hold numbers 2-24, gain register settings above decimal value should used. With converter's intrinsic gain error, this minimum full-scale input signal higher lower. defining minimum full-scale Calibration Range (FSCR) under Analog Characteristics, margin retained accommodate intrinsic gain error. Inversely, input full-scale signal increased point which modulator reaches density limit percent, which under nominal conditions occurs when full-scale input signal times nominal full-scale value. With chip's intrinsic gain error, this maximum full-scale input signal maybe higher lower. defining maximum
When user transmits perform single conversion command, single, fully settled conversion performed using word rate polarity selections configuration register. Once command byte transmitted, serial port enters data mode where waits until conversion complete. When conversion data available, falls logic flag indicate that data available. Forty SCLKs then needed read conversion data word. first SCLKs used clear flag. During first SCLKs, must logic last SCLKs needed read conversion result. Note that user forced read conversion single conversion mode serial port will remain data mode until SCLK transitions times. After reading data, serial port returns command mode, where waits command issued. single conversion mode will take longer than conversions performed continuous conversion mode. number clock cycles single conversion takes each Output Word Rate (OWR) setting listed Table (FRS (FRS clock ambiguity internal synchronization between SCLK input oscillator.
Note: single conversion mode, more than conversion actually performed, only final, fully settled result output conversion data register.
DS742F3
CS5530
Table Conversion Timing Single Mode
(WR3-WR0)
Clock Cycles
0000 0001 0010 0011 0100 1000 1001 1010 1011 1100
171448 335288 662968 1318328 2629048 7592 17848 28088 48568 89528
205738 402346 795562 1581994 3154858 9110 21418 33706 58282 107434
SCLKs required clock last conversion before converter returns command mode. number clock cycles continuous conversion takes each Output Word Setting listed Table first conversion from part continuous conversion mode will longer than following conversions start-up overhead. (FRS (FRS clock ambiguity internal synchronization between SCLK input oscillator.
Note: When changing channels, after performing calibrations and/or single conversions, user must ignore first three (for OWRs less than 3200 Sps, MCLK 4.9152 MHz) first five (for 3200 Sps) conversions continuous conversion mode, residual filter coefficients must flushed from filter before accurate conversions performed.
2.5.2 Continuous Conversion Mode
When user transmits perform continuous conversion command, converter begins continuous conversions using word rate polarity selections configuration register. Once command byte transmitted, serial port enters data mode where waits until conversion complete. After conversion done, falls logic flag indicate that data available. Forty SCLKs then needed read conversion. first SCLKs used clear flag. last SCLKs needed read conversion result. `00000000' provided during first SCLKs when flag cleared, converter remains this conversion mode continues convert using same word rate polarity information. continuous conversion mode, every conversion word needs read. user needs only read conversion words required application rises falls indicate availability conversion data. Note that conversion read before next conversion data becomes available, will lost replaced conversion data. exit this conversion mode, user must provide `11111111' during first SCLKs after falls. user decides exit,
Table Conversion Timing Continuous Mode
(WR3-WR0)
Clock Cycles Clock Cycles (First Conversion) (All Other Conversions)
0000 0001 0010 0011 0100 1000 1001 1010 1011 1100 0000 0001 0010 0011 0100 1000 1001 1010 1011 1100
89528 171448 335288 662968 1318328 2472 12728 17848 28088 48568 107434 205738 402346 795562 1581994 2966 15274 21418 33706 58282
40960 81920 163840 327680 655360 1280 2560 5120 10240 20480 49152 98304 196608 393216 786432 1536 3072 6144 12288 24576
DS742F3
CS5530
Using Multiple ADCs Synchronously Some applications require synchronous data outputs from multiple ADCs converting different analog channels. Multiple CS5530 devices synchronized single system using following guidelines: ADCs system must operated from same oscillator source. ADCs system must share common SCLK lines. software reset must performed same time ADCs after system power-up selecting ADCs using their respective pins, writing reset sequence parts, using SCLK). start conversion command must sent ADCs system same time. clock cycles ambiguity first conversion single conversion) will same ADCs, provided that they were reset same time. Conversions obtained monitoring only ADC, (bring high part) reading data each part individually, before next conversion data words ready. example synchronous system using CS5530 devices shown Figure Conversion Output Coding CS5530 outputs 24-bit data conversion words. read conversion word user must read conversion data register. conversion data register bits long outputs conversions first. last byte conversion data register contains overflow flag bit. overrange flag (OF) monitors determine valid conversion performed.
CS5530 SCLK OSC2
CS5530 SCLK OSC2 CLOCK SOURCE
Figure Synchronizing Multiple ADCs
CS5530 output data conversions binary format when operating unipolar mode two's complement when operating bipolar mode. Table shows code mapping both unipolar bipolar modes. tables refers positive full-scale voltage range converter specified gain range, -VFS refers negative full-scale voltage range converter. total differential input range (between AIN+ AIN-) from unipolar mode, from -VFS bipolar mode.
Table Output Coding Unipolar Input Offset Voltage Binary VFS-1.5 FFFFFF -FFFFFE Bipolar Input Voltage Two's Complement 7FFFFF 7FFFFF -7FFFFE 000000 -FFFFFF 800001 -800000 800000
>(VFS-1.5 LSB) FFFFFF >(VFS-1.5 LSB) VFS-1.5
VFS/2-0.5 800000 -7FFFFF +0.5 000001 -000000
-0.5
-VFS+0.5
<(+0.5 LSB)
000000 <(-VFS+0.5 LSB)
DS742F3
CS5530
2.7.1 Conversion Data Output Descriptions
CS5530 (24-BIT CONVERSIONS)
D31(MSB)
Conversion Data Bits [31:8]
These bits depict latest output conversion.
(Over-range Flag Bit)
clear when over-range condition occurred. when input signal more positive than positive full-scale, more negative than zero (unipolar mode) when input more negative than negative full-scale (bipolar mode). These bits masked logic zero.
Other Bits [7:3], [1:0]
DS742F3
CS5530
Digital Filter CS5530 linear phase digital filter which programmed achieve range output word rates (OWRs) stated Configuration Register Description section. uses Sinc5 digital filter output word rates 3200 3840 (MCLK 4.9152 MHz). Other output word rates achieved using Sinc5 filter followed Sinc3 filter with programmable decimation rate.Figure shows magnitude response filter, while Figures show magnitude phase response filter Sps. Sinc3 active output word rates
except 3200 3840 (MCLK 4.9152 MHz) rate. Z-transforms filters shown Figure Sinc3 filter, programmable decimation ratio, which equal 3840/OWR when 3200/OWR when converter's digital filters scale with MCLK. example, with output word rate Sps, filter's corner frequency MCLK increased MHz, increases 1.0175 percent filter's corner frequency moves 31.54 Note that converter specified MCLK clock frequencies greater than MHz.
Phase (Degrees) -180
Gain (dB)
-120
Frequency (Hz)
Figure Digital Filter Response (Word Rate Sps)
-120
Flatness Frequency -0.01 -0.05 -0.11 -0.19 -0.30 -0.43 -0.59 -0.77 -1.09 -3.13
Frequency (Hz)
Gain (dB)
Figure Filter Phase Plot Sinc Sinc
Note:
Frequency (Hz)
text regarding Sinc3 filter's decimation ratio "D".
Figure Z-Transforms Digital Filters
Figure Filter Magnitude Plot
DS742F3
CS5530
Clock Generator CS5530 includes on-chip inverting amplifier which connected with external crystal provide master clock chip. Figure illustrates on-chip oscillator. includes loading capacitors feedback resistor form Pierce oscillator configuration. chips designed operate using 4.9152 crystal; however, other crystals with frequencies between used. lead crystal should connected OSC1 other OSC2. Lead lengths should minimized reduce stray capacitance. Note that while using on-chip oscillator, neither OSC1 OSC2 capable directly driving chip logic. When on-chip oscillator used, voltage OSC2 typically peak-to-peak. This signal compatible with external logic unless additional external circuitry added. OSC2 output should used onchip oscillator output used drive other circuitry. designer external CMOS compatible oscillator drive OSC2 with clock ADC. external clock into OSC2 must overdrive microampere output on-chip amplifier. This will harm onchip circuitry. this scheme, OSC1 should left unconnected.
2.10 Power Supply Arrangements CS5530 designed operate from single dual analog supplies single digital supply. following power supply connections possible: +2.5 -2.5 supply +2.5 +3.0 +5.0 should maintained tolerance. supply -2.5 -3.0 should maintained tolerance. extend from +2.7 +5.5 with additional restriction that [(VD+) (VA-) Figure illustrates CS5530 connected with single +5.0 supply measure differential inputs relative common mode Figure illustrates CS5530 connected with ±2.5 bipolar analog supplies digital supply measure ground referenced bipolar signals. Figures illustrates CS5532 connected with analog supplies digital supply measure ground referenced bipolar signals.
MCLK
OSC1
OSC2
NOTE: capacitors chip should added externally.
Figure On-chip Oscillator Model
DS742F3
CS5530
Analog Supply
VREF+ VREF3 OSC2
Optional Clock Source 4.9152
OSC1
CS5530 AIN1+ AIN1NC SCLK DGND
Serial Data Interface
Figure CS5530 Configured with Single Supply
+2.5 Analog Supply
VREF+ VREF3 OSC2
Digital Supply Optional Clock Source 4.9152
OSC1
CS5530 AIN1+ AIN1NC SCLK DGND
Serial Data Interface
-2.5 Analog Supply
Figure CS5530 Configured with ±2.5 Analog Supplies
DS742F3
CS5530
Analog Supply
VREF+ VREF3 OSC2
OSC1
Optional Clock Source 4.9152
CS5530 AIN1+ AIN1NC SCLK DGND
Serial Data Interface
Analog Supply
Figure CS5530 Configured with Analog Supplies
DS742F3
CS5530
2.11 Getting Started This converter several features. From software programmer's prospective, what should done first? begin, 4.9152 4.096 crystal takes approximately start. accommodate this, recommended that software delay approximately inserted before start processor's initialization code. Next, since CS5530 does provide power-on-reset function, user must first initialize known state. This accomplished resetting ADC's serial port with Serial Port Initialization sequence. This sequence resets serial port command mode accomplished transmitting SYNC1 command bytes (0xFF hexadecimal), followed SYNC0 command (0xFE hexadecimal). Once serial port command mode, user must reset internal logic performing system reset sequence (see 2.3.2 System Reset Sequence). After converter properly reset, configuration register bits should configured appropriate, example, voltage reference selection, word rate, signal polarity(unipolar bipolar) should configured. Calibrations conversions then performed appropriate. 2.12 Layout optimal performance, CS5530 should placed entirely over analog ground plane. grounded pins ADC, including DGND pin, should connected analog ground plane that runs beneath chip. split-plane system, place analog-digital plane split immediately adjacent digital portion chip.
DS742F3
CS5530
DESCRIPTIONS
DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT AMPLIFIER CAPACITOR CONNECT AMPLIFIER CAPACITOR CONNECT POSITIVE ANALOG POWER NEGATIVE ANALOG POWER LOGIC OUTPUT (ANALOG) LOGIC OUTPUT (ANALOG) MASTER CLOCK MASTER CLOCK
AIN1+
AIN1C1
VREF+
CS5530
VOLTAGE REFERENCE INPUT VOLTAGE REFERENCE INPUT DIGITAL GROUND POSITIVE DIGITAL POWER CHIP SELECT SERIAL DATA INPUT SERIAL DATA SERIAL CLOCK INPUT
VAA0 OSC2 OSC1
VREFDGND SCLK
Clock Generator
OSC1; OSC2 Master Clock
inverting amplifier inside chip connected between these pins used with crystal provide master clock device. Alternatively, external (CMOS compatible) clock (powered relative VD+) supplied into OSC2 provide master clock device. Control Pins Serial Data
Chip Select
When active low, port will recognize SCLK. When high will output high impedance state. should changed when SCLK
Serial Data Input
input serial input port. Data will input rate determined SCLK.
Serial Data Output
serial data output. will output high impedance state
SCLK Serial Clock Input
clock signal this determines input/output rate data SDI/SDO pins respectively. This input Schmitt trigger allow slow rise time signals. SCLK will recognize clocks only when low.
Logic Output (Analog), Logic Output (Analog)
logic states A1-A0 mimic A1-A0 bits Configuration Register. Logic Output VA-, Logic Output VA+.
DS742F3
CS5530
Measurement Reference Inputs
AIN1+, AIN1- Differential Analog Input
Differential input pins into device.
VREF+, VREF- Voltage Reference Input
Fully differential inputs which establish voltage reference on-chip modulator.
Amplifier Capacitor Inputs
Connections instrumentation amplifier's capacitor. Power Supply Connections
Positive Analog Power
Positive analog supply voltage.
Positive Digital Power
Positive digital supply voltage (nominally +3.0
Negative Analog Power
Negative analog supply voltage.
DGND Digital Ground
Digital Ground.
SPECIFICATION DEFINITIONS
Linearity Error
deviation code from straight line which connects endpoints transfer function. endpoint located below first code transition other endpoint located beyond code transition ones. Units percent fullscale.
Differential Nonlinearity
deviation code's width from ideal width. Units LSBs.
Full-scale Error
deviation last code transition from ideal [{(VREF+) (VREF-)} LSB]. Units LSBs.
Unipolar Offset
deviation first code transition from ideal (1/2 above voltage AINpin.). When unipolar mode (U/B Units LSBs.
Bipolar Offset
deviation mid-scale transition (111.111 000.000) from ideal (1/2 below voltage AIN- pin). When bipolar mode (U/B Units LSBs.
DS742F3
CS5530
PACKAGE DRAWINGS
SSOP PACKAGE DRAWING
SIDE VIEW
VIEW
SEATING PLANE
VIEW
INCHES -0.002 0.064 0.009 0.272 0.291 0.197 0.024 0.025 0.084 0.010 0.074 0.015 0.295 0.323 0.220 0.027 0.040
MILLIMETERS -2.13 0.05 0.25 1.62 1.88 0.22 0.38 6.90 7.50 7.40 8.20 5.00 5.60 0.61 0.69 0.63 1.03
NOTE
Notes: "E1" reference datums included mold flash protrusions, include mold mismatch measured parting line, mold flash protrusions shall exceed 0.20 side. Dimension does include dambar protrusion/intrusion. Allowable dambar protrusion shall 0.13 total excess dimension maximum material condition. Dambar intrusion shall reduce dimension more than 0.07 least material condition. These dimensions apply flat section lead between 0.10 0.25 from lead tips.
DS742F3
CS5530
ORDERING INFORMATION
Model Number Bits Channels Linearity Error (Max) Temperature Range Package
CS5530-IS CS5530-ISZ
±0.003% ±0.003%
-40°C +85°C -40°C +85°C
20-pin 0.2" Plastic SSOP 20-pin 0.2" Plastic SSOP, Lead Free
ENVIRONMENTAL, MANUFACTURING, HANDLING INFORMATION
Model Number Peak Reflow Temp Rating Floor Life
CS5530-IS CS5530-ISZ
Days Days
DS742F3
CS5530
Revision History
REVISION DATE CHANGES
2006 2006 2006 2006 2007 2009 2009
Advance Release Updated power consumption values. Updated noise density plot. Updated temperature range specification. Corrected input current 1200 Changed temp range +85. Increased input current noise spec. Minor correction Figure Input Model AIN+ AIN- Pins (page 11).
Contacting Cirrus Logic Support
product questions inquiries contact Cirrus Logic Sales Representative. find nearest www.cirrus.com
IMPORTANT NOTICE Cirrus Logic, Inc. subsidiaries ("Cirrus") believe that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). Customers advised obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, indemnification, limitation liability. responsibility assumed Cirrus this information, including this information basis manufacture sale items, infringement patents other rights third parties. This document property Cirrus furnishing this information, Cirrus grants license, express implied under patents, mask work rights, copyrights, trademarks, trade secrets other intellectual property rights. Cirrus owns copyrights associated with information contained herein gives consent copies made information only within your organization with respect Cirrus integrated circuits other products Cirrus. This consent does extend other copying such copying general distribution, advertising promotional purposes, creating work resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS DESIGNED, AUTHORIZED WARRANTED PRODUCTS SURGICALLY IMPLANTED INTO BODY, AUTOMOTIVE SAFETY SECURITY DEVICES, LIFE SUPPORT PRODUCTS OTHER CRITICAL APPLICATIONS. INCLUSION CIRRUS PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK CIRRUS DISCLAIMS MAKES WARRANTY, EXPRESS, STATUTORY IMPLIED, INCLUDING IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE, WITH REGARD CIRRUS PRODUCT THAT USED SUCH MANNER. CUSTOMER CUSTOMER'S CUSTOMER USES PERMITS CIRRUS PRODUCTS CRITICAL APPLICATIONS, CUSTOMER AGREES, SUCH USE, FULLY INDEMNIFY CIRRUS, OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS OTHER AGENTS FROM LIABILITY, INCLUDING ATTORNEYS' FEES COSTS, THAT RESULT FROM ARISE CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, Cirrus Logic logo designs trademarks Cirrus Logic, Inc. other brand product names this document trademarks service marks their respective owners. trademark Motorola, Inc. Microwire trademark National Semiconductor Corporation.
DS742F3

Features Description Chopper-stabilized CS5530 highly integr

Top Searches for this datasheet

Other recent searches