28/44-Pin, 16-Bit, Flash Microcontrollers with On-The-Go (OTG) nanoWat
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PIC24FJ64GB004 Family Data Sheet
28/44-Pin, 16-Bit, Flash Microcontrollers with On-The-Go (OTG) nanoWatt Technology
2009 Microchip Technology Inc.
DS39940C
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Trademarks Microchip name logo, Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC UNI/O registered trademarks Microchip Technology Incorporated U.S.A. other countries. FilterLab, Hampshire, HI-TECH Linear Active Thermistor, MXDEV, MXLAB, SEEVAL Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2009, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
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28/44-Pin, 16-Bit, Flash Microcontrollers with On-The-Go (OTG) nanoWatt Technology
Universal Serial Features:
v2.0 On-The-Go (OTG) Compliant Dual Role Capable either Host Peripheral Low-Speed (1.5 Mb/s) Full-Speed Mb/s) Operation Host mode Full-Speed Operation Device mode High-Precision 0.25% Accuracy using Internal Oscillator External Crystal Required Internal Voltage Boost Assist Voltage Generation Interface Off-Chip Charge Pump Voltage Generation Supports Endpoints bidirectional): module location device endpoint buffers On-Chip Transceiver Interface Off-Chip Transceiver Supports Control, Interrupt, Isochronous Bulk Transfers On-Chip Pull-up Pull-Down Resistors
Power Management Modes:
Selectable Power Management modes with nanoWatt Technology Extremely Power: Deep Sleep mode allows near total power-down typical with RTCC WDT), along with ability wake-up external triggers self-wake programmable RTCC alarm Extreme low-power DSBOR Deep Sleep, LPBOR other modes Sleep mode shuts down peripherals core substantial power reduction, fast wake-up Idle mode shuts down peripherals significant power reduction, down typical Doze mode enables clock slower than peripherals Alternate Clock modes allow on-the-fly switching lower clock speed selective power reduction during mode down typical
Special Microcontroller Features:
Operating Voltage Range 2.0V 3.6V Self-Reprogrammable under Software Control 5.5V Tolerant Input (digital pins only) High-Current Sink/Source mA/18 Pins Flash Program Memory: 10,000 erase/write cycle endurance (minimum) 20-year data retention minimum Selectable write protection boundary Fail-Safe Clock Monitor Operation: Detects clock failure switches on-chip oscillator On-Chip 2.5V Regulator Power-on Reset (POR), Power-up Timer (PWRT) Oscillator Start-up Timer (OST) Flexible Watchdog Timers (WDT) Reliable Operation: Standard programmable normal operation Extreme low-power with programmable period days Deep Sleep mode In-Circuit Serial Programming(ICSPTM) In-Circuit Debug (ICD) Pins JTAG Boundary Scan Support
High-Performance CPU:
Modified Harvard Architecture MIPS Operation Internal Oscillator with 0.25% Typical Accuracy: Multiple divide options 17-Bit 17-Bit Single-Cycle Hardware Fractional/integer Multiplier 32-Bit 16-Bit Hardware Divider 16-Bit Working Register Array Compiler Optimized Instruction Architecture: base instructions Flexible addressing modes Linear Program Memory Addressing Mbytes Linear Data Memory Addressing Kbytes Address Generation Units Separate Read Write Addressing Data Memory
Program Memory (Bytes)
Remappable Peripherals Compare/PWM Output Comparators 10-Bit (ch) Remappable Pins UART IrDA® Capture Input PMP/PSP SRAM (Bytes) CTMU RTCC I2C2
Timers 16-Bit
32GB002 64GB002 32GB004 64GB004
PIC24FJ Device
Pins
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Analog Features:
10-Bit, 13-Channel Analog-to-Digital (A/D) Converter: ksps conversion rate Conversion available during Sleep Idle Three Analog Comparators with Programmable Input/Output Configuration Charge Time Measurement Unit (CTMU): Supports capacitive touch sensing touch screens capacitive switches Provides high-resolution time measurement simple temperature sensing Hardware Real-Time Clock/Calendar (RTCC): Provides clock, calendar alarm functions Functions even Deep Sleep mode 3-Wire/4-Wire modules (support Frame modes) with 8-Level FIFO Buffer I2Cmodules support Multi-Master/Slave mode 7-Bit/10-Bit Addressing UART modules: Supports RS-485, RS-232 LIN/J2602 On-chip hardware encoder/decoder IrDA® Auto-wake-up Start Auto-Baud Detect (ABD) 4-level deep FIFO buffer Five 16-Bit Timers/Counters with Programmable Prescaler Five 16-Bit Capture Inputs, each with Dedicated Time Base Five 16-Bit Compare/PWM Outputs, each with Dedicated Time Base Programmable, 32-Bit Cyclic Redundancy Check (CRC) Generator Configurable Open-Drain Outputs Digital Pins External Interrupt Sources
Peripheral Features:
Peripheral Select: Allows independent mapping many peripherals available pins (44-pin devices) Continuous hardware integrity checking safety interlocks prevent unintentional configuration changes 8-Bit Parallel Master Port (PMP/PSP): 16-bit multiplexed addressing, with dedicated address pins 44-pin devices Programmable polarity control lines Supports legacy Parallel Slave Port
Diagrams
28-Pin SPDIP, SOIC(1)
MCLR OSCI/CLKI/C1IND/PMCS1/CN30/RA2 OSCO/CLKO/PMA0/CN29/RA3 SOSCI/C2IND/RP4/PMBE/CN1/RB4 TMS/USBID/CN27/RB5
VUSB PGEC2/D-/VMIO/RP11/CN15/RB11 PGED2/D+/VPIO/RP10/CN16/RB10 VCAP/VDDCORE DISVREG TDO/SDA1/RP9/PMD3/RCV/CN21/RB9 TDI/RP7/PMD5/INT0/CN23/RB7 VBUS
PIC24FJXXGB002
Legend: Note
represents remappable peripheral pins. Gray shading indicates 5.5V tolerant input pins. Alternative multiplexing SDA1 SCL1 when I2C1SEL set.
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Diagrams
28-Pin QFN(1,3)
MCLR
OSCI/CLKI/C1IND/PMCS1/CN30/RA2 OSCO/CLKO/PMA0/CN29/RA3
PIC24FJXXGB00218
TMS/USBID//CN27/RB5 VBUS SOSCI/C2IND/RP4/PMBE/CN1/RB4 TDI/RP7/PMD5/INT0/CN23/RB7
VUSB PGEC2/D-/VMIO/RP11/CN15/RB11 PGED2/D+/VPIO/RP10/CN16/RB10 VCAP/VDDCORE DISVREG TDO/SDA1/RP9/PMD3/RCV/CN21/RB9
Legend: Note
represents remappable peripheral pins. Gray shading indicates 5.5V tolerant input pins. Alternative multiplexing SDA1 SCL1 when I2C1SEL set. back devices should connected VSS.
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Diagrams
44-PIN TQFP,
USBOEN/SCL1/RP8/PMD4/CN22/RB8 RP7/PMD5/INT0/CN23/RB7 VBUS CN27/USBID/RB5 RP21/PMA3/CN26/RC5 RP20/PMA4/CN25/RC4 AN12/RP19/PMBE/CN28/RC3 TDI/PMA9/RA9 SOSCO/SCLKI/T1CK/C2INC/CN0/RA4
44-Pin QFN(1,3)
Legend: Note
represents remappable peripheral pins. Gray shading indicates 5.5V tolerant input pins. Alternative multiplexing SDA1 SCL1 when I2C1SEL set. back devices should connected VSS.
TMS/PMA10/RA10 TCK/PMA7/RA7 AVSS AVDD MCLR
SDA1/RP9/PMD3/RCV/CN21/RB9 RP22/PMA1/CN18/RC6 RP23/PMA0/CN17/RC7 RP24/PMA5/CN20/RC8 RP25/PMA6/CN19/RC9 DISVREG VCAP/VDDCORE PGED2/D+/VPIO/RP10/CN16/RB10 PGEC2/D-/VMIO/RP11/CN15/RB11 VUSB
PIC24FJXXGB004
SOSCI/C2IND/RP4/CN1/RB4 TDO/PMA8/RA8 OSCO/CLKO/CN29/RA3 OSCI/CLKI/C1IND/PMCS1/CN30/RA2 AN8/RP18/PMA2/CN10/RC2 AN7/RP17/CN9/RC1 AN6/RP16/CN8/RC0
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Table Contents
Device Overview Guidelines Getting Started with 16-Bit Microcontrollers. Memory Organization Flash Program Memory. Resets Interrupt Controller Oscillator Configuration Power-Saving Features. 10.0 Ports 11.0 Timer1 12.0 Timer2/3 Timer4/5 13.0 Input Capture with Dedicated Timers 14.0 Output Compare with Dedicated Timers 15.0 Serial Peripheral Interface (SPI). 16.0 Inter-Integrated Circuit (I2CTM) 17.0 Universal Asynchronous Receiver Transmitter (UART) 18.0 Universal Serial with On-The-Go Support (USB OTG) 19.0 Parallel Master Port (PMP). 20.0 Real-Time Clock Calendar (RTCC) 21.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator 22.0 10-Bit High-Speed Converter 23.0 Triple Comparator Module. 24.0 Comparator Voltage Reference. 25.0 Charge Time Measurement Unit (CTMU) 26.0 Special Features 27.0 Development Support. 28.0 Instruction Summary 29.0 Electrical Characteristics 30.0 Packaging Information. Appendix Revision History. Microchip Site Customer Change Notification Service Customer Support Reader Response Product Identification System
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VALUED CUSTOMERS
intention provide valued customers with best documentation possible ensure successful your Microchip products. this end, will continue improve publications better suit your needs. publications will refined enhanced volumes updates introduced. have questions comments regarding this publication, please contact Marketing Communications Department E-mail docerrors@microchip.com Reader Response Form back this data sheet (480) 792-4150. welcome your feedback.
Most Current Data Sheet
obtain most up-to-date version this data sheet, please register Worldwide site http://www.microchip.com determine version data sheet examining literature number found bottom outside corner page. last character literature number version number, (e.g., DS30000A version document DS30000).
Errata
errata sheet, describing minor operational differences from data sheet recommended workarounds, exist current devices. device/documentation issues become known will publish errata sheet. errata will specify revision silicon revision document which applies. determine errata sheet exists particular device, please check with following: Microchip's Worldwide site; http://www.microchip.com Your local Microchip sales office (see last page) When contacting sales office, please specify which device, revision silicon data sheet (include literature number) using.
Customer Notification System
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DEVICE OVERVIEW
This document contains device-specific information following devices: PIC24FJ32GB002 PIC24FJ64GB002 PIC24FJ32GB004 PIC24FJ64GB004 Instruction-Based Power-Saving Modes: There three instruction-based power-saving modes: Idle Mode core shut down while leaving peripherals active. Sleep Mode core peripherals that require system clock shut down leaving peripherals active that their clock clock from other devices. Deep Sleep Mode core, peripherals (except RTCC DSWDT), Flash SRAM shut down optimal current savings extend battery life portable applications.
This family expands existing line Microchip`s 16-bit microcontrollers, combining expanded peripheral feature enhanced computational performance with connectivity option: On-The-Go (OTG). PIC24FJ64GB004 family provides platform high-performance applications which need more than 8-bit platform, require power digital signal processor.
1.1.3
OSCILLATOR OPTIONS FEATURES
1.1.1
Core Features
16-BIT ARCHITECTURE
devices PIC24FJ64GB004 family offer five different oscillator options, allowing users range choices developing application hardware. These include: Crystal modes using crystals ceramic resonators. External Clock modes offering option divide-by-2 clock output. Fast Internal Oscillator (FRC) with nominal output, which also divided under software control provide clock speeds kHz. Phase Lock Loop (PLL) frequency multiplier available external oscillator modes Oscillator, which allows clock speeds MHz. separate Low-Power Internal Oscillator (LPRC) with fixed output, which provides low-power option timing-insensitive applications. internal oscillator block also provides stable reference source Fail-Safe Clock Monitor. This option constantly monitors main clock source against reference signal provided internal oscillator enables controller switch internal oscillator, allowing continued low-speed operation safe application shutdown.
Central PIC24F devices 16-bit modified Harvard architecture, first introduced with Microchip's dsPIC® digital signal controllers. PIC24F core offers wide range enhancements, such 16-bit data 24-bit address paths with ability move information between data memory spaces Linear addressing Mbytes (program space) Kbytes (data) 16-element working register array with built-in software stack support hardware multiplier with support integer math Hardware support 16-bit division instruction that supports multiple addressing modes optimized high-level languages, such Operational performance MIPS
1.1.2
POWER-SAVING TECHNOLOGY
devices PIC24FJ64GB004 family incorporate range features that significantly reduce power consumption during operation. items include: On-the-Fly Clock Switching: device clock changed under software control Timer1 source internal, Low-Power Internal Oscillator during operation, allowing user incorporate power-saving ideas into their software designs. Doze Mode Operation: When timing-sensitive applications, such serial communications, require uninterrupted operation peripherals, clock speed selectively reduced, allowing incremental power savings without missing beat.
1.1.4
EASY MIGRATION
Regardless memory size, devices share same rich peripherals, allowing smooth migration path applications grow evolve. consistent pinout scheme used throughout entire family also aids migrating from device next larger device. PIC24F family pin-compatible with devices dsPIC33 family, shares some compatibility with pinout schema PIC18 dsPIC30 devices. This extends ability applications grow from relatively simple, powerful complex, still selecting Microchip device.
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On-The-Go
PIC24FJ64GB004 family devices introduces On-The-Go functionality single chip lower count Microchip devices. This module provides on-chip functionality target device compatible with standard, well limited stand-alone functionality embedded host. implementing Host Negotiation Protocol (HNP), module also dynamically switch between device host operation, allowing much wider range versatile USB-enabled applications microcontroller platform. addition host functionality, PIC24FJ64GB004 family devices provide true single chip solution, including on-chip transceiver voltage boost generator sourcing power during host operations. Parallel Master/Enhanced Parallel Slave Port: general purpose ports reconfigured enhanced parallel data communications. this mode, port configured both master slave operations, supports 8-bit 16-bit data transfers with external address lines Master modes. Real-Time Clock/Calendar: This module implements full-featured clock calendar with alarm functions hardware, freeing timer resources program memory space core application.
Details Individual Family Members
Devices PIC24FJ64GB004 family available 28-pin 44-pin packages. general block diagram devices shown Figure 1-1. devices differentiated from each other several ways: Flash Program Memory: PIC24FJ32GB0 devices Kbytes PIC24FJ64GB0 devices Kbytes Available Pins Ports: 28-pin devices pins ports 44-pin devices pins three ports Available Interrupt-on-Change Notification (ICN) Inputs: 28-pin devices 44-pin devices Available Remappable Pins: 28-pin devices pins 44-pin devices pins Available Address Pins: 28-pin devices pins 44-pin devices pins Available Input Channels: 28-pin devices pins 44-pin devices pins other features devices this family identical. These summarized Table 1-1. list features available PIC24FJ64GB004 family devices, sorted function, shown Table 1-2. Note that this table shows location individual peripheral features they multiplexed same pin. This information provided pinout diagrams beginning this data sheet. Multiplexed features sorted priority given feature, with highest priority peripheral being listed first.
Other Special Features
Peripheral Select: Peripheral Select feature allows most digital peripherals mapped over fixed digital pins. Users independently input and/or output many digital peripherals pins. Communications: PIC24FJ64GB004 family incorporates range serial communication peripherals handle range application requirements. There independent I2Cmodules that support both Master Slave modes operation. Devices also have, through Peripheral Select (PPS) feature, independent UARTs with built-in IrDA® encoder/decoders modules. Analog Features: members PIC24FJ64GB004 family include 10-bit Converter module triple comparator module. module incorporates programmable acquisition time, allowing channel selected conversion initiated without waiting sampling period, well faster sampling speeds. comparator module includes three analog comparators that configurable wide range operations. CTMU Interface: This module provides convenient method precision time measurement pulse generation, serve interface capacitive sensors.
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TABLE 1-1: DEVICE FEATURES PIC24FJ64GB004 FAMILY
Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/ traps) Ports Total Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART (3-wire/4-wire) I2CParallel Communications (PMP/PSP) JTAG Boundary Scan 10-Bit Analog-to-Digital Module (input channels) Analog Comparators CTMU Interface Resets (and delays) POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, Lock) Base Instructions, Multiple Addressing Mode Variations 28-Pin QFN, SOIC SPDIP Peripherals accessible through remappable pins. 44-Pin TQFP 2(1) 2(1) 5(1) 5(1) 5(1) Ports 11,008 22,016 8,192 (41/4) Ports PIC24FJ32GB002 PIC24FJ64GB002 PIC24FJ32GB004 PIC24FJ64GB004 11,008 22,016
Instruction Packages Note
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FIGURE 1-1: PIC24FJ64GB004 FAMILY GENERAL BLOCK DIAGRAM
Data
Table Data Access Control Block Data Latch Program Counter Repeat Stack Control Control Logic Logic Data Address Latch Read Write PORTB I/O) PORTA(1) I/O)
Interrupt Controller
Address Latch Program Memory Data Latch
PORTC(1) I/O)
Address
Inst Latch Inst Register Instruction Decode Control OSCO/CLKO OSCI/CLKI Timing Generation FRC/LPRC Oscillators Precision Band Reference DISVREG Voltage Regulator Control Signals Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer LVD(2) Literal Data
RP(1) RP0:RP25
Divide Support Multiplier
Array
REFO
16-Bit
VDDCORE/VCAP
VDD,
MCLR
Timer1
Timer2/3(3)
Timer4/5(3)
RTCC
10-Bit
Comparators(3)
PMP/PSP PWM/OC 1-5(3) 1/2(3)
1-5(3) Note
ICNs(1)
UART 1/2(3)
CTMU
pins features implemented device pinout configurations. Table specific implementations count. functionality provided when on-board voltage regulator enabled. These peripheral I/Os only accessible through remappable pins.
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TABLE 1-2: PIC24FJ64GB004 FAMILY PINOUT DESCRIPTIONS
Number Function 28-Pin SPDIP/ SOIC 28-Pin 44-Pin QFN/TQFP Input Buffer Description
AN10 AN11 AN12 ASCL1 ASDA1 AVDD AVSS C1INA C1INB C1INC C1IND C2INA C2INB C2INC C2IND C3INA C3INB C3INC C3IND CLKI CLKO Legend:
Analog Inputs.
Alternate I2C1 Synchronous Serial Clock Input/Output. Alternate I2C1 Synchronous Serial Data Input/Output. Positive Supply Analog modules. Ground Reference Analog modules. Comparator Input Comparator Input Comparator Input Comparator Input Comparator Input Comparator Input Comparator Input Comparator Input Comparator Input Comparator Input Comparator Input Comparator Input Main Clock Input Connection. System Clock Output.
input buffer Analog level input/output
Schmitt Trigger input buffer I2C= I2C/SMBus input buffer
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TABLE 1-2: PIC24FJ64GB004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number Function 28-Pin SPDIP/ SOIC 28-Pin 44-Pin QFN/TQFP Input Buffer Description
CN10 CN11 CN12 CN13 CN15 CN16 CN17 CN18 CN19 CN20 CN21 CN22 CN23 CN25 CN26 CN27 CN28 CN29 CN30 CTED1 CTED2 CVREF DDMH DMLN DPLN DISVREG Legend:
Interrupt-on-Change Inputs.
CTMU External Edge Input CTMU External Edge Input Comparator Voltage Reference Output. Differential Plus Line (internal transceiver). Differential Minus Line (internal transceiver). External Pull-up Control Output. External Pull-down Control Output. External Pull-up Control Output. External Pull-down Control Output. Voltage Regulator Disable.
input buffer Analog level input/output
Schmitt Trigger input buffer I2C= I2C/SMBus input buffer
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TABLE 1-2: PIC24FJ64GB004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number Function 28-Pin SPDIP/ SOIC 28-Pin 44-Pin QFN/TQFP Input Buffer Description
INT0 MCLR OSCI OSCO PGEC1 PGED1 PGEC2 PGED2 PGEC3 PGED3 PMA0 PMA1 PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMCS1 PMBE PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMRD PMWR Legend:
External Interrupt Input. Master Clear (device Reset) Input. This line brought cause Reset. Main Oscillator Input Connection. Main Oscillator Output Connection. In-Circuit Clock. In-Circuit Debugger/Emulator/ICSP Programming Data. In-Circuit Debugger/Emulator/ICSP Programming Clock. In-Circuit Debugger/Emulator/ICSP Programming Data. In-Circuit Debugger/Emulator/ICSP Programming Clock. In-Circuit Debugger/Emulator/ICSP Programming Data. Parallel Master Port Address Input (Buffered Slave modes) Output (Master modes). Parallel Master Port Address Input (Buffered Slave modes) Output (Master modes). Parallel Master Port Address (Demultiplexed Master modes).
ST/TTL Parallel Master Port Chip Select Strobe/Address Parallel Master Port Byte Enable Strobe. ST/TTL Parallel Master Port Data (Demultiplexed Master mode) ST/TTL Address/Data (Multiplexed Master modes). ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL Parallel Master Port Read Strobe. Parallel Master Port Write Strobe.
input buffer Analog level input/output
Schmitt Trigger input buffer I2C= I2C/SMBus input buffer
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TABLE 1-2: PIC24FJ64GB004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number Function 28-Pin SPDIP/ SOIC 28-Pin 44-Pin QFN/TQFP Input Buffer Description
RA10 RB10 RB11 RB13 RB14 RB15 REFO Legend:
PORTA Digital I/O.
PORTB Digital I/O.
PORTC Digital I/O.
Receive Input (from external transceiver). Reference Clock Output.
input buffer Analog level input/output
Schmitt Trigger input buffer I2C= I2C/SMBus input buffer
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TABLE 1-2: PIC24FJ64GB004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number Function 28-Pin SPDIP/ SOIC 28-Pin 44-Pin QFN/TQFP Input Buffer Description
RP10 RP11 RP13 RP14 RP15 RP16 RP17 RP18 RP19 RP20 RP21 RP22 RP23 RP24 RP25 RTCC SESSEND SESSVLD SCL1 SCL2 SDA1 SDA2 SOSCI SOSCO T1CK USBID USBOEN Legend:
Remappable Peripheral (input output).
Real-Time Clock Alarm/Seconds Pulse Output. VBUS Session Status Input. VBUS Session Valid Status Input. I2C1 Synchronous Serial Clock Input/Output. I2C2 Synchronous Serial Clock Input/Output. I2C1 Data Input/Output. I2C2 Data Input/Output. Secondary Oscillator/Timer1 Clock Input. Secondary Oscillator/Timer1 Clock Output. Timer1 Clock Input. JTAG Test Clock/Programming Clock Input. JTAG Test Data/Programming Data Input. JTAG Test Data Output. JTAG Test Mode Select Input. (OTG mode only). Output Enable Control (for external transceiver).
input buffer Analog level input/output
Schmitt Trigger input buffer I2C= I2C/SMBus input buffer
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TABLE 1-2: PIC24FJ64GB004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number Function 28-Pin SPDIP/ SOIC 28-Pin 44-Pin QFN/TQFP Input Buffer Description
VBUS VBUSCHG VBUSON VBUSST VBUSVLD VCAP VCPCON VDDCORE VMIO VPIO VREFVREF+ VUSB Legend:
Voltage, Host mode (5V). External VBUS Control Output External Charge Pump Control. Internal Charge Pump Feedback Control. VBUS Valid Status Input. External Filter Capacitor Connection (regulator enabled). VBUS PWM/Charge Output. Positive Supply Peripheral Digital Logic Pins. Positive Supply Microcontroller Core Logic (regulator disabled). Differential Minus Input/Output (external transceiver). Differential Plus Input/Output (external transceiver). Comparator Reference Voltage (low) Input. Comparator Reference Voltage (high) Input. Ground Reference Logic Pins. Voltage (3.3V).
input buffer Analog level input/output
Schmitt Trigger input buffer I2C= I2C/SMBus input buffer
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GUIDELINES GETTING STARTED WITH 16-BIT MICROCONTROLLERS
Basic Connection Requirements
FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS
C2(2)
Getting started with PIC24FJ64GB004 family 16-bit microcontrollers requires attention minimal device connections before proceeding with development. following pins must always connected: pins (see Section "Power Supply Pins") AVDD AVSS pins, regardless whether analog device features used (see Section "Power Supply Pins") MCLR (see Section "Master Clear (MCLR) Pin") ENVREG/DISVREG VCAP/VDDCORE pins (PIC24FJ devices only) (see Section "Voltage Regulator Pins (ENVREG/DISVREG VCAP/VDDCORE)") These pins must also connected they being used application: PGECx/PGEDx pins used In-Circuit Serial Programming(ICSPTM) debugging purposes (see Section "ICSP Pins") OSCI OSCO pins when external oscillator source used (see Section "External Oscillator Pins") Additionally, following pins required: VREF+/VREF- pins used when external voltage reference analog modules implemented Note: AVDD AVSS pins must always connected, regardless whether analog modules being used.
MCLR
(EN/DIS)VREG VCAP/VDDCORE
PIC24FXXXX C6(2)
C3(2)
AVDD AVSS
C5(2)
C4(2)
(all values recommendations): through ceramic tantalum ceramic Note Section "Voltage Regulator Pins (ENVREG/DISVREG VCAP/VDDCORE)" explanation ENVREG/DISVREG connections. example shown PIC24F device with five VDD/VSS AVDD/AVSS pairs. Other devices have more less pairs; adjust number decoupling capacitors appropriately.
minimum mandatory connections shown Figure 2-1.
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2.2.1
Power Supply Pins
DECOUPLING CAPACITORS
Master Clear (MCLR)
decoupling capacitors every pair power supply pins, such VDD, VSS, AVDD AVSS required. Consider following criteria when using decoupling capacitors: Value type capacitor: (100 nF), 10-20V capacitor recommended. capacitor should low-ESR device with resonance frequency range higher. Ceramic capacitors recommended. Placement printed circuit board: decoupling capacitors should placed close pins possible. recommended place capacitors same side board device. space constricted, capacitor placed another layer using via; however, ensure that trace length from capacitor greater than 0.25 inch mm). Handling high-frequency noise: board experiencing high-frequency noise (upward tens MHz), second ceramic type capacitor parallel above described decoupling capacitor. value second capacitor range 0.01 0.001 Place this second capacitor next each primary decoupling capacitor. high-speed circuit designs, consider implementing decade pair capacitances close power ground pins possible (e.g., parallel with 0.001 Maximizing performance: board layout from power supply circuit, power return traces decoupling capacitors first, then device pins. This ensures that decoupling capacitors first power chain. Equally important keep trace length between capacitor power pins minimum, thereby reducing trace inductance.
MCLR provides specific device functions: device Reset, device programming debugging. programming debugging required application, direct connection that required. addition other components, help increase application's resistance spurious Resets from voltage sags, beneficial. typical configuration shown Figure 2-1. Other circuit designs implemented, depending application's requirements. During programming debugging, resistance capacitance that added must considered. Device programmers debuggers drive MCLR pin. Consequently, specific voltage levels (VIH VIL) fast signal transitions must adversely affected. Therefore, specific values will need adjusted based application requirements. example, recommended that capacitor isolated from MCLR during programming debugging operations using jumper (Figure 2-2). jumper replaced normal run-time operations. components associated with MCLR should placed within 0.25 inch pin.
FIGURE 2-2:
EXAMPLE MCLR CONNECTIONS
MCLR PIC24FXXXX
Note
2.2.2
TANK CAPACITORS
recommended. suggested starting value Ensure that MCLR specifications met. will limit current flowing into MCLR from external capacitor event MCLR breakdown, Electrostatic Discharge (ESD) Electrical Overstress (EOS). Ensure that MCLR specifications met.
boards with power traces running longer than inches length, suggested tank capacitor integrated circuits including microcontrollers supply local power source. value tank capacitor should determined based trace resistance that connects power supply source device, maximum current drawn device application. other words, select tank capacitor that meets acceptable voltage device. Typical values range from
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Voltage Regulator Pins (ENVREG/DISVREG VCAP/VDDCORE)
This section applies only PIC24FJ devices with on-chip voltage regulator.
ICSP Pins
Note:
on-chip voltage regulator enable/disable (ENVREG DISVREG, depending device family) must always connected directly either supply voltage ground. particular connection determined whether regulator used: ENVREG, enable regulator, ground disable regulator DISVREG, ground enable regulator, disable regulator Refer Section 26.2 "On-Chip Voltage Regulator" details connecting using on-chip regulator. When regulator enabled, low-ESR (<5) capacitor required VCAP/VDDCORE stabilize voltage regulator output voltage. VCAP/VDDCORE must connected VDD, must capacitor connected ground. type ceramic tantalum. suitable example Murata GRM21BF50J106ZE01 6.3V), equivalent. Designers Figure evaluate equivalence candidate devices. placement this capacitor should close VCAP/VDDCORE. recommended that trace length exceed 0.25 inch mm). Refer Section 29.0 "Electrical Characteristics" additional information. When regulator disabled, VCAP/VDDCORE must tied voltage supply VDDCORE level. Refer Section 29.0 "Electrical Characteristics" information VDDCORE.
PGECx PGEDx pins used In-Circuit Serial Programming (ICSP) debugging purposes. recommended keep trace length between ICSP connector ICSP pins device short possible. ICSP connector expected experience event, series resistor recommended, with value range tens ohms, exceed 100. Pull-up resistors, series diodes capacitors PGECx PGEDx pins recommended they will interfere with programmer/debugger communications device. such discrete components application requirement, they should removed from circuit during programming debugging. Alternatively, refer AC/DC characteristics timing requirements information respective device Flash programming specification information capacitive loading limits input voltage high (VIH) input (VIL) requirements. device emulation, ensure that "Communication Channel Select" (i.e., PGECx/PGEDx pins) programmed into device matches physical connections ICSP MPLAB® MPLAB MPLAB REAL ICEemulator. more information REAL emulator connection requirements, refer following documents that available Microchip site. "MPLAB® In-Circuit Debugger User's Guide" (DS51331) "Using MPLAB® (poster) (DS51265) "MPLAB® Design Advisory" (DS51566) "Using MPLAB® (poster) (DS51765) "MPLAB® Design Advisory" (DS51764) "MPLAB® REAL ICEIn-Circuit Emulator User's Guide" (DS51616) "Using MPLAB® REAL ICEIn-Circuit Emulator" (poster) (DS51749)
FIGURE 2-3:
FREQUENCY PERFORMANCE SUGGESTED VCAP
0.01
0.001
0.01
Frequency (MHz)
1000 10,000
Note:
Data Murata GRM21BF50J106ZE01 shown. Measurements 25°C, bias.
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External Oscillator Pins
Many microcontrollers have options least oscillators: high-frequency Primary Oscillator low-frequency Secondary Oscillator (refer Section "Oscillator Configuration" details). oscillator circuit should placed same side board device. Place oscillator circuit close respective oscillator pins with more than inch between circuit components pins. load capacitors should placed next oscillator itself, same side board. grounded copper pour around oscillator circuit isolate from surrounding circuits. grounded copper pour should routed directly ground. signal traces power traces inside ground pour. Also, using two-sided board, avoid traces other side board where crystal placed. suggested layout shown Figure 2-4. additional information design guidance oscillator circuits, please refer these Microchip Application Notes, available corporate site (www.microchip.com): AN826, "Crystal Oscillator Basics Crystal Selection rfPIC® PICmicro® Devices" AN849, "Basic PICmicro® Oscillator Design" AN943, "Practical PICmicro® Oscillator Analysis Design" AN949, "Making Your Oscillator Work"
Configuration Analog Digital Pins During ICSP Operations
MPLAB REAL emulator selected debugger, automatically initializes input pins (ANx) "digital" pins, setting bits AD1PCFGL register. bits this register that correspond pins that initialized MPLAB REAL emulator, must cleared user application firmware; otherwise, communication errors will result between debugger device. your application needs certain pins analog input pins during debug session, user application must clear corresponding bits AD1PCFGL register during initialization module. When MPLAB REAL emulator used programmer, user application firmware must correctly configure AD1PCFGL register. Automatic initialization this register only done during debugger operation. Failure correctly configure register(s) will result pins being recognized analog input pins, resulting port value being read logic `0', which affect user application functionality.
Unused I/Os
FIGURE 2-4:
SUGGESTED PLACEMENT OSCILLATOR CIRCUIT
Unused pins should configured outputs driven logic state. Alternatively, connect resistor unused pins drive output logic low.
Main Oscillator Guard Ring Guard Trace Secondary Oscillator
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Note:
This data sheet summarizes features this group PIC24F devices. intended comprehensive reference source. more information, refer "PIC24F Family Reference Manual", Section "CPU" (DS39703).
most instructions, core capable executing data program data) memory read, working register (data) read, data memory write program (instruction) memory read instruction cycle. result, three parameter instructions supported, allowing trinary operations (that executed single cycle. high-speed, 17-bit 17-bit multiplier been included significantly enhance core arithmetic capability throughput. multiplier supports Signed, Unsigned Mixed mode, 16-bit 16-bit 8-bit 8-bit integer multiplication. multiply instructions execute single cycle. 16-bit been enhanced with integer divide assist hardware that supports iterative non-restoring divide algorithm. operates conjunction with REPEAT instruction looping mechanism selection iterative divide instructions support 32-bit 16-bit), divided 16-bit, integer signed unsigned division. divide operations require cycles complete, interruptible cycle boundary. PIC24F vectored exception scheme with sources non-maskable traps interrupt sources. Each interrupt source assigned seven priority levels. block diagram shown Figure 3-1.
PIC24F 16-bit (data), modified Harvard architecture with enhanced instruction 24-bit instruction word with variable length opcode field. Program Counter (PC) bits wide addresses instructions user program memory space. single-cycle instruction prefetch mechanism used help maintain throughput provides predictable execution. instructions execute single cycle, with exception instructions that change program flow, double-word move (MOV.D) instruction table instructions. Overhead-free program loop constructs supported using REPEAT instructions, which interruptible point. PIC24F devices have sixteen, 16-bit working registers programmer's model. Each working registers data, address address offset register. 16th working register (W15) operates Software Stack Pointer interrupts calls. upper Kbytes data space memory optionally mapped into program space word boundary defined 8-bit Program Space Visibility Page Address (PSVPAG) register. program data space mapping feature lets instruction access program space were data space. Instruction Architecture (ISA) been significantly enhanced beyond that PIC18, maintains acceptable level backward compatibility. PIC18 instructions addressing modes supported either directly through simple macros. Many enhancements have been driven compiler efficiency needs. core supports Inherent operand), Relative, Literal, Memory Direct three groups addressing modes. modes support Register Direct various Register Indirect modes. Each group offers seven addressing modes. Instructions associated with predefined addressing modes depending upon their functional requirements.
Programmer's Model
programmer's model PIC24F shown Figure 3-2. registers programmer's model memory mapped manipulated directly instructions. description each register provided Table 3-1. registers associated with programmer's model memory mapped.
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FIGURE 3-1:
Table Data Access Control Block Interrupt Controller Program Counter Loop Stack Control Control Logic Logic Data Address Latch RAGU WAGU Data Data Latch
PIC24F CORE BLOCK DIAGRAM
Address Latch
Program Memory Address Data Latch Latch Literal Data
Instruction Decode Control
Instruction
Control Signals Various Blocks
Hardware Multiplier Divide Support
Register Array
16-Bit
Peripheral Modules
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TABLE 3-1:
through SPLIM TBLPAG PSVPAG RCOUNT CORCON
CORE REGISTERS
Description Working Register Array 23-Bit Program Counter STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register Control Register
Register(s) Name
FIGURE 3-2:
PROGRAMMER'S MODEL
(WREG) Frame Pointer Stack Pointer Stack Pointer Limit Value Register Program Counter Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register Working/Address Registers
Divider Working Registers
Multiplier Registers
SPLIM TBLPAG PSVPAG RCOUNT
STATUS Register (SR)
Control Register (CORCON)
IPL3
Registers bits shaded PUSH.S POP.S instructions.
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Control Registers
STATUS REGISTER
R/W-0 R/W-0(1) IPL1
REGISTER 3-1:
R/W-0(1) IPL2 Legend: Readable Value 15-9
R/W-0(1) IPL0
R/W-0
R/W-0
R/W-0
R/W-0
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read Half Carry/Borrow carry from low-order (for byte-sized data) low-order (for word-sized data) result occurred carry from low-order result occurred IPL<2:0>: Interrupt Priority Level Status bits(1,2) interrupt priority level (15); user interrupts disabled interrupt priority level (14) interrupt priority level (13) interrupt priority level (12) interrupt priority level (11) interrupt priority level (10) interrupt priority level interrupt priority level REPEAT Loop Active REPEAT loop progress REPEAT loop progress Negative Result negative Result non-negative (zero positive) Overflow Overflow occurred signed (2's complement) arithmetic this arithmetic operation overflow occurred Zero operation which effects some time past most recent operation which effects cleared (i.e., non-zero result) Carry/Borrow carry from Most Significant result occurred carry from Most Significant result occurred Status bits read-only when NSTDIS (INTCON1<15>) Status bits concatenated with IPL3 (CORCON<3>) form Interrupt Priority Level (IPL). value parentheses indicates when IPL3
Note
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REGISTER 3-2:
Legend: Readable Value 15-4 Clearable Writable Unimplemented bit, read cleared unknown R/C-0 IPL3
CORCON: CONTROL REGISTER
R/W-0
Unimplemented: Read IPL3: Interrupt Priority Level Status bit(1) interrupt priority level greater than interrupt priority level less PSV: Program Space Visibility Data Space Enable Program space visible data space Program space visible data space Unimplemented: Read User interrupts disabled when IPL3
Note
Arithmetic Logic Unit (ALU)
PIC24F bits wide capable addition, subtraction, shifts logic operations. Unless otherwise mentioned, arithmetic operations complement nature. Depending operation, affect values Carry (C), Zero (Z), Negative (N), Overflow (OV) Digit Carry (DC) Status bits register. Status bits operate Borrow Digit Borrow bits, respectively, subtraction operations. perform 8-bit 16-bit operations, depending mode instruction that used. Data operation come from register array, data memory, depending addressing mode instruction. Likewise, output data from written register array data memory location.
PIC24F incorporates hardware support both multiplication division. This includes dedicated hardware multiplier support hardware 16-bit divisor division.
3.3.1
MULTIPLIER
contains high-speed, 17-bit 17-bit multiplier. supports unsigned, signed mixed sign operation several multiplication modes: 16-bit 16-bit signed 16-bit 16-bit unsigned 16-bit signed 5-bit (literal) unsigned 16-bit unsigned 16-bit unsigned 16-bit unsigned 5-bit (literal) unsigned 16-bit unsigned 16-bit signed 8-bit unsigned 8-bit unsigned
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3.3.2 DIVIDER 3.3.3 MULTI-BIT SHIFT SUPPORT
divide block supports signed unsigned integer divide operations with following data sizes: 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide PIC24F supports both single single-cycle, multi-bit arithmetic logic shifts. Multi-bit shifts implemented using shifter block, capable performing 15-bit arithmetic right shift, 15-bit left shift, single cycle. multi-bit shift instructions only support Register Direct Addressing both operand source result destination. full summary instructions that shift operation provided below Table 3-2.
quotient divide instructions ends remainder Sixteen-bit signed unsigned instructions specify register both 16-bit divisor (Wn), register (aligned) pair (W(m 1):Wm) 32-bit dividend. divide algorithm takes cycle divisor, both 32-bit/16-bit 16-bit/16-bit instructions take same number cycles execute.
TABLE 3-2:
Instruction
INSTRUCTIONS THAT SINGLE MULTI-BIT SHIFT OPERATION
Description Arithmetic Shift Right Source Register More Bits. Shift Left Source Register More Bits. Logical Shift Right Source Register More Bits.
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MEMORY ORGANIZATION
Harvard architecture devices, PIC24F microcontrollers feature separate program data memory spaces busses. This architecture also allows direct access program memory from data space during code execution. from either 23-bit Program Counter (PC) during program execution, from table operation data space remapping, described Section "Interfacing Program Data Memory Spaces". User access program memory space restricted lower half address range (000000h 7FFFFFh). exception TBLRD/TBLWT operations which TBLPAG<7> permit access Configuration bits Device sections configuration memory space. Memory maps PIC24FJ64GB004 family devices shown Figure 4-1.
Program Address Space
program address memory space PIC24FJ64GB004 family devices instructions. space addressable 24-bit value derived
FIGURE 4-1:
PROGRAM SPACE MEMORY PIC24FJ64GB004 FAMILY DEVICES
PIC24FJ32GB00X
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory (11K instructions) User Memory Space User Flash Program Memory (22K instructions)
PIC24FJ64GB00X
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table 000000h 000002h 000004h 0000FEh 000100h 000104h 0001FEh 000200h
Flash Config Words
0057FEh 005800h
Flash Config Words Unimplemented Read Unimplemented Read
00ABFEh 00AC00h
7FFFFFh 800000h
Reserved Configuration Memory Space
Reserved
Device Config Registers
Device Config Registers
F7FFFEh F80000h F8000Eh F80010h
Reserved
Reserved
DEVID
DEVID
FEFFFEh FF0000h FFFFFFh
Note:
Memory areas shown scale.
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4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.3 FLASH CONFIGURATION WORDS
program memory space organized word-addressable blocks. Although treated bits wide, more appropriate think each address program memory lower upper word, with upper byte upper word being unimplemented. lower word always even address, while upper word address (Figure 4-2). Program memory addresses always word-aligned lower word addresses incremented decremented during code execution. This arrangement also provides compatibility with data memory space addressing makes possible access data program memory space. PIC24FJ64GB004 family devices, four words on-chip program memory reserved configuration information. device Reset, configuration information copied into appropriate Configuration registers. addresses Flash Configuration Word devices PIC24FJ64GB004 family shown Table 4-1. Their location memory shown with other memory vectors Figure 4-1. Configuration Words program memory compact format. actual Configuration bits mapped several different registers configuration memory space. Their order Flash Configuration Words reflect corresponding arrangement configuration space. Additional details device Configuration Words provided Section 26.1 "Configuration Bits".
4.1.2
HARD MEMORY VECTORS
PIC24F devices reserve addresses between 00000h 000200h hard coded program execution vectors. hardware Reset vector provided redirect code execution from default value device Reset actual start code. GOTO instruction programmed user 000000h with actual address start code 000002h. PIC24F devices also have interrupt vector tables, located from 000004h 0000FFh 000100h 0001FFh. These vector tables allow each many device interrupt sources handled separate ISRs. more detailed discussion interrupt vector tables provided Section "Interrupt Vector Table".
TABLE 4-1:
FLASH CONFIGURATION WORDS PIC24FJ64GB004 FAMILY DEVICES
Program Memory (Words) 11,008 22,016 Configuration Word Addresses 0057F8h: 0057FEh 00ABF8h: 00ABFEh
Device
PIC24FJ32GB0 PIC24FJ64GB0
FIGURE 4-2:
Address 000001h 000003h 000005h 000007h
PROGRAM MEMORY ORGANIZATION
most significant word 00000000 00000000 00000000 00000000 Program Memory `Phantom' Byte (read `0') Instruction Width least significant word 000000h 000002h 000004h 000006h Address (LSW Address)
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Data Address Space
PIC24F core separate, 16-bit wide data memory space, addressable single linear range. data space accessed using Address Generation Units (AGUs), each read write operations. data space memory shown Figure 4-3. Effective Addresses (EAs) data memory space bits wide point bytes within data space. This gives data space address range Kbytes words. lower half data memory space (that when EA<15> used implemented memory addresses, while upper half (EA<15> reserved program space visibility area (see Section 4.3.3 "Reading Data from Program Memory Using Program Space Visibility"). PIC24FJ64GB004 family devices implement total Kbytes data memory. Should point location outside this area, zero word byte will returned.
4.2.1
DATA SPACE WIDTH
data memory space organized byte-addressable, 16-bit wide blocks. Data aligned data memory registers 16-bit words, data space resolve bytes. Least Significant Bytes (LSBs) each word have even addresses, while Most Significant Bytes (MSBs) have addresses.
FIGURE 4-3:
DATA SPACE MEMORY PIC24FJ64GB004 FAMILY DEVICES
Address 0001h 07FFh 0801h Address 0000h 07FEh 0800h 1FFEh 2000h 27FEh 2800h Unimplemented Read Space
Space Data
Near Data Space
Implemented Data
1FFFh 2001h 27FFh 2801h
7FFFh 8001h
7FFFh 8000h
Program Space Visibility Area
FFFFh
FFFEh
Note:
Data memory areas shown scale.
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4.2.2 DATA MEMORY ORGANIZATION ALIGNMENT
maintain backward compatibility with PIC® devices improve data space memory usage efficiency, PIC24F instruction supports both word byte operations. consequence byte accessibility, Effective Address calculations internally scaled step through word-aligned memory. example, core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result value byte operations word operations. Data byte reads will read complete word which contains byte using determine which byte select. selected byte placed onto data path. That data memory registers organized parallel, byte-wide entities with shared (word) address decode, separate write lines. Data byte writes only write corresponding side array register which matches byte address. word accesses must aligned even address. Misaligned word data fetches supported, care must taken when mixing byte word operations translating from 8-bit code. misaligned read write attempted, address error trap will generated. error occurred read, instruction underway completed; occurred write, instruction will executed write will occur. either case, trap then executed, allowing system and/or user examine machine state prior execution address Fault. byte loads into register loaded into Least Significant Byte. Most Significant Byte modified. Sign-Extend (SE) instruction provided allow users translate 8-bit signed data 16-bit signed values. Alternatively, 16-bit unsigned data, users clear register executing Zero-Extend (ZE) instruction appropriate address. Although most instructions capable operating word byte data sizes, should noted that some instructions operate only words.
4.2.3
NEAR DATA SPACE
8-Kbyte area between 0000h 1FFFh referred near data space. Locations this space directly addressable 13-bit absolute address field within memory direct instructions. remainder data space indirectly addressable. Additionally, whole data space addressable using instructions, which support Memory Direct Addressing with 16-bit address field.
4.2.4
SPACE
first Kbytes near data space, from 0000h 07FFh, primarily occupied with Special Function Registers (SFRs). These used PIC24F core peripheral modules controlling operation device. SFRs distributed among modules that they control generally grouped together module. Much space contains unused addresses; these read `0'. diagram space, showing where SFRs actually implemented, shown Table 4-2. Each implemented area indicates 32-byte region where least address implemented SFR. complete listing implemented SFRs, including their addresses, shown Tables through 4-27.
TABLE 4-2:
IMPLEMENTED REGIONS DATA SPACE
Space Address xx00 xx20 Core Timers UART A/D/CTMU RTCC CRC/Comp System/DS Capture Comparators NVM/PMD xx40 xx60 xx80 xxA0 Interrupts Compare xxC0 xxE0
000h 100h 200h 300h 400h 500h 600h 700h
Legend: implemented SFRs this block
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TABLE 4-3:
File Name WREG0 WREG1 WREG2 WREG3 WREG4 WREG5 WREG6 WREG7 WREG8 WREG9 WREG10 WREG11 WREG12 WREG13 WREG14 WREG15 SPLIM TBLPAG PSVPAG RCOUNT CORCON DISICNT Legend: Addr 0000 0002 0004 0006 0008 000A 000C 000E 0010 0012 0014 0016 0018 001A 001C 001E 0020 002E 0030 0032 0034 0036 0042 0044 0052
CORE REGISTERS
Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 xxxx 0000 Program Counter Register High Byte Table Memory Page Address Register Program Space Visibility Page Address Register IPL2 IPL1 IPL0 IPL3 0000 0000 0000 xxxx 0000 0000 xxxx
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Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Stack Pointer Limit Value Register Program Counter Word Register Repeat Loop Counter Register
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Disable Interrupts Counter Register
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-4:
File Addr Name CNEN1 0060 CNEN2 0062 CNPU2 006A Legend: Note
REGISTER
CN30IE CN13IE CN29IE CN13PUE CN12IE CN28IE
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CN11IE CN27IE
CN10IE(1) CN26IE
CN9IE(1) CN25IE
CN8IE(1)
CN7IE CN23IE CN7PUE
CN6IE CN22IE CN6PUE
CN5IE CN21IE CN5PUE
CN4IE CN20IE(1) CN4PUE
CN3IE CN19IE(1) CN3PUE
CN2IE CN18IE(1) CN2PUE
CN1IE CN17IE(1) CN1PUE
CN0IE CN16IE CN0PUE
Resets 0000 0000 0000 0000
CN15IE
CNPU1 0068 CN15PUE
CN12PUE
CN11PUE CN10PUE(1) CN9PUE(1) CN8PUE(1)
CN30PUE CN29PUE CN28PUE(1) CN27PUE CN26PUE(1) CN25PUE(1)
CN23PUE CN22PUE CN21PUE CN20PUE(1) CN19PUE(1) CN18PUE(1) CN17PUE(1) CN16PUE
unimplemented, read `0'. Reset values shown hexadecimal. Unimplemented 28-pin devices; read `0'.
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TABLE 4-5:
File Name Addr INTCON1 INTCON2 IFS0 IFS1 IFS2 IFS3 IFS4 IFS5 IEC0 IEC1 IEC2 IEC3 IEC4 IEC5 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC9 IPC10 IPC11 IPC12 IPC15 IPC16 IPC18 IPC19 IPC21 INTTREG 0080 0082 0084 0086 0088 008A 008C 008E 0094 0096 0098 009A 009C 009E 00A4 00A6 00A8 00AA 00AC 00AE 00B0 00B2 00B4 00B6 00B8 00BA 00BC 00C2 00C4 00C8 00CA 00CE 00E0
INTERRUPT CONTROLLER REGISTER
NSTDIS ALTIVT U2TXIF U2TXIE CPUIRQ DISI U2RXIF RTCIF U2RXIE RTCIE T1IP2 T2IP2 CNIP2 T4IP2 U2TXIP2 IC5IP2 CRCIP2 AD1IF INT2IF PMPIF CTMUIF AD1IE INT2IE PMPIE CTMUIE T1IP1 T2IP1 CNIP1 T4IP1 U2TXIP1 IC5IP1 CRCIP1 VHOLD U1TXIF T5IF U1TXIE T5IE T1IP0 T2IP0 CNIP0 T4IP0 U2TXIP0 IC5IP0 CRCIP0 U1RXIF T4IF U1RXIE T4IE ILR3 SPI1IF OC4IF SPI1IE OC4IE OC1IP2 OC2IP2 SPI1IP2 CMIP2 OC4IP2 IC4IP2 RTCIP2 ILR2 SPF1IF OC3IF OC5IF SPF1IE OC3IE OC5IE OC1IP1 OC2IP1 SPI1IP1 CMIP1 OC4IP1 IC4IP1 RTCIP1 ILR1 T3IF LVDIF T3IE LVDIE OC1IP0 OC2IP0 SPI1IP0 CMIP0 OC4IP0 IC4IP0 RTCIP0 ILR0 T2IF IC5IF T2IE IC5IE OC2IF IC4IF USB1IF OC2IE IC4IE USB1IE IC1IP2 IC2IP2 SPF1IP2 AD1IP2 OC3IP2 INT2IP2 SPI2IP2 IC3IP2 OC5IP2 PMPIP2 SI2C2IP2 U1ERIP2 IC2IF IC3IF IC2IE IC3IE IC1IP1 IC2IP1 SPF1IP1 AD1IP1 OC3IP1 INT2IP1 SPI2IP1 IC3IP1 OC5IP1 PMPIP1 SI2C2IP1 U1ERIP1 OSCFAIL INT1EP IC1IF MI2C1IF SPI2IF SI2C2IF U1ERIF IC1IE MI2C1IE SPI2IE SI2C2IE U1ERIE INT0IP1 T3IP1 U1TXIP1 INT1IP1 T5IP1 SPF2IP1 LVDIP1 INT0EP INT0IF SI2C1IF SPF2IF INT0IE SI2C1IE SPF2IE INT0IP0 T3IP0 U1TXIP0 INT1IP0 T5IP0 SPF2IP0 LVDIP0 Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444
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MATHERR ADDRERR STKERR INT1IF INT1IE IC1IP0 IC2IP0 SPF1IP0 AD1IP0 OC3IP0 INT2IP0 SPI2IP0 IC3IP0 OC5IP0 PMPIP0 SI2C2IP0 U1ERIP0 T1IF CNIF CRCIF T1IE CNIE CRCIE INT2EP OC1IF CMIF MI2C2IF U2ERIF OC1IE CMIE MI2C2IE U2ERIE INT0IP2 T3IP2 U1TXIP2 INT1IP2 T5IP2 SPF2IP2 LVDIP2
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4440 4444 0044 4444 0004 4440 4444 0044 4440 0040 0040 0440 0400 4440 0004 0040 0400 0000
U1RXIP2 U1RXIP1 U1RXIP0
MI2C1IP2 MI2C1IP1 MI2C1IP0
SI2C1IP2 SI2C1IP1 SI2C1IP0
U2RXIP2 U2RXIP1 U2RXIP0
MI2C2IP2 MI2C2IP1 MI2C2IP0 U2ERIP2 U2ERIP1 U2ERIP0
CTMUIP2 CTMUIP1 CTMUIP0
USB1IP2 USB1IP1 USB1IP0
VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-6:
File Name TMR1 T1CON TMR2 TMR3HLD TMR3 T2CON T3CON TMR4 TMR5HLD TMR5 Addr 0100 0102 0104 0106 0108 010A 010C 010E 0110 0112 0114 0116 0118 011A 011C 011E 0120
TIMER REGISTER
Resets 0000 FFFF TGATE TCKPS1 TCKPS0 TSYNC 0000 0000 0000 0000 FFFF FFFF TGATE TGATE TCKPS1 TCKPS1 TCKPS0 TCKPS0 0000 0000 0000 0000 0000 FFFF FFFF TGATE TGATE TCKPS1 TCKPS1 TCKPS0 TCKPS0 0000 0000
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Timer1 Register Timer1 Period Register TSIDL Timer2 Register Timer3 Holding Register (for 32-bit timer operations only) Timer3 Register Timer2 Period Register Timer3 Period Register TSIDL TSIDL
Timer4 Register Timer5 Holding Register (for 32-bit operations only) Timer5 Register Timer4 Period Register Timer5 Period Register TSIDL TSIDL
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T4CON T5CON Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-7:
File Name IC1CON1 IC1CON2 IC1BUF IC1TMR IC2CON1 IC2CON2 IC2BUF IC2TMR IC3CON1 IC3CON2 IC3BUF IC3TMR IC4CON1 IC4CON2 IC4BUF IC4TMR IC5CON1 IC5CON2 IC5BUF IC5TMR Legend: Addr 0140 0142 0144 0146 0148 014A 014C 014E 0150 0152 0154 0156 0158 015A 015C 015E 0160 0162 0164 0166
INPUT CAPTURE REGISTER
ICSIDL IC32 ICTRIG ICI1 TRIGSTAT ICI0 ICOV ICBNE ICM2 ICM1 ICM0 Resets 0000 0000 xxxx ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 0000 xxxx ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 0000 xxxx ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 0000 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
2009 Microchip Technology Inc.
ICTSEL2 ICTSEL1 ICTSEL0
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
Input Capture Buffer Register Timer Value Register ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 IC32 ICTRIG ICI1 TRIGSTAT
Input Capture Buffer Register Timer Value Register ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 IC32 ICTRIG ICI1 TRIGSTAT
Input Capture Buffer Register Timer Value Register ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 IC32 ICTRIG ICI1 TRIGSTAT
Input Capture Buffer Register Timer Value Register ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 IC32 ICTRIG ICI1 TRIGSTAT ICI0 ICOV ICBNE ICM2 ICM1 ICM0
PIC24FJ64GB004 FAMILY
xxxx 0000 0000 xxxx SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
DS39940C-page
Input Capture Buffer Register Timer Value Register
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-8:
File Name OC1CON1 OC1CON2 OC1RS OC1R OC1TMR OC2CON1 OC2CON2 OC2RS OC2R OC2TMR OC3CON1 OC3CON2 OC3RS OC3R OC3TMR Addr 0190 0192 0194 0196 0198 019A 019C 019E 01A0 01A2 01A4 01A6 01A8 01AA 01AC 01AE 01B0 01B2 01B4 01B6 01B8 01BA 01BC 01BE 01C0
OUTPUT COMPARE REGISTER
FLTMD OCSIDL ENFLT2 DCB0 ENFLT1 OC32 ENFLT0 OCTRIG OCFLT2 TRIGSTAT OCFLT1 OCTRIS OCFLT0 TRIGMODE OCM2 OCM1 OCM0 Resets 0000 000C 0000 0000 xxxx OCFLT1 OCTRIS OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 000C 0000 0000 xxxx OCFLT1 OCTRIS OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 000C 0000 0000 xxxx OCFLT1 OCTRIS OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 000C 0000 0000 xxxx OCFLT1 OCTRIS OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 000C 0000 0000 xxxx SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
DS39940C-page
PIC24FJ64GB004 FAMILY
OCTSEL2 OCTSEL1 OCTSEL0 OCINV DCB1
FLTOUT FLTTRIEN
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
Output Compare Secondary Register Output Compare Register Timer Value Register FLTMD OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 OCINV DCB1 ENFLT2 DCB0 ENFLT1 OC32 ENFLT0 OCTRIG OCFLT2 TRIGSTAT FLTOUT FLTTRIEN
Output Compare Secondary Register Output Compare Register Timer Value Register FLTMD OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 OCINV DCB1 ENFLT2 DCB0 ENFLT1 OC32 ENFLT0 OCTRIG OCFLT2 TRIGSTAT FLTOUT FLTTRIEN
Output Compare Secondary Register Output Compare Register Timer Value Register FLTMD OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 OCINV DCB1 ENFLT2 DCB0 ENFLT1 OC32 ENFLT0 OCTRIG OCFLT2 TRIGSTAT FLTOUT FLTTRIEN
2009 Microchip Technology Inc.
OC4CON1 OC4CON2 OC4RS OC4R OC4TMR OC5CON1 OC5CON2 OC5RS OC5R OC5TMR Legend:
Output Compare Secondary Register Output Compare Register Timer Value Register FLTMD OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 OCINV DCB1 ENFLT2 DCB0 ENFLT1 OC32 ENFLT0 OCTRIG OCFLT2 TRIGSTAT FLTOUT FLTTRIEN
Output Compare Secondary Register Output Compare Register Timer Value Register
unimplemented, read `0'. Reset values shown hexadecimal.
2009 Microchip Technology Inc.
TABLE 4-9:
File Name I2C1RCV I2C1TRN I2C1BRG I2C1CON I2C1STAT I2C1ADD I2C1MSK I2C2RCV I2C2TRN I2C2BRG I2C2CON I2C2STAT I2C2ADD I2C2MSK Legend: Addr 0200 0202 0204 0206 0208 020A 020C 0210 0212 0214 0216 0218 021A 021C
I2CREGISTER
I2CEN I2CEN I2CSIDL I2CSIDL SCLREL SCLREL IPMIEN IPMIEN A10M A10M DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV ACKDT DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV ACKDT Resets 0000 00FF 0000 RSEN 1000 0000 0000 0000 0000 00FF 0000 RSEN 1000 0000 0000 0000
Receive Register Transmit Register Baud Rate Generator Register ACKEN RCEN
ACKSTAT TRSTAT
Address Register Address Mask Register Receive Register Transmit Register Baud Rate Generator Register ACKEN RCEN
ACKSTAT TRSTAT
Address Register Address Mask Register
PIC24FJ64GB004 FAMILY
unimplemented, read `0'. Reset values shown hexadecimal.
DS39940C-page
TABLE 4-10:
File Name U1MODE U1STA U1TXREG U1RXREG U1BRG U2MODE U2STA U2TXREG U2RXREG U2BRG Legend: Addr 0220 0222 0224 0226 0228 0230 0232 0234 0236 0238
UART REGISTER MAPS
UARTEN UARTEN USIDL UTXISEL0 USIDL UTXISEL0 IREN IREN RTSMD UTXBRK RTSMD UTXBRK UTXEN UTXEN UEN1 UTXBF Baud Rate Generator Prescaler Register UEN1 UTXBF Baud Rate Generator Prescaler Register UEN0 TRMT WAKE LPBACK ABAUD ADDEN RXINV RIDLE BRGH PERR PDSEL1 FERR PDSEL0 OERR STSEL URXDA UTXISEL1 UTXINV URXISEL1 URXISEL0 UEN0 TRMT WAKE LPBACK ABAUD ADDEN RXINV RIDLE BRGH PERR PDSEL1 FERR PDSEL0 OERR STSEL URXDA Resets 0000 0110 xxxx 0000 0000 0000 0110 xxxx 0000 0000
UTXISEL1 UTXINV
URXISEL1 URXISEL0
Transmit Register Receive Register
Transmit Register Receive Register
unimplemented, read `0'. Reset values shown hexadecimal.
DS39940C-page
PIC24FJ64GB004 FAMILY
TABLE 4-11:
File Name SPI1STAT SPI1CON1 SPI1CON2 SPI1BUF SPI2STAT SPI2CON1 SPI2CON2 SPI2BUF Legend: Addr 0240 0242 0244 0248 0260 0262 0264 0268
REGISTER MAPS
SPIEN FRMEN SPIEN FRMEN SPIFSD SPIFSD SPISIDL SPIFPOL SPISIDL SPIFPOL DISSCK DISSCK DISSDO DISSDO SRMPT SSEN SRMPT SSEN SPIROV SPIROV SRXMPT MSTEN SRXMPT MSTEN SISEL2 SPRE2 SISEL2 SPRE2 SISEL1 SPRE1 SISEL1 SPRE1 SISEL0 SPRE0 SISEL0 SPRE0 SPITBF PPRE1 SPIFE SPITBF PPRE1 SPIFE SPIRBF PPRE0 SPIBEN SPIRBF PPRE0 SPIBEN Resets 0000 0000 0000 0000 0000 0000 0000 0000
SPIBEC2 SPIBEC1 SPIBEC0 MODE16
Transmit Receive Buffer SPIBEC2 SPIBEC1 SPIBEC0 MODE16
Transmit Receive Buffer
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-12:
File Name TRISA PORTA LATA ODCA Legend: Note Addr 02C0 02C2 02C4 02C6
PORTA REGISTER
10(1) TRISA10 RA10 LATA10 ODA10 9(1) TRISA9 LATA9 ODA9 8(1) TRISA8 LATA8 ODA8 7(1) TRISA7 LATA7 ODA7 TRISA4 LATA4 ODA4 TRISA3 LATA3 ODA3 Bit2 TRISA2 LATA2 ODA2 TRISA1 LATA1 ODA1 TRISA0 LATA0 ODA0 Resets 079F xxxx xxxx 0000
2009 Microchip Technology Inc.
unimplemented, read `0'. Reset values shown hexadecimal. Reset values shown 44-pin devices. Bits unimplemented 28-pin devices; read `0'.
TABLE 4-13:
File Name TRISB PORTB LATB ODCB Legend: Addr 02C8 02CA 02CC 02CE
PORTB REGISTER
TRISB11 RB11 LATB11 ODB11 TRISB10 RB10 LATB10 ODB10 TRISB9 LATB9 ODB9 TRISB8 LATB8 ODB8 TRISB7 LATB7 ODB7 TRISB5 LATB5 ODB5 TRISB4 LATB4 ODB4 TRISB3 LATB3 ODB3 TRISB2 LATB2 ODB2 TRISB1 LATB1 ODB1 TRISB0 LATB0 ODB0 Resets EFBF xxxx xxxx 0000
TRISB15 TRISB14 TRISB13 RB15 LATB15 ODB15 RB14 LATB14 ODB14 RB13 LATB13 ODB13
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-14:
File Name TRISC PORTC LATC ODCC Legend: Note Addr 02D0 02D2 02D4 02D6
PORTC REGISTER
9(1) TRISC9 LATC9 ODC9 8(1) TRISC8 LATC8 ODC8 7(1) TRISC7 LATC7 ODC7 6(1) TRISC6 LATC6 ODC6 5(1) TRISC5 LATC5 ODC5 4(1) TRISC4 LATC4 ODC4 3(1) TRISC3 LATC3 ODC3 2(1) TRISC2 LATC2 ODC2 1(2(1) TRISC1 LATC1 ODC1 0(1) TRISC0 LATC0 ODC0 Resets 03FF xxxx xxxx 0000
unimplemented, read `0'. Reset values shown hexadecimal. Reset values shown 44-pin devices. Bits unimplemented 28-pin devices; read `0'.
TABLE 4-15:
File Name PADCFG1 Legend: Addr 02FC
CONFIGURATION REGISTER
PMPTTL Resets 0000
2009 Microchip Technology Inc.
RTSECSEL1 RTSECSEL0
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-16:
File Name ADC1BUF0 ADC1BUF1 ADC1BUF2 ADC1BUF3 ADC1BUF4 ADC1BUF5 ADC1BUF6 ADC1BUF7 ADC1BUF8 ADC1BUF9 ADC1BUFA ADC1BUFB ADC1BUFC ADC1BUFD ADC1BUFE ADC1BUFF AD1CON1 AD1CON2 AD1CON3 AD1CHS AD1PCFG AD1CSSL Legend: Note Addr 0300 0302 0304 0306 0308 030A 030C 030E 0310 0312 0314 0316 0318 031A 031C 031E 0320 0322 0324 0328 032C 0330
REGISTER
Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer ADON VCFG2 ADRC CH0NB PCFG15 CSSL15 VCFG1 CSSL14 ADSIDL VCFG0 SAMC4 CH0SB4
PIC24FJ64GB004 FAMILY
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx SSRC1 ADCS6 SSRC0 SMPI3 ADCS5 PCFG5 CSSL5 SMPI2 ADCS4 CH0SA4 PCFG4 CSSL4 SMPI1 ADCS3 CH0SA3 PCFG3 CSSL3 ASAM SMPI0 ADCS2 CH0SA2 PCFG2 CSSL2 SAMP BUFM ADCS1 CH0SA1 PCFG1 CSSL1 DONE ALTS ADCS0 CH0SA0 PCFG0 CSSL0 0000 0000 0000 0000 0000 0000
DS39940C-page
SAMC3 CH0SB3 CSSL11
CSCNA SAMC2 CH0SB2 PCFG10 CSSL10
FORM1 SAMC1 CH0SB1 PCFG9 CSSL9
FORM0 SAMC0 CH0SB0
SSRC2 BUFS ADCS7 CH0NA
PCFG14 PCFG13 PCFG12(1) PCFG11 CSSL13 CSSL12
PCFG8(1) PCFG7(1) PCFG6(1) CSSL8(1) CSSL7(1) CSSL6(1)
unimplemented, read `0', reserved, maintain `0'. Reset values shown hexadecimal. Bits available 28-pin devices; read `0'.
TABLE 4-17:
File Name CTMUCON CTMUICON Legend: Addr
CTMU REGISTER
ITRIM4 CTMUSIDL ITRIM3 TGEN Resets 0000 0000
033C CTMUEN 033E ITRIM5
EDGEN EDGSEQEN IDISSEN ITRIM0 IRNG1
CTTRIG EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT IRNG0
ITRIM2 ITRIM1
unimplemented, read `0'. Reset values shown hexadecimal.
DS39940C-page
PIC24FJ64GB004 FAMILY
TABLE 4-18:
File Name U1OTGIR U1OTGIE U1OTGSTAT U1OTGCON U1PWRC U1IR U1IE U1EIR U1EIE U1STAT U1CON U1ADDR U1BDTP1 U1FRML U1FRMH U1TOK(2) U1SOF(2) U1CNFG1 U1CNFG2 Legend: Note Addr 0480 0482 0484 0486 0488 048A(1) 048C(1) 048E(1) 0490(1) 0492 0494(1) 0496 0498 049A 049C 049E 04A0 04A6 04A8
REGISTER
UTEYE UOEMON UVCMPSEL PID3 PID2 PID1 IDIF IDIE DPPULUP UACTPND STALLIF STALLIF STALLIE STALLIE BTSEF BTSEF BTSEE BTSEE ENDPT3 JSTATE(1) LSPDEN(1) T1MSECIF T1MSECIE DMPULUP ATTACHIF(1) ATTACHIE(1) ENDPT2 LSTATEIF LSTATEIE LSTATE RESUMEIF RESUMEIF RESUMEIE RESUMEIE DMAEF DMAEF DMAEE DMAEE ENDPT1 PKTDIS TOKBUSY(1) ACTVIF ACTVIE USLPGRD IDLEIF IDLEIF IDLEIE IDLEIE BTOEF BTOEF BTOEE BTOEE ENDPT0 USBRST SESVDIF SESVDIE SESVD VBUSON TRNIF TRNIF TRNIE TRNIE DFN8EF DFN8EF DFN8EE DFN8EE HOSTEN HOSTEN SESENDIF SESENDIE SESEND OTGEN SOFIF SOFIF SOFIE SOFIE CRC16EF CRC16EF CRC16EE CRC16EE PPBI RESUME RESUME VBUSCHG USUSPND UERRIF UERRIF UERRIE UERRIE CRC5EF EOFEF(1) CRC5EE EOFEE(1) PPBRST PPBRST VBUSVDIF VBUSVDIE VBUSVD VBUSDIS USBPWR URSTIF DETACHIF(1) URSTIE PIDEF PIDEF PIDEE PIDEE USBEN SOFEN(1) Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PPB1 UVCMPDIS PPB0 UTRDIS 0000 0000 0000 0000
DPPULDWN DMPULDWN
DETACHIE(1) 0000
2009 Microchip Technology Inc.
Device Address (DEVADDR) Register Buffer Descriptor Table Base Address Register Frame Count Register Byte Frame Count Register High Byte PID0 USBSIDL PUVBUS Start-Of-Frame Count Register EXTI2CEN UVBUSDIS
unimplemented, read `0'. Reset values shown hexadecimal. Alternate register definitions when module operating Host mode. This register available Host mode only.
TABLE 4-18:
File Name U1EP0 U1EP1 U1EP2 U1EP3 U1EP4 U1EP5 U1EP6 U1EP7 U1EP8 U1EP9 U1EP10 U1EP11 U1EP12 U1EP13 U1EP14 U1EP15 U1PWMRRS U1PWMCON Legend: Note Addr 04AA 04AC 04AE 04B0 04B2 04B4 04B6 04B8 04BA 04BC 04BE 04C0 04C2 04C4 04C6 04C8 04CC 04CE
REGISTER (CONTINUED)
PWMEN LSPD(1) RETRYDIS(1) EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
2009 Microchip Technology Inc.
PIC24FJ64GB004 FAMILY
DS39940C-page
Power Supply Duty Cycle Register PWMPOL CNTEN
Power Supply Period Register
unimplemented, read `0'. Reset values shown hexadecimal. Alternate register definitions when module operating Host mode. This register available Host mode only.
TABLE 4-19:
File Name Addr PMCON PMMODE PMADDR PMDOUT1 PMDOUT2 0606 PMDIN1 PMDIN2 PMAEN PMSTAT Legend: Note 0608 060A 060C 060E 0600 0602 0604
PARALLEL MASTER/SLAVE PORT REGISTER
PMPEN BUSY IRQM1 PSIDL IRQM0 PTBEEN MODE16 CSF1 WAITB1 CSF0 WAITB0 WAITM3 WAITM2 CS1P WAITM1 WAITM0 WRSP WAITE1 ADDR1 RDSP WAITE0 ADDR0 Resets 0000 0000 0000 0000 0000 0000 0000 PTEN1 OB1E PTEN0 OB0E 0000 0000 OB3E OB2E
ADRMUX1 ADRMUX0 INCM1 INCM0
PTWREN PTRDEN MODE1 MODE0
ADDR10(1) ADDR9(1) ADDR8(1) ADDR7(1) ADDR6(1) ADDR5(1) ADDR4(1) ADDR3(1) ADDR2(1) Parallel Port Data Register (Buffers Parallel Port Data Register (Buffers Parallel Port Data Register (Buffers Parallel Port Data Register (Buffers
PTEN14 IBOV
IB3F
PTEN10(1) PTEN9(1) PTEN8(1) PTEN7(1) PTEN6(1) PTEN5(1) PTEN4(1) PTEN3(1) PTEN2(1) IB2F IB1F IB0F OBUF
unimplemented, read `0'. Reset values shown hexadecimal. Bits available 28-pin devices; read `0'.
TABLE 4-20:
File Name ALRMVAL ALCFGRPT RTCVAL RCFGCAL Legend: Addr 0620 0622 0624 0626
REAL-TIME CLOCK CALENDAR REGISTER
Resets xxxx ARPT5 CAL5 ARPT4 CAL4 ARPT3 CAL3 ARPT2 CAL2 ARPT1 CAL1 ARPT0 CAL0 0000 xxxx xxxx
DS39940C-page
PIC24FJ64GB004 FAMILY
Alarm Value Register Window Based ALRMPTR<1:0> ALRMEN CHIME RTCEN AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 RTCOE RTCPTR1 RTCPTR0 ARPT7 CAL7 ARPT6 CAL6 RTCC Value Register Window Based RTCPTR<1:0> RTCWREN RTCSYNC HALFSEC
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-21:
File Name CRCCON1 CRCCON2 CRCXORL CRCXORH CRCDATL CRCDATH CRCWDATL CRCWDATH Legend: Addr 0640 0642 0644 0646 0648 064A 064C 064E
REGISTER
CRCEN CSIDL CRCGO PLEN4 LENDIAN PLEN3 PLEN2 PLEN1 PLEN0 Resets 0000 0000 0000 0000 xxxx xxxx xxxx xxxx
VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0
CRCMPT CRCISEL
Data Input Register Word Data Input Register High Word Result Register Word Result Register High Word
2009 Microchip Technology Inc.
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-22:
File Name CMSTAT CVRCON CM1CON CM2CON CM3CON Legend: Addr 0650 0652 0654 065C 0664
COMPARATORS REGISTER
CMIDL CPOL CPOL CPOL C3EVT C2EVT CEVT CEVT CEVT C1EVT COUT COUT COUT CVROE CVRR CVRSS CREF CREF CREF CVR3 C3OUT CVR2 C2OUT CVR1 CCH1 CCH1 CCH1 C1OUT CVR0 CCH0 CCH0 CCH0 Resets 0000 0000 0000 0000 0000
CVREFP CVREFM1 CVREFM0 CVREN
EVPOL1 EVPOL0 EVPOL1 EVPOL0 EVPOL1 EVPOL0
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-23:
File Name RPINR0 RPINR1 RPINR3 RPINR4 RPINR7 RPINR8 RPINR9 RPINR11 RPINR18 RPINR19 RPINR20 RPINR21 RPINR22 RPINR23 RPOR0 Addr 0680 0682 0686 0688 068E 0690 0692 0696 06A4 06A6 06A8 06AA 06AC 06AE 06C0 06C2 06C4 06C6 06C8 06CA 06CC 06CE 06D0 06D2 06D4 06D6 06D8
PERIPHERAL SELECT REGISTER
INT1R4 T3CKR4 T5CKR4 IC2R4 IC4R4 OCFBR4 U1CTSR4 U2CTSR4 SCK1R4 SCK2R4 RP1R4 RP3R4 RP5R4 RP7R4 RP9R4 RP11R4 RP13R4 RP15R4 RP17R4 RP19R4 RP21R4 RP23R4 RP25R4 INT1R3 T3CKR3 T5CKR3 IC2R3 IC4R3 OCFBR3 U1CTSR3 U2CTSR3 SCK1R3 SCK2R3 RP1R3 RP3R3 RP5R3 RP7R3 RP9R3 RP11R3 RP13R3 RP15R3 RP17R3 RP19R3 RP21R3 RP23R3 RP25R3 INT1R2 T3CKR2 T5CKR2 IC2R2 IC4R2 OCFBR2 U1CTSR2 U2CTSR2 SCK1R2 SCK2R2 RP1R2 RP3R2 RP5R2 RP7R2 RP9R2 RP11R2 RP13R2 RP15R2 RP17R2 RP19R2 RP21R2 RP23R2 RP25R2 INT1R1 T3CKR1 T5CKR1 IC2R1 IC4R1 OCFBR1 U1CTSR1 U2CTSR1 SCK1R1 SCK2R1 RP1R1 RP3R1 RP5R1 RP7R1 RP9R1 RP11R1 RP13R1 RP15R1 RP17R1 RP19R1 RP21R1 RP23R1 RP25R1 INT1R0 T3CKR0 T5CKR0 IC2R0 IC4R0 OCFBR0 U1CTSR0 U2CTSR0 SCK1R0 SCK2R0 RP1R0 RP3R0 RP5R0 RP7R0 RP9R0 RP11R0 RP13R0 RP15R0 RP17R0 RP19R0 RP21R0 RP23R0 RP25R0 INT2R4 T2CKR4 T4CKR4 IC1R4 IC3R4 IC5R4 OCFAR4 U1RXR4 U2RXR4 SDI1R4 SS1R4 SDI2R4 SS2R4 RP0R4 RP2R4 RP4R4 RP6R4 RP8R4 RP10R4 RP14R4 RP16R4 RP18R4 RP20R4 RP22R4 RP24R4 INT2R3 T2CKR3 T4CKR3 IC1R3 IC3R3 IC5R3 OCFAR3 U1RXR3 U2RXR3 SDI1R3 SS1R3 SDI2R3 SS2R3 RP0R3 RP2R3 RP4R3 RP6R3 RP8R3 RP10R3 RP14R3 RP16R3 RP18R3 RP20R3 RP22R3 RP24R3 INT2R2 T2CKR2 T4CKR2 IC1R2 IC3R2 IC5R2 OCFAR2 U1RXR2 U2RXR2 SDI1R2 SS1R2 SDI2R2 SS2R2 RP0R2 RP2R2 RP4R2 RP6R2 RP8R2 RP10R2 RP14R2 RP16R2 RP18R2 RP20R2 RP22R2 RP24R2 INT2R1 T2CKR1 T4CKR1 IC1R1 IC3R1 IC5R1 OCFAR1 U1RXR1 U2RXR1 SDI1R1 SS1R1 SDI2R1 SS2R1 RP0R1 RP2R1 RP4R1 RP6R1 RP8R1 RP10R1 RP14R1 RP16R1 RP18R1 RP20R1 RP22R1 RP24R1 INT2R0 T2CKR0 T4CKR0 IC1R0 IC3R0 IC5R0 OCFAR0 U1RXR0 U2RXR0 SDI1R0 SS1R0 SDI2R0 SS2R0 RP0R0 RP2R0 RP4R0 RP6R0 RP8R0 RP10R0 RP14R0 RP16R0 RP18R0 RP20R0 RP22R0 RP24R0 Resets 1F00 001F 1F1F 1F1F 1F1F 1F1F 001F 1F1F 1F1F 1F1F 1F1F 001F 1F1F 001F 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
2009 Microchip Technology Inc.
PIC24FJ64GB004 FAMILY
DS39940C-page
RPOR1 RPOR2 RPOR3 RPOR4 RPOR5 RPOR6 RPOR7 RPOR8(1) RPOR9(1) RPOR10(1) RPOR11(1) RPOR12(1) Legend: Note
unimplemented, read `0'. Reset values shown hexadecimal. Registers unimplemented 28-pin devices; read `0'.
TABLE 4-24:
File Name RCON OSCCON CLKDIV OSCTUN REFOCON Legend: Note Addr 0740 0742 0744 0748 074E
SYSTEM REGISTER
TRAPR ROEN IOPUWR COSC2 DOZE2 COSC1 DOZE1 ROSSLP COSC0 DOZE0 ROSEL DOZEN RODIV3 DPSLP NOSC2 RCDIV2 RODIV2 NOSC1 RCDIV1 RODIV1 PMSLP NOSC0 RCDIV0 RODIV0 EXTR CLKLOCK CPDIV1 IOLOCK CPDIV0 SWDTEN LOCK PLLEN TUN5 WDTO TUN4 SLEEP TUN3 IDLE TUN2 TUN1 OSWEN TUN0 Resets Note Note 0100 0000 0000
DS39940C-page
PIC24FJ64GB004 FAMILY
POSCEN SOSCEN
unimplemented, read `0'. Reset values shown hexadecimal. Reset value RCON register dependent type Reset event. Section "Resets" more information. Reset value OSCCON register dependent both type Reset event device configuration. Section "Oscillator Configuration" more information.
TABLE 4-25:
File Name DSCON DSWAKE DSGPR0 DSGPR1 Legend: Note Addr 075A 075C 075E
DEEP SLEEP REGISTER
DSEN DSINT0 DSFLT DSWDT DSRTC DSMCLR Resets(1) 0000 0001 0000 0000
DSBOR RELEASE DSPOR
Deep Sleep General Purpose Register Deep Sleep General Purpose Register
2009 Microchip Technology Inc.
unimplemented, read `0'. Reset values shown hexadecimal. Deep Sleep registers only reset event.
TABLE 4-26:
File Name NVMCON NVMKEY Legend: Note Addr 0760 0766
REGISTER
WREN WRERR ERASE Resets
NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1) 0000
NVMKEY Register<7:0>
unimplemented, read `0'. Reset values shown hexadecimal. Reset value shown only. Value other Reset states dependent state memory write erase operations time Reset.
2009 Microchip Technology Inc.
TABLE 4-27:
File Name PMD1 PMD2 PMD3 PMD4 Legend: Addr 0770 0772 0774 0776
REGISTER
T5MD T4MD T3MD T2MD IC5MD T1MD IC4MD IC3MD IC2MD IC1MD I2C1MD CRCMD U2MD UPWMMD U1MD SPI2MD OC5MD SPI1MD OC4MD OC3MD OC2MD I2C2MD LVDMD ADC1MD OC1MD USB1MD Resets 0000 0000 0000 0000
CMPMD RTCCMD PMPMD
REFOMD CTMUMD
unimplemented, read `0'. Reset values shown hexadecimal.
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4.2.5 SOFTWARE STACK
addition working register, register PIC24F devices also used Software Stack Pointer. pointer always points first available free word grows from lower higher addresses. predecrements stack pops post-increments stack pushes, shown Figure 4-4. Note that push during CALL instruction, zero-extended before push, ensuring that always clear. Note: push during exception processing will concatenate register prior push.
Interfacing Program Data Memory Spaces
PIC24F architecture uses 24-bit wide program space 16-bit wide data space. architecture also modified Harvard scheme, meaning that data also present program space. this data successfully, must accessed that preserves alignment information both spaces. Aside from normal execution, PIC24F architecture provides methods which program space accessed during operation: Using table instructions access individual bytes words anywhere program space Remapping portion program space into data space (program space visibility) Table instructions allow application read write small areas program memory. This makes method ideal accessing data tables that need updated from time time. also allows access bytes program word. remapping method allows application access large block data read-only basis, which ideal look-ups from large table static data; only access least significant word program word.
Stack Pointer Limit Value (SPLIM) register, associated with Stack Pointer, sets upper address boundary stack. SPLIM uninitialized Reset. case Stack Pointer, SPLIM<0> forced because stack operations must word-aligned. Whenever generated using source destination pointer, resulting address compared with value SPLIM. contents Stack Pointer (W15) SPLIM register equal, push operation performed, stack error trap will occur. stack error trap will occur subsequent push operation. Thus, example, desirable cause stack error trap when stack grows beyond address 2000h RAM, initialize SPLIM with value, 1FFEh. Similarly, Stack Pointer underflow (stack error) trap generated when Stack Pointer address found less than 0800h. This prevents stack from interfering with Special Function Register (SFR) space. write SPLIM register should immediately followed indirect read operation using W15.
4.3.1
ADDRESSING PROGRAM SPACE
Since address ranges data program spaces bits, respectively, method needed create 23-bit 24-bit program address from 16-bit data registers. solution depends interface method used. table operations, 8-bit Table Memory Page Address (TBLPAG) register used define word region within program space. This concatenated with 16-bit arrive full 24-bit program space address. this format, Most Significant TBLPAG used determine operation occurs user memory (TBLPAG<7> configuration memory (TBLPAG<7> remapping operations, 8-bit Program Space Visibility Page Address (PSVPAG) register used define word page program space. When Most Significant `1', PSVPAG concatenated with lower bits form 23-bit program space address. Unlike table operations, this limits remapping operations strictly user memory area. Table 4-28 Figure show program created table operations remapping accesses from data Here, P<23:0> refers program space word, whereas D<15:0> refers data space word.
FIGURE 4-4:
0000h
CALL STACK FRAME
Stack Grows Towards Higher Address
PC<15:0> 000000000 PC<22:16> <Free Word>
(before CALL) (after CALL) [-W15] PUSH [W15++]
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TABLE 4-28: PROGRAM SPACE ADDRESS CONSTRUCTION
Access Space User User Configuration Program Space Visibility (Block Remap/Read) Note User Program Space Address <23> TBLPAG<7:0> 0xxx xxxx TBLPAG<7:0> 1xxx xxxx PSVPAG<7:0> xxxx xxxx <22:16> <15> PC<22:1> xxxx xxxx xxxx xxxx xxx0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<14:0>(1) xxxx xxxx xxxx <14:1> Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write)
Data EA<15> always this case, used calculating program space address. address PSVPAG<0>.
FIGURE 4-5:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter Bits
Table Operations(2)
TBLPAG Bits Bits Bits
Select Program Space Visibility(1) (Remapping) PSVPAG Bits
Bits Bits
User/Configuration Space Select
Byte Select
Note program space addresses always fixed order maintain word alignment data program data spaces. Table operations required word-aligned. Table read operations permitted configuration memory space.
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4.3.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS
TBLRDH (Table Read High): Word mode, maps entire upper word program address (P<23:16>) data address. Note that D<15:8>, `phantom' byte, will always `0'. Byte mode, maps upper lower byte program word D<7:0> data address, above. Note that data will always when upper `phantom' byte selected (byte select
TBLRDL TBLWTL instructions offer direct method reading writing lower word address within program space without going through data space. TBLRDH TBLWTH instructions only method read write upper bits program space word data. incremented each successive 24-bit program word. This allows program memory addresses directly data space addresses. Program memory thus regarded two, 16-bit word-wide address spaces, residing side side, each with same address range. TBLRDL TBLWTL access space which contains least significant data word, TBLRDH TBLWTH access space which contains upper data byte. table instructions provided move byte word-sized (16-bit) data from program space. Both function either byte word operations. TBLRDL (Table Read Low): Word mode, maps lower word program space location (P<15:0>) data address (D<15:0>). Byte mode, either upper lower byte lower program word mapped lower byte data address. upper byte selected when byte select `1'; lower byte selected when `0'.
similar fashion, table instructions, TBLWTH TBLWTL, used write individual bytes words program space address. details their operation explained Section "Flash Program Memory". table operations, area program memory space accessed determined Table Memory Page Address register (TBLPAG). TBLPAG covers entire program memory space device, including user configuration spaces. When TBLPAG<7> table page located user memory space. When TBLPAG<7> page located configuration space. Note: Only table read operations will execute configuration memory space, only then, implemented areas, such Device Table write operations allowed.
FIGURE 4-6:
TBLPAG
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
Data EA<15:0> 000000h 00000000 020000h 030000h 00000000 00000000 00000000 `Phantom' Byte
TBLRDH.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.W address table operation determined data within page defined TBLPAG register. Only read operations shown; write operations also valid user memory area.
800000h
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4.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY
24-bit program word used contain data. upper bits program space locations used data should programmed with `1111 1111' `0000 0000' force NOP. This prevents possible issues should area code ever accidentally executed. Note: access temporarily disabled during table reads/writes.
upper Kbytes data space optionally mapped into word page program space. This provides transparent access stored constant data from data space without need special instructions (i.e., TBLRDL/H). Program space access through data space occurs Most Significant (MSb) data space program space visibility enabled setting Control register (CORCON<2>). location program memory space mapped into data space determined Program Space Visibility Page Address register (PSVPAG). This 8-bit register defines possible pages words program space. effect, PSVPAG functions upper bits program memory address, with bits functioning lower bits. Note that incrementing each program memory word, lower bits data space addresses directly lower bits corresponding program space addresses. Data reads this area additional cycle instruction being executed, since program memory fetches required. Although each data space address, 8000h higher, maps directly into corresponding program memory address (see Figure 4-7), only lower bits
operations that executed outside REPEAT loop, MOV.D instructions will require instruction cycle addition specified execution time. other instructions will require instruction cycles addition specified execution time. operations that which executed inside REPEAT loop, there will some instances that require instruction cycles addition specified execution time instruction: Execution first iteration Execution last iteration Execution prior exiting loop interrupt Execution upon re-entering loop after interrupt serviced other iteration REPEAT loop will allow instruction accessing data, using PSV, execute single cycle.
FIGURE 4-7:
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> EA<15>
Program Space
PSVPAG 000000h 010000h 018000h data page designated PSVPAG mapped into upper half data memory space.
Data Space
0000h Data EA<14:0>
8000h
Area .while lower bits specify exact address within area. This corresponds exactly same lower bits actual program space address.
FFFFh
800000h
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NOTES:
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Note:
FLASH PROGRAM MEMORY
This data sheet summarizes features this group PIC24F devices. intended comprehensive reference source. more information, refer "PIC24F Family Reference Manual", Section "Program Memory" (DS39715).
RTSP accomplished using TBLRD (table read) TBLWT (table write) instructions. With RTSP, user write program memory data blocks instructions (192 bytes) time erase program memory blocks instructions (1536 bytes) time.
Table Instructions Flash Programming
PIC24FJ64GB004 family devices contains internal Flash program memory storing executing application code. memory readable, writable erasable when operating with over 2.35V. regulator disabled, VDDCORE must over 2.25V.) programmed four ways: In-Circuit Serial Programming(ICSPTM) Run-Time Self-Programming (RTSP) JTAG Enhanced In-Circuit Serial Programming (Enhanced ICSP)
Regardless method used, programming Flash memory done with table read table write instructions. These allow direct read write access program memory space from data memory while device normal operating mode. 24-bit target address program memory formed using TBLPAG<7:0> bits Effective Address (EA) from register specified table instruction, shown Figure 5-1. TBLRDL TBLWTL instructions used read write bits<15:0> program memory. TBLRDL TBLWTL access program memory both Word Byte modes. TBLRDH TBLWTH instructions used read write bits<23:16> program memory. TBLRDH TBLWTH also access program memory Word Byte mode.
ICSP allows PIC24FJ64GB004 family device serially programmed while application circuit. This simply done with lines programming clock programming data (which named PGECx PGEDx, respectively), three other lines power (VDD), ground (VSS) Master Clear (MCLR). This allows customers manufacture boards with unprogrammed devices then program microcontroller just before shipping product. This also allows most recent firmware custom firmware programmed.
FIGURE 5-1:
ADDRESSING TABLE REGISTERS
Bits Using Program Counter Program Counter
Working Using Table Instruction TBLPAG Bits Bits
User/Configuration Space Select
24-Bit
Byte Select
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RTSP Operation JTAG Operation
PIC24F Flash program memory array organized into rows instructions bytes. RTSP allows user erase blocks eight rows (512 instructions) time program time. also possible program single words. 8-row erase blocks single write blocks edge-aligned, from beginning program memory, boundaries 1536 bytes bytes, respectively. When data written program memory using TBLWT instructions, data written directly memory. Instead, data written using table writes stored holding latches until programming sequence executed. number TBLWT instructions executed write will successfully performed. However, TBLWT instructions required write full memory. ensure that data corrupted during write, unused addresses should programmed with FFFFFFh. This because holding latches reset unknown state, addresses left Reset state, they overwrite locations rows which were rewritten. basic sequence RTSP programming Table Pointer, then series TBLWT instructions load buffers. Programming performed setting control bits NVMCON register. Data loaded order holding registers written multiple times before performing write operation. Subsequent writes, however, will wipe previous writes. Note: Writing location multiple times without erasing recommended. PIC24F family supports JTAG programming boundary scan. Boundary scan improve manufacturing process verifying connectivity. Programming performed with industry standard JTAG programmers supporting Serial Vector Format (SVF).
Enhanced In-Circuit Serial Programming
Enhanced In-Circuit Serial Programming uses on-board bootloader, known program executive, manage programming process. Using data frame format, program executive erase, program verify program memory. more information Enhanced ICSP, device programming specification.
Control Registers
There SFRs used read write program Flash memory: NVMCON NVMKEY. NVMCON register (Register 5-1) controls which blocks erased, which memory type programmed when programming cycle starts. NVMKEY write-only register that used write protection. start programming erase sequence, user must consecutively write NVMKEY register. Refer Section "Programming Operations" further details.
Programming Operations
table write operations single-word writes instruction cycles), because only buffers written. programming cycle required programming each row.
complete programming sequence necessary programming erasing internal Flash RTSP mode. During programming erase operation, processor stalls (waits) until operation finished. Setting (NVMCON<15>) starts operation automatically cleared when operation finished.
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REGISTER 5-1:
R/SO-0, HC(1) Legend: Readable Value Only Writable Hardware Clearable cleared R/W-0(1) ERASE R/W-0(1) NVMOP3(2) R/W-0(1) NVMOP2(2) R/W-0(1) NVMOP1(2)
NVMCON: FLASH MEMORY CONTROL REGISTER
R/W-0, HS(1) WRERR R/W-0(1) NVMOP0(2) Hardware Settable unknown WREN
R/W-0(1)
Unimplemented bit, read
Write Control bit(1) Initiates Flash memory program erase operation. operation self-timed cleared hardware once operation complete. Program erase operation complete inactive WREN: Write Enable bit(1) Enable Flash program/erase operations Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag bit(1) improper program erase sequence attempt, termination occurred (bit automatically attempt bit) program erase operation completed normally Unimplemented: Read ERASE: Erase/Program Enable bit(1) Perform erase operation specified NVMOP<3:0> next command Perform program operation specified NVMOP<3:0> next command Unimplemented: Read NVMOP<3:0>: Operation Select bits(1,2) 1111 Memory bulk erase operation (ERASE operation (ERASE 0)(3) 0011 Memory word program operation (ERASE operation (ERASE 0010 Memory page erase operation (ERASE operation (ERASE 0001 Memory program operation (ERASE operation (ERASE These bits only reset POR. other combinations NVMOP<3:0> unimplemented. Available ICSPmode only. Refer device programming specification.
12-7
Note
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5.6.1 PROGRAMMING ALGORITHM FLASH PROGRAM MEMORY
user program Flash program memory time. this, necessary erase 8-row erase block containing desired row. general process follows: Read eight rows program memory (512 instructions) store data RAM. Update program data with desired data. Erase block (see Example 5-1): NVMOP bits (NVMCON<3:0>) `0010' configure block erase. ERASE (NVMCON<6>) WREN (NVMCON<14>) bits. Write starting address block erased into TBLPAG registers. Write NVMKEY. Write NVMKEY. (NVMCON<15>). erase cycle begins stalls duration erase cycle. When erase done, cleared automatically. Write first instructions from data into program memory buffers (see Example 5-1). Write program block Flash memory: NVMOP bits `0001' configure programming. Clear ERASE WREN bit. Write NVMKEY. Write NVMKEY. bit. programming cycle begins stalls duration write cycle. When write Flash memory done, cleared automatically. Repeat steps using next available instructions from block data incrementing value TBLPAG, until instructions written back Flash memory.
protection against accidental operations, write initiate sequence NVMKEY must used allow erase program operation proceed. After programming command been executed, user must wait programming time until programming complete. instructions following start programming sequence should NOPs, shown Example 5-5.
EXAMPLE 5-1:
ERASING PROGRAM MEMORY BLOCK ASSEMBLY LANGUAGE CODE
Initialize NVMCON
NVMCON block erase operation #0x4042, NVMCON Init pointer ERASED #tblpage(PROG_ADDR), TBLPAG #tbloffset(PROG_ADDR), TBLWTL [W0] DISI BSET #0x55, NVMKEY #0xAA, NVMKEY NVMCON,
Initialize Page Boundary Initialize in-page EA[15:0] pointer base address erase block Block interrupts with priority next instructions Write Write Start erase sequence Insert NOPs after erase command asserted
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EXAMPLE 5-2: ERASING PROGRAM MEMORY BLOCK LANGUAGE CODE
Address write
example using MPLAB
unsigned long progAddr 0xXXXXXX; unsigned offset;
//Set pointer first memory location written TBLPAG progAddr>>16; Initialize Page Boundary offset progAddr 0xFFFF; Initialize lower word address _builtin_tblwtl(offset, 0x0000); base address erase block with dummy latch write Initialize NVMCON Block interrupts with priority next instructions function perform unlock sequence
NVMCON 0x4042; asm("DISI #5"); _builtin_write_NVM();
EXAMPLE 5-3:
LOADING WRITE BUFFERS ASSEMBLY LANGUAGE CODE
NVMCON programming operations #0x4001, NVMCON Initialize NVMCON pointer first program memory location written program memory selected, writes enabled #0x0000, TBLPAG Initialize Page Boundary #0x6000, example program memory address Perform TBLWT instructions write latches 0th_program_word #LOW_WORD_0, #HIGH_BYTE_0, TBLWTL [W0] Write word into program latch TBLWTH [W0++] Write high byte into program latch 1st_program_word #LOW_WORD_1, #HIGH_BYTE_1, TBLWTL [W0] Write word into program latch TBLWTH [W0++] Write high byte into program latch 2nd_program_word #LOW_WORD_2, #HIGH_BYTE_2, TBLWTL [W0] Write word into program latch TBLWTH [W0++] Write high byte into program latch 63rd_program_word #LOW_WORD_31, #HIGH_BYTE_31, TBLWTL [W0] Write word into program latch TBLWTH [W0] Write high byte into program latch
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EXAMPLE 5-4: LOADING WRITE BUFFERS LANGUAGE CODE
example using MPLAB #define NUM_INSTRUCTION_PER_ROW unsigned offset; unsigned unsigned long progAddr 0xXXXXXX; unsigned //Set NVMCON programming NVMCON 0x4001;
Address write Buffer data write
Initialize NVMCON
//Set pointer first memory location written TBLPAG progAddr>>16; Initialize Page Boundary offset progAddr 0xFFFF; Initialize lower word address //Perform TBLWT instructions write necessary number latches for(i=0; 2*NUM_INSTRUCTION_PER_ROW; i++) _builtin_tblwtl(offset, progData[i++]); Write address word _builtin_tblwth(offset, progData[i]); Write upper byte offset offset Increment address
EXAMPLE 5-5:
DISI BSET BTSC
INITIATING PROGRAMMING SEQUENCE ASSEMBLY LANGUAGE CODE
Block interrupts with priority next instructions Write Write Start erase sequence #0x55, NVMKEY #0xAA, NVMKEY NVMCON,
NVMCON,
wait completed
EXAMPLE 5-6:
asm("DISI #5");
INITIATING PROGRAMMING SEQUENCE LANGUAGE CODE
Block interrupts with priority next instructions Perform unlock sequence
example using MPLAB
_builtin_write_NVM();
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5.6.2 PROGRAMMING SINGLE WORD FLASH PROGRAM MEMORY
Flash location been erased, programmed using table write instructions write instruction word (24-bit) into write latch. TBLPAG register loaded with Most Significant Bytes Flash address. TBLWTL TBLWTH instructions write desired data into write latches specify lower bits program memory address write configure NVMCON register word write, NVMOP bits (NVMCON<3:0>) `0011'. write performed executing unlock sequence setting (see Example 5-7).
EXAMPLE 5-7:
PROGRAMMING SINGLE WORD FLASH PROGRAM MEMORY ASSEMBLY LANGUAGE CODE
Setup pointer data Program Memory #tblpage(PROG_ADDR), TBLPAG ;Initialize Page Boundary #tbloffset(PROG_ADDR), ;Initialize register with program memory address TBLWTL TBLWTH #LOW_WORD, #HIGH_BYTE, [W0] [W0++] Write word into program latch Write high byte into program latch
Setup NVMCON programming word data Program Memory #0x4003, NVMCON NVMOP bits 0011 DISI BSET #0x55, NVMKEY #0xAA, NVMKEY NVMCON, Disable interrupts while sequence written Write sequence
Start write cycle Insert NOPs after erase Command asserted
EXAMPLE 5-8:
PROGRAMMING SINGLE WORD FLASH PROGRAM MEMORY LANGUAGE CODE
example using MPLAB unsigned unsigned unsigned unsigned offset; long progAddr 0xXXXXXX; progDataL 0xXXXX; char progDataH 0xXX;
Address word program Data program lower word Data program upper byte
//Set NVMCON word programming NVMCON 0x4003;
Initialize NVMCON
//Set pointer first memory location written TBLPAG progAddr>>16; Initialize Page Boundary offset progAddr 0xFFFF; Initialize lower word address //Perform TBLWT instructions write latches _builtin_tblwtl(offset, progDataL); _builtin_tblwth(offset, progDataH); asm("DISI #5"); _builtin_write_NVM();
Write address word Write upper byte Block interrupts with priority next instructions function perform unlock sequence
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NOTES:
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Note:
RESETS
This data sheet summarizes features this group PIC24F devices. intended comprehensive reference source. more information, refer "PIC24F Family Reference Manual", Section "Reset" (DS39712).
active source Reset will make SYSRST signal active. Many registers associated with peripherals forced known Reset state. Most registers unaffected Reset; their status unknown unchanged other Resets. Note: Refer specific peripheral section this manual register Reset states.
Reset module combines Reset sources controls device Master Reset Signal, SYSRST. following list device Reset sources: POR: Power-on Reset MCLR: Reset SWR: RESET Instruction WDT: Watchdog Timer Reset BOR: Brown-out Reset Configuration Mismatch Reset TRAPR: Trap Conflict Reset IOPUWR: Illegal Opcode Reset UWR: Uninitialized Register Reset
types device Reset will corresponding status RCON register indicate type Reset (see Register 6-1). Power-on Reset will clear bits, except bits (RCON<1:0>), which set. user clear time during code execution. RCON bits only serve status bits. Setting particular Reset status software will cause device Reset occur. RCON register also other bits associated with Watchdog Timer device power-saving states. function these bits discussed other sections this data sheet. Note: status bits RCON register should cleared after they read that next RCON register value after device Reset will meaningful.
simplified block diagram Reset module shown Figure 6-1.
FIGURE 6-1:
RESET SYSTEM BLOCK DIAGRAM
RESET Instruction Glitch Filter
MCLR Module Sleep Idle Rise Detect Brown-out Reset SYSRST
Enable Voltage Regulator Trap Conflict Illegal Opcode Configuration Mismatch Uninitialized Register
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REGISTER 6-1:
R/W-0, TRAPR R/W-0, EXTR
RCON: RESET CONTROL REGISTER(1)
R/CO-0, DPSLP R/W-0, R/W-0 PMSLP R/W-1,
R/W-0, IOPUWR
R/W-0,
R/W-0 SWDTEN(2)
R/W-0, WDTO
R/W-0, SLEEP
R/W-0, IDLE
R/W-1,
Legend: Readable Value
Clear Only Writable
Hardware Settable Unimplemented bit, read cleared unknown
13-11
TRAPR: Trap Reset Flag Trap Conflict Reset occurred Trap Conflict Reset occurred IOPUWR: Illegal Opcode Uninitialized Access Reset Flag illegal opcode detection, illegal address mode uninitialized register used Address Pointer caused Reset illegal opcode uninitialized Reset occurred Unimplemented: Read DPSLP: Deep Sleep Mode Flag Deep Sleep occurred Deep Sleep occurred Configuration Word Mismatch Reset Flag Configuration Word Mismatch Reset occurred Configuration Word Mismatch Reset occurred PMSLP: Program Memory Power During Sleep Program memory bias voltage remains powered during Sleep Program memory bias voltage powered down during Sleep voltage regulator enters Standby mode EXTR: External Reset (MCLR) Master Clear (pin) Reset occurred Master Clear (pin) Reset occurred SWR: Software Reset (Instruction) Flag RESET instruction been executed RESET instruction been executed SWDTEN: Software Enable/Disable bit(2) enabled disabled WDTO: Watchdog Timer Time-out Flag time-out occurred time-out occurred SLEEP: Wake From Sleep Flag Device been Sleep mode Device been Sleep mode IDLE: Wake-up From Idle Flag Device been Idle mode Device been Idle mode Reset status bits cleared software. Setting these bits software does cause device Reset. FWDTEN Configuration (unprogrammed), always enabled, regardless SWDTEN setting.
Note
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REGISTER 6-1:
RCON: RESET CONTROL REGISTER(1) (CONTINUED)
BOR: Brown-out Reset Flag Brown-out Reset occurred. Note that also after Power-on Reset. Brown-out Reset occurred POR: Power-on Reset Flag Power-on Reset occurred Power-on Reset occurred Reset status bits cleared software. Setting these bits software does cause device Reset. FWDTEN Configuration (unprogrammed), always enabled, regardless SWDTEN setting.
Note
TABLE 6-1:
RESET FLAG OPERATION
Setting Event Trap Conflict Event Illegal Opcode Uninitialized Register Access Configuration Mismatch Reset MCLR Reset RESET Instruction Time-out PWRSAV #SLEEP Instruction PWRSAV #IDLE Instruction POR, PWRSAV #SLEEP instruction with DSCON <DSEN> Clearing Event PWRSAV Instruction,
Flag TRAPR (RCON<15>) IOPUWR (RCON<14>) (RCON<9>) EXTR (RCON<7>) (RCON<6>) WDTO (RCON<4>) SLEEP (RCON<3>) IDLE (RCON<2>) (RCON<1>) (RCON<0>) DPSLP (RCON<10>) Note:
Reset flag bits cleared user software.
Clock Source Selection Reset
Device Reset Times
clock switching enabled, system clock source device Reset chosen shown Table 6-2. clock switching disabled, system clock source always selected according oscillator Configuration bits. Refer Section "Oscillator Configuration" further details.
Reset times various types device Reset summarized Table 6-3. Note that System Reset signal, SYSRST, released after PWRT delay times expire. time which device actually begins execute code will also depend system oscillator delays, which include Oscillator Start-up Timer (OST) lock time. lock times occur parallel with applicable SYSRST delay times. FSCM delay determines time which
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