64/80/100-Pin, 16-Bit Flash Microcontrollers with On-The-Go (OTG)
|
|
|
Top Searches for this datasheet
PIC24FJ256GB110 Family Data Sheet
64/80/100-Pin, 16-Bit Flash Microcontrollers with On-The-Go (OTG)
2008 Microchip Technology Inc.
DS39897B
Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
Code protection constantly evolving. Microchip committed continuously improving code protection features products. Attempts break Microchip's code protection feature violation Digital Millennium Copyright Act. such acts allow unauthorized access your software other copyrighted work, have right relief under that Act.
Information contained this publication regarding device applications like provided only your convenience superseded updates. your responsibility ensure that your application meets with your specifications. MICROCHIP MAKES REPRESENTATIONS WARRANTIES KIND WHETHER EXPRESS IMPLIED, WRITTEN ORAL, STATUTORY OTHERWISE, RELATED INFORMATION, INCLUDING LIMITED CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY FITNESS PURPOSE. Microchip disclaims liability arising from this information use. Microchip devices life support and/or safety applications entirely buyer's risk, buyer agrees defend, indemnify hold harmless Microchip from damages, claims, suits, expenses resulting from such use. licenses conveyed, implicitly otherwise, under Microchip intellectual property rights.
Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, MATE, rfPIC SmartShunt registered trademarks Microchip Technology Incorporated U.S.A. other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2008, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
DS39897B-page
2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
64/80/100-Pin, 16-Bit Flash Microcontrollers with On-The-Go (OTG)
Power Management:
On-Chip 2.5V Voltage Regulator Switch between Clock Sources Real Time Idle, Sleep Doze modes with Fast Wake-up Two-Speed Start-up mode: mA/MIPS, 2.0V Typical Sleep mode Current Down Typical Standby Current with Oscillator: 2.0V typical
High-Performance CPU:
Modified Harvard Architecture MIPS Operation Internal Oscillator 17-Bit 17-Bit Single-Cycle Hardware Multiplier 32-Bit 16-Bit Hardware Divider 16-Bit Working Register Array Compiler Optimized Instruction Architecture with Flexible Addressing modes Linear Program Memory Addressing, Mbytes Linear Data Memory Addressing, Kbytes Address Generation Units Separate Read Write Addressing Data Memory
Universal Serial Features:
v2.0 On-The-Go (OTG) Compliant Dual Role Capable either Host Peripheral Low-Speed (1.5 Mb/s) Full-Speed Mb/s) Operation Host mode Full-Speed Operation Device mode High-Precision Internal Voltage Boost Assist Voltage Generation Interface Off-Chip Charge Pump Voltage Generation Supports Endpoints bidirectional): Module location device endpoint buffers On-Chip Transceiver with On-Chip Voltage Regulator Interface Off-Chip Transceiver Supports Control, Interrupt, Isochronous Bulk Transfers On-Chip Pull-up Pull-Down Resistors
Analog Features:
10-Bit, 16-Channel Analog-to-Digital (A/D) Converter ksps: Conversions available Sleep mode Three Analog Comparators with Programmable Input/ Output Configuration Charge Time Measurement Unit (CTMU)
Program Memory (Bytes)
10-Bit (ch)
SRAM (Bytes)
Remappable Peripherals UART w/IrDA® Capture Input Timers 16-Bit Compare/ Output Remappable Pins I2C
Comparators
PMP/PSP
PIC24FJ64GB106 PIC24FJ128GB106 PIC24FJ192GB106 PIC24FJ256GB106 PIC24FJ64GB108 PIC24FJ128GB108 PIC24FJ192GB108 PIC24FJ256GB108 PIC24FJ64GB110 PIC24FJ128GB110 PIC24FJ192GB110 PIC24FJ256GB110
128K 192K 256K 128K 192K 256K 128K 192K 256K
Device
2008 Microchip Technology Inc.
DS39897B-page
USBOTG
CTMU
JTAG
Pins
PIC24FJ256GB110 FAMILY
Peripheral Features:
Peripheral Select: Allows independent mapping many peripherals time Continuous hardware integrity checking safety interlocks prevent unintentional configuration changes available pins (100-pin devices) Three 3-Wire/4-Wire modules (supports Frame modes) with 8-Level FIFO Buffer Three I2Cmodules support Multi-Master/Slave modes 7-Bit/10-Bit Addressing Four UART modules: Supports RS-485, RS-232, LIN/J6202 protocols IrDA® On-chip hardware encoder/decoder IrDA Auto-wake-up Auto-Baud Detect (ABD) 4-level deep FIFO buffer Five 16-Bit Timers/Counters with Programmable Prescaler Nine 16-Bit Capture Inputs, each with Dedicated Time Base Nine 16-Bit Compare/PWM Outputs, each with Dedicated Time Base 8-Bit Parallel Master Port (PMP/PSP): address pins Programmable polarity control lines Hardware Real-Time Clock/Calendar (RTCC): Provides clock, calendar alarm functions Programmable Cyclic Redundancy Check (CRC) Generator External Interrupt Sources
Special Microcontroller Features:
Operating Voltage Range 2.0V 3.6V Self-Reprogrammable under Software Control 5.5V Tolerant Input (digital pins only) Configurable Open-Drain Outputs Digital High-Current Sink/Source mA/18 Selectable Power Management modes: Sleep, Idle Doze modes with fast wake-up Fail-Safe Clock Monitor Operation: Detects clock failure switches on-chip, low-power oscillator On-Chip Regulator Power-on Reset (POR), Power-up Timer (PWRT), Low-Voltage Detect (LVD) Oscillator Start-up Timer (OST) Flexible Watchdog Timer (WDT) with On-Chip. Low-Power Oscillator Reliable Operation In-Circuit Serial Programming(ICSPTM) In-Circuit Debug (ICD) Pins JTAG Boundary Scan Programming Support Brown-out Reset (BOR) Flash Program Memory: 10,000 erase/write cycle endurance (minimum) 20-year data retention minimum Selectable write protection boundary Write protection option Flash Configuration Words
DS39897B-page
2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
Diagram (64-Pin TQFP)
PMD4/CN62/RE4 PMD3/CN61/RE3 PMD2/CN60/RE2 PMD1/CN59/RE1 PMD0/CN58/RE0 VCMPST2/CN69/RF1 VBUSST/VCMPST1/CN68/RF0 ENVREG VCAP/VDDCORE C3INA/CN16/RD7 C3INB/CN15/RD6 PMRD/RP20/CN14/RD5 PMWR/RP25/CN13/RD4 RP22/PMBE/CN52/RD3 DPH/RP23/CN51/RD2 RP24/VCPCON/CN50/RD1
PMD5/CN63/RE5 PMD6/SCL3/CN64/RE6 PMD7/SDA3/CN65/RE7 PMA5/RP21/C1IND/CN8/RG6 RP26/PMA4/C1INC/CN9/RG7 PMA3/RP19/C2IND/CN10/RG8 MCLR RP27/PMA2/C2INC/CN11/RG9 VPIO/C2INA/AN3/CN5/RB3 VMIO/RP13/C2INB/AN2/CN4/RB2 PGEC1/RP1/VREF-/AN1/CN3/RB1
RPI37/SOSCO/C3INC/TICK/ CN0/RC14 SOSCI/C3IND/CN1/RC13 RP11/DMH/CN49/INT0/RD0 RP12/PMCS1/CN56/RD11 RP3/SCL1/PMCS2/CN55/RD10 RP4/DPLN/SDA1/CN54/RD9 RP2/DMLN/RTCC/CN53/RD8 OSCO/CLKO/CN22/RC15 OSCI/CLKI/CN23/RC12 D+/RG2 D-/RG3 VUSB VBUS RP16/USBID/CN71/RF3
PIC24FJXXXGB106
Legend:
represents remappable pins Peripheral Select feature.
2008 Microchip Technology Inc.
TCK/PMA11/AN12/CTED2/CN30/RB12 TDI/PMA10/AN13/CTED1/CN31/RB13 CTPLS/RP14/PMA1/AN14/CN32/RB14 RP29/PMA0/AN15/REFO/CN12/RB15 PMA9/RP10/SDA2/CN17/RF4 PMA8/RP17/SCL2/CN18/RF5
PGEC2/AN6/RP6/CN24/RB6 PGED2/RCV/RP7/AN7/CN25/RB7 AVDD AVSS RP8/AN8/CN26/RB8 PMA7/RP9/AN9/CN27/RB9 TMS/PMA13/AN10/CVREF/CN28/RB10 TDO/AN11/PMA12/CN29/RB11
DS39897B-page
PIC24FJ256GB110 FAMILY
Diagram (80-Pin TQFP)
PMD1/CN59/RE1 PMD0/CN58/RE0 CN77/RG0 CN78/RG1 VCMPST2/CN69/RF1 VBUSST/VCMPST1/CN68/RF0
PMRD/RP20/CN14/RD5 PMWR/RP25/CN13/RD4 CN19/RD13 RPI42/CN57/RD12
VCAP/VDDCORE C3INA/CN16/RD7 C3INB/CN15/RD6
RP22/PMBE/CN52/RD3 DPH/RP23/CN51/RD2 RP24/VCPCON/CN50/RD1
PMD4/CN62/RE4 PMD3/CN61/RE3
PMD2/CN60/RE2
ENVREG
PMD5/CN63/RE5 PMD6/SCL3/CN64/RE6 PMD7/SDA3/CN65/RE7 RPI38/CN45/RC1 RPI40/CN47/RC3 PMA5/RP21/C1IND/CN8/RG6 RP26/PMA4/C1INC/CN9/RG7 PMA3/RP19/C2IND/CN10/RG8 MCLR RP27/PMA2/C2INC/CN11/RG9 TMS/RPI33/CN66/RE8 TDO/RPI34/CN67/RE9 VPIO/C2INA/AN3/CN5/RB3 VMIO/RP13/C2INB/AN2/CN4/RB2 PGEC1/RP1/AN1/CN3/RB1 PGED1/RP0/AN0/CN2/RB0
RPI37/SOSCO/C3INC/T1CK/CN0/RC14 SOSCI/C3IND/CN1/RC13 RP11/DMH/CN49/INT0/RD0 RP12/PMCS1/CN56/RD11 RP3/PMCS2/SCL1/CN55/RD10 RP4/DPLN/SDA1/CN54/RD9 RP2/DMLN/RTCC/CN53/RD8 RPI35/SDA2/CN44/RA15 RPI36/SCL2/CN43/RA14 OSCO/CLKO/CN22/RC15 OSCI/CLKI/CN23/RC12 D+/RG2 D-/RG3 VUSB VBUS RP15/CN74/RF8 RP30/CN70/RF2 RP16/USBID/CN71/RF3
PIC24FJXXXGB108
PGED2/RCV/RP7/AN7/CN25/RB7
AN11/PMA12/CN29/RB11
AVSS RP8/AN8/CN26/RB8
RP9/AN9/CN27/RB9
RP5/CN21/RD15
AVDD
RP10/PMA9/CN17/RF4
PMA6/VREF+/CN42/RA10
TCK/AN12/CTED2/PMA11/CN30/RB12
TDI/AN13/CTED1/PMA10/CN31/RB13
Legend:
RPIn represent remappable pins Peripheral Select feature.
DS39897B-page
CTPLS/RP14/PMA1/AN14/CN32/RB14
RP29/PMA0/AN15/REFO/CN12/RB15 RPI43/CN20/RD14
PGEC2/AN6/RP6/CN24/RB6
PMA7/VREF-/CN41/RA9
AN10/CVREF/PMA13/CN28/RB10
RP17/PMA8/CN18/RF5
2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
Diagram (100-Pin TQFP)
PMD2/CN60/RE2 CN80/RG13 CN79/RG12 CN81/RG14 PMD1/CN59/RE1 PMD0/CN58/RE0 CN40/RA7 CN39/RA6 CN77/RG0 CN78/RG1 VCMPST2/CN69/RF1 VBUSST/VCMPST1/CN68/RF0 ENVREG VCAP/VDDCORE C3INA/CN16/RD7 C3INB/CN15/RD6 PMRD/RP20/CN14/RD5 PMWR/RP25/CN13/RD4 CN19/RD13 RPI42/CN57/RD12 RP22/PMBE/CN52/RD3 DPH/RP23/CN51/RD2 RP24/VCPCON/CN50/RD1
PMD4/CN62/RE4 PMD3/CN61/RE3
CN82/RG15 PMD5/CN63/RE5 PMD6/SCL3/CN64/RE6 PMD7/SDA3/CN65/RE7 RPI38/CN45/RC1 RPI39/CN46/RC2 RPI40/CN47/RC3 RPI41/CN48/RC4 PMA5/RP21/C1IND/CN8/RG6 RP26/PMA4/C1INC/CN9/RG7 RP19/PMA3/C2IND/CN10/RG8 MCLR RP27/PMA2/C2INC/CN11/RG9 TMS/CN33/RA0 RPI33/CN66/RE8 RPI34/CN67/RE9 VPIO/C2INA/AN3/CN5/RB3 VMIO/RP13/C2INB/AN2/CN4/RB2 PGEC1/RP1/AN1/CN3/RB1 PGED1/RP0/AN0/CN2/RB0
RPI37/SOSCO/C3INC/T1CK/ CN0/RC14 SOSCI/C3IND/CN1/RC13 RP11/DMH/CN49/INT0/RD0 RP12/PMCS1/CN56/RD11 RP3/PMCS2/CN55/RD10 RP4/DPLN/CN54/RD9 RP2/DMLN/RTCC/CN53/RD8 RPI35/SDA1/CN44/RA15 RPI36/SCL1/CN43/RA14 OSCO/CLKO/CN22/RC15 OSCI/CLKI/CN23/RC12 TDO/CN38/RA5 TDI/CN37/RA4 SDA2/CN36/RA3 SCL2/CN35/RA2 D+/RG2 D-/RG3 VUSB VBUS RP15/CN74/RF8 RP30/CN70/RF2 RP16/USBID/CN71/RF3
PIC24FJXXXGB110
PGEC2/AN6/RP6/CN24/RB6 PGED2/RCV/RP7/AN7/CN25/RB7 PMA7/VREF-/CN41/RA9 PMA6/VREF+/CN42/RA10 AVDD AVSS RP8/AN8/CN26/RB8 RP9/AN9/CN27/RB9 AN10/CVREF/PMA13/CN28/RB10 AN11/PMA12/CN29/RB11 TCK/CN34/RA1 RP31/CN76/RF13 RPI32/CN75/RF12 AN12/CTED2/PMA11/CN30/RB12 AN13/CTED1/PMA10/CN31/RB13 CTPLS/RP14/PMA1/AN14/CN32/RB14 RP29/PMA0/AN15/REFO/CN12/RB15
Legend:
RPIn represent remappable pins Peripheral Select feature.
2008 Microchip Technology Inc.
RPI43/CN20/RD14 RP5/CN21/RD15 RP10/PMA9/CN17/RF4 RP17/PMA8/CN18/RF5
DS39897B-page
PIC24FJ256GB110 FAMILY
Table Contents
Device Overview Memory Organization Flash Program Memory Resets Interrupt Controller Oscillator Configuration Power-Saving Features Ports 10.0 Timer1 11.0 Timer2/3 Timer4/5 12.0 Input Capture with Dedicated Timers 13.0 Output Compare with Dedicated Timers 14.0 Serial Peripheral Interface (SPI). 15.0 Inter-Integrated Circuit (I2CTM) 16.0 Universal Asynchronous Receiver Transmitter (UART) 17.0 Universal Serial with On-The-Go Support (USB OTG) 18.0 Parallel Master Port (PMP). 19.0 Real-Time Clock Calendar (RTCC) 20.0 Programmable Cyclic Redundancy Check (CRC) Generator 21.0 10-bit High-Speed Converter. 22.0 Triple Comparator Module. 23.0 Comparator Voltage Reference. 24.0 Charge Time Measurement Unit (CTMU) 25.0 Special Features 26.0 Development Support. 27.0 Instruction Summary 28.0 Electrical Characteristics 29.0 Packaging Information. Appendix Revision History. Index Microchip Site Customer Change Notification Service Customer Support Reader Response Product Identification System.
DS39897B-page
2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
VALUED CUSTOMERS
intention provide valued customers with best documentation possible ensure successful your Microchip products. this end, will continue improve publications better suit your needs. publications will refined enhanced volumes updates introduced. have questions comments regarding this publication, please contact Marketing Communications Department E-mail docerrors@microchip.com Reader Response Form back this data sheet (480) 792-4150. welcome your feedback.
Most Current Data Sheet
obtain most up-to-date version this data sheet, please register Worldwide site http://www.microchip.com determine version data sheet examining literature number found bottom outside corner page. last character literature number version number, (e.g., DS30000A version document DS30000).
Errata
errata sheet, describing minor operational differences from data sheet recommended workarounds, exist current devices. device/documentation issues become known will publish errata sheet. errata will specify revision silicon revision document which applies. determine errata sheet exists particular device, please check with following: Microchip's Worldwide site; http://www.microchip.com Your local Microchip sales office (see last page) When contacting sales office, please specify which device, revision silicon data sheet (include literature number) using.
Customer Notification System
Register site www.microchip.com receive most current information products.
2008 Microchip Technology Inc.
DS39897B-page
PIC24FJ256GB110 FAMILY
NOTES:
DS39897B-page
2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
DEVICE OVERVIEW
This document contains device-specific information following devices: PIC24FJ64GB106 PIC24FJ128GB106 PIC24FJ192GB106 PIC24FJ256GB106 PIC24FJ64GB108 PIC24FJ128GB108 PIC24FJ192GB108 PIC24FJ256GB108 PIC24FJ64GB110 PIC24FJ128GB110 PIC24FJ192GB110 PIC24FJ256GB110 Doze Mode Operation: When timing-sensitive applications, such serial communications, require uninterrupted operation peripherals, clock speed selectively reduced, allowing incremental power savings without missing beat. Instruction-Based Power-Saving Modes: microcontroller suspend operations, selectively shut down core while leaving peripherals active, with single instruction software.
1.1.3
This expands existing line Microchip`s 16-bit microcontrollers, combining expanded peripheral feature enhanced computational performance with connectivity option: On-The-Go. PIC24FJ256GB110 family provides platform high-performance applications which need more than 8-bit platform, don't require power digital signal processor.
OSCILLATOR OPTIONS FEATURES
devices PIC24FJ256GB110 family offer five different oscillator options, allowing users range choices developing application hardware. These include: Crystal modes using crystals ceramic resonators. External Clock modes offering option divide-by-2 clock output. Fast Internal Oscillator (FRC) with nominal output, which also divided under software control provide clock speeds kHz. Phase Lock Loop (PLL) frequency multiplier, available external oscillator modes oscillator, which allows clock speeds MHz. separate internal oscillator (LPRC) with fixed output, which provides low-power option timing-insensitive applications. internal oscillator block also provides stable reference source Fail-Safe Clock Monitor. This option constantly monitors main clock source against reference signal provided internal oscillator enables controller switch internal oscillator, allowing continued low-speed operation safe application shutdown.
1.1.1
Core Features
16-BIT ARCHITECTURE
Central PIC24F devices 16-bit modified Harvard architecture, first introduced with Microchip's dsPIC® digital signal controllers. PIC24F core offers wide range enhancements, such 16-bit data 24-bit address paths with ability move information between data memory spaces Linear addressing Mbytes (program space) Kbytes (data) 16-element working register array with built-in software stack support hardware multiplier with support integer math Hardware support 16-bit division instruction that supports multiple addressing modes optimized high-level languages such Operational performance MIPS
1.1.4
EASY MIGRATION
1.1.2
POWER-SAVING TECHNOLOGY
devices PIC24FJ256GB110 family incorporate range features that significantly reduce power consumption during operation. items include: On-the-Fly Clock Switching: device clock changed under software control Timer1 source internal, low-power oscillator during operation, allowing user incorporate power-saving ideas into their software designs.
Regardless memory size, devices share same rich peripherals, allowing smooth migration path applications grow evolve. consistent pinout scheme used throughout entire family also aids migrating from device next larger, even jumping from 64-pin 100-pin devices. PIC24F family pin-compatible with devices dsPIC33 family, shares some compatibility with pinout schema PIC18 dsPIC30. This extends ability applications grow from relatively simple, powerful complex, still selecting Microchip device.
2008 Microchip Technology Inc.
DS39897B-page
PIC24FJ256GB110 FAMILY
On-The-Go
With PIC24FJ256GB110 family devices, Microchip introduces On-The-Go functionality single chip product line. This module provides on-chip functionality target device compatible with standard, well limited stand-alone functionality embedded host. implementing Host Negotiation Protocol (HNP), module also dynamically switch between device host operation, allowing much wider range versatile USB-enabled applications microcontroller platform. addition host functionality, PIC24FJ256GB110 family devices provide true single-chip solution, including on-chip transceiver voltage regulator, voltage boost generator sourcing power during host operations. Parallel Master/Enhanced Parallel Slave Port: general purpose ports reconfigured enhanced parallel data communications. this mode, port configured both master slave operations, supports 8-bit 16-bit data transfers with external address lines Master modes. Real-Time Clock/Calendar: This module implements full-featured clock calendar with alarm functions hardware, freeing timer resources program memory space core application.
Details Individual Family Members
Devices PIC24FJ256GB110 family available 64-pin, 80-pin 100-pin packages. general block diagram devices shown Figure 1-1. devices differentiated from each other four ways: Flash program memory Kbytes PIC24FJ64GB1 devices, Kbytes PIC24FJ128GB1 devices, Kbytes PIC24FJ192GB1 devices Kbytes PIC24FJ256GB1 devices). Available pins ports pins ports 64-pin devices, pins ports 80-pin devices pins ports 100-pin devices). Available Interrupt-on-Change Notification (ICN) inputs 64-pin devices, 80-pin devices, 100-pin devices). Available remappable pins pins 64-pin devices, pins 80-pin devices pins 100-pin devices)
Other Special Features
Peripheral Select: peripheral select feature allows most digital peripherals mapped over fixed digital pins. Users independently input and/or output many digital peripherals pins. Communications: PIC24FJ256GB110 family incorporates range serial communication peripherals handle range application requirements. There three independent modules that support both Master Slave modes operation. Devices also have, through peripheral select feature, four independent UARTs with built-in IrDA encoder/decoders three modules. Analog Features: members PIC24FJ256GB110 family include 10-bit Converter module triple comparator module. module incorporates programmable acquisition time, allowing channel selected conversion initiated without waiting sampling period, well faster sampling speeds. comparator module includes three analog comparators that configurable wide range operations. CTMU Interface: addition their other analog features, members PIC24FJ256GB110 family include brand CTMU interface module. This provides convenient method precision time measurement pulse generation, serve interface capacitive sensors.
other features devices this family identical. These summarized Table 1-1. list features available PIC24FJ256GB110 family devices, sorted function, shown Table 1-4. Note that this table shows location individual peripheral features they multiplexed same pin. This information provided pinout diagrams beginning data sheet. Multiplexed features sorted priority given feature, with highest priority peripheral being listed first.
DS39897B-page
2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
TABLE 1-1: DEVICE FEATURES PIC24FJ256GB110 FAMILY: 64-PIN DEVICES
Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) Ports Total Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART (3-wire/4-wire) I2CParallel Communications (PMP/PSP) JTAG Boundary Scan/Programming 10-Bit Analog-to-Digital Module (input channels) Analog Comparators CTMU Interface Resets (and delays) 4(1) 3(1) POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, Lock) Base Instructions, Multiple Addressing Mode Variations 64-Pin TQFP Peripherals accessible through remappable pins. 5(1) 9(1) 9(1) 22,016 64GB106 128GB106 128K 44,032 16,384 (62/4) Ports I/O, Input only) 192GB106 192K 67,072 256GB106 256K 87,552
Instruction Packages Note
2008 Microchip Technology Inc.
DS39897B-page
PIC24FJ256GB110 FAMILY
TABLE 1-2: DEVICE FEATURES PIC24FJ256GB110 FAMILY: 80-PIN DEVICES
Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) Ports Total Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART (3-wire/4-wire) I2CParallel Communications (PMP/PSP) JTAG Boundary Scan/Programming 10-Bit Analog-to-Digital Module (input channels) Analog Comparators CTMU Interface Resets (and delays) 4(1) 3(1) POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, Lock) Base Instructions, Multiple Addressing Mode Variations 80-Pin TQFP Peripherals accessible through remappable pins. 5(1) 9(1) 9(1) 22,016 64GB108 128GB108 128K 44,032 16,384 (62/4) Ports I/O, Input only) 192GB108 192K 67,072 256GB108 256K 87,552
Instruction Packages Note
DS39897B-page
2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
TABLE 1-3: DEVICE FEATURES PIC24FJ256GB110 FAMILY: 100-PIN DEVICES
Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) Ports Total Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART (3-wire/4-wire) I2CParallel Communications (PMP/PSP) JTAG Boundary Scan/Programming 10-Bit Analog-to-Digital Module (input channels) Analog Comparators CTMU Interface Resets (and delays) 4(1) 3(1) POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, Lock) Base Instructions, Multiple Addressing Mode Variations 100-Pin TQFP Peripherals accessible through remappable pins. 5(1) 9(1) 9(1) 22,016 64GB110 128GB110 128K 44,032 16,384 (62/4) Ports I/O, Input only) 192GB110 192K 67,072 256GB110 256K 87,552
Instruction Packages Note
2008 Microchip Technology Inc.
DS39897B-page
PIC24FJ256GB110 FAMILY
FIGURE 1-1: PIC24FJ256GB110 FAMILY GENERAL BLOCK DIAGRAM
Data
Table Data Access Control Block Data Latch Program Counter Repeat Stack Control Control Logic Logic Data Address Latch Read Write PORTB I/O) PORTA(1) I/O)
Interrupt Controller
Address Latch Program Memory Data Latch
PORTC(1) I/O)
Address
Inst Latch Inst Register Instruction Decode Control OSCO/CLKO OSCI/CLKI Timing Generation FRC/LPRC Oscillators Precision Band Reference ENVREG Voltage Regulator Control Signals Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer LVD(2) Literal Data
PORTD(1) I/O)
PORTE(1) Divide Support 17x17 Multiplier Array I/O)
REFO
16-Bit
PORTF(1) I/O)
PORTG(1) I/O)
VDDCORE/VCAP
VDD,
MCLR
Timer1
Timer2/3(3)
Timer4/5(3)
RTCC
10-Bit
Comparators(3)
PMP/PSP PWM/OC 1-9(3) 1/2/3(3)
1-9(3) Note
ICNs(1)
1/2/3
UART 1/2/3/4(3)
CTMU
pins features implemented device pinout configurations. Table specific implementations count. functionality provided when on-board voltage regulator enabled. These peripheral I/Os only accessible through remappable pins.
DS39897B-page
2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
TABLE 1-4:
Function
PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS
Number 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP Input Buffer Positive Supply Analog modules. Ground Reference Analog modules. Comparator Input Comparator Input Comparator Input Comparator Input Comparator Input Comparator Input Comparator Input Comparator Input Comparator Input Comparator Input Comparator Input Comparator Input Main Clock Input Connection. System Clock Output. Analog Inputs. Description
AN10 AN11 AN12 AN13 AN14 AN15 AVDD AVSS C1INA C1INB C1INC C1IND C2INA C2INB C2INC C2IND C3INA C3INB C3INC C3IND CLKI CLKO Legend:
input buffer Analog level input/output
Schmitt Trigger input buffer I2C= I2C/SMBus input buffer
2008 Microchip Technology Inc.
DS39897B-page
PIC24FJ256GB110 FAMILY
TABLE 1-4:
Function
PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP Input Buffer Schmitt Trigger input buffer I2C= I2C/SMBus input buffer Description
CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 CN18 CN19 CN20 CN21 CN22 CN23 CN24 CN25 CN26 CN27 CN28 CN29 CN30 CN31 CN32 CN33 CN34 CN35 CN36 CN37 CN38 CN39 CN40 CN41 CN42 Legend:
Interrupt-on-Change Inputs.
input buffer Analog level input/output
DS39897B-page
2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
TABLE 1-4:
Function
PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP Input Buffer CTMU External Edge Input CTMU External Edge Input CTMU Pulse Output. Comparator Voltage Reference Output. Description
CN43 CN44 CN45 CN46 CN47 CN48 CN49 CN50 CN51 CN52 CN53 CN54 CN55 CN56 CN57 CN58 CN59 CN60 CN61 CN62 CN63 CN64 CN65 CN66 CN67 CN68 CN69 CN70 CN71 CN74 CN75 CN76 CN77 CN78 CN79 CN80 CN81 CN82 CTED1 CTED2 CTPLS CVREF Legend:
Interrupt-on-Change Inputs.
input buffer Analog level input/output
Schmitt Trigger input buffer I2C= I2C/SMBus input buffer
2008 Microchip Technology Inc.
DS39897B-page
PIC24FJ256GB110 FAMILY
TABLE 1-4:
Function
PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP Input Buffer ST/TTL Parallel Master Port Chip Select Strobe/Address Parallel Master Port Chip Select Strobe/Address Parallel Master Port Byte Enable Strobe. Description
DDMH DMLN DPLN ENVREG INT0 MCLR OSCI OSCO PGEC1 PGED1 PGEC2 PGED2 PGEC3 PGED3 PMA0 PMA1 PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMCS1 PMCS2 PMBE Legend:
Differential Plus line (internal transceiver). Differential Minus line (internal transceiver). External Pull-up Control Output. External Pull-down Control Output. External Pull-up Control Output. External Pull-down Control Output. Voltage Regulator Enable. External Interrupt Input. Master Clear (device Reset) Input. This line brought cause Reset. Main Oscillator Input Connection. Main Oscillator Output Connection. In-Circuit Clock. In-Circuit Debugger/Emulator/ICSP Programming Data. In-Circuit Debugger/Emulator/ICSP Programming Clock. In-Circuit Debugger/Emulator/ICSP Programming Data. In-Circuit Debugger/Emulator/ICSP Programming Clock. In-Circuit Debugger/Emulator/ICSP Programming Data. Parallel Master Port Address Input (Buffered Slave modes) Output (Master modes). Parallel Master Port Address Input (Buffered Slave modes) Output (Master modes). Parallel Master Port Address (Demultiplexed Master modes).
input buffer Analog level input/output
Schmitt Trigger input buffer I2C= I2C/SMBus input buffer
DS39897B-page
2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
TABLE 1-4:
Function
PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP Input Buffer ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL Schmitt Trigger input buffer I2C= I2C/SMBus input buffer PORTB Digital I/O. Parallel Master Port Read Strobe. Parallel Master Port Write Strobe. PORTA Digital I/O. Description
PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMRD PMWR RA10 RA14 RA15 RB10 RB11 RB12 RB13 RB14 RB15 Legend:
Parallel Master Port Data (Demultiplexed Master mode) Address/Data (Multiplexed Master modes).
input buffer Analog level input/output
2008 Microchip Technology Inc.
DS39897B-page
PIC24FJ256GB110 FAMILY
TABLE 1-4:
Function
PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP Input Buffer Reference Clock Output. Schmitt Trigger input buffer I2C= I2C/SMBus input buffer PORTE Digital I/O. Receive Input (from external transceiver). PORTD Digital I/O. PORTC Digital I/O. Description
RC12 RC13 RC14 RC15 RD10 RD11 RD12 RD13 RD14 RD15 REFO Legend:
input buffer Analog level input/output
DS39897B-page
2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
TABLE 1-4:
Function
PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP Input Buffer Schmitt Trigger input buffer I2C= I2C/SMBus input buffer Remappable Peripheral (input output). PORTG Digital I/O. PORTF Digital I/O. Description
RF12 RF13 RG12 RG13 RG14 RG15 RP10 RP11 RP12 RP13 RP14 RP15 RP16 RP17 RP18 RP19 Legend:
input buffer Analog level input/output
2008 Microchip Technology Inc.
DS39897B-page
PIC24FJ256GB110 FAMILY
TABLE 1-4:
Function
PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP Input Buffer Real-Time Clock Alarm/Seconds Pulse Output. I2C1 Synchronous Serial Clock Input/Output. I2C2 Synchronous Serial Clock Input/Output. I2C3 Synchronous Serial Clock Input/Output. I2C1 Data Input/Output. I2C2 Data Input/Output. I2C3 Data Input/Output. Secondary Oscillator/Timer1 Clock Input. Secondary Oscillator/Timer1 Clock Output. Timer1 Clock. JTAG Test Clock/Programming Clock Input. JTAG Test Data/Programming Data Input. JTAG Test Data Output. JTAG Test Mode Select Input. (OTG mode only). Output Enable Control (for external transceiver). Remappable Peripheral (input only). Description
RP20 RP21 RP22 RP23 RP24 RP25 RP26 RP27 RP28 RP29 RP30 RP31 RPI32 RPI33 RPI34 RPI35 RPI36 RPI37 RPI38 RPI39 RPI40 RPI41 RPI42 RPI43 RTCC SCL1 SCL2 SCL3 SDA1 SDA2 SDA3 SOSCI SOSCO T1CK USBID USBOEN Legend:
Remappable Peripheral (input output).
input buffer Analog level input/output
Schmitt Trigger input buffer I2C= I2C/SMBus input buffer
DS39897B-page
2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
TABLE 1-4:
Function
PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP Input Buffer Description
VBUS VBUSON VBUSST VCAP VCMPST1 VCMPST2 VCPCON VDDCORE VMIO VPIO VREFVREF+ VUSB Legend:
Voltage, Host mode (5V). External Charge Pump Control. Internal Charge Pump Feedback Control. External Filter Capacitor Connection (regulator enabled). VBUS Boost Generator, Comparator Input VBUS Boost Generator, Comparator Input VBUS PWM/Charge Output. Positive Supply Peripheral Digital Logic Pins. Positive Supply Microcontroller Core Logic (regulator disabled). Differential Minus Input/Output (external transceiver). Differential Plus Input/Output (external transceiver). Comparator Reference Voltage (low) Input. Comparator Reference Voltage (high) Input. Ground Reference Logic Pins. Voltage (3.3V)
input buffer Analog level input/output
Schmitt Trigger input buffer I2C= I2C/SMBus input buffer
2008 Microchip Technology Inc.
DS39897B-page
PIC24FJ256GB110 FAMILY
NOTES:
DS39897B-page
2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
Note:
This data sheet summarizes features this group PIC24F devices. intended comprehensive reference source. more information, refer "PIC24F Family Reference Manual", "Section CPU" (DS39703).
most instructions, core capable executing data program data) memory read, working register (data) read, data memory write program (instruction) memory read instruction cycle. result, three parameter instructions supported, allowing trinary operations (that executed single cycle. high-speed, 17-bit 17-bit multiplier been included significantly enhance core arithmetic capability throughput. multiplier supports Signed, Unsigned Mixed mode, 16-bit 16-bit 8-bit 8-bit, integer multiplication. multiply instructions execute single cycle. 16-bit been enhanced with integer divide assist hardware that supports iterative non-restoring divide algorithm. operates conjunction with REPEAT instruction looping mechanism selection iterative divide instructions support 32-bit 16-bit), divided 16-bit, integer signed unsigned division. divide operations require cycles complete interruptible cycle boundary. PIC24F vectored exception scheme with sources non-maskable traps interrupt sources. Each interrupt source assigned seven priority levels. block diagram shown Figure 2-1.
PIC24F 16-bit (data) modified Harvard architecture with enhanced instruction 24-bit instruction word with variable length opcode field. Program Counter (PC) bits wide addresses instructions user program memory space. single-cycle instruction prefetch mechanism used help maintain throughput provides predictable execution. instructions execute single cycle, with exception instructions that change program flow, double-word move (MOV.D) instruction table instructions. Overhead-free program loop constructs supported using REPEAT instructions, which interruptible point. PIC24F devices have sixteen, 16-bit working registers programmer's model. Each working registers data, address address offset register. 16th working register (W15) operates Software Stack Pointer interrupts calls. upper Kbytes data space memory optionally mapped into program space word boundary defined 8-bit Program Space Visibility Page Address (PSVPAG) register. program data space mapping feature lets instruction access program space were data space. Instruction Architecture (ISA) been significantly enhanced beyond that PIC18, maintains acceptable level backward compatibility. PIC18 instructions addressing modes supported, either directly, through simple macros. Many enhancements have been driven compiler efficiency needs. core supports Inherent operand), Relative, Literal, Memory Direct three groups addressing modes. modes support Register Direct various Register Indirect modes. Each group offers seven addressing modes. Instructions associated with predefined addressing modes depending upon their functional requirements.
Programmer's Model
programmer's model PIC24F shown Figure 2-2. registers programmer's model memory mapped manipulated directly instructions. description each register provided Table 2-1. registers associated with programmer's model memory mapped.
2008 Microchip Technology Inc.
DS39897B-page
PIC24FJ256GB110 FAMILY
FIGURE 2-1:
Table Data Access Control Block Interrupt Controller Program Counter Loop Stack Control Control Logic Logic Data Address Latch RAGU WAGU Data Data Latch
PIC24F CORE BLOCK DIAGRAM
Address Latch
Program Memory Address Data Latch Latch Literal Data
Instruction Decode Control
Instruction
Control Signals Various Blocks
Hardware Multiplier Divide Support
Register Array
16-Bit
Peripheral Modules
DS39897B-page
2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
TABLE 2-1:
through SPLIM TBLPAG PSVPAG RCOUNT CORCON
CORE REGISTERS
Description Working Register Array 23-Bit Program Counter STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register Control Register
Register(s) Name
FIGURE 2-2:
PROGRAMMER'S MODEL
(WREG) Frame Pointer Stack Pointer Stack Pointer Limit Value Register Program Counter Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register Working/Address Registers
Divider Working Registers
Multiplier Registers
SPLIM TBLPAG PSVPAG RCOUNT
STATUS Register (SR)
Control Register (CORCON)
IPL3
Registers bits shadowed PUSH.S POP.S instructions.
2008 Microchip Technology Inc.
DS39897B-page
PIC24FJ256GB110 FAMILY
Control Registers
STATUS REGISTER
R/W-0 R/W-0(1) IPL1
REGISTER 2-1:
R/W-0(1) IPL2 Legend: Readable Value 15-9
R/W-0(1) IPL0
R/W-0
R/W-0
R/W-0
R/W-0
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read Half Carry/Borrow carry from low-order (for byte-sized data) low-order (for word-sized data) result occurred carry from low-order result occurred IPL2:IPL0: Interrupt Priority Level Status bits(1,2) interrupt priority level (15); user interrupts disabled interrupt priority level (14) interrupt priority Level (13) interrupt priority level (12) interrupt priority level (11) interrupt priority level (10) interrupt priority level interrupt priority level REPEAT Loop Active REPEAT loop progress REPEAT loop progress Negative Result negative Result non-negative (zero positive) Overflow Overflow occurred signed (2's complement) arithmetic this arithmetic operation overflow occurred Zero operation which effects some time past most recent operation which effects cleared (i.e., non-zero result) Carry/Borrow carry from Most Significant result occurred carry from Most Significant result occurred Status bits read-only when NSTDIS (INTCON1<15>) Status bits concatenated with IPL3 (CORCON<3>) form Interrupt Priority Level (IPL). value parentheses indicates when IPL3
Note
DS39897B-page
2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
REGISTER 2-2:
Legend: Readable Value 15-4 Clearable Writable Unimplemented bit, read cleared unknown R/C-0 IPL3
CORCON: CONTROL REGISTER
R/W-0
Unimplemented: Read IPL3: Interrupt Priority Level Status bit(1) interrupt priority level greater than interrupt priority level less PSV: Program Space Visibility Data Space Enable Program space visible data space Program space visible data space Unimplemented: Read User interrupts disabled when IPL3
Note
Arithmetic Logic Unit (ALU)
PIC24F bits wide capable addition, subtraction, shifts logic operations. Unless otherwise mentioned, arithmetic operations complement nature. Depending operation, affect values Carry (C), Zero (Z), Negative (N), Overflow (OV) Digit Carry (DC) Status bits register. Status bits operate Borrow Digit Borrow bits, respectively, subtraction operations. perform 8-bit 16-bit operations, depending mode instruction that used. Data operation come from register array, data memory, depending addressing mode instruction. Likewise, output data from written register array data memory location.
PIC24F incorporates hardware support both multiplication division. This includes dedicated hardware multiplier support hardware 16-bit divisor division.
2.3.1
MULTIPLIER
contains high-speed, 17-bit 17-bit multiplier. supports unsigned, signed mixed sign operation several multiplication modes: 16-bit 16-bit signed 16-bit 16-bit unsigned 16-bit signed 5-bit (literal) unsigned 16-bit unsigned 16-bit unsigned 16-bit unsigned 5-bit (literal) unsigned 16-bit unsigned 16-bit signed 8-bit unsigned 8-bit unsigned
2008 Microchip Technology Inc.
DS39897B-page
PIC24FJ256GB110 FAMILY
2.3.2 DIVIDER 2.3.3 MULTI-BIT SHIFT SUPPORT
divide block supports signed unsigned integer divide operations with following data sizes: 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide PIC24F supports both single single-cycle, multi-bit arithmetic logic shifts. Multi-bit shifts implemented using shifter block, capable performing 15-bit arithmetic right shift, 15-bit left shift, single cycle. multi-bit shift instructions only support Register Direct Addressing both operand source result destination. full summary instructions that shift operation provided below Table 2-2.
quotient divide instructions ends remainder Sixteen-bit signed unsigned instructions specify register both 16-bit divisor (Wn), register (aligned) pair (W(m 1):Wm) 32-bit dividend. divide algorithm takes cycle divisor, both 32-bit/16-bit 16-bit/16-bit instructions take same number cycles execute.
TABLE 2-2:
Instruction
INSTRUCTIONS THAT SINGLE MULTI-BIT SHIFT OPERATION
Description Arithmetic shift right source register more bits. Shift left source register more bits. Logical shift right source register more bits.
DS39897B-page
2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
MEMORY ORGANIZATION
Harvard architecture devices, PIC24F microcontrollers feature separate program data memory spaces busses. This architecture also allows direct access program memory from data space during code execution. from either 23-bit Program Counter (PC) during program execution, from table operation data space remapping, described Section "Interfacing Program Data Memory Spaces". User access program memory space restricted lower half address range (000000h 7FFFFFh). exception TBLRD/TBLWT operations which TBLPAG<7> permit access Configuration bits Device sections configuration memory space. Memory maps PIC24FJ256GB110 family devices shown Figure 3-1.
Program Address Space
program address memory space PIC24FJ256GB110 family devices instructions. space addressable 24-bit value derived
FIGURE 3-1:
PROGRAM SPACE MEMORY PIC24FJ256GB110 FAMILY DEVICES
PIC24FJ128GB1XX
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory (44K instructions)
PIC24FJ64GB1XX
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory (22K instructions) Flash Config Words User Memory Space
PIC24FJ192GB1XX
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table
PIC24FJ256GB1XX
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table 000000h 000002h 000004h 0000FEh 000100h 000104h 0001FEh 000200h
User Flash Program Memory (67K instructions)
Flash Config Words
User Flash Program Memory (87K instructions)
00ABFEh 00AC00h 0157FEh 015800h 020BFEh 020C00h
Flash Config Words Unimplemented Read Unimplemented Read
Flash Config Words Unimplemented Read
02ABFEh 02AC00h
Unimplemented Read
7FFFFFh 800000h
Reserved Configuration Memory Space
Reserved
Reserved
Reserved
Device Config Registers
Device Config Registers
Device Config Registers
Device Config Registers
F7FFFEh F80000h F8000Eh F80010h
Reserved
Reserved
Reserved
Reserved
DEVID
DEVID
DEVID
DEVID
FEFFFEh FF0000h FFFFFFh
Note:
Memory areas shown scale.
2008 Microchip Technology Inc.
DS39897B-page
PIC24FJ256GB110 FAMILY
3.1.1 PROGRAM MEMORY ORGANIZATION 3.1.3 FLASH CONFIGURATION WORDS
program memory space organized word-addressable blocks. Although treated bits wide, more appropriate think each address program memory lower upper word, with upper byte upper word being unimplemented. lower word always even address, while upper word address (Figure 3-2). Program memory addresses always word-aligned lower word, addresses incremented decremented during code execution. This arrangement also provides compatibility with data memory space addressing makes possible access data program memory space. PIC24FJ256GB110 family devices, three words on-chip program memory reserved configuration information. device Reset, configuration information copied into appropriate Configuration registers. addresses Flash Configuration Word devices PIC24FJ256GB110 family shown Table 3-1. Their location memory shown with other memory vectors Figure 3-1. Configuration Words program memory compact format. actual Configuration bits mapped several different registers configuration memory space. Their order Flash Configuration Words reflect corresponding arrangement configuration space. Additional details device Configuration Words provided Section 25.1 "Configuration Bits".
3.1.2
HARD MEMORY VECTORS
PIC24F devices reserve addresses between 00000h 000200h hard coded program execution vectors. hardware Reset vector provided redirect code execution from default value device Reset actual start code. GOTO instruction programmed user 000000h with actual address start code 000002h. PIC24F devices also have interrupt vector tables, located from 000004h 0000FFh 000100h 0001FFh. These vector tables allow each many device interrupt sources handled separate ISRs. more detailed discussion interrupt vector tables provided Section "Interrupt Vector Table".
TABLE 3-1:
FLASH CONFIGURATION WORDS PIC24FJ256GB110 FAMILY DEVICES
Program Memory (Words) 22,016 44,032 67,072 87,552 Configuration Word Addresses 00ABFAh: 00ABFEh 0157FAh: 0157FEh 020BFAh: 020BFEh 02ABFAh: 02ABFEh
Device
PIC24FJ64GB PIC24FJ128GB PIC24FJ192GB PIC24FJ256GB
FIGURE 3-2:
Address 000001h 000003h 000005h 000007h
PROGRAM MEMORY ORGANIZATION
most significant word 00000000 00000000 00000000 00000000 Program Memory `Phantom' Byte (read `0') Instruction Width least significant word 000000h 000002h 000004h 000006h Address (LSW Address)
DS39897B-page
2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
Data Address Space
PIC24F core separate, 16-bit wide data memory space, addressable single linear range. data space accessed using Address Generation Units (AGUs), each read write operations. data space memory shown Figure 3-3. Effective Addresses (EAs) data memory space bits wide point bytes within data space. This gives data space address range Kbytes words. lower half data memory space (that when EA<15> used implemented memory addresses, while upper half (EA<15> reserved program space visibility area (see Section 3.3.3 "Reading Data from Program Memory Using Program Space Visibility"). PIC24FJ256GB110 family devices implement total Kbytes data memory. Should point location outside this area, zero word byte will returned.
3.2.1
DATA SPACE WIDTH
data memory space organized byte-addressable, 16-bit wide blocks. Data aligned data memory registers 16-bit words, data space resolve bytes. Least Significant Bytes each word have even addresses, while Most Significant Bytes have addresses.
FIGURE 3-3:
DATA SPACE MEMORY PIC24FJ256GB110 FAMILY DEVICES
Address 0001h 07FFh 0801h 1FFFh 2001h Data Address 0000h 07FEh 0800h 1FFEh 2000h Space
Space
Near Data Space
Implemented Data
47FFh 4801h Unimplemented Read 7FFFh 8001h
47FEh 4800h
7FFFh 8000h
Program Space Visibility Area
FFFFh
FFFEh
Note:
Data memory areas shown scale.
2008 Microchip Technology Inc.
DS39897B-page
PIC24FJ256GB110 FAMILY
3.2.2 DATA MEMORY ORGANIZATION ALIGNMENT
maintain backward compatibility with PIC® devices improve data space memory usage efficiency, PIC24F instruction supports both word byte operations. consequence byte accessibility, Effective Address calculations internally scaled step through word-aligned memory. example, core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result value byte operations word operations. Data byte reads will read complete word which contains byte, using determine which byte select. selected byte placed onto data path. That data memory registers organized parallel, byte-wide entities with shared (word) address decode separate write lines. Data byte writes only write corresponding side array register which matches byte address. word accesses must aligned even address. Misaligned word data fetches supported, care must taken when mixing byte word operations, translating from 8-bit code. misaligned read write attempted, address error trap will generated. error occurred read, instruction underway completed; occurred write, instruction will executed write will occur. either case, trap then executed, allowing system and/or user examine machine state prior execution address Fault. byte loads into register loaded into Least Significant Byte. Most Significant Byte modified. sign-extend instruction (SE) provided allow users translate 8-bit signed data 16-bit signed values. Alternatively, 16-bit unsigned data, users clear register executing zero-extend (ZE) instruction appropriate address. Although most instructions capable operating word byte data sizes, should noted that some instructions operate only words.
3.2.3
NEAR DATA SPACE
8-Kbyte area between 0000h 1FFFh referred near data space. Locations this space directly addressable 13-bit absolute address field within memory direct instructions. remainder data space addressable indirectly. Additionally, whole data space addressable using instructions, which support Memory Direct Addressing with 16-bit address field.
3.2.4
SPACE
first Kbytes near data space, from 0000h 07FFh, primarily occupied with Special Function Registers (SFRs). These used PIC24F core peripheral modules controlling operation device. SFRs distributed among modules that they control generally grouped together module. Much space contains unused addresses; these read `0'. diagram space, showing where SFRs actually implemented, shown Table 3-2. Each implemented area indicates 32-byte region where least address implemented SFR. complete listing implemented SFRs, including their addresses, shown Tables through 3-30.
TABLE 3-2:
IMPLEMENTED REGIONS DATA SPACE
Space Address xx00 xx20 Core Timers I2CA/D UART A/D/CTMU RTC/Comp SPI/UART System xx40 xx60 Capture SPI/I2C NVM/PMD UART xx80 xxA0 Interrupts Compare xxC0 xxE0
000h 100h 200h 300h 400h 500h 600h 700h
Legend: implemented SFRs this block
DS39897B-page
2008 Microchip Technology Inc.
TABLE 3-3:
Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Stack Pointer Limit Value Register Program Counter Word Register Repeat Loop Counter Register IPL2 IPL1 IPL0 Disable Interrupts Counter Register IPL3 Program Counter Register High Byte Table Memory Page Address Register Program Space Visibility Page Address Register
CORE REGISTERS
Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 xxxx 0000 0000 0000 0000 xxxx 0000 0000 xxxx
File Name
Addr
WREG0
0000
WREG1
0002
WREG2
0004
WREG3
0006
WREG4
0008
WREG5
000A
2008 Microchip Technology Inc.
WREG6
000C
WREG7
000E
WREG8
0010
WREG9
0012
WREG10
0014
WREG11
0016
WREG12
0018
WREG13
001A
WREG14
001C
WREG15
001E
SPLIM
0020
002E
PIC24FJ256GB110 FAMILY
0030
TBLPAG
0032
PSVPAG
0034
RCOUNT
0036
0042
CORCON
0044
DISICNT
0052
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
DS39897B-page
TABLE 3-4:
CN13PDE CN29PDE CN61PDE CN9IE CN25IE CN41IE(1) CN57IE(1) CN56IE CN8PUE CN24PUE CN55PUE CN71PUE CN70PUE(1) CN69PUE CN54PUE CN53PUE CN23PUE CN22PUE CN7PUE CN6PUE CN5PUE CN4PUE CN71IE CN70IE(1) CN69IE CN68IE CN3PUE CN55IE CN54IE CN53IE CN52IE CN51IE CN67IE(1) CN9PUE CN25PUE CN40IE(2) CN39IE(2) CN38IE(2) CN37IE(2) CN36IE(2) CN35IE(2) CN24IE CN23IE CN22IE CN21IE(1) CN20IE(1) CN19IE(1) CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN18IE CN34IE(2) CN50IE CN66IE(1) CN82IE(2) CN2PUE CN18PUE CN51PUE CN50PUE CN68PUE CN67PUE(1) CN66PUE(1) CN71PDE CN70PDE(1) CN69PDE CN68PDE CN67PDE(1) CN66PDE(1) CN13IE CN29IE CN45IE(1) CN61IE CN77IE(1) CN13PUE CN29PUE CN61PUE CN60PUE CN59PUE CN58PUE CN57PUE(1) CN56PUE CN28PUE CN27PUE CN26PUE CN12PUE CN11PUE CN10PUE CN76IE(2) CN75IE(2) CN74IE(1) CN60IE CN59IE CN58IE CN44IE(1) CN43IE(1) CN42IE(1) CN28IE CN27IE CN26IE CN12IE CN11IE CN10IE CN60PDE CN59PDE CN58PDE CN57PDE(1) CN56PDE CN55PDE CN54PDE CN53PDE CN52PDE CN51PDE CN50PDE CN49PDE CN65PDE CN1IE CN17IE CN33IE(2) CN49IE CN65IE CN81IE(2) CN1PUE CN17PUE CN49PUE CN65PUE CN28PDE CN27PDE CN26PDE CN25PDE CN24PDE CN23PDE CN22PDE CN21PDE(1) CN20PDE(1) CN19PDE(1) CN18PDE CN17PDE CN12PDE CN11PDE CN10PDE CN9PDE CN8PDE CN7PDE CN6PDE CN5PDE CN4PDE CN3PDE CN2PDE CN1PDE CN0PDE CN16PDE CN32PDE CN64PDE CN0IE CN16IE CN32IE CN48IE(2) CN64IE CN80IE(2) CN0PUE CN16PUE CN32PUE CN52PUE CN64PUE Resets 0000 0000 0000 CN48PDE(2) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CN48PUE(2) 0000 0000 CN82PUE(2) CN81PUE(2) CN80PUE(2) 0000
REGISTER
File Name
Addr
CNPD1
0054
CN15PDE
CN14PDE
DS39897B-page
CN82PDE(2) CN81PDE(2) CN80PDE(2) 0000 CN21PUE(1) CN20PUE(1) CN19PUE(1)
CNPD2
0056
CN31PDE
CN30PDE
CNPD3
0058 CN47PDE(1) CN46PDE(2) CN45PDE(1) CN44PDE(1) CN43PDE(1) CN42PDE(1) CN41PDE(1) CN40PDE(2) CN39PDE(2) CN38PDE(2) CN37PDE(2) CN36PDE(2) CN35PDE(2) CN34PDE(2) CN33PDE(2)
CNPD4
005A
CN63PDE
CN62PDE
CNPD5
005C CN79PDE(2) CN78PDE(1) CN77PDE(1) CN76PDE(2) CN75PDE(2) CN74PDE(1)
CNPD6
005E
CNEN1
0060
CN15IE
CN14IE
CNEN2
0062
CN31IE
CN30IE
CNEN3
0064
CN47IE(1)
CN46IE(2)
CNEN4
0066
CN63IE
CN62IE
CNEN5
0068
CN79IE(2)
CN78IE(1)
CNEN6(2) 006A
CNPU1
006C CN15PUE
CN14PUE
CNPU2
006E
CN31PUE
CN30PUE
CNPU3
0070 CN47PUE(1) CN46PUE(2) CN45PUE(1) CN44PUE(1) CN43PUE(1) CN42PUE(1) CN41PUE(1) CN40PUE(2) CN39PUE(2) CN38PUE(2) CN37PUE(2) CN36PUE(2) CN35PUE(2) CN34PUE(2) CN33PUE(2)
CNPU4
0072
CN63PUE
CN62PUE
CNPU5
0074 CN79PUE(2) CN78PUE(1) CN77PUE(1) CN76PUE(2) CN75PUE(2) CN74PUE(1)
PIC24FJ256GB110 FAMILY
CNPU6(2) 0076
Legend: Note
unimplemented, read `0'. Reset values shown hexadecimal. Unimplemented 64-pin devices; read `0'. Unimplemented 64-pin 80-pin devices; read `0'.
2008 Microchip Technology Inc.
TABLE 3-5:
AD1IF INT2IF PMPIF CTMUIF IC9IF AD1IE INT2IE PMPIE CTMUIE IC9IE T1IP1 T2IP1 RTCIP2 RTCIP1 INT4IP2 INT4IP1 MI2C2P2 MI2C2P1 MI2C2P0 INT4IP0 RTCIP0 OC6IP2 OC6IP1 OC6IP0 IC4IP2 IC4IP1 IC4IP0 SPF3IP1 SPF3IP0 U2RXIP2 U2RXIP1 U2RXIP0 OC4IP2 OC4IP1 OC4IP0 IC7IP2 IC7IP1 IC7IP0 OC3IP2 INT2IP2 SPI2IP2 IC3IP2 OC5IP2 PMPIP2 SI2C2P2 INT3IP2 CMIP2 CMIP1 CMIP0 AD1IP2 SPI1IP2 SPI1IP1 SPI1IP0 SPF1IP2 SPF1IP1 AD1IP1 OC3IP1 INT2IP1 SPI2IP1 IC3IP1 OC5IP1 PMPIP1 SI2C2P1 INT3IP1 U1ERIP2 U1ERIP1 U3ERIP2 U3ERIP1 MI2C3P2 MI2C3P1 U4TXIP2 IC9IP2 U4TXIP1 IC9IP1 CNIP1 IC8IP1 T4IP1 U2TXIP1 IC5IP1 OC7IP1 CRCIP1 U3TXIP1 SPI3IP1 SPI3IP0 U3TXIP0 CRCIP0 OC7IP0 IC5IP0 U2TXIP0 T4IP0 IC8IP0 CNIP0 T2IP0 OC2IP2 OC2IP1 OC2IP0 IC2IP2 IC2IP1 T1IP0 OC1IP2 OC1IP1 OC1IP0 IC1IP2 IC1IP1 OC9IE SPI3IE SPF3IE U4TXIE U4RXIE U4ERIE USB1IE MI2C3IE SI2C3IE IC1IP0 IC2IP0 SPF1IP0 AD1IP0 MI2C1P0 OC3IP0 INT2IP0 SPI2IP0 IC3IP0 OC5IP0 PMPIP0 SI2C2P0 INT3IP0 U1ERIP0 CTMUIP2 CTMUIP1 CTMUIP0 U3ERIP0 MI2C3P0 U4TXIP0 IC9IP0 LVDIE INT4IE INT3IE OC8IE OC7IE OC6IE OC5IE IC6IE IC5IE IC4IE IC3IE CRCIE U3TXIE T5IE T4IE OC4IE OC3IE IC8IE IC7IE INT1IE CNIE U1TXIE U1RXIE SPI1IE SPF1IE T3IE T2IE OC2IE IC2IE T1IE OC9IF SPI3IF SPF3IF U4TXIF U4RXIF U4ERIF USB1IF MI2C3IF SI2C3IF U3TXIF LVDIF CRCIF U2ERIF U3RXIF OC1IE CMIE MI2C2IE U2ERIE U3RXIE INT0IP2 T3IP2 U1TXIP2 SI2C1P2 INT1IP2 T5IP2 SPF2IP2 IC6IP2 OC8IP2 LVDIP2 SI2C3P2 OC9IP2 INT4IF INT3IF MI2C2IF OC8IF OC7IF OC6IF OC5IF IC6IF IC5IF IC4IF IC3IF T5IF T4IF OC4IF OC3IF IC8IF IC7IF INT1IF CNIF CMIF MI2C1IF SPI2IF SI2C2IF U1ERIF U3ERIF IC1IE MI2C1IE SPI2IE SI2C2IE U1ERIE U3ERIE INT0IP1 T3IP1 U1TXIP1 SI2C1P1 INT1IP1 T5IP1 SPF2IP1 IC6IP1 OC8IP1 LVDIP1 SI2C3P1 OC9IP1 U1TXIF U1RXIF SPI1IF SPF1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT2EP INT1EP MATHERR ADDRERR STKERR OSCFAIL INT0EP INT0IF SI2C1IF SPF2IF INT0IE SI2C1IE SPF2IE INT0IP0 T3IP0 U1TXIP0 SI2C1P0 INT1IP0 T5IP0 SPF2IP0 IC6IP0 OC8IP0 LVDIP0 SI2C3P0 U4RXIP2 U4RXIP1 U4RXIP0 OC9IP0
INTERRUPT CONTROLLER REGISTER
Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4440 4444 0044 4444 4404 4440 4444 0044 4440 4444 0044 0440 0440 0400 4440 0004 0040 4440 4444 4444 0044
File Name
Addr
INTCON1
0080
NSTDIS
INTCON2
0082
ALTIVT
DISI
IFS0
0084
IFS1
0086
U2TXIF
U2RXIF
IFS2
0088
IFS3
008A
RTCIF
IFS4
008C
2008 Microchip Technology Inc.
MI2C1P2 MI2C1P1 U2ERIP2 U2ERIP1 U2ERIP0 U3RXIP2 U3RXIP1 U3RXIP0 USB1IP2 USB1IP1 USB1IP0 SPF3IP2
IFS5
008E
IEC0
0094
IEC1
0096
U2TXIE
U2RXIE
IEC2
0098
IEC3
009A
RTCIE
IEC4
009C
IEC5
009E
IPC0
00A4
T1IP2
IPC1
00A6
T2IP2
IPC2
00A8
U1RXIP2 U1RXIP1 U1RXIP0
IPC3
00AA
IPC4
00AC
CNIP2
IPC5
00AE
IC8IP2
PIC24FJ256GB110 FAMILY
IPC6
00B0
T4IP2
IPC7
00B2
U2TXIP2
IPC8
00B4
IPC9
00B6
IC5IP2
IPC10
00B8
OC7IP2
IPC11
00BA
IPC12
00BC
IPC13
00BE
IPC15
00C2
IPC16
00C4
CRCIP2
IPC18
00C8
IPC19
00CA
IPC20
00CC
U3TXIP2
IPC21
00CE
U4ERIP2 U4ERIP1 U4ERIP0
IPC22
00D0
SPI3IP2
IPC23
00D2
DS39897B-page
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-6:
Timer1 Register Timer1 Period Register Timer2 Register Timer3 Holding Register (for 32-bit timer operations only) Timer3 Register Timer2 Period Register Timer3 Period Register Timer4 Register Timer5 Holding Register (for 32-bit operations only) Timer5 Register Timer4 Period Register Timer5 Period Register TSIDL TGATE TSIDL TGATE TCKPS1 TCKPS1 TCKPS0 TCKPS0 TSIDL TGATE TCKPS1 TCKPS0 TSIDL TGATE TCKPS1 TCKPS0 TSIDL TGATE TCKPS1 TCKPS0 TSYNC Resets 0000 FFFF 0000 0000 0000 0000 FFFF FFFF 0000 0000 0000 0000 0000 FFFF FFFF 0000 0000
TIMER REGISTER
File Name
Addr
TMR1
0100
0102
DS39897B-page
T1CON
0104
TMR2
0106
TMR3HLD
0108
TMR3
010A
010C
010E
T2CON
0110
T3CON
0112
TMR4
0114
TMR5HLD
0116
TMR5
0118
011A
011C
T4CON
011E
T5CON
0120
PIC24FJ256GB110 FAMILY
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
2008 Microchip Technology Inc.
TABLE 3-7:
ICSIDL Input Capture Buffer Register Timer Value Register ICSIDL Input Capture Buffer Register Timer Value Register ICSIDL Input Capture Buffer Register Timer Value Register ICSIDL Input Capture Buffer Register Timer Value Register ICSIDL Input Capture Buffer Register Timer Value Register ICSIDL IC32 ICTRIG ICTSEL2 ICTSEL1 ICTSEL0 ICI1 TRIGSTAT ICI0 ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 IC32 ICTRIG TRIGSTAT ICTSEL2 ICTSEL1 ICTSEL0 ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 IC32 ICTRIG TRIGSTAT ICTSEL2 ICTSEL1 ICTSEL0 ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 IC32 ICTRIG TRIGSTAT ICTSEL2 ICTSEL1 ICTSEL0 ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 IC32 ICTRIG TRIGSTAT ICTSEL2 ICTSEL1 ICTSEL0 ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 IC32 ICTRIG TRIGSTAT ICTSEL2 ICTSEL1 ICTSEL0 ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0
INPUT CAPTURE REGISTER
Resets 0000 0000 0000 xxxx 0000 0000 0000 xxxx 0000 0000 0000 xxxx 0000 0000 0000 xxxx 0000 0000 0000 xxxx 0000 0000 0000 xxxx ICI1 TRIGSTAT ICI0 ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 0000 0000 0000 xxxx IC32 ICTRIG ICI1 TRIGSTAT Input Capture Buffer Register Timer Value Register ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 IC32 ICTRIG ICI1 TRIGSTAT Input Capture Buffer Register Timer Value Register ICI0 ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 0000 0000 0000 xxxx 0000 0000 0000 xxxx
File Name SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
Addr
IC1CON1
0140
IC1CON2
0142
IC1BUF
0144
IC1TMR
0146
IC2CON1
0148
IC2CON2
014A
IC2BUF
014C
2008 Microchip Technology Inc.
Input Capture Buffer Register Timer Value Register ICSIDL IC32 ICTSEL2 ICTSEL1 ICTSEL0 ICTRIG Input Capture Buffer Register Timer Value Register ICSIDL ICTSEL2 ICTSEL1 ICTSEL0
IC2TMR
014E
IC3CON1
0150
IC3CON2
0152
IC3BUF
0154
IC3TMR
0156
IC4CON1
0158
IC4CON2
015A
IC4BUF
015C
IC4TMR
015E
IC5CON1
0160
IC5CON2
0162
IC5BUF
0164
IC5TMR
0166
PIC24FJ256GB110 FAMILY
IC6CON1
0168
IC6CON2
016A
IC6BUF
016C
IC6TMR
016E
IC7CON1
0170
IC7CON2
0172
IC7BUF
0174
IC7TMR
0176
IC8CON1
0178
IC8CON2
017A
IC8BUF
017C
IC8TMR
017E
IC9CON1
0180
IC9CON2
0182
IC9BUF
0184
IC9TMR
0186
DS39897B-page
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-8:
OCSIDL OCINV Output Compare Secondary Register Output Compare Register Timer Value Register OCSIDL OCINV Output Compare Secondary Register Output Compare Register Timer Value Register OCSIDL OCINV Output Compare Secondary Register Output Compare Register Timer Value Register OCSIDL OCINV Output Compare Secondary Register Output Compare Register Timer Value Register OCSIDL OCINV Output Compare Register Timer Value Register OCSIDL OCINV OC32 OCTSEL2 OCTSEL1 OCTSEL0 ENFLT0 OCTRIG TRIGSTAT OCTRIS OCFLT0 TRIGMODE OCM2 OCM1 OCM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 OC32 OCTRIG TRIGSTAT Output Compare Secondary Register OCTSEL2 OCTSEL1 OCTSEL0 ENFLT0 OCTRIS OCFLT0 TRIGMODE OCM2 OCM1 OCM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 OC32 OCTRIG TRIGSTAT OCTRIS OCTSEL2 OCTSEL1 OCTSEL0 ENFLT0 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 OC32 OCTRIG TRIGSTAT OCTRIS OCTSEL2 OCTSEL1 OCTSEL0 ENFLT0 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 OC32 OCTRIG TRIGSTAT OCTRIS OCTSEL2 OCTSEL1 OCTSEL0 ENFLT0 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 OC32 OCTRIG TRIGSTAT OCTRIS OCTSEL2 OCTSEL1 OCTSEL0 ENFLT0 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 Resets 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 Timer Value Register OCSIDL OCINV OCTSEL2 OCTSEL1 OCTSEL0 OC32 ENFLT0 OCTRIG TRIGSTAT Output Compare Secondary Register Output Compare Register Timer Value Register OCTRIS OCFLT0 TRIGMODE OCM2 OCM1 OCM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 xxxx 0000 0000 0000 0000 xxxx
OUTPUT COMPARE REGISTER
File Name
Addr
OC1CON1
0190
OC1CON2
0192
FLTMD
FLTOUT FLTTRIEN
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
DS39897B-page
Output Compare Secondary Register Output Compare Register
OC1RS
0194
OC1R
0196
OC1TMR
0198
OC2CON1
019A
OC2CON2
019C
FLTMD
FLTOUT FLTTRIEN
OC2RS
019E
OC2R
01A0
OC2TMR
01A2
OC3CON1
01A4
OC3CON2
01A6
FLTMD
FLTOUT FLTTRIEN
OC3RS
01A8
OC3R
01AA
OC3TMR
01AC
OC4CON1
01AE
OC4CON2
01B0
FLTMD
FLTOUT FLTTRIEN
OC4RS
01B2
OC4R
01B4
OC4TMR
01B6
PIC24FJ256GB110 FAMILY
OC5CON1
01B8
OC5CON2
01BA
FLTMD
FLTOUT FLTTRIEN
OC5RS
01BC
OC5R
01BE
OC5TMR
01C0
OC6CON1
01C2
OC6CON2
01C4
FLTMD
FLTOUT FLTTRIEN
OC6RS
01C6
OC6R
01C8
OC6TMR
01CA
OC7CON1
01CC
OC7CON2
01CE
FLTMD
FLTOUT FLTTRIEN
OC7RS
01D0
OC7R
01D2
OC7TMR
01D4
2008 Microchip Technology Inc.
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-8:
OCSIDL OCINV Output Compare Secondary Register Output Compare Register Timer Value Register OCSIDL OCINV Output Compare Secondary Register Output Compare Register Timer Value Register OC32 OCTRIG TRIGSTAT OCTRIS OCTSEL2 OCTSEL1 OCTSEL0 ENFLT0 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 OC32 OCTRIG TRIGSTAT OCTRIS OCTSEL2 OCTSEL1 OCTSEL0 ENFLT0 OCFLT0 TRIGMODE OCM2 OCM1 OCM0
OUTPUT COMPARE REGISTER (CONTINUED)
Resets 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 xxxx
File Name
Addr
OC8CON1
01D6
OC8CON2
01D8
FLTMD
FLTOUT FLTTRIEN
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
OC8RS
01DA
OC8R
01DC
OC8TMR
01DE
OC9CON1
01E0
2008 Microchip Technology Inc.
I2CSIDL I2CSIDL SCLREL IPMIEN A10M DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV ACKDT GCSTAT SCLREL IPMIEN A10M DISSLW SMEN ADD10 GCEN IWCOL STREN I2COV ACKDT GCSTAT ADD10 IWCOL I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN I2COV ACKDT Receive Register Transmit Register Baud Rate Generator Register ACKEN Address Register Address Mask Register Receive Register Transmit Register Baud Rate Generator Register ACKEN Address Register Address Mask Register Receive Register Transmit Register Baud Rate Generator Register ACKEN Address Register Address Mask Register RCEN RSEN RCEN RSEN RCEN RSEN
OC9CON2
01E2
FLTMD
FLTOUT FLTTRIEN
OC9RS
01E4
OC9R
01E6
OC9TMR
01E8
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-9:
I2CREGISTER
Resets 0000 00FF 0000 1000 0000 0000 0000 0000 00FF 0000 1000 0000 0000 0000 0000 00FF 0000 1000 0000 0000 0000
File Name
Addr
I2C1RCV
0200
I2C1TRN
0202
I2C1BRG
0204
PIC24FJ256GB110 FAMILY
I2C1CON
0206
I2CEN
I2C1STAT
0208
ACKSTAT TRSTAT
I2C1ADD
020A
I2C1MSK
020C
I2C2RCV
0210
I2C2TRN
0212
I2C2BRG
0214
I2C2CON
0216
I2CEN
I2C2STAT
0218
ACKSTAT TRSTAT
I2C2ADD
021A
I2C2MSK
021C
I2C3RCV
0270
I2C3TRN
0272
I2C3BRG
0274
I2C3CON
0276
I2CEN
I2C3STAT
0278
ACKSTAT TRSTAT
I2C3ADD
027A
I2C3MSK
027C
DS39897B-page
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-10:
USIDL UTXISEL0 Baud Rate Generator Prescaler Register UTXISEL0 Baud Rate Generator Prescaler Register UTXISEL0 Baud Rate Generator Prescaler Register UTXISEL0 Baud Rate Generator Prescaler Register UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN USIDL IREN RTSMD UEN1 UEN0 WAKE LPBACK ABAUD RXINV RIDLE BRGH PERR PDSEL1 FERR PDSEL0 OERR STSEL URXDA Receive Register Transmit Register UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR USIDL IREN RTSMD UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 FERR PDSEL0 OERR STSEL URXDA Receive Register Transmit Register UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR USIDL IREN RTSMD UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 OERR STSEL URXDA Receive Register Transmit Register UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA IREN RTSMD UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL Resets 0000 0110 xxxx 0000 0000 0000 0110 xxxx 0000 0000 0000 0110 xxxx 0000 0000 0000 0110 xxxx Receive Register 0000 0000
UART REGISTER MAPS
File Name
Addr
U1MODE
0220
UARTEN
U1STA
0222
UTXISEL1 UTXINV
DS39897B-page
Transmit Register SPISIDL SPIFPOL DISSCK DISSCK DISSDO DISSDO MODE16 SPISIDL SPIFPOL SPISIDL SPIFPOL DISSCK DISSDO MODE16 SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SSEN SRMPT SSEN Transmit Receive Buffer SPIBEC2 SPIBEC1 SPIBEC0 MODE16 SRMPT SSEN Transmit Receive Buffer SPIROV SRXMPT MSTEN SISEL2 SPRE2 SISEL1 SPRE1 SISEL0 SPRE0 SPITBF PPRE1 SPIFE SPIRBF PPRE0 SPIBEN SPIROV SPIROV SRXMPT MSTEN SRXMPT MSTEN SISEL2 SPRE2 SISEL2 SPRE2 SISEL1 SPRE1 SISEL1 SPRE1 SISEL0 SPRE0 SISEL0 SPRE0 SPITBF PPRE1 SPIFE SPITBF PPRE1 SPIFE SPIRBF PPRE0 SPIBEN SPIRBF PPRE0 SPIBEN Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Transmit Receive Buffer SPIBEC2 SPIBEC1 SPIBEC0
U1TXREG
0224
U1RXREG
0226
U1BRG
0228
U2MODE
0230
UARTEN
U2STA
0232
UTXISEL1 UTXINV
U2TXREG
0234
U2RXREG
0236
U2BRG
0238
U3MODE
0250
UARTEN
U3STA
0252
UTXISEL1 UTXINV
U3TXREG
0254
U3RXREG
0256
U3BRG
0258
U4MODE
02B0
UARTEN
U4STA
02B2
UTXISEL1 UTXINV
U4TXREG
02B4
U4RXREG
02B6
U4BRG
02B8
PIC24FJ256GB110 FAMILY
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-11:
REGISTER MAPS
File Name
Addr
SPI1STAT
0240
SPIEN
SPI1CON1
0242
SPI1CON2
0244
FRMEN
SPIFSD
SPI1BUF
0248
SPI2STAT
0260
SPIEN
SPI2CON1
0262
SPI2CON2
0264
FRMEN
SPIFSD
SPI2BUF
0268
SPI3STAT
0280
SPIEN
SPI3CON1
0282
SPI3CON2
0284
FRMEN
SPIFSD
SPI3BUF
0288
2008 Microchip Technology Inc.
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-12:
ODA10 ODA9 ODA7 ODA6 ODA5 ODA4 ODA3 ODA2 ODA1 LATA10 LATA9 LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 RA10 TRISA10 TRISA9 TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 LATA0 ODA0 7(2) 6(2) 5(2) 4(2) 3(2) Bit2(2) 1(2) 0(2)
PORTA REGISTER MAP(1)
Resets 36FF xxxx xxxx 0000
File Name
Addr
TRISA
02C0
TRISA15 TRISA14
PORTA
02C2
RA15
RA14
LATA
02C4
LATA15
LATA14
ODCA
02C6
ODA15
ODA14
2008 Microchip Technology Inc.
TRISB10 RB10 LATB10 ODB10 ODB9 ODB8 ODB7 ODB6 ODB5 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 ODB4 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 LATB3 ODB3 TRISB2 LATB2 ODB2 TRISB1 LATB1 ODB1 TRISB0 LATB0 ODB0 RB13 LATB13 ODB13 ODB12 ODB11 LATB12 LATB11 RB12 RB11 4(1) TRISC4 LATC4 ODC4 3(2) TRISC3 LATC3 ODC3 2(1) TRISC2 LATC2 ODC2 1(2) TRISC1 LATC1 ODC1 RC13 LATC13 ODC13 ODC12 LATC12 RC12(3) 13(1) 12(1) TRISD9 RD10 LATD10 ODD11 ODD10 LATD9 ODD9 TRISD8 LATD8 ODD8 TRISD7 LATD7 ODD7 TRISD6 LATD6 ODD6 TRISD5 LATD5 ODD5 TRISD4 LATD4 ODD4 TRISD3 LATD3 ODD3 TRISD2 LATD2 ODD2 TRISD1 LATD1 ODD1 TRISD0 LATD0 ODD0 RD13 LATD13 ODD13 ODD12 LATD12 RD12 RD11 LATD11
Legend: Note
unimplemented, read `0'. Reset values shown hexadecimal. Reset values shown 100-pin devices. PORTA associated bits unimplemented 64-pin devices read `0'. Bits available 80-pin 100-pin devices only, unless otherwise noted. Bits implemented 100-pin devices only; otherwise read `0'.
TABLE 3-13:
PORTB REGISTER
Resets FFFF xxxx xxxx 0000
File Name
Addr
TRISB
02C8
TRISB15 TRISB14 TRISB13 TRISB12 TRISB11
PORTB
02CA
RB15
RB14
LATB
02CC
LATB15
LATB14
ODCB
02CE
ODB15
ODB14
Legend:
Reset values shown hexadecimal.
TABLE 3-14:
PORTC REGISTER
Resets F01E xxxx xxxx 0000
PIC24FJ256GB110 FAMILY
File Name
Addr
TRISC
02D0
TRISC15 TRISC14 TRISC13 TRISC12
PORTC
02D2
RC15(3,4)
RC14
LATC
02D4
LATC15
LATC14
ODCC
02D6
ODC15
ODC14
Legend: Note
unimplemented, read `0'. Reset values shown hexadecimal. Reset values shown 100-pin devices. Bits unimplemented 64-pin 80-pin devices; read `0'. Bits unimplemented 64-pin devices; read `0'. RC12 RC15 only available when primary oscillator disabled when mode selected (POSCMD1:POSCMD0 Configuration bits 00); otherwise read `0'. RC15 only available when POSCMD1:POSCMD0 Configuration bits OSCIOFN Configuration
TABLE 3-15:
PORTD REGISTER
Resets FFFF xxxx xxxx 0000
File Name
Addr
15(1)
14(1)
TRISD
02D8
TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10
PORTD
02DA
RD15
RD14
LATD
02DC
LATD15
LATD14
DS39897B-page
ODCD
02DE
ODD15
ODD14
Legend: Note
unimplemented, read `0'. Reset values shown hexadecimal. Reset values shown 100-pin devices. Bits unimplemented 64-pin devices; read `0'.
TABLE 3-16:
ODE9 ODE8 ODE7 ODE6 ODE5 ODE4 ODE3 ODE2 ODE1 LATE9 LATE8 LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 ODE0 TRISE9 TRISE8 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 9(1) 8(1) Resets 03FF xxxx xxxx 0000
PORTE REGISTER
File Name
Addr
TRISE
02E0
DS39897B-page
13(1) ODF8 ODF7 ODF6 ODF5 ODF4 LATF8 LATF7 LATF6 LATF5 LATF4 LATF3 ODF3 TRISF8 TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF13 RF13 LATF13 ODF13 ODF12 LATF12 RF12 TRISF12 12(1) 8(2) 7(2) 6(2) 2(2) TRISF2 LATF2 ODF2 TRISF1 LATF1 ODF1 TRISF0 LATF0 ODF0 Resets 31FF xxxx xxxx 0000 13(1) ODG9 ODG8 LATG9 LATG8 LATG7 ODG7 TRISG9 TRISG8 TRISG7 TRISG6 LATG6 ODG6 12(1) TRISG3 LATG3 ODG3 TRISG2 LATG2 ODG2 1(1) TRISG1 LATG1 ODG1 0(1) TRISG0 LATG0 ODG0 Resets F3CF xxxx xxxx 0000 RG13 LATG13 ODG13 ODG12 LATG12 RG12 RTSECSEL PMPTTL Resets 0000
PORTE
02E2
LATE
02E4
ODCE
02E6
Legend: Note
unimplemented, read `0'. Reset values shown hexadecimal. Reset values shown 100-pin devices. Bits unimplemented 64-pin devices; read `0'.
TABLE 3-17:
PORTF REGISTER
File Name
Addr
TRISF
02E8
PORTF
02EA
LATF
02EC
ODCF
02EE
Legend: Note
unimplemented, read `0'. Reset values shown hexadecimal. Reset values shown 100-pin devices. Bits unimplemented 64-pin 80-pin devices; read `0'. Bits unimplemented 64-pin devices; read `0'.
PIC24FJ256GB110 FAMILY
TABLE 3-18:
PORTG REGISTER
File Name
Addr
15(1)
14(1)
TRISG
02F0
TRISG15 TRISG14 TRISG13 TRISG12
PORTG
02F2
RG15
RG14
LATG
02F4
LATG15
LATG14
ODCG
02F6
ODG15
ODG14
Legend: Note
unimplemented, read `0'. Reset values shown hexadecimal. Reset values shown 100-pin devices. Bits unimplemented 64-pin 80-pin devices; read `0'.
TABLE 3-19:
CONFIGURATION REGISTER
File Name
Addr
PADCFG1
02FC
2008 Microchip Technology Inc.
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-20:
Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer VCFG0 ADCS7 CH0NA PCFG7 CSSL7 PCFG6 CSSL6 PCFG13 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 ADCS6 CSCNA BUFS ADSIDL FORM1 FORM0 SSRC2 SSRC1 SSRC0 SMPI3 ADCS5 PCFG5 CSSL5 SMPI2 ADCS4 CH0SA4 PCFG4 CSSL4 SMPI1 ADCS3 CH0SA3 PCFG3 CSSL3 ASAM SMPI0 ADCS2 CH0SA2 PCFG2 CSSL2 SAMP BUFM ADCS1 CH0SA1 PCFG17 PCFG1 CSSL1 CSS17 DONE ALTS ADCS0 CH0SA0 PCFG16 PCFG0 CSSL0 CSS16
REGISTER
Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000
File Name
Addr
ADC1BUF0
0300
ADC1BUF1
0302
ADC1BUF2
0304
ADC1BUF3
0306
ADC1BUF4
0308
ADC1BUF5
030A
2008 Microchip Technology Inc.
CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0
ADC1BUF6
030C
ADC1BUF7
030E
ADC1BUF8
0310
ADC1BUF9
0312
ADC1BUFA
0314
ADC1BUFB
0316
ADC1BUFC
0318
ADC1BUFD
031A
ADC1BUFE
031C
ADC1BUFF
031E
AD1CON1
0320
ADON
AD1CON2
0322
VCFG2
VCFG1
AD1CON3
0324
ADRC
AD1CHS0
0328
CH0NB
PIC24FJ256GB110 FAMILY
AD1PCFGH
032A
AD1PCFGL
032C
PCFG15
PCFG14
AD1CSSL
0330
CSSL15
CSSL14
AD1CSSH
0332
Legend:
unimplemented, read `0', reserved, maintain `0'. Reset values shown hexadecimal.
TABLE 3-21:
CTMU REGISTER
Resets 0000 0000
File Name
Addr
CTMUCON
033C CTMUEN
CTMUICON 033E
ITRIM5
ITRIM4
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
DS39897B-page
TABLE 3-22:
UTEYE UOEMON PID3 PID2 PID1 LSPDEN(1) JSTATE(1) TOKBUSY RESET PKTDIS ENDPT3 ENDPT2 ENDPT1 ENDPT0 BTSEE DMAEE BTOEE DFN8EE HOSTEN HOSTEN BTSEE DMAEE BTOEE DFN8EE BTSEF DMAEF BTOEF DFN8EF BTSEF DMAEF BTOEF DFN8EF STALLIE ATTACHIE(1) RESUMEIE IDLEIE TRNIE SOFIE CRC16EF CRC16EF CRC16EE CRC16EE PPBI RESUME RESUME STALLIE RESUMEIE IDLEIE TRNIE SOFIE STALLIF ATTACHIF(1) RESUMEIF IDLEIF TRNIF SOFIF STALLIF RESUMEIF IDLEIF TRNIF SOFIF UERRIF UERRIF UERRIE UERRIE CRC5EF EOFEF(1) CRC5EE EOFEE(1) PPBRST PPBRST UACTPND USLPGRD USUSPND DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG LSTATE SESVD SESEND IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE VBUSVD VBUSDIS USBPWR URSTIF DETACHIF(1) URSTIE PIDEF PIDEF PIDEE PIDEE USBEN SOFEN(1) IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF VBUSVDIF VBUSVDIE Resets 0000 0000 0000 0000 0000 0000 0000 0000 DETACHIE(1) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PID0 USBSIDL PUVBUS Start-Of-Frame Count Register PPB1 EXTI2CEN UVBUSDIS UVCMPDIS PPB0 UTRDIS 0000 0000 0000 0000
REGISTER
File Name
Addr
U1OTGIR
0480
U1OTGIE
0482
DS39897B-page
Device Address (DEVADDR) Register Buffer Descriptor Table Base Address Register Frame Count Register Byte Frame Count Register High Byte
U1OTGSTAT
0484
U1OTGCON
0486
U1PWRC
0488
U1IR
048A(1)
U1IE
048C(1)
U1EIR
048E(1)
U1EIE
0490(1)
U1STAT
0492
U1CON
0494(1)
U1ADDR
0496
U1BDTP1
0498
U1FRML
049A
U1FRMH
049C
PIC24FJ256GB110 FAMILY
U1TOK(2)
049E
U1SOF(2)
04A0
U1CNFG1
04A6
U1CNFG2
04A8
Legend: Note
unimplemented, read `0'. Reset values shown hexadecimal. Alternate register definitions when module operating Host mode. This register available Host mode only.
2008 Microchip Technology Inc.
TABLE 3-22:
Power Supply Duty Cycle Register PWMPOL CNTEN EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPCONDIS EPRXEN EPCONDIS EPRXEN EPCONDIS EPRXEN EPCONDIS EPRXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPCONDIS EPRXEN EPTXEN EPCONDIS EPRXEN EPTXEN EPCONDIS EPRXEN EPTXEN EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPCONDIS EPRXEN EPTXEN EPSTALL EPCONDIS EPRXEN EPTXEN EPSTALL EPCONDIS EPRXEN EPTXEN EPSTALL LSPD(1) EPCONDIS EPRXEN EPTXEN EPSTALL RETRYDIS(1) EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
REGISTER (CONTINUED)
File Name
Addr
U1EP0
04AA
U1EP1
04AC
U1EP2
04AE
U1EP3
04B0
U1EP4
04B2
U1EP5
04B4
U1EP6
04B6
2008 Microchip Technology Inc.
Power Supply Period Register PSIDL IRQM0 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 INCM1 INCM0 MODE16 MODE1 ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN MODE0 ADDR8 CSF1 WAITB1 ADDR7 CSF0 WAITB0 ADDR6 WAITM3 ADDR5 CS2P WAITM2 ADDR4 CS1P WAITM1 ADDR3 WAITM0 ADDR2 WRSP WAITE1 ADDR1 RDSP WAITE0 ADDR0 Parallel Port Data Register (Buffers Parallel Port Data Register (Buffers Parallel Port Data Register (Buffers Parallel Port Data Register (Buffers PTEN13 IB3F PTEN12 PTEN11 PTEN10 IB2F PTEN9 IB1F PTEN8 IB0F PTEN7 PTEN6 OBUF PTEN5 PTEN4 PTEN3 OB3E PTEN2 OB2E PTEN1 OB1E PTEN0 OB0E
U1EP7
04B8
U1EP8
04BA
U1EP9
04BC
U1EP10
04BE
U1EP11
04C0
U1EP12
04C2
U1EP13
04C4
U1EP14
04C6
U1EP15
04C8
U1PWMRRS
04CC
U1PWMCON
04CE
PWMEN
PIC24FJ256GB110 FAMILY
Legend: Note
unimplemented, read `0'. Reset values shown hexadecimal. Alternate register definitions when module operating Host mode. This register available Host mode only.
TABLE 3-23:
PARALLEL MASTER/SLAVE PORT REGISTER
Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000
File Name Addr
PMCON
0600
PMPEN
PMMODE
0602
BUSY
IRQM1
PMADDR
0604
PMDOUT1
PMDOUT2 0606
PMDIN1
0608
PMDIN2
060A
PMAEN
060C
PTEN15
PTEN14
PMSTAT
060E
IBOV
DS39897B-page
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-24:
Alarm Value Register Window Based ALRMPTR<1:0> AMASK3 RTCC Value Register Window Based RTCPTR<1:0> RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 Resets xxxx 0000 xxxx 0000
REAL-TIME CLOCK CALENDAR REGISTER
File Name
Addr
ALRMVAL
0620
ALCFGRPT
0622
ALRMEN
CHIME
DS39897B-page
CPOL CEVT COUT EVPOL1 EVPOL0 CREF CEVT COUT EVPOL1 EVPOL0 CREF CEVT COUT EVPOL1 EVPOL0 CREF CPOL CPOL CVREN CVROE CVRR CVRSS CVR3 C3EVT C2EVT C1EVT C3OUT CVR2 C2OUT CVR1 CCH1 CCH1 CCH1 C1OUT CVR0 CCH0 CCH0 CCH0 Resets 0000 0000 0000 0000 0000 CSIDL Data Input Register Result Register VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRCGO PLEN3 PLEN2 PLEN1 PLEN0 Resets 0040 0000 0000 0000
RTCVAL
0624
RCFGCAL
0626
RTCEN
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-25:
COMPARATORS REGISTER
File Name
Addr
CMSTAT
0630
CMIDL
CVRCON
0632
CM1CON
0634
CM2CON
0636
CM3CON
0638
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-26:
REGISTER
File Name
Addr
PIC24FJ256GB110 FAMILY
CRCCON
0640
CRCXOR
0642
CRCDAT
0644
CRCWDAT
0646
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
2008 Microchip Technology Inc.
TABLE 3-27:
INT1R5 INT3R5 T1CKR5 T3CKR5 T5CKR5 IC2R5 IC4R5 IC6R5 IC8R5 OCFBR5 IC9R5 U3RXR5 U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 U2CTSR5 U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0 SCK1R5 U3CTSR5 U3CTSR4 U3CTSR3 U3CTSR2 U3CTSR1 U3CTSR0 SCK2R5 U4CTSR5 U4CTSR4 U4CTSR3 U4CTSR2 U4CTSR1 U4CTSR0 SCK3R5 RP1R5 RP3R5 RP5R5(1) RP7R5 RP9R5 RP11R5 RP13R5 RP17R5 RP19R5 RP21R5 RP23R5 RP25R5 RP27R5 RP29R5 RP29R4 RP29R3 RP27R4 RP27R3 RP25R4 RP25R3 RP23R4 RP23R3 RP21R4 RP21R3 RP21R2 RP23R2 RP25R2 RP27R2 RP29R2 RP19R4 RP19R3 RP19R2 RP17R4 RP17R3 RP17R2 RP17R1 RP19R1 RP21R1 RP23R1 RP25R1 RP27R1 RP29R1 RP13R4 RP13R3 RP13R2 RP13R1 RP11R4 RP11R3 RP11R2 RP11R1 RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 RP11R0 RP13R0 RP17R0 RP19R0 RP21R0 RP23R0 RP25R0 RP27R0 RP29R0 RP7R4 RP7R3 RP7R2 RP7R1 RP7R0 RP5R4(1) RP5R3(1) RP5R2(1) RP5R1(1) RP5R0(1) RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 SCK3R4 SCK3R3 SCK3R2 SCK3R1 SCK3R0 SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 SS1R5 SDI2R5 SS2R5 U4RXR5 SDI3R5 SS3R5 RP0R5 RP2R5 RP4R5 RP6R5 RP8R5 RP10R5 RP12R5 RP14R5 RP16R5 RP18R5 RP20R5 RP22R5 RP24R5 RP26R5 RP28R5 RP30R5 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 SDI1R5 U2RXR5 U1RXR5 U1RXR4 U2RXR4 SDI1R4 SS1R4 SDI2R4 SS2R4 U4RXR4 SDI3R4 SS3R4 RP0R4 RP2R4 RP4R4 RP6R4 RP8R4 RP10R4 RP12R4 RP14R4 RP16R4 RP18R4 RP20R4 RP22R4 RP24R4 RP26R4 RP28R4 RP30R4 U3RXR4 U3RXR3 U3RXR2 U3RXR1 U3RXR0 IC9R4 IC9R3 IC9R2 IC9R1 IC9R0 U1RXR3 U2RXR3 SDI1R3 SS1R3 SDI2R3 SS2R3 U4RXR3 SDI3R3 SS3R3 RP0R3 RP2R3 RP4R3 RP6R3 RP8R3 RP10R3 RP12R3 RP14R3 RP16R3 RP18R3 RP20R3 RP22R3 RP24R3 RP26R3 RP28R3 RP30R3 OCFBR4 OCFBR3 OCFBR2 OCFBR1 OCFBR0 OCFAR5 OCFAR4 OCFAR3 IC8R4 IC8R3 IC8R2 IC8R1 IC8R0 IC7R5 IC7R4 IC7R3 IC6R4 IC6R3 IC6R2 IC6R1 IC6R0 IC5R5 IC5R4 IC5R3 IC4R4 IC4R3 IC4R2 IC4R1 IC4R0 IC3R5 IC3R4 IC3R3 IC3R2 IC5R2 IC7R2 OCFAR2 U1RXR2 U2RXR2 SDI1R2 SS1R2 SDI2R2 SS2R2 U4RXR2 SDI3R2 SS3R2 RP0R2 RP2R2 RP4R2 RP6R2 RP8R2 RP10R2 RP12R2 RP14R2 RP16R2 RP18R2 RP20R2 RP22R2 RP24R2 RP26R2 RP28R2 RP30R2 IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 IC1R5 IC1R4 IC1R3 IC1R2 T5CKR4 T5CKR3 T5CKR2 T5CKR1 T5CKR0 T4CKR5 T4CKR4 T4CKR3 T4CKR2 T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0 T2CKR5 T2CKR4 T2CKR3 T2CKR2 T1CKR4 T1CKR3 T1CKR2 T1CKR1 T1CKR0 INT4R5 INT4R4 INT4R3 INT4R2 INT4R1 T2CKR1 T4CKR1 IC1R1 IC3R1 IC5R1 IC7R1 OCFAR1 U1RXR1 U2RXR1 SDI1R1 SS1R1 SDI2R1 SS2R1 U4RXR1 SDI3R1 SS3R1 RP0R1 RP2R1 RP4R1 RP6R1 RP8R1 RP10R1 RP12R1 RP14R1 RP16R1 RP18R1 RP20R1 RP22R1 RP24R1 RP26R1 RP28R1 RP30R1 INT3R4 INT3R3 INT3R2 INT3R1 INT3R0 INT2R5 INT2R4 INT2R3 INT2R2 INT2R1 INT1R4 INT1R3 INT1R2 INT1R1 INT1R0 INT2R0 INT4R0 T2CKR0 T4CKR0 IC1R0 IC3R0 IC5R0 IC7R0 OCFAR0 U1RXR0 U2RXR0 SDI1R0 SS1R0 SDI2R0 SS2R0 U4RXR0 SDI3R0 SS3R0 RP0R0 RP2R0 RP4R0 RP6R0 RP8R0 RP10R0 RP12R0 RP14R0 RP16R0 RP18R0 RP20R0 RP22R0 RP24R0 RP26R0 RP28R0 RP30R0
PERIPHERAL SELECT REGISTER
Resets 3F00 3F3F 3F3F 3F3F 3F3F 3F3F 3F3F 3F3F 3F3F 3F3F 3F00 3F00 3F3F 3F3F 3F3F 3F3F 3F3F 003F 3F3F 3F3F 003F 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
File Name
Addr
RPINR0
0680
RPINR1
0682
RPINR2
0684
RPINR3
0686
RPINR4
0688
RPINR7
068E
2008 Microchip Technology Inc.
RP15R5(1) RP15R4(1) RP15R3(1) RP15R2(1) RP15R1(1) RP15R0(1) RP31R5(2) RP31R4(2) RP31R3(2) RP31R2(2) RP31R1(2) RP31R0(2)
RPINR8
0690
RPINR9
0692
RPINR10
0694
RPINR11
0696
RPINR15
069E
RPINR17
06A2
RPINR18
06A4
RPINR19
06A6
RPINR20
06A8
RPINR21
06AA
RPINR22
06AC
RPINR23
06AE
RPINR27
06B6
RPINR28
06B8
PIC24FJ256GB110 FAMILY
RPINR29
06BA
RPOR0
06C0
RPOR1
06C2
RPOR2
06C4
RPOR3
06C6
RPOR4
06C8
RPOR5
06CA
RPOR6
06CC
RPOR7
06CE
RPOR8
06D0
RPOR9
06D2
RPOR10
06D4
RPOR11
06D6
RPOR12
06D8
RPOR13
06DA
RPOR14
06DC
DS39897B-page
RPOR15
06DE
Legend: Note
unimplemented, read `0'. Reset values shown hexadecimal. Bits unimplemented 64-pin devices; read `0'. Bits unimplemented 64-pin 80-pin devices; read `0'.
TABLE 3-28:
COSC1 DOZE1 ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 TUN5 TUN4 TUN3 TUN2 TUN1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0 CPDIV1 CPDIV0 TUN0 COSC0 NOSC2 NOSC1 NOSC0 CLKLOCK IOLOCK LOCK POSCEN SOSCEN OSWEN VREGS EXTR SWDTEN WDTO SLEEP IDLE Resets Note Note 0100 0000 0000
SYSTEM REGISTER
File Name
Addr
RCON
0740
TRAPR
IOPUWR
OSCCON
0742
COSC2
DS39897B-page
WRERR ERASE Resets NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1) 0000 NVMKEY Register<7:0> T3MD IC6MD IC9MD CMPMD RTCCMD PMPMD CRCMD IC5MD IC4MD IC3MD IC2MD IC1MD OC8MD T2MD T1MD I2C1MD U2MD OC7MD UPWMMD U1MD OC6MD U4MD SPI2MD OC5MD SPI1MD OC4MD U3MD OC3MD I2C3MD REFOMD CTMUMD OC2MD I2C2MD LVDMD ADC1MD OC1MD USB1MD OC9MD SPI3MD Resets 0000 0000 0000 0000 0000 0000
CLKDIV
0744
DOZE2
OSCTUN
0748
REFOCON
074E
ROEN
Legend: Note
unimplemented, read `0'. Reset values shown hexadecimal. Reset value RCON register dependent type Reset event. Section "Resets" more information. Reset value OSCCON register dependent both type Reset event device configuration. Section "Oscillator Configuration" more information.
TABLE 3-29:
REGISTER
File Name
Addr
NVMCON
0760
WREN
NVMKEY
0766
Legend: Note
unimplemented, read `0'. Reset values shown hexadecimal. Reset value shown only. Value other Reset states dependent state memory write erase operations time Reset.
TABLE 3-30:
REGISTER
PIC24FJ256GB110 FAMILY
File Name
Addr
PMD1
0770
T5MD
T4MD
PMD2
0772
IC8MD
IC7MD
PMD3
0774
PMD4
0776
PMD5
0778
PMD6
077A
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
3.2.5 SOFTWARE STACK
addition working register, register PIC24F devices also used Software Stack Pointer. pointer always points first available free word grows from lower higher addresses. pre-decrements stack pops post-increments stack pushes, shown Figure 3-4. Note that push during CALL instruction, zero-extended before push, ensuring that always clear. Note: push during exception processing will concatenate register prior push.
Interfacing Program Data Memory Spaces
PIC24F architecture uses 24-bit wide program space 16-bit wide data space. architecture also modified Harvard scheme, meaning that data also present program space. this data successfully, must accessed that preserves alignment information both spaces. Aside from normal execution, PIC24F architecture provides methods which program space accessed during operation: Using table instructions access individual bytes words anywhere program space Remapping portion program space into data space (program space visibility) Table instructions allow application read write small areas program memory. This makes method ideal accessing data tables that need updated from time time. also allows access bytes program word. remapping method allows application access large block data read-only basis, which ideal look from large table static data. only access least significant word program word.
Stack Pointer Limit Value register (SPLIM), associated with Stack Pointer, sets upper address boundary stack. SPLIM uninitialized Reset. case Stack Pointer, SPLIM<0> forced because stack operations must word-aligned. Whenever generated using source destination pointer, resulting address compared with value SPLIM. contents Stack Pointer (W15) SPLIM register equal, push operation performed, stack error trap will occur. stack error trap will occur subsequent push operation. Thus, example, desirable cause stack error trap when stack grows beyond address 2000h RAM, initialize SPLIM with value, 1FFEh. Similarly, Stack Pointer underflow (stack error) trap generated when Stack Pointer address found less than 0800h. This prevents stack from interfering with Special Function Register (SFR) space. write SPLIM register should immediately followed indirect read operation using W15.
3.3.1
ADDRESSING PROGRAM SPACE
Since address ranges data program spaces bits, respectively, method needed create 23-bit 24-bit program address from 16-bit data registers. solution depends interface method used. table operations, 8-bit Table Memory Page Address register (TBLPAG) used define word region within program space. This concatenated with 16-bit arrive full 24-bit program space address. this format, Most Significant TBLPAG used determine operation occurs user memory (TBLPAG<7> configuration memory (TBLPAG<7> remapping operations, 8-bit Program Space Visibility Page Address register (PSVPAG) used define word page program space. When Most Significant `1', PSVPAG concatenated with lower bits form 23-bit program space address. Unlike table operations, this limits remapping operations strictly user memory area. Table 3-31 Figure show program created table operations remapping accesses from data Here, P<23:0> refers program space word, whereas D<15:0> refers data space word.
FIGURE 3-4:
0000h
CALL STACK FRAME
Stack Grows Towards Higher Address
PC<15:0> 000000000 PC<22:16> <Free Word>
(before CALL) (after CALL) [-W15] PUSH [W15++]
2008 Microchip Technology Inc.
DS39897B-page
PIC24FJ256GB110 FAMILY
TABLE 3-31: PROGRAM SPACE ADDRESS CONSTRUCTION
Access Space User User Configuration Program Space Visibility (Block Remap/Read) Note User Program Space Address <23> TBLPAG<7:0> 0xxx xxxx TBLPAG<7:0> 1xxx xxxx PSVPAG<7:0> xxxx xxxx <22:16> <15> PC<22:1> xxxx xxxx xxxx xxxx xxx0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<14:0>(1) xxxx xxxx xxxx <14:1> Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write)
Data EA<15> always this case, used calculating program space address. address PSVPAG<0>.
FIGURE 3-5:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter Bits
Table Operations(2)
TBLPAG Bits Bits Bits
Select Program Space Visibility(1) (Remapping) PSVPAG Bits
Bits Bits
User/Configuration Space Select
Byte Select
Note program space addresses always fixed order maintain word alignment data program data spaces. Table operations required word-aligned. Table read operations permitted configuration memory space.
DS39897B-page
2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
3.3.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS
TBLRDH (Table Read High): Word mode, maps entire upper word program address (P<23:16>) data address. Note that D<15:8>, `phantom' byte, will always `0'. Byte mode, maps upper lower byte program word D<7:0> data address, above. Note that data will always when upper `phantom' byte selected (byte select
TBLRDL TBLWTL instructions offer direct method reading writing lower word address within program space without going through data space. TBLRDH TBLWTH instructions only method read write upper bits program space word data. incremented each successive 24-bit program word. This allows program memory addresses directly data space addresses. Program memory thus regarded two, 16-bit word-wide address spaces, residing side side, each with same address range. TBLRDL TBLWTL access space which contains least significant data word, TBLRDH TBLWTH access space which contains upper data byte. table instructions provided move byte word-sized (16-bit) data from program space. Both function either byte word operations. TBLRDL (Table Read Low): Word mode, maps lower word program space location (P<15:0>) data address (D<15:0>). Byte mode, either upper lower byte lower program word mapped lower byte data address. upper byte selected when byte select `1'; lower byte selected when `0'.
similar fashion, table instructions, TBLWTH TBLWTL, used write individual bytes words program space address. details their operation explained Section "Flash Program Memory". table operations, area program memory space accessed determined Table Memory Page Address register (TBLPAG). TBLPAG covers entire program memory space device, including user configuration spaces. When TBLPAG<7> table page located user memory space. When TBLPAG<7> page located configuration space. Note: Only table read operations will execute configuration memory space, only then, implemented areas such Device Table write operations allowed.
FIGURE 3-6:
TBLPAG
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
Data EA<15:0> 000000h 00000000 020000h 030000h 00000000 00000000 00000000 `Phantom' Byte
TBLRDH.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.W address table operation determined data within page defined TBLPAG register. Only read operations shown; write operations also valid user memory area.
800000h
2008 Microchip Technology Inc.
DS39897B-page
PIC24FJ256GB110 FAMILY
3.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY
24-bit program word used contain data. upper bits program space locations used data should programmed with `1111 1111' `0000 0000' force NOP. This prevents possible issues should area code ever accidentally executed. Note: access temporarily disabled during table reads/writes.
upper Kbytes data space optionally mapped into word page program space. This provides transparent access stored constant data from data space without need special instructions (i.e., TBLRDL/H). Program space access through data space occurs Most Significant data space `1', program space visibility enabled setting Control register (CORCON<2>). location program memory space mapped into data space determined Program Space Visibility Page Address register (PSVPAG). This 8-bit register defines possible pages words program space. effect, PSVPAG functions upper bits program memory address, with bits functioning lower bits. Note that incrementing each program memory word, lower bits data space addresses directly lower bits corresponding program space addresses. Data reads this area additional cycle instruction being executed, since program memory fetches required. Although each data space address, 8000h higher, maps directly into corresponding program memory address (see Figure 3-7), only lower bits
operations that executed outside REPEAT loop, MOV.D instructions will require instruction cycle addition specified execution time. other instructions will require instruction cycles addition specified execution time. operations that which executed inside REPEAT loop, there will some instances that require instruction cycles addition specified execution time instruction: Execution first iteration Execution last iteration Execution prior exiting loop interrupt Execution upon re-entering loop after interrupt serviced other iteration REPEAT loop will allow instruction accessing data, using PSV, execute single cycle.
FIGURE 3-7:
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> EA<15>
Program Space
PSVPAG 000000h 010000h 018000h data page designated PSVPAG mapped into upper half data memory space.
Data Space
0000h Data EA<14:0>
8000h
Area .while lower bits specify exact address within area. This corresponds exactly same lower bits actual program space address.
FFFFh
800000h
DS39897B-page
2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
Note:
FLASH PROGRAM MEMORY
This data sheet summarizes features this group PIC24F devices. intended comprehensive reference source. more information, refer "PIC24F Family Reference Manual", "Section Program Memory" (DS39715).
RTSP accomplished using TBLRD (table read) TBLWT (table write) instructions. With RTSP, user write program memory data blocks instructions (192 bytes) time, erase program memory blocks instructions (1536 bytes) time.
Table Instructions Flash Programming
PIC24FJ256GB110 family devices contains internal Flash program memory storing executing application code. programmed four ways: In-Circuit Serial Programming(ICSPTM) Run-Time Self-Programming (RTSP) JTAG Enhanced In-Circuit Serial Programming(Enhanced ICSPTM)
Regardless method used, programming Flash memory done with table read table write instructions. These allow direct read write access program memory space from data memory while device normal operating mode. 24-bit target address program memory formed using TBLPAG<7:0> bits Effective Address (EA) from register specified table instruction, shown Figure 4-1. TBLRDL TBLWTL instructions used read write bits<15:0> program memory. TBLRDL TBLWTL access program memory both Word Byte modes. TBLRDH TBLWTH instructions used read write bits<23:16> program memory. TBLRDH TBLWTH also access program memory Word Byte mode.
ICSP allows PIC24FJ256GB110 family device serially programmed while application circuit. This simply done with lines programming clock programming data (which named PGECx PGEDx, respectively), three other lines power (VDD), ground (VSS) Master Clear (MCLR). This allows customers manufacture boards with unprogrammed devices then program microcontroller just before shipping product. This also allows most recent firmware custom firmware programmed.
FIGURE 4-1:
ADDRESSING TABLE REGISTERS
Bits Using Program Counter Program Counter
Working Using Table Instruction TBLPAG Bits Bits
User/Configuration Space Select
24-Bit
Byte Select
2008 Microchip Technology Inc.
DS39897B-page
PIC24FJ256GB110 FAMILY
RTSP Operation JTAG Operation
PIC24F Flash program memory array organized into rows instructions bytes. RTSP allows user erase blocks eight rows (512 instructions) time program time. also possible program single words. 8-row erase blocks single write blocks edge-aligned, from beginning program memory, boundaries 1536 bytes bytes, respectively. When data written program memory using TBLWT instructions, data written directly memory. Instead, data written using table writes stored holding latches until programming sequence executed. number TBLWT instructions executed write will successfully performed. However, TBLWT instructions required write full memory. ensure that data corrupted during write, unused addresses should programmed with FFFFFFh. This because holding latches reset unknown state, addresses left Reset state, they overwrite locations rows which were rewritten. basic sequence RTSP programming Table Pointer, then series TBLWT instructions load buffers. Programming performed setting control bits NVMCON register. Data loaded order holding registers written multiple times before performing write operation. Subsequent writes, however, will wipe previous writes. Note: Writing location multiple times without erasing recommended. PIC24F family supports JTAG programming boundary scan. Boundary scan improve manufacturing process verifying pin-to-PCB connectivity. Programming performed with industry standard JTAG programmers supporting Serial Vector Format (SVF).
Enhanced In-Circuit Serial Programming
Enhanced In-Circuit Serial Programming uses on-board bootloader, known program executive, manage programming process. Using data frame format, program executive erase, program verify program memory. more information Enhanced ICSP, device programming specification.
Control Registers
There SFRs used read write program Flash memory: NVMCON NVMKEY. NVMCON register (Register 4-1) controls which blocks erased, which memory type programmed when programming cycle starts. NVMKEY write-only register that used write protection. start programming erase sequence, user must consecutively write NVMKEY register. Refer Section "Programming Operations" further details.
Programming Operations
table write operations single-word writes instruction cycles), because only buffers written. programming cycle required programming each row.
complete programming sequence necessary programming erasing internal Flash RTSP mode. During programming erase operation, processor stalls (waits) until operation finished. Setting (NVMCON<15>) starts operation automatically cleared when operation finished.
DS39897B-page
2008 Microchip Technology Inc.
PIC24FJ256GB110 FAMILY
REGISTER 4-1:
R/SO-0(1) Legend: Readable Value Only Writable Unimplemented bit, read cleared unknown R/W-0(1) ERASE R/W-0(1) NVMOP3(2) R/W-0(1) NVMOP2(2) R/W-0(1) NVMOP1(2)
NVMCON: FLASH MEMORY CONTROL REGISTER
R/W-0(1) WRERR R/W-0(1) NVMOP0(2) WREN
R/W-0(1)
Write Control bit(1) Initiates Flash memory program erase operation. operation self-timed cleared hardware once operation complete. Program erase operation complete inactive WREN: Write Enable bit(1) Enable Flash program/erase operations Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag bit(1) improper program erase sequence attempt termination occurred (bit automatically attempt bit) program erase operation completed normally Unimplemented: Read ERASE: Erase/Program Enable bit(1) Perform erase operation specified NVMOP3:NVMOP0 next command Perform program operation specified NVMOP3:NVMOP0 next command Unimplemented: Read NVMOP3:NVMOP0: Operation Select bits(1,2) 1111 Memory bulk erase operation (ERASE operation (ERASE 0)(3) 0011 Memory word program operation (ERASE operation (ERASE 0010 Memory page erase operation (ERASE operation (ERASE 0001 Memory program operation (ERASE operation (ERASE These bits only reset POR. other combinations NVMOP3:NVMOP0 unimplemented. Available ICSPmode only. Refer device programming specification.
12-7
Note
2008 Microchip Technology Inc.
DS39897B-page
PIC24FJ256GB110 FAMILY
4.6.1 PROGRAMMING ALGORITHM FLASH PROGRAM MEMORY
user program Flash program memory time. this, necessary erase 8-row erase block containing desired row. general process Read eight rows program memory (512 instructions) store data RAM. Update program data with desired data. Erase block (see Example 4-1): NVMOP bits (NVMCON<3:0>) `0010' configure block erase. ERASE (NVMCON<6>) WREN (NVMCON<14>) bits. Write starting address block erased into TBLPAG registers. Write NVMKEY. Write NVMKEY. (NVMCON<15>). erase cycle begins stalls duration erase cycle. When erase done, cleared automatically. Write first instructions from data into program memory buffers (see Example 4-1). Write program block Flash memory: NVMOP bits `0001' configure programming. Clear ERASE WREN bit. Write NVMKEY. Write NVMKEY. bit. programming cycle begins stalls duration write cycle. When write
Other recent searches
TPA3008D2 - TPA3008D2 TPA3008D2 Datasheet
ETR1109 - ETR1109 ETR1109 Datasheet
CQ202-4MS - CQ202-4MS CQ202-4MS Datasheet
CQ202-4NS - CQ202-4NS CQ202-4NS Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
