PIC32MX5XX/6XX/7XX Family Silicon Errata Data Sheet Clarification

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PIC32MX5XX/6XX/7XX Family Silicon Errata Data Sheet Clarification

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PIC32MX5XX/6XX/7XX
PIC32MX5XX/6XX/7XX Family Silicon Errata Data Sheet Clarification
PIC32MX5XX/6XX/7XX family devices that have received conform functionally current Device Data Sheet (DS61156A), except anomalies described this document. silicon issues discussed following pages silicon revisions with Device Revision listed Table silicon issues summarized Table errata described this document will addressed future revisions PIC32MX5XX/6XX/7XX silicon. Note: This document summarizes silicon errata issues from revisions silicon, previous well current. Only issues indicated last column Table apply current silicon revision (A0). example, identify silicon revision level using MPLAB conjunction with REAL ICEin-circuit emulator: Using appropriate interface, connect device REAL ICEin-circuit emulator. From main menu MPLAB IDE, select Configure>Select Device, then select target part number dialog box. Select MPLAB hardware tool (Debugger>Select Tool). Perform "Connect" operation device (Debugger>Connect). Depending development tool used, part number Device Revision value appear Output window. Note: unable extract silicon revision level, please contact your local Microchip sales office assistance.
Data Sheet clarifications corrections start page following discussion silicon issues. silicon revision level identified using current version MPLAB® Microchip's programmers, debuggers, emulation tools, which available Microchip corporate site (www.microchip.com).
Device Revision values various PIC32MX5XX/6XX/7XX silicon revisions shown Table
TABLE
SILICON DEVREV VALUES
Part Number Device ID(1) 0x4317053 0x4309053 0x430C053 0x430E053 0x4333053 0x430F053 0x4311053 0x4307053 Revision Silicon Revision(2)
PIC32MX575F256H PIC32MX575F512H PIC32MX675F512H PIC32MX795F512H PIC32MX575F256L PIC32MX575F512L PIC32MX675F512L PIC32MX795F512L Note
Device Revision (DEVID DEVREV) located last implemented addresses program memory. Refer "PIC32MX Flash Programming Specification" (DS61145) detailed information Device Revision your specific device.
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TABLE
Module I2CEthernet Parallel Master Port Output Compare UART Output Compare Output Compare Timers Output Compare Oscillator
SILICON ISSUE SUMMARY
Feature Item Number Issue Summary Affected Revisions(1) RMII Interrupt Generation Slave Mode module does override TRIS bits. Pause frames sent normal rate. interrupt generated module cannot cleared when module disabled. interrupt used wake device will reflected interrupt flag until write strobe. Fault detection asynchronous. SPIBUSY SRMT bits assert time before transaction. TXBF deasserts clock after interrupt generated. USBPLL does automatically suspend Idle mode. mode, output waveform clock longer than expected value. Fault interrupt will generated firmware clears Fault while Fault still asserted. Pattern Match mode, module append results result buffer. Synchronized External Clock mode, first period count short. Outgoing data corruption when frame signal coincident with clock. TXABAT, TXLARB TXERR erroneously cleared aborted read CiFIFOCONn register. Requested aborts message setting CxCON.ABAT clearing CiFIFOCON.TXREQ complete. CFIFOCONx.FRESET CFIFOCONx.UINC bits settable normal write. DeviceNet filtering does function. Fault erroneously cleared aborted read. Slave mode, buffer under-run condition will assert interrupt flag. TOKBUSY does correctly indicate status when transfer completes within Start-of-Frame (SOF) threshold. Host mode, interval between first packets less than what specified specification. When code-protect enabled, held reset during Clear Sequence (RCS). Clock switching Two-Speed Start-up cause general exception when reserved DDPCON register '0'. Clock source switching cause general exception when switching from slow clock fast clock.
Electrical Specification Fault Input Mode Pattern Match External Clock Frame Slave Mode DeviceNetPWM Fault Input Mode Slave Mode Host Mode Clock Switch -Speed Start-Up Clock Switch
Oscillator Note
Only those issues indicated last column apply current silicon revision.
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PIC32MX5XX/6XX/7XX
Silicon Errata Issues
Note: This document summarizes silicon errata issues from revisions silicon, previous well current. Only issues indicated shaded column following tables apply current silicon revision (A0).
Module: Parallel Master Port
Slave mode, interrupt will wake device; however, interrupt source will reflected interrupt flag until write strobe. Work around There possible solutions this issue: multiple wake-up sources used, firmware poll configured wakeup source interrupt flags. none set, assume source PMP. Firmware wait period exceeding write strobe length, then poll interrupt flag.
Module: CTRIS correctly controlled module during initialization. Work around Before enabling module, TRIS bits pin. Affected Silicon Revisions
Affected Silicon Revisions
Module: Ethernet
RMII mode only, pause frames sent normal rate. This reduces available network bandwidth device connected network hub. This does reduce functionality violate specifications. Work around bandwidth concern, connect PIC32 device network using Ethernet switch. Affected Silicon Revisions
Module: Output Compare
Fault input detection asynchronous. There Peripheral (PB) clock delay between Fault input assertion shutdown appropriate OCMP output pin. Work around Ensure that device driven OCMP module tolerate this shutdown delay. Affected Silicon Revisions
Module:
SPIBUSY SRMT bits assert time before transaction. Work around Firmware must provide time delay between assertion these bits performing operation that requires transaction complete. Affected Silicon Revisions
Module:
interrupt generated module cannot cleared when module disabled. Work around Ensure interrupt serviced interrupt flag cleared before turning module. Affected Silicon Revisions
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Module: UART
UxSTA.TXBF clears clock cycle after interrupt generated. When using divisor other than polling UART transmit interrupt flag with next instruction reading UxSTA.TXBF bit, result reflect actual TXBF status. Work around There possible solutions this issue: Only divisor 1:1. firmware polling transmit interrupt flag TXBF flag, insert read UxSTA register between these operations discard result. This read will ensure status TXBF flag correct when next read this register occurs.
Module: Output Compare
mode, firmware attempts clear OCFLT while Fault still exists, second interrupt will generated this Fault when firmware exits Interrupt Service Routine (ISR). OCFLT will remain while Fault detected. Work around ISR, clear OSxFLT bit, test OCxFLT before exiting ISR. set, interrupt generate second interrupt. Affected Silicon Revisions
Affected Silicon Revisions
Module:
Pattern Match mode, module append results result buffer. Work around firmware read result append result buffer. Affected Silicon Revisions
Module:
When U1CNFG1.USBSIDL set, USBPLL does automatically suspend Idle mode. Work around firmware manually suspend clock before entering Sleep mode. Affected Silicon Revisions
Module: Timers
When Timer module first enabled prescaler value number input clocks required increment timer from input clock, value stated prescaler. Work around None. Affected Silicon Revisions
Module: Output Compare
mode, output waveform clock longer than expected value. Work around Load OCRS with value less than number expected achieve desired output. Affected Silicon Revisions
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PIC32MX5XX/6XX/7XX
Module:
Outgoing data will corrupted when Frame Slave mode with FRMCNT frame pulse coincident with clock. Work around There workaround operation when Frame pulse coincident with clock. Provide frame signal that precedes clock signal. Affected Silicon Revisions
Module:
Requested aborts message setting CxCON.ABAT clearing CiFIFOCON.TXREQ complete. protocol violated. Work around After general abort request, firmware should poll until CxCON.BUSY wait message times. CxCON.ABAT remains high, message successfully aborted module must reset clearing setting CxCON.ON. After FIFO specific abort request, firmware should poll until CxCON.BUSY wait message times. CFIFOCONx.TXREQ remains high, message successfully aborted FIFO must reset setting CFIFOCONx.FRESET polling until CFIFOCONx.FRESET
Module:
TXABAT, TXLARB TXERR erroneously cleared aborted read CiFIFOCONn register. aborted read occurs when load instruction pipeline started execution, aborted interrupt. Work around Disable interrupts before reading contents CiFIFOCONn register, then re-enable interrupts after reading register. Affected Silicon Revisions
Affected Silicon Revisions
Module:
CFIFOCONx.FRESET CFIFOCONx.UINC bits settable normal Special Function Register (SFR) write. Work around register operations change state these bits. Affected Silicon Revisions
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Module:
DeviceNetmessage filtering does function. Work around hardware filter Standard Identifier (SID) firmware decode DeviceNet identifier. Affected Silicon Revisions
Module:
TOKBUSY does correctly indicate status when transfer completes within Start-ofFrame (SOF) threshold. Work around firmware semaphore track when token written U1TOK. Firmware then clears semaphore when transfer complete. Affected Silicon Revisions
Module: Output Compare
Output Compare module reinitialize clear Fault aborted read OCxCON register. aborted read occurs when read instruction pipeline started execution, aborted interrupt. Work around Disable interrupts before reading contents OCxCON register, then re-enable interrupts after reading register. Affected Silicon Revisions
Module:
Host mode, interval between first packets less than what specified specification. Work around None. Affected Silicon Revisions
Module:
When code-protect enabled, held reset during Clear Sequence (RCS). period does exceed period, will reset part sequence will restart. Work around periods equal longer than Since concurrently, firmware will have reduced period which service first time. Affected Silicon Revisions
Module:
Slave mode with TXISEL buffer underrun condition will assert interrupt flag. Work around None. Affected Silicon Revisions
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PIC32MX5XX/6XX/7XX
Module: Oscillator
Clock switching Two-Speed Start-up cause general exception when reserved DDPCON register '0'. Work around Ensure that reserved DDPCON register '1'. example, DDPCON 0x100; Affected Silicon Revisions
Module: Oscillator
Clock source switching cause general exception when switching from slow clock fast clock. Work around Clock source switches should performed first switching FRC, then switching target clock source. Note: peripheral library being used, clock switching performed automatically through FRC.
Affected Silicon Revisions
2009 Microchip Technology Inc.
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PIC32MX5XX/6XX/7XX
Data Sheet Clarifications
following typographic corrections clarifications noted latest version device data sheet (DS61156A): Note: Corrections shown bold. Where possible, original bold text formatting been removed clarity.
data sheet clarifications this time.
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2009 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
APPENDIX REVISION HISTORY
Document (8/2009) Initial release this document; issued revision silicon. Includes silicon issues (I2CTM), (Ethernet), (ADC), (Parallel Master Port), (Output Compare), (SPI), (UART). Document (11/2009) Added silicon issues (USB), (Output Compare), (Output Compare), (DMA), (Timers), (SPI), 1417 (CAN), (Output Compare), (SPI), (USB), (USB), (WDT), (Oscillator), (Oscillator).
2009 Microchip Technology Inc.
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PIC32MX5XX/6XX/7XX
NOTES:
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2009 Microchip Technology Inc.
Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
Code protection constantly evolving. Microchip committed continuously improving code protection features products. Attempts break Microchip's code protection feature violation Digital Millennium Copyright Act. such acts allow unauthorized access your software other copyrighted work, have right relief under that Act.
Information contained this publication regarding device applications like provided only your convenience superseded updates. your responsibility ensure that your application meets with your specifications. MICROCHIP MAKES REPRESENTATIONS WARRANTIES KIND WHETHER EXPRESS IMPLIED, WRITTEN ORAL, STATUTORY OTHERWISE, RELATED INFORMATION, INCLUDING LIMITED CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY FITNESS PURPOSE. Microchip disclaims liability arising from this information use. Microchip devices life support and/or safety applications entirely buyer's risk, buyer agrees defend, indemnify hold harmless Microchip from damages, claims, suits, expenses resulting from such use. licenses conveyed, implicitly otherwise, under Microchip intellectual property rights.
Trademarks Microchip name logo, Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC UNI/O registered trademarks Microchip Technology Incorporated U.S.A. other countries. FilterLab, Hampshire, HI-TECH Linear Active Thermistor, MXDEV, MXLAB, SEEVAL Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2009, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
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PIC32MX5XX/6XX/7XX Family Silicon Errata Data Sheet Clarification

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