USB, Ethernet 32-bit Flash Microcontrollers 2009 Microchip Techno
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PIC32MX5XX/6XX/7XX Data Sheet
USB, Ethernet 32-bit Flash Microcontrollers
2009 Microchip Technology Inc.
DS61156B
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Trademarks Microchip name logo, Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC UNI/O registered trademarks Microchip Technology Incorporated U.S.A. other countries. FilterLab, Hampshire, HI-TECH Linear Active Thermistor, MXDEV, MXLAB, SEEVAL Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2009, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
DS61156B-page
2009 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
High-Performance USB, CAN, Ethernet 32-bit Flash Microcontrollers
High-Performance 32-bit RISC CPU:
MIPS32® M4K32-bit core with 5-stage pipeline maximum frequency 1.56 DMIPS/MHz (Dhrystone 2.1) performance zero wait state Flash access Single-cycle multiply high-performance divide unit MIPS16emode smaller code size sets core register files (32-bit) reduce interrupt latency Prefetch Cache module speed execution from Flash
Peripheral Features (Continued):
Internal oscillators UART modules with: RS-232, RS-485 support IrDA® with on-chip hardware encoder decoder four modules five I2Cmodules Separate PLLs clocks Parallel master slave port (PMP/PSP) with 8-bit 16-bit data address lines Hardware Real-Time Clock/Calendar (RTCC) Five 16-bit Timers/Counters (two 16-bit pairs combine create 32-bit timers) Five Capture inputs Five Compare/PWM outputs Five external interrupt pins High-speed pins capable toggling High-current sink/source mA/18 pins Configurable open-drain output digital pins
Microcontroller Features:
Operating voltage range 2.3V 3.6V 256K 512K Flash memory (plus additional Boot Flash) 128K SRAM memory Pin-compatible with most PIC24/dsPIC® devices Multiple power management modes Multiple interrupt vectors with individually programmable priority Fail-Safe Clock Monitor mode Configurable Watchdog Timer with on-chip Low-Power oscillator reliable operation
Debug Features:
programming debugging Interfaces: 2-wire interface with unintrusive access real-time data exchange with application 4-wire MIPS® standard enhanced JTAG interface Unintrusive hardware-based instruction trace IEEE Standard 1149.2-compatible (JTAG) boundary scan
Peripheral Features:
Atomic Set, Clear, Invert operation select peripheral registers 8-channel hardware with automatic data size detection 2.0-compliant full-speed device On-TheGo (OTG) controller: Dedicated channels 10/100 Mbps Ethernet with RMII interface: Dedicated channels module: 2.0B Active with DeviceNetaddressing support Dedicated channels crystal oscillator
Analog Features:
16-channel 10-bit Analog-to-Digital Converter: Msps conversion rate Conversion available during Sleep Idle Analog Comparators tolerant input pins (digital pins only)
2009 Microchip Technology Inc.
DS61156B-page
PIC32MX5XX/6XX/7XX
TABLE PIC32MX FEATURES
Timers/Capture/Compare Program Memory (KB) 10-bit Msps (Channels) Data Memory (KB)
Channels (Programmable/ Dedicated)
Comparators
PIC32MX575F256H PIC32MX575F512H PIC32MX675F512H PIC32MX695F512H PIC32MX795F512H
12(1) 12(1) 12(1)
5/5/5 5/5/5 5/5/5 5/5/5 5/5/5
12(1) 12(1)
PIC32MX575F256L
12(1)
5/5/5
PIC32MX575F512L
12(1)
5/5/5
PIC32MX675F512L
12(1) 12(1)
5/5/5
PIC32MX695F512L
5/5/5
PIC32MX795F512L Legend: Note
12(1)
5/5/5
TQFP XBGA This device features boot Flash memory. pins available UART modules. Refer "Pin Diagrams" section more information. Some pins between UART, SPI, modules shared. Refer "Pin Diagrams" section more information. Refer Section 32.0 "Packaging Information" detailed information.
DS61156B-page
2009 Microchip Technology Inc.
Packages(4)
UART(2,3)
PMP/PSP
Ethernet
I2CTM(3)
Device
Trace
SPI(3)
JTAG
Pins
PIC32MX5XX/6XX/7XX
Diagrams
64-Pin
Pins tolerant
PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1
C1TX/RF1 C1RX/RF0 VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL1A/SDO1A/U1ATX/OC4/RD3 SDA1A/SDI1A/U1ARX/OC3/RD2 SCK1A/U1BTX/U1ARTS/OC2/RD1
PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0
PIC32MX575F256H PIC32MX575F512H
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 IC4/PMCS1/PMA14/INT4/RD11 SCL1/IC3/PMCS2/PMA15/INT3/RD10 RTCC/IC1/INT1/RD8 OSC2/CLKO/RC15 OSC1/CLKI/RC12 D+/RG2 D-/RG3 VUSB VBUS USBID/RF3
PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/SS3A/U3BRX/U3ACTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN15/OCFB/PMALL/PMA0/CN12/RB15
Note:
metal plane bottom device connected pins recommended connected externally.
2009 Microchip Technology Inc.
DS61156B-page
PIC32MX5XX/6XX/7XX
Diagrams (Continued)
64-Pin
Pins tolerant
AETXD0/ERXD2/RF1 AETXD1/ERXD3/RF0
ERXERR/PMD4/RE4
ERXCLK/PMD3/RE3
ERXDV/PMD2/RE2
ERXD0/PMD1/RE1
ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 AVDD AVSS PGEC2/AN6/OCFA/RB6 AN9/C2OUT/PMA7/RB9 TDO/AN11/PMA12/RB11 TDI/AN13/PMA10/RB13 PGED2/AN7/RB7 TCK/AN12/PMA11/RB12 SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 AN8/SS3A/U3BRX/U3ACTS/C1OUT/RB8 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5 TMS/AN10/CVREFOUT/PMA13/RB10 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 OSC2/CLKO/RC15 OSC1/CLKI/RC12 D+/RG2 D-/RG3 VUSB VBUS USBID/RF3
PIC32MX675F512H PIC32MX695F512H
VCAP/VDDCORE
SCL1A/SDO1A/U1ATX/OC4/RD3
Note:
metal plane bottom device connected pins recommended connected externally.
DS61156B-page
SDA1A/SDI1A/U1ARX/OC3/RD2
ETXCLK/AERXERR/CN16/RD7
AETXEN/ETXERR/CN15/RD6
OC5/IC5/PMWR/CN13/RD4
ERXD1/PMD0/RE0
PMRD/CN14/RD5
2009 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Diagrams (Continued)
64-Pin
Pins tolerant
ERXERR/PMD4/RE4
ERXCLK/PMD3/RE3
ERXDV/PMD2/RE2
ERXD0/PMD1/RE1
ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 TCK/AN12/PMA11/RB12 PGED2/AN7/RB7 AVDD
AVSS PGEC2/AN6/OCFA/RB6
SCL1A/SDO1A/U1ATX/OC4/RD3
SDA1A/SDI1A/U1ARX/OC3/RD2
ETXCLK/AERXERR/CN16/RD7
AETXEN/ETXERR/CN15/RD6
C1TX/AETXD0/ERXD2/RF1 C1RX/AETXD1/ERXD3/RF0
OC5/IC5/PMWR/CN13/RD4
ERXD1/PMD0/RE0
PMRD/CN14/RD5
VCAP/VDDCORE
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 OSC2/CLKO/RC15 OSC1/CLKI/RC12 D+/RG2 D-/RG3 VUSB VBUS USBID/RF3
PIC32MX795F512H
TDO/AN11/PMA12/RB11
AN9/C2OUT/PMA7/RB9
TDI/AN13/PMA10/RB13
Note:
metal plane bottom device connected pins recommended connected externally.
2009 Microchip Technology Inc.
TMS/AN10/CVREFOUT/PMA13/RB10
DS61156B-page
PIC32MX5XX/6XX/7XX
Diagrams (Continued)
64-Pin TQFP
Pins tolerant
PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1
C1TX/RF1 C1RX/RF0 VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL1A/SDO1A/U1ATX/OC4/RD3 SDA1A/SDI1A/U1ARX/OC3/RD2 SCK1A/U1BTX/U1ARTS/OC2/RD1
PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0
PIC32MX575F256H PIC32MX575F512H
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 IC4/PMCS1/PMA14/INT4/RD11 SCL1/IC3/PMCS2/PMA15/INT3/RD10 RTCC/IC1/INT1/RD8 OSC2/CLKO/RC15 OSC1/CLKI/RC12 D+/RG2 D-/RG3 VUSB VBUS USBID/RF3
PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/SS3A/U3BRX/U3ACTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN15/OCFB/PMALL/PMA0/CN12/RB15
DS61156B-page
2009 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Diagrams (Continued)
64-Pin TQFP
Pins tolerant
ERXERR/PMD4/RE4
ERXCLK/PMD3/RE3
ERXDV/PMD2/RE2
ERXD0/PMD1/RE1
ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED2/AN7/RB7 TCK/AN12/PMA11/RB12
SCL1A/SDO1A/U1ATX/OC4/RD3
SDA1A/SDI1A/U1ARX/OC3/RD2
ETXCLK/AERXERR/CN16/RD7
AETXEN/ETXERR/CN15/RD6
OC5/IC5/PMWR/CN13/RD4
AETXD0/ERXD2/RF1 AETXD1/ERXD3/RF0
ERXD1/PMD0/RE0
PMRD/CN14/RD5
VCAP/VDDCORE
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 OSC2/CLKO/RC15 OSC1/CLKI/RC12 D+/RG2 D-/RG3 VUSB VBUS USBID/RF3
PIC32MX675F512H PIC32MX695F512H
AN8/SS3A/U3BRX/U3ACTS/C1OUT/RB8
SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4
AVSS
PGEC2/AN6/OCFA/RB6
AN9/C2OUT/PMA7/RB9
TDO/AN11/PMA12/RB11
TDI/AN13/PMA10/RB13
2009 Microchip Technology Inc.
SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
AVDD
TMS/AN10/CVREFOUT/PMA13/RB10
DS61156B-page
PIC32MX5XX/6XX/7XX
Diagrams (Continued)
64-Pin TQFP
Pins tolerant
C1TX/AETXD0/ERXD2/RF1 C1RX/AETXD1/ERXD3/RF0
ERXERR/PMD4/RE4
ERXCLK/PMD3/RE3
ERXDV/PMD2/RE2
ERXD0/PMD1/RE1
ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 AVSS AVDD PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 TDO/AN11/PMA12/RB11 TDI/AN13/PMA10/RB13 AN9/C2OUT/PMA7/RB9 TCK/AN12/PMA11/RB12 TMS/AN10/CVREFOUT/PMA13/RB10 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 OSC2/CLKO/RC15 OSC1/CLKI/RC12 D+/RG2 D-/RG3 VUSB VBUS USBID/RF3
PIC32MX795F512H
DS61156B-page
VCAP/VDDCORE
SCL1A/SDO1A/U1ATX/OC4/RD3
SDA1A/SDI1A/U1ARX/OC3/RD2
ETXCLK/AERXERR/CN16/RD7
AETXEN/ETXERR/CN15/RD6
OC5/IC5/PMWR/CN13/RD4
ERXD1/PMD0/RE0
PMRD/CN14/RD5
2009 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Diagrams (Continued)
100-Pin TQFP
Pins tolerant
PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 PMD9/RG1 C1TX/PMD10/RF1 C1RX/PMD11/RF0 VCAP/VDDCORE PMD15/CN16/RD7 PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 PMD13/CN19/RD13 IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1
RG15 PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/SDI1/RC4 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 TMS/RA0 INT1/RE8 INT2/RE9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 IC4/PMCS1/PMA14/RD11 SCK1/IC3/PMCS2/PMA15/RD10 SS1/IC2/RD9 RTCC/IC1/RD8 SDA1/INT4/RA15 SCL1/INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKI/RC12 TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 D+/RG2 D-/RG3 VUSB VBUS SCL1A/SDO1A/U1ATX/RF8 SDA1A/SDI1A/U1ARX/RF2 USBID/RF3
PIC32MX575F512L PIC32MX575F256L
PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VREF-/CVREF-/PMA7/RA9 VREF+/CVREF+/PMA6/RA10 AVDD AVSS AN8/C1OUT/RB8 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AN11/PMA12/RB11 TCK/RA1 AC1TX/SCK3A/U3BTX/U3ARTS/RF13 AC1RX/SS3A/U3BRX/U3ACTS/RF12 AN12/PMA11/RB12 AN13/PMA10/RB13 AN14/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 SS1A/U1BRX/U1ACTS/CN20/RD14 SCK1A/U1BTX/U1ARTS/CN21/RD15
2009 Microchip Technology Inc.
SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
DS61156B-page
PIC32MX5XX/6XX/7XX
Diagrams (Continued)
100-Pin TQFP
Pins tolerant
AERXERR/RG15 PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/SDI1/RC4 MCLR TMS/RA0 AERXD0/INT1/RE8 AERXD1/INT2/RE9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0
PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 ETXERR/PMD9/RG1 ETXD0/PMD10/RF1 ETXD1/PMD11/RF0 VCAP/VDDCORE ETXCLK/PMD15/CN16/RD7 ETXEN/PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 ETXD3/PMD13/CN19/RD13 ETXD2/IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1
PIC32MX675F512L PIC32MX695F512L
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 EMDC/IC4/PMCS1/PMA14/RD11 SCK1/IC3/PMCS2/PMA15/RD10 SS1/IC2/RD9 RTCC/EMDIO/IC1/RD8 AETXEN/SDA1/INT4/RA15 AETXCLK/SCL1/INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKI/RC12 TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 D+/RG2 D-/RG3 VUSB VBUS SCL1A/SDO1A/U1ATX/RF8 SDA1A/SDI1A/U1ARX/RF2 USBID/RF3
DS61156B-page
PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VREF-/CVREF-/AERXD2/PMA7/RA9 VREF+/CVREF+/AERXD3/PMA6/RA10 AVDD AVSS AN8/C1OUT/RB8 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AN11/ERXERR/AETXERR/PMA12/RB11 TCK/RA1 SCK3A/U3BTX/U3ARTS/RF13 SS3A/U3BRX/U3ACTS/RF12 AN12/ERXD0/AECRS/PMA11/RB12 AN13/ERXD1/AECOL/PMA10/RB13 SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
2009 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Diagrams (Continued)
100-Pin TQFP
Pins tolerant
PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 C2RX/PMD8/RG0 C2TX/ETXERR/PMD9/RG1 C1TX/ETXD0/PMD10/RF1 C1RX/ETXD1/PMD11/RF0 VCAP/VDDCORE ETXCLK/PMD15/CN16/RD7 ETXEN/PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 ETXD3/PMD13/CN19/RD13 ETXD2/IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1
AERXERR/RG15 PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/AC2TX/RC2 T4CK/AC2RX/RC3 T5CK/SDI1/RC4 MCLR TMS/RA0 AERXD0/INT1/RE8 AERXD1/INT2/RE9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 EMDC/IC4/PMCS1/PMA14/RD11 SCK1/IC3/PMCS2/PMA15/RD10
SS1/IC2/RD9
RTCC/EMDIO/IC1/RD8 AETXEN/SDA1/INT4/RA15 AETXCLK/SCL1/INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKI/RC12 TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 D+/RG2 D-/RG3 VUSB VBUS SCL1A/SDO1A/U1ATX/RF8 SDA1A/SDI1A/U1ARX/RF2 USBID/RF3
PIC32MX795F512L
PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VREF-/CVREF-/AERXD2/PMA7/RA9 VREF+/CVREF+/AERXD3/PMA6/RA10 AVDD AVSS AN8/C1OUT/RB8 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AN11/ERXERR/AETXERR/PMA12/RB11 TCK/RA1 AC1TX/SCK3A/U3BTX/U3ARTS/RF13 AC1RX/SS3A/U3BRX/U3ACTS/RF12 AN12/ERXD0/AECRS/PMA11/RB12 AN13/ERXD1/AECOL/PMA10/RB13
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SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
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Diagrams (Continued)
121-Pin XBGA(1)
PIC32MX575F256L PIC32MX575F512L PIC32MX675F512L PIC32MX695F512L PIC32MX795F512L
Pins tolerant
RG13 RD12
RG15
VCAP/ VDDCORE
RC14
RG12 RG14 RC13 RD11
RD13 RD10
RA15 RA14
MCLR RC12 RC15
VBUS VUSB
AVDD RB11 RB12
RA10 RF12 RB14 RD15
AVSS RB10 RF13 RB13 RB15 RD14
Note Refer Table Table Table full names.
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TABLE
Number PMD4/RE4 PMD3/RE3 TRD0/RG13 PMD0/RE0 PMD8/RG0 C1TX/PMD10/RF1 IC5/PMD12/RD12 OC3/RD2 OC2/RD1 Connect (NC) RG15 PMD2/RE2 PMD1/RE1 TRD3/RA7 C1RX/PMD11/RF0 VCAP/VDDCORE PMRD/CN14/RD5 OC4/RD3 SOSCO/T1CK/CN0/RC14 PMD6/RE6 TRD1/RG12 TRD2/RG14 TRCLK/RA6 Connect (NC) PMD15/CN16/RD7 OC5/PMWR/CN13/RD4 SOSCI/CN1/RC13 IC4/PMCS1/PMA14/RD11 T2CK/RC1 PMD7/RE7 PMD5/RE5 Connect (NC) PMD14/CN15/RD6 PMD13/CN19/RD13 SDO1/OC1/INT0/RD0 Connect (NC) SCK1/IC3/PMCS2/PMA15/RD10 T5CK/SDI1/RC4 T4CK/RC3 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 T3CK/RC2 PMD9/RG1
NAMES: PIC32MX575F256L PIC32MX575F512L DEVICES
Full Name Number SDA1/INT4/RA15 RTCC/IC1/RD8 SS1/IC2/RD9 SCL1/INT3/RA14 MCLR SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 Connect (NC) Connect (NC) OSC1/CLKI/RC12 OSC2/CLKO/RC15 INT1/RE8 INT2/RE9 TMS/RA0 Connect (NC) Connect (NC) TDO/RA5 SDA2/RA3 TDI/RA4 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 Connect (NC) Connect (NC) VBUS VUSB D+/RG2 SCL2/RA2 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGED2/AN7/RB7 AVDD AN11/PMA12/RB11 TCK/RA1 AN12/PMA11/RB12 Connect (NC) Connect (NC) SCL1A/SDO1A/U1ATX/RF8 D-/RG3 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 VREF+/CVREF+/PMA6/RA10 Full Name
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TABLE
Number AN8/C1OUT/RB8 Connect (NC) AC1RX/SS3A/U3BRX/U3ACTS/RF12 AN14/PMALH/PMA1/RB14 SCK1A/U1BTX/U1ARTS/CN21/RD15 USBID/RF3 SDA1A/SDI1A/U1ARX/RF2 PGEC2/AN6/OCFA/RB6 VREF-/CVREF-/PMA7/RA9
NAMES: PIC32MX575F256L PIC32MX575F512L DEVICES (CONTINUED)
Full Name Number AVSS AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AC1TX/SCK3A/U3BTX/U3ARTS/RF13 AN13/PMA10/RB13 AN15/OCFB/PMALL/PMA0/CN12/RB15 SS1A/U1BRX/U1ACTS/CN20/RD14 SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5 Full Name
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TABLE
Number PMD4/RE4 PMD3/RE3 TRD0/RG13 PMD0/RE0 PMD8/RG0 ETXD0/PMD10/RF1 ETXD2/IC5/PMD12/RD12 OC3/RD2 OC2/RD1 Connect (NC) AERXERR/RG15 PMD2/RE2 PMD1/RE1 TRD3/RA7 ETXD1/PMD11/RF0 VCAP/VDDCORE PMRD/CN14/RD5 OC4/RD3 SOSCO/T1CK/CN0/RC14 PMD6/RE6 TRD1/RG12 TRD2/RG14 TRCLK/RA6 Connect (NC) ETXCLK/PMD15/CN16/RD7 OC5/PMWR/CN13/RD4 SOSCI/CN1/RC13 EMDC/IC4/PMCS1/PMA14/RD11 T2CK/RC1 PMD7/RE7 PMD5/RE5 Connect (NC) ETXEN/PMD14/CN15/RD6 ETXD3/PMD13/CN19/RD13 SDO1/OC1/INT0/RD0 Connect (NC) SCK1/IC3/PMCS2/PMA15/RD10 T5CK/SDI1/RC4 T4CK/RC3 T3CK/RC2 EXTERR/PMD9/RG1
NAMES: PIC32MX675F512L PIC32MX695F512L DEVICES
Full Name Number Full Name AETXEN/SDA1/INT4/RA15 RTCC/EMDIO/IC1/RD8 SS1/IC2/RD9 AETXCLK/SCL1/INT3/RA14 MCLR Connect (NC) Connect (NC) OSC1/CLKI/RC12 OSC2/CLKO/RC15 AERXD0/INT1/RE8 AERXD1/INT2/RE9 TMS/RA0 Connect (NC) Connect (NC) TDO/RA5 SDA2/RA3 TDI/RA4 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 Connect (NC) Connect (NC) VBUS VUSB D+/RG2 SCL2/RA2 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGED2/AN7/RB7 AVDD AN11/ERXERR/AETXERR/PMA12/RB11 TCK/RA1 AN12/ERXD0/AECRS/PMA11/RB12 Connect (NC) Connect (NC) SCL1A/SDO1A/U1ATX/RF8 D-/RG3 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 VREF+/CVREF+/AERXD3/PMA6/RA10
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TABLE
Number AN8/C1OUT/RB8 Connect (NC) SS3A/U3BRX/U3ACTS/RF12 USBID/RF3 SDA1A/SDI1A/U1ARX/RF2 PGEC2/AN6/OCFA/RB6 VREF-/CVREF-/AERXD2/PMA7/RA9
NAMES: PIC32MX675F512L PIC32MX695F512L DEVICES (CONTINUED)
Full Name Number AVSS AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 SCK3A/U3BTX/U3ARTS/RF13 AN13/ERXD1/AECOL/PMA10/RB13 SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5 Full Name
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TABLE
Number PMD4/RE4 PMD3/RE3 TRD0/RG13 PMD0/RE0 C2RX/PMD8/RG0 C1TX/ETXD0/PMD10/RF1 ETXD2/IC5/PMD12/RD12 OC3/RD2 OC2/RD1 Connect (NC) AERXERR/RG15 PMD2/RE2 PMD1/RE1 TRD3/RA7 C1RX/ETXD1/PMD11/RF0 VCAP/VDDCORE PMRD/CN14/RD5 OC4/RD3 SOSCO/T1CK/CN0/RC14 PMD6/RE6 TRD1/RG12 TRD2/RG14 TRCLK/RA6 Connect (NC) ETXCLK/PMD15/CN16/RD7 OC5/PMWR/CN13/RD4 SOSCI/CN1/RC13 EMDC/IC4/PMCS1/PMA14/RD11 T2CK/RC1 PMD7/RE7 PMD5/RE5 Connect (NC) ETXEN/PMD14/CN15/RD6 ETXD3/PMD13/CN19/RD13 SDO1/OC1/INT0/RD0 Connect (NC) SCK1/IC3/PMCS2/PMA15/RD10 T5CK/SDI1/RC4 T4CK/AC2RX/RC3 T3CK/AC2TX/RC2 C2TX/EXTERR/PMD9/RG1
NAMES: PIC32MX795F512L DEVICE
Full Name Number Full Name AETXEN/SDA1/INT4/RA15 RTCC/EMDIO/IC1/RD8 SS1/IC2/RD9 AETXCLK/SCL1/INT3/RA14 MCLR Connect (NC) Connect (NC) OSC1/CLKI/RC12 OSC2/CLKO/RC15 AERXD0/INT1/RE8 AERXD1/INT2/RE9 TMS/RA0 Connect (NC) Connect (NC) TDO/RA5 SDA2/RA3 TDI/RA4 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 Connect (NC) Connect (NC) VBUS VUSB D+/RG2 SCL2/RA2 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGED2/AN7/RB7 AVDD AN11/ERXERR/AETXERR/PMA12/RB11 TCK/RA1 AN12/ERXD0/AECRS/PMA11/RB12 Connect (NC) Connect (NC) SCL1A/SDO1A/U1ATX/RF8 D-/RG3 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 VREF+/CVREF+/AERXD3/PMA6/RA10
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TABLE
Number AN8/C1OUT/RB8 Connect (NC) AC1RX/SS3A/U3BRX/U3ACTS/RF12 USBID/RF3 SDA1A/SDI1A/U1ARX/RF2 PGEC2/AN6/OCFA/RB6 VREF-/CVREF-/AERXD2/PMA7/RA9
NAMES: PIC32MX795F512L DEVICE
Full Name Number AVSS AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AC1TX/SCK3A/U3BTX/U3ARTS/RF13 AN13/ERXD1/AECOL/PMA10/RB13 SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5 Full Name
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Table Contents
Device Overview Guidelines Getting Started with 32-bit Microcontrollers PIC32MX MCU. Memory Organization Flash Program Memory. Resets Interrupt Controller Oscillator Configuration Prefetch Cache. 10.0 Direct Memory Access (DMA) Controller 11.0 On-The-Go (OTG). 12.0 Ports 13.0 Timer1 14.0 Timer2/3, Timer4/5 15.0 Input Capture. 16.0 Output Compare. 17.0 Serial Peripheral Interface (SPI). 18.0 Inter-Integrated Circuit (I2CTM) 19.0 Universal Asynchronous Receiver Transmitter (UART) 20.0 Parallel Master Port (PMP) 21.0 Real-Time Clock Calendar (RTCC). 22.0 10-bit Analog-to-Digital Converter (ADC) 23.0 Controller Area Network (CAN) 24.0 Ethernet Controller 25.0 Comparator 26.0 Comparator Voltage Reference (CVref) 27.0 Power-Saving Features 28.0 Special Features 29.0 Instruction 30.0 Development Support. 31.0 Electrical Characteristics 32.0 Packaging Information. Index
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Most Current Data Sheet
obtain most up-to-date version this data sheet, please register Worldwide site http://www.microchip.com determine version data sheet examining literature number found bottom outside corner page. last character literature number version number, (e.g., DS30000A version document DS30000).
Errata
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NOTES:
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DEVICE OVERVIEW
This document contains device-specific information PIC32MX5XX/6XX/7XX devices. Figure shows general block diagram core peripheral modules PIC32MX5XX/6XX/7XX family devices. Table lists functions various pins shown pinout diagrams. Note This data sheet summarizes features PIC32MX5XX/6XX/7XX family devices. intended comprehensive reference source. complement information this data sheet, refer related section "PIC32MX Family Reference Manual", which available from Microchip site (www.microchip.com/PIC32). Some registers associated bits described this section available devices. Refer Section "Memory Organization" this data sheet device-specific register information.
FIGURE 1-1:
BLOCK DIAGRAM(1,2)
OSC2/CLKO OSC1/CLKI VCAP/VDDCORE OSC/SOSC Oscillators FRC/LPRC Oscillators DIVIDERS PLL-USB Timing Generation Precision Band Reference USBCLK SYSCLK PBCLK Voltage Regulator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset CN1-22 Timer1-5 CAN1, CAN2 OC1-5 VDDVSS MCLR
Peripheral Clocked SYSCLK PORTA JTAG BSCAN PORTB EJTAG Priority Interrupt Controller
Peripheral Clocked PBCLK
ETHERNET
DMAC
PORTC PORTD
MIPS32® M4KCPU Core
IC1-5
SPI1,1A,2A,3A
Matrix
I2C1,2,1A, 2A,3A
PORTE Prefetch Module Data Peripheral Bridge
10-bit
PORTF 128-bit wide Program Flash Memory Flash Controller
UART1A,1B,2A, 2B,3A,3B RTCC Comparators
PORTG
Note
Some features available device variants. functionality provided when on-board voltage regulator enabled.
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TABLE 1-1:
Name
PINOUT DESCRIPTIONS
Number(1) Type Buffer Type Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog ST/CMOS External clock source input. Always associated with OSC1 function. Oscillator crystal output. Connects crystal resonator Crystal Oscillator mode. Optionally functions CLKO modes. Always associated with OSC2 function. Description
64-pin QFN/TQFP
100-pin TQFP
121-pin XBGA
AN10 AN11 AN12 AN13 AN14 AN15 CLKI CLKO
Analog input channels.
OSC1 OSC2
ST/CMOS Oscillator crystal input. buffer when configured mode; CMOS otherwise. Oscillator crystal output. Connects crystal resonator Crystal Oscillator mode. Optionally functions CLKO modes.
SOSCI SOSCO
ST/CMOS 32.768 low-power oscillator crystal input; CMOS otherwise. 32.768 low-power oscillator crystal output. Power Input Analog Analog input Output
Legend: CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels input buffer
Note numbers provided reference only. "Pin Diagrams" section device availability.
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TABLE 1-1:
Name
PINOUT DESCRIPTIONS (CONTINUED)
Number(1) Type Buffer Type Output Compare Fault input. Output Compare output Output Compare output Output Compare output Output Compare output Output Compare output Output Compare Fault input. External interrupt External interrupt External interrupt Power Input Capture inputs 1-5. Description
64-pin QFN/TQFP
100-pin TQFP
121-pin XBGA
CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 CN18 CN19 CN20 CN21 OCFA OCFB INT0 INT1 INT2
Change notification inputs. software programmed internal weak pull-ups inputs.
Legend: CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels input buffer
Analog Analog input Output
Note numbers provided reference only. "Pin Diagrams" section device availability.
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TABLE 1-1:
Name
PINOUT DESCRIPTIONS (CONTINUED)
Number(1) Type Buffer Type Analog Analog input Output Power Input PORTC bidirectional port. PORTB bidirectional port. Description
64-pin QFN/TQFP
100-pin TQFP
121-pin XBGA
INT3 INT4 RA10 RA14 RA15 RB10 RB11 RB12 RB13 RB14 RB15 RC12 RC13 RC14 RC15
External interrupt External interrupt PORTA bidirectional port.
Legend: CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels input buffer
Note numbers provided reference only. "Pin Diagrams" section device availability.
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TABLE 1-1:
Name
PINOUT DESCRIPTIONS (CONTINUED)
Number(1) Type Buffer Type Analog Analog input Output Power Input PORTF bidirectional port. PORTE bidirectional port. Description
64-pin QFN/TQFP
100-pin TQFP
121-pin XBGA
RD10 RD11 RD12 RD13 RD14 RD15 RF12 RF13
PORTD bidirectional port.
Legend: CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels input buffer
Note numbers provided reference only. "Pin Diagrams" section device availability.
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TABLE 1-1:
Name
PINOUT DESCRIPTIONS (CONTINUED)
Number(1) Type Buffer Type Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. Timer4 external clock input. Timer5 external clock input. UART1A clear send. UART1A ready send. UART1A receive. UART1A transmit. UART2A clear send. UART2A ready send. UART2A receive. UART2A transmit. UART3A clear send. UART3A ready send. UART3A receive. UART3A transmit. UART1B receive. UART1B transmit. UART2B receive. UART2B transmit. UART3B receive. UART3B transmit. Power Input PORTG input pins. Description
64-pin QFN/TQFP
100-pin TQFP
121-pin XBGA
RG12 RG13 RG14 RG15 T1CK T2CK T3CK T4CK T5CK U1ACTS U1ARTS U1ARX U1ATX U2ACTS U2ARTS U2ARX U2ATX U3ACTS U3ARTS U3ARX U3ATX U1BRX U1BTX U2BRX U2BTX U3BRX U3BTX
PORTG bidirectional port.
Legend: CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels input buffer
Analog Analog input Output
Note numbers provided reference only. "Pin Diagrams" section device availability.
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TABLE 1-1:
Name
PINOUT DESCRIPTIONS (CONTINUED)
Number(1) Type Buffer Type Description
64-pin QFN/TQFP
100-pin TQFP
121-pin XBGA
SCK1 SDI1 SDO1 SCK1A SDI1A SDO1A SS1A SCK2A SDI2A SDO2A SS2A SCK3A SDI3A SDO3A SS3A SCL1 SDA1 SCL1A SDA1A SCL2 SDA2 SCL2A SDA2A SCL3A SDA3A RTCC CVREFCVREF+ CVREFOUT C1INC1IN+ C1OUT
Synchronous serial clock input/output SPI1. SPI1 data SPI1 data out. SPI1 slave synchronization frame pulse I/O. Synchronous serial clock input/output SPI1A. SPI1A data SPI1A data out. SPI1A slave synchronization frame pulse I/O. Synchronous serial clock input/output SPI2A. SPI2A data SPI2A data out. SPI2A slave synchronization frame pulse I/O. Synchronous serial clock input/output SPI3A. SPI3A data SPI3A data out. SPI3A slave synchronization frame pulse I/O. Synchronous serial clock input/output I2C1. Synchronous serial data input/output I2C1. Synchronous serial clock input/output I2C1A. Synchronous serial data input/output I2C1A. Synchronous serial clock input/output I2C2. Synchronous serial data input/output I2C2. Synchronous serial clock input/output I2C2A. Synchronous serial data input/output I2C2A. Synchronous serial clock input/output I2C3A. Synchronous serial data input/output I2C3A. JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin. Real-Time Clock alarm output. Comparator Voltage Reference (low). Comparator Voltage Reference (high). Comparator Voltage Reference output. Comparator negative input. Comparator positive input. Comparator output. Power Input
Legend: CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels input buffer
Analog Analog input Output
Note numbers provided reference only. "Pin Diagrams" section device availability.
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TABLE 1-1:
Name
PINOUT DESCRIPTIONS (CONTINUED)
Number(1) Type Buffer Type TTL/ST Description
64-pin QFN/TQFP
100-pin TQFP
121-pin XBGA
C2INC2IN+ C2OUT PMA0
Comparator negative input. Comparator positive input. Comparator output. Parallel Master Port Address input (Buffered Slave modes) output (Master modes). Parallel Master Port Address input (Buffered Slave modes) output (Master modes). Parallel Master Port Address (Demultiplexed Master modes).
PMA1
TTL/ST
PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMA14 PMA15 PMCS1 PMCS2
Parallel Master Port Chip Select Strobe. Parallel Master Port Chip Select Strobe. Power Input
Legend: CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels input buffer
Analog Analog input Output
Note numbers provided reference only. "Pin Diagrams" section device availability.
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TABLE 1-1:
Name
PINOUT DESCRIPTIONS (CONTINUED)
Number(1) Type Buffer Type TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST Parallel Master Port Address Latch Enable low-byte (Multiplexed Master modes). Parallel Master Port Address Latch Enable high-byte (Multiplexed Master modes). Parallel Master Port Read Strobe. Parallel Master Port Write Strobe. power monitor. internal transceiver supply. Host power control output. Detect. CAN1 receive pin. CAN1 transmit pin. Alternate CAN1 receive pin. Alternate CAN1 transmit pin. CAN2 receive pin. CAN2 transmit pin. Alternate CAN2 receive pin. Alternate CAN2 transmit pin. Ethernet Receive Data Ethernet Receive Data Power Input Description
64-pin QFN/TQFP
100-pin TQFP
121-pin XBGA
PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMD8 PMD9 PMD10 PMD11 PMD12 PMD13 PMD14 PMD15 PMALL PMALH PMRD PMWR VBUS VUSB VBUSON DUSBID C1RX C1TX AC1RX AC1TX C2RX C2TX AC2RX AC2TX ERXD0 ERXD1
Parallel Master Port Data (Demultiplexed Master mode) Address/Data (Multiplexed Master modes).
Legend: CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels input buffer
Analog Analog input Output
Note numbers provided reference only. "Pin Diagrams" section device availability.
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TABLE 1-1:
Name
PINOUT DESCRIPTIONS (CONTINUED)
Number(1) Type Buffer Type Analog Analog input Output Power Input Description
64-pin QFN/TQFP
100-pin TQFP
121-pin XBGA
ERXD2 ERXD3 ERXERR ERXDV ERXCLK ETXD0 ETXD1 ETXD2 ETXD3 ETXERR ETXEN ETXCLK ECOL ECRS EMDC EMDIO AERXD0 AERXD1 AERXD2 AERXD3 AERXERR AERXDV AERXCLK AETXD0 AETXD1 AETXD2 AETXD3 AETXERR AETXEN AETXCLK AECOL AECRS TRCLK TRD0 TRD1 TRD2 TRD3
Ethernet Receive Data Ethernet Receive Data Ethernet Receive Error Input. Ethernet Receive Data Valid. Ethernet Receive Clock. Ethernet Transmit Data Ethernet Transmit Data Ethernet Transmit Data Ethernet Transmit Data Ethernet Transmit Error. Ethernet Transmit Enable. Ethernet Transmit Clock. Ethernet Collision Detect. Ethernet Carrier Sense. Ethernet Management Data Clock. Ethernet Management Data. Alternate Ethernet Receive Data Alternate Ethernet Receive Data Alternate Ethernet Receive Data Alternate Ethernet Receive Data Alternate Ethernet Receive Error Input. Alternate Ethernet Receive Data Valid. Alternate Ethernet Receive Clock. Alternate Ethernet Transmit Data Alternate Ethernet Transmit Data Alternate Ethernet Transmit Data Alternate Ethernet Transmit Data Alternate Ethernet Transmit Error. Alternate Ethernet Transmit Enable. Alternate Ethernet Transmit Clock. Alternate Ethernet Collision Detect. Alternate Ethernet Carrier Sense. Trace Clock. Trace Data Bits 0-3.
Legend: CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels input buffer
Note numbers provided reference only. "Pin Diagrams" section device availability.
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TABLE 1-1:
Name
PINOUT DESCRIPTIONS (CONTINUED)
Number(1) Type Buffer Type Description
64-pin QFN/TQFP
100-pin TQFP
121-pin XBGA B10, F10,
PGED1 PGEC1 PGED2 PGEC2 MCLR AVDD AVSS
Data programming/debugging communication channel Clock input programming/debugging communication channel Data programming/debugging communication channel Clock input programming/debugging communication channel Master Clear (Reset) input. This active-low Reset device. Positive supply analog modules. This must connected times. Ground reference analog modules. Positive supply peripheral logic pins.
VCAP/ VDDCORE
logic filter capacitor connection. Ground reference logic pins. This must connected times.
VREF+ VREF-
Analog Analog
Analog voltage reference (high) input. Analog voltage reference (low) input. Power Input
Legend: CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels input buffer
Analog Analog input Output
Note numbers provided reference only. "Pin Diagrams" section device availability.
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NOTES:
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GUIDELINES GETTING STARTED WITH 32-BIT MICROCONTROLLERS
Decoupling Capacitors
decoupling capacitors power supply pins, such VDD, VSS, AVDD, AVSS required. Figure 2-1. Consider following criteria when using decoupling capacitors: Value type capacitor: value (100 nF), 10-20V recommended. capacitor should Equivalent Series Resistance (low-ESR) capacitor have resonance frequency range higher. further recommended that ceramic capacitors used. Placement printed circuit board: decoupling capacitors should placed close pins possible. recommended that capacitors placed same side board device. space constricted, capacitor placed another layer using via; however, ensure that trace length from capacitor within onequarter inch length. Handling high frequency noise: board experiencing high frequency noise, upward tens MHz, second ceramic-type capacitor parallel above described decoupling capacitor. value second capacitor range 0.01 0.001 Place this second capacitor next primary decoupling capacitor. high-speed circuit designs, consider implementing decade pair capacitances close power ground pins possible. example, parallel with 0.001 Maximizing performance: board layout from power supply circuit, power return traces decoupling capacitors first, then device pins. This ensures that decoupling capacitors first power chain. Equally important keep trace length between capacitor power pins minimum thereby reducing track inductance.
Note This data sheet summarizes features PIC32MX5XX/6XX/7XX family devices. intended comprehensive reference source. complement information this data sheet, refer related section "PIC32MX Family Reference Manual", which available from Microchip site (www.microchip.com/PIC32) Some registers associated bits described this section available devices. Refer Section "Memory Organization" this data sheet device-specific register information.
Basic Connection Requirements
Getting started with PIC32MX5XX/6XX/7XX family 32-bit Microcontrollers (MCU) requires attention minimal device connections before proceeding with development. following list names, which must always connected: pins (see Section "Decoupling Capacitors") AVDD AVSS pins-even module used (see Section "Decoupling Capacitors") VCAP/VDDCORE (see Section "Capacitor Internal Voltage Regulator (VCAP/VDDCORE)") MCLR (see Section "Master Clear (MCLR) Pin") PGECx/PGEDx pins-used In-Circuit Serial Programming (ICSPTM) debugging purposes (see Section "ICSP Pins") OSC1 OSC2 pins-when external oscillator source used (see Section "External Oscillator Pins") following required, well: VREF+/VREF- pins-used when external voltage reference module implemented Note: AVDD AVSS pins must connected, regardless voltage reference source.
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FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION
Ceramic
Master Clear (MCLR)
MCLR provides specific device functions: Device Reset Device programming debugging Pulling MCLR generates device Reset. Figure shows typical MCLR circuit. During device programming debugging, resistance capacitance that added must considered. Device programmers debuggers drive MCLR pin. Consequently, specific voltage levels (VIH VIL) fast signal transitions must adversely affected. Therefore, specific values will need adjusted based application requirements. example, shown Figure 2-2, recommended that capacitor isolated from MCLR during programming debugging operations. Place components shown Figure within one-quarter inch from MCLR pin.
CEFC
MCLR VCAP/VDDCORE
PIC32MX
AVDD Ceramic Ceramic AVSS Ceramic
Ceramic
2.2.1
BULK CAPACITORS
bulk capacitor recommended improve power supply stability. Typical values range from This capacitor should located close device possible.
FIGURE 2-2:
EXAMPLE MCLR CONNECTIONS
MCLR PIC32MX
2.3.1
Capacitor Internal Voltage Regulator (VCAP/VDDCORE)
INTERNAL REGULATOR MODE
low-ESR ohm) capacitor required VCAP/VDDCORE pin, which used stabilize internal voltage regulator output. VCAP/VDDCORE must connected VDD, must have CEFC capacitor, with least rating, connected ground. type ceramic tantalum. Refer Section 31.0 "Electrical Characteristics" additional information CEFC specifications.
Note
recommended. suggested starting value Ensure that MCLR specifications met. will limit current flowing into MCLR from external capacitor event MCLR breakdown, Electrostatic Discharge (ESD) Electrical Overstress (EOS). Ensure that MCLR specifications met. capacitor sized prevent unintentional Resets from brief glitches extend device Reset period during POR.
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ICSP Pins JTAG
PGECx PGEDx pins used In-Circuit Serial Programming(ICSPTM) debugging purposes. recommended keep trace length between ICSP connector ICSP pins device short possible. ICSP connector expected experience event, series resistor recommended, with value range tens Ohms, exceed Ohms. Pull-up resistors, series diodes, capacitors PGECx PGEDx pins recommended they will interfere with programmer/debugger communications device. such discrete components application requirement, they should removed from circuit during programming debugging. Alternatively, refer AC/DC characteristics timing requirements information respective device Flash programming specification information capacitive loading limits input voltage high (VIH) input (VIL) requirements. Ensure that "Communication Channel Select" (i.e., PGECx/PGEDx pins) programmed into device matches physical connections ICSP MPLAB® MPLAB MPLAB REAL ICETM. more information REAL connection requirements, refer following documents that available Microchip site. "MPLAB® In-Circuit Debugger User's Guide" DS51331 "Using MPLAB® (poster) DS51265 "MPLAB® Design Advisory" DS51566 "Using MPLAB® (poster) DS51765 "MPLAB® Design Advisory" DS51764 "MPLAB® REAL ICEIn-Circuit Debugger User's Guide" DS51616 "Using MPLAB® REAL ICETM" (poster) DS51749 TMS, TDO, TDI, pins used testing debugging according Joint Test Action Group (JTAG) standard. recommended keep trace length between JTAG connector JTAG pins device short possible. JTAG connector expected experience event, series resistor recommended, with value range tens Ohms, exceed Ohms. Pull-up resistors, series diodes, capacitors TMS, TDO, TDI, pins recommended they will interfere with programmer/debugger communications device. such discrete components application requirement, they should removed from circuit during programming debugging. Alternatively, refer AC/DC characteristics timing requirements information respective device Flash programming specification information capacitive loading limits input voltage high (VIH) input (VIL) requirements.
Trace
trace pins connected hardware-traceenabled programmer provide compress real time instruction trace. When used trace TRD3, TRD2, TRD1, TRD0, TRCLK pins should dedicated this use. trace hardware requires series resistor between trace pins trace connector.
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External Oscillator Pins
Many MCUs have options least oscillators: high-frequency primary oscillator low-frequency secondary oscillator (refer Section "Oscillator Configuration" details). oscillator circuit should placed same side board device. Also, place oscillator circuit close respective oscillator pins, exceeding one-half inch distance between them. load capacitors should placed next oscillator itself, same side board. grounded copper pour around oscillator circuit isolate them from surrounding circuits. grounded copper pour should routed directly ground. signal traces power traces inside ground pour. Also, using two-sided board, avoid traces other side board where crystal placed. suggested layout shown Figure 2-3.
Configuration Analog Digital Pins During ICSP Operations
MPLAB REAL selected debugger, automatically initializes input pins (ANx) "digital" pins setting bits ADPCFG register. bits this register that correspond pins that initialized MPLAB REAL ICE, must cleared user application firmware; otherwise, communication errors will result between debugger device. your application needs certain pins analog input pins during debug session, user application must clear corresponding bits ADPCFG register during initialization module. When MPLAB REAL used programmer, user application firmware must correctly configure ADPCFG register. Automatic initialization this register only done during debugger operation. Failure correctly configure register(s) will result pins being recognized analog input pins, resulting port value being read logic '0', which affect user application functionality.
FIGURE 2-3:
SUGGESTED OSCILLATOR CIRCUIT PLACEMENT
Oscillator Secondary Guard Trace
2.10
Unused I/Os
Guard Ring
Unused pins should allowed float inputs. They configured outputs driven logic-low state. Alternatively, inputs reserved connecting through resistor configuring input.
Main Oscillator
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PIC32MX
Note This data sheet summarizes features PIC32MX5XX/6XX/7XX family devices. intended comprehensive reference source. complement information this data sheet, refer Section "MCU" (DS61113) "PIC32MX Family Reference Manual", which available from Microchip site (www.microchip.com/PIC32). Resources MIPS32® M4K® Processor Core available http://www.mips.com. Some registers associated bits described this section available devices. Refer Section "Memory Organization" this data sheet device-specific register information. module heart PIC32MX5XX/6XX/7XX family processor. fetches instructions, decodes each instruction, fetches source operands, executes each instruction writes results instruction execution proper destinations. Atomic interrupt enable/disable shadow registers minimize latency interrupt handlers field manipulation instructions MIPS16eCode Compression 16-bit encoding 32-bit instructions improve code density Special PC-relative instructions efficient loading addresses constants SAVE RESTORE macro instructions setting tearing down stack frames within subroutines Improved support handling 16-bit data types Simple Fixed Mapping Translation (FMT) mechanism Simple Dual Interface Independent 32-bit address data busses Transactions aborted improve interrupt latency Autonomous Multiply/Divide Unit Maximum issue rate 32x16 multiply clock Maximum issue rate 32x32 multiply every other clock Early-in iterative divide. Minimum maximum clock latency (dividend (rs) sign extension-dependent) Power Control Minimum frequency: Low-Power mode (triggered WAIT instruction) Extensive local gated clocks EJTAG Debug Instruction Trace Support single stepping Virtual instruction data address/value Breakpoints tracing with trace compression
Features
5-stage pipeline 32-bit Address Data Paths MIPS32 Enhanced Architecture (Release Multiply-Accumulate Multiply-Subtract Instructions Targeted Multiply Instruction Zero/One Detect Instructions WAIT Instruction Conditional Move Instructions (MOVN, MOVZ) Vectored interrupts Programmable exception vector base
FIGURE 3-1:
BLOCK DIAGRAM
EJTAG Trace Execution Core (RF/ALU/Shift) Off-Chip Debug Dual Matrix
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Trace
Interface
System Coprocessor
Power Management
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Architecture Overview
3.2.2 MULTIPLY/DIVIDE UNIT (MDU)
PIC32MX5XX/6XX/7XX family core contains several logic blocks working together parallel, providing efficient high performance computing engine. following blocks included with core: Execution Unit Multiply/Divide Unit (MDU) System Control Co-processor (CP0) Fixed Mapping Translation (FMT) Dual Internal interfaces Power Management MIPS16e Support Enhanced JTAG (EJTAG) Controller PIC32MX5XX/6XX/7XX family core includes multiply/divide unit (MDU) that contains separate pipeline multiply divide operations. This pipeline operates parallel with integer unit (IU) pipeline does stall when pipeline stalls. This allows operations partially masked system stalls and/or other integer unit instructions. high-performance consists 32x16 booth recoded multiplier, result/accumulation registers LO), divide state machine, necessary multiplexers control logic. first number shown (`32' 32x16) represents operand. second number (`16' 32x16) represents operand. PIC32MX core only checks value latter (rt) operand determine many times operation must pass through multiplier. 16x16 32x16 operations pass through multiplier once. 32x32 operation passes through multiplier twice. supports execution 16x16 32x16 multiply operation every clock cycle; 32x32 multiply operations issued every other clock cycle. Appropriate interlocks implemented stall issuance back-to-back 32x32 multiply operations. multiply operand size automatically determined logic built into MDU. Divide operations implemented with simple clock iterative algorithm. early-in detection checks sign extension dividend (rs) operand. bits wide, iterations skipped. 16bit-wide iterations skipped, 24-bitwide iterations skipped. attempt issue subsequent instruction while divide still active causes pipeline stall until divide operation completed. Table lists repeat rate (peak issue rate cycles until operation reissued) latency (number cycles until result available) PIC32MX core multiply divide instructions. approximate latency repeat rates listed terms pipeline clocks.
3.2.1
EXECUTION UNIT
PIC32MX5XX/6XX/7XX family core execution unit implements load/store architecture with single-cycle operations (logical, shift, add, subtract) autonomous multiply/divide unit. core contains thirty-two 32-bit General Purpose Registers (GPRs) used integer operations address calculation. additional register file shadow (containing thirty-two registers) added minimize context switching overhead during interrupt/exception processing. register file consists read ports write port fully bypassed minimize operation latency pipeline. execution unit includes: 32-bit adder used calculating data address Address unit calculating next instruction address Logic branch determination branch target address calculation Load aligner Bypass multiplexers used avoid stalls when executing instructions streams where data producing instructions followed closely consumers their results Leading Zero/One detect unit implementing instructions Arithmetic Logic Unit (ALU) performing bitwise logical operations Shifter Store Aligner
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TABLE 3-1: PIC32MX5XX/6XX/7XX FAMILY CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT LATENCIES REPEAT RATES
Opcode MULT/MULTU, MADD/MADDU, MSUB/MSUBU DIV/DIVU Operand Size (mul (div bits bits bits bits bits bits bits bits MIPS architecture defines that result multiply divide operation placed registers. Using Move-From-HI (MFHI) MoveFrom-LO (MFLO) instructions, these values transferred General Purpose Register file. addition HI/LO targeted operations, MIPS32 architecture also defines multiply instruction, MUL, which places least significant results primary register file instead HI/LO register pair. avoiding explicit MFLO instruction, required when using register, supporting multiple destination registers, throughput multiply-intensive operations increased. other instructions, multiply-add (MADD) multiply-subtract (MSUB), used perform multiplyaccumulate multiply-subtract operations. MADD instruction multiplies numbers then adds product current contents registers. Similarly, MSUB instruction multiplies operands then subtracts product from registers. MADD MSUB operations commonly used algorithms. Latency Repeat Rate
3.2.3
SYSTEM CONTROL CO-PROCESSOR (CP0)
MIPS architecture, responsible virtual-to-physical address translation, exception control system, processor's diagnostics capability, operating modes (Kernel, User, Debug), whether interrupts enabled disabled. Configuration information, such presence options like MIPS16e, also available accessing registers, listed Table 3-2.
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TABLE 3-2: CO-PROCESSOR REGISTERS
Function Reserved PIC32MX5XX/6XX/7XX family core. Enables access RDHWR instruction selected hardware registers. Reports address most recent address-related exception. Processor cycle count. Reserved PIC32MX5XX/6XX/7XX family core. Timer interrupt control. Processor status control. Interrupt system status control. Shadow register status control. Provides mapping from vectored interrupt shadow set. Cause last general exception. Program counter last exception. Processor identification revision. Exception vector base register. Configuration register. Configuration register Configuration register Configuration register Reserved PIC32MX5XX/6XX/7XX family core. Debug control exception status. Program counter last debug exception. Reserved PIC32MX5XX/6XX/7XX family core. Program counter last error. Debug handler scratchpad register.
Register Register Number Name 17-22 25-29 Note Reserved HWREna BadVAddr(1) Count
Reserved Compare Status(1) IntCtl
SRSCtl(1) SRSMap Cause(1) EPC(1) PRId EBASE Config Config1 Config2 Config3 Reserved Debug
DEPC(2) Reserved ErrorEPC(1) DESAVE(2)
Registers used exception processing. Registers used during debug.
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Co-processor also contains logic identifying managing exceptions. Exceptions caused variety sources, including alignment errors data, external events, program errors. Table lists exception types order priority.
TABLE 3-3:
Exception Reset DINT Interrupt AdEL DDBL/DDBS AdEL AdES DDBL
PIC32MX5XX/6XX/7XX FAMILY CORE EXCEPTION TYPES
Description Assertion MCLR Power-on Reset (POR). EJTAG Debug Single Step. EJTAG Debug Interrupt. Caused assertion external EJ_DINT input, setting EjtagBrk register. Assertion signal. Assertion unmasked hardware software interrupt signal. EJTAG debug hardware instruction break matched. Fetch address alignment error. Fetch reference protected address. Instruction fetch error. EJTAG Breakpoint (execution SDBBP instruction). Execution SYSCALL instruction. Execution BREAK instruction. Execution Reserved Instruction. Execution co-processor instruction co-processor that enabled. Execution CorExtend instruction when CorExtend enabled. Execution arithmetic instruction that overflowed. Execution trap (when trap condition true). EJTAG Data Address Break (address only) EJTAG Data Value Break Store (address value). Load address alignment error Load reference protected address. Store address alignment error. Store protected address. Load store error. EJTAG data hardware breakpoint matched load data compare.
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Power Management EJTAG Debug Support
PIC32MX5XX/6XX/7XX family core offers number power management features, including lowpower design, active power management, powerdown modes operation. core static design that supports slowing halting clocks, which reduces system power consumption during idle periods. PIC32MX5XX/6XX/7XX family core provides Enhanced JTAG (EJTAG) interface software debug application kernel code. addition standard User mode Kernel modes operation, PIC32MX5XX/6XX/7XX family core provides Debug mode that entered after debug exception (derived from hardware breakpoint, single-step exception, etc.) taken continues until Debug Exception Return (DERET) instruction executed. During this time, processor executes debug exception handler routine. EJTAG interface operates through Test Access Port (TAP), serial communication port used transferring test data PIC32MX5XX/6XX/7XX family core. addition standard JTAG instructions, special instructions defined EJTAG specification define which registers selected they used.
3.3.1
INSTRUCTION-CONTROLLED POWER MANAGEMENT
mechanism invoking Power-Down mode through execution WAIT instruction. more information power management, Section 27.0 "Power-Saving Features".
3.3.2
LOCAL CLOCK GATING
majority power consumed PIC32MX5XX/6XX/7XX family core clock tree clocking registers. PIC32MX family uses extensive local gated-clocks reduce this dynamic power consumption.
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Note:
MEMORY ORGANIZATION
This data sheet summarizes features PIC32MX5XX/6XX/7XX family devices. intended comprehensive reference source. detailed information, refer Section "Memory Organization" (DS61115) "PIC32MX Family Reference Manual", which available from Microchip site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX Memory Layout
PIC32MX5XX/6XX/7XX microcontrollers provide unified virtual memory address space. memory regions, including program, data memory, SFRs, Configuration registers, reside this address space their respective unique addresses. program data memories optionally partitioned into user kernel memories. addition, data memory made executable, allowing PIC32MX5XX/6XX/7XX devices execute from data memory. features include: 32-bit native data width Separate User (KUSEG) Kernel (KSEG0/KSEG1) mode address space Flexible program Flash memory partitioning Flexible data partitioning data program space Separate boot Flash memory protected code Robust exception handling intercept runaway code Simple memory mapping with Fixed Mapping Translation (FMT) unit Cacheable (KSEG0) non-cacheable (KSEG1) address regions
PIC32MX5XX/6XX/7XX microcontrollers implement address schemes: virtual physical. hardware resources such program memory, data memory peripherals located their respective physical addresses. Virtual addresses exclusively used fetch execute instructions well access peripherals. Physical addresses used master peripherals such Flash controller that access memory independently CPU. memory maps PIC32MX5XX/6XX/7XX devices shown Figure 4-1, Figure 4-2, Figure 4-3.
4.1.1
PERIPHERAL REGISTERS LOCATIONS
Table through Table 4-44 contain peripheral address maps PIC32MX5XX/6XX/7XX devices. Peripherals located mapped byte boundaries. Peripherals mapped Kbyte boundaries.
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FIGURE 4-1: MEMORY RESET PIC32MX575F256H PIC32MX575F256L DEVICES(1)
Virtual Memory 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD040000 0xBD03FFFF Program Flash(2) 0xBD000000 0xA0008000 0xA0007FFF RAM(2) 0xA0000000 0x9FC02FF0 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 KSEG0 Reserved 0x9D040000 0x9D03FFFF Program Flash(2) 0x9D000000 0x80008000 0x80007FFF RAM(2) 0x80000000 0x00000000 Note Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00008000 0x00007FFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF SFRs 0x1F800000 Reserved 0x1D040000 0x1D03FFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory 0xFFFFFFFF
Memory areas shown scale. size this memory region programmable (see Section "Memory Organization" (DS61115)) changed initialization code provided end-user development tools (refer specific development tool documentation information).
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FIGURE 4-2: MEMORY RESET PIC32MX575F512H, PIC32MX575F512L, PIC32MX675F512H, PIC32MX675F512L DEVICES
Virtual Memory 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD080000 0xBD07FFFF Program Flash(2) 0xBD000000 0xA0010000 0xA000FFFF RAM(2) 0xA0000000 0x9FC02FF0 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 KSEG0 Reserved 0x9D080000 0x9D07FFFF Program Flash(2) 0x9D000000 0x80010000 0x8000FFFF RAM(2) 0x80000000 0x00000000 Note Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00010000 0x0000FFFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF SFRs 0x1F800000 Reserved 0x1D080000 0x1D07FFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory 0xFFFFFFFF
Memory areas shown scale. size this memory region programmable (see Section "Memory Organization" (DS61115)) changed initialization code provided end-user development tools (refer specific development tool documentation information).
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FIGURE 4-3: MEMORY RESET PIC32MX695F512H, PIC32MX695F512L, PIC32MX795F512H, PIC32MX795F512L DEVICES
Virtual Memory 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD080000 0xBD07FFFF Program Flash(2) 0xBD000000 0xA0020000 0xA001FFFF RAM(2) 0xA0000000 0x9FC02FF0 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 KSEG0 Reserved 0x9D080000 0x9D07FFFF Program Flash(2) 0x9D000000 0x80020000 0x8001FFFF RAM(2) 0x80000000 0x00000000 Note Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00020000 0x0001FFFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF SFRs 0x1F800000 Reserved 0x1D080000 0x1D07FFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory 0xFFFFFFFF
Memory areas shown scale. size this memory region programmable (see Section "Memory Organization" (DS61115)) changed initialization code provided end-user development tools (refer specific development tool documentation information).
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TABLE 4-1:
Virtual Address (BF88_#) Register Name
MATRIX REGISTER
Bits Range Resets
0040 0000 0000 0000 0000 0000 0000 xxxx xxxx BMXPUPBA<19:16> 0000 0000 xxxx xxxx
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
2000 2010
BMXCON(1) BMXDKPBA(1)
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
BMXCHEDMA
BMXWSDRM
BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F BMXARB<2:0>
BMXDKPBA<15:0> BMXDUDBA<15:0> BMXDUPBA<15:0> BMXDRMSZ<31:0>
2020 BMXDUDBA
2030 BMXDUPBA
2040
BMXDRMSZ
2050 BMXPUPBA
BMXPUPBA<15:0> BMXPFMSZ<31:0>
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2060
BMXPFMSZ
2070 BMXBOOTSZ Legend: Note
0000 BMXBOOTSZ<31:0> 15:0 3000 unknown value Reset; unimplemented, read `0'. Reset values shown hexadecimal. This register corresponding CLR, SET, Registers virtual address, plus offset 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
PIC32MX5XX/6XX/7XX
TABLE 4-2:
Virtual Address (BF88_#) Range Register Name
INTERRUPT REGISTER PIC32MX575F256H PIC32MX575F512H DEVICES(1)
Bits Resets
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PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
1000 INTCON INTSTAT IPTMR
31:16 15:0 31:16 15:0 31:16
MVEC
TRC<2:0>
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000 0000 0000 0000 0000
RIPL<2:0>
1010
VEC<5:0>
1020
IPTMR<31:0> 15:0 U1ATXIF U1ARXIF U1AEIF OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 0000 0000
1030
IFS0
31:16
I2C1MIF
I2CSIF
I2CBIF
SPI1ATXIF SPI1ARXIF SPI1AEIF I2C1AMIF I2C1ASIF INT2IF I2C1ABIF OC2IF CAN1IF U3ATXIF
15:0 31:16
INT3IF IC3EIF
OC3IF IC2EIF
IC3IF IC1EIF
T3IF
IC2IF USBIF U3ARXIF
T2IF FCEIF U3AEIF
INT1IF DMA7IF U2ATXIF
OC1IF DMA6IF U2ARXIF
IC1IF DMA5IF U2AEIF
T1IF DMA4IF
INT0IF DMA3IF
CS1IF DMA2IF
CS0IF DMA1IF
CTIF DMA0IF
0000 0000
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1040
IFS1 15:0 RTCCIF FSCMIF
SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF I2C3AMIF I2C3ASIF U3BEIF I2C3ASIF U2BTXIF I2C2AMIF U2BRXIF I2C2ASIF U2BEIF I2C2ABIF U1BTXIF
CMP2IF
CMP1IF
PMPIF
AD1IF
CNIF
0000
1050
IFS2
31:16 15:0
U1ATXIE
U3BTXIF U1ARXIE
U3BRXIF U1AEIE
U1BRXIF
U1BEIF
PMPEIF
IC5EIF
IC4EIF
0000 0000
1060
IEC0
31:16
I2C1MIE
I2C1SIE
I2C1BIE SPI1ATXIE SPI1ARXIE SPI1AEIE I2C1AMIE I2C1ASIE INT2IE I2C1ABIE OC2IE CAN1IE U3ATXIE
OC5IE
IC5IE
T5IE
INT4IE
OC4IE
IC4IE
T4IE
0000
15:0 31:16 1070 IEC1 15:0
INT3IE IC3EIE
OC3IE IC2EIE
IC3IE IC1EIE
T3IE
IC2IE USBIE U3ARXIE
T2IE FCEIE U3AEIE
INT1IE DMA7IE U2ATXIE
OC1IE DMA6IE U2ARXIE
IC1IE DMA5IE U2AEIE
T1IE DMA4IE
INT0IE DMA3IE
CS1IE DMA2IE
CS0IE DMA1IE
CTIE DMA0IE
0000 0000
RTCCIE
FSCMIE
SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE I2C3AMIE I2C3ASIE U3BEIE I2C3ASIE U2BTXIE I2C2AMIE U2BRXIE I2C2ASIE U2BEIE I2C2ABIE U1BTXIE
CMP2IE
CMP1IE
PMPIE
AD1IE
CNIE
0000
1080
IEC2
31:16 15:0
U3BTXIE INT0IP<2:0> CS0IP<2:0> INT1IP<2:0> IC1IP<2:0>
U3BRXIE
U1BRXIE
U1BEIE CS1IP<2:0> CTIP<2:0> OC1IP<2:0> T1IP<2:0>
PMPEIE
IC5EIE
IC4EIE
0000 0000 0000 0000 0000 0000
1090
IPC0
31:16 15:0
INT0IS<1:0> CS0IS<1:0> INT1IS<1:0> IC1IS<1:0>
CS1IS<1:0> CTIS<1:0> OC1IS<1:0> T1IS<1:0>
10A0 Legend: Note
IPC1
31:16 15:0
unknown value Reset; unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-2:
Virtual Address (BF88_#) Range Register Name
INTERRUPT REGISTER PIC32MX575F256H PIC32MX575F512H DEVICES(1) (CONTINUED)
Bits Resets
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
2009 Microchip Technology Inc.
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
10B0
IPC2
31:16 15:0
INT2IP<2:0> IC2IP<2:0> INT3IP<2:0> IC3IP<2:0> INT4IP<2:0> IC4IP<2:0> IC5IP<2:0> AD1IP<2:0>
INT2IS<1:0> IC2IS<1:0> INT3IS<1:0> IC3IS<1:0> INT4IS<1:0> IC4IS<1:0>
OC2IP<2:0> T2IP<2:0> OC3IP<2:0> T3IP<2:0> OC4IP<2:0> T4IP<2:0> OC5IP<2:0> T5IP<2:0> CNIP<2:0> U1AIP<2:0>
OC2IS<1:0> T2IS<1:0> OC3IS<1:0> T3IS<1:0> OC4IS<1:0> T4IS<1:0> OC5IS<1:0> T5IS<1:0> CNIS<1:0> U1AIS<1:0> SPI1AIS<1:0> I2C1AIS<1:0>
10C0
IPC3
31:16 15:0
10D0
IPC4
31:16 15:0
10E0
IPC5
31:16 15:0 31:16
IC5IS<1:0> AD1IS<1:0>
10F0
IPC6 15:0 I2C1IP<2:0> I2C1IS<1:0>
SPI1AIP<2:0> I2C1AIP<2:0>
DS61156B-page
U2AIP<2:0> 1100 IPC7 31:16 SPI2AIP<2:0> I2C2AIP<2:0> 15:0 31:16 1110 IPC8 15:0 CMP1IP<2:0> RTCCIP<2:0>
U2AIS<1:0> SPI2AIS<1:0> I2C2AIS<1:0> CMP1IS<1:0> RTCCIS<1:0> PMPIP<2:0> FSCMIP<2:0> U3AIP<2:0> SPI3AIP<2:0> I2C3AIP<2:0> PMPIS<1:0> FSCMIS<1:0> U3AIS<1:0> SPI3AIS<1:0> I2C3AIS<1:0> DMA2IS<1:0> DMA0IS<1:0> DMA6IS<1:0> DMA4IS<1:0> CAN1IS<1:0> FCEIS<1:0> U2BIS<1:0> 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CMP2IP<2:0> CMP2IS<1:0>
PIC32MX5XX/6XX/7XX
1120
IPC9
31:16 15:0
DMA3IP<2:0> DMA1IP<2:0> DMA7IP<2:0> DMA5IP<2:0> USBIP<2:0> U3BIP<2:0> U1BIP<2:0>
DMA3IS<1:0> DMA1IS<1:0> DMA7IS<1:0> DMA5IS<1:0>
DMA2IP<2:0> DMA0IP<2:0> DMA6IP<2:0> DMA4IP<2:0> CAN1IP<2:0> FCEIP<2:0> U2BIP<2:0>
1130
IPC10
31:16 15:0
1140
IPC11
31:16 15:0
USBIS<1:0> U3BIS<1:0> U1BIS<1:0>
1150
IPC12
31:16 15:0
Legend: Note
unknown value Reset; unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-3:
Virtual Address (BF88_#) Range Register Name
INTERRUPT REGISTER PIC32MX675F512H PIC32MX695F512H DEVICES(1)
Bits Resets
DS61156B-page
PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
1000 INTCON 1010 INTSTAT 1020 IPTMR
31:16 15:0 31:16 15:0 31:16 15:0
MVEC
TRC<2:0> RIPL<2:0>
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000 0000 0000 0000 0000 0000
VEC<5:0>
IPTMR<31:0> U1ATXIF U1ARXIF U1AEIF IC2IF USBIF U3ARXIF I2C3ASIF U3BEIF IC2IE USBIE U3ARXIE T2IF FCEIF U3AEIF I2C3ASIF U2BTXIF T2IE FCEIE U3AEIE INT1IF DMA7IF U2ATXIF I2C2AMIF U2BRXIF INT1IE DMA7IE U2ATXIE OC5IF OC1IF DMA6IF U2ARXIF I2C2ASIF U2BEIF OC5IE OC1IE DMA6IE U2ARXIE IC5IF IC1IF DMA5IF U2AEIF CMP2IF U1BRXIF T5IE T1IE DMA4IE CMP2IE U1BRXIE CMP1IF U1BEIF INT4IE INT0IE DMA3IE CMP1IE U1BEIE CS1IP<2:0> CTIP<2:0> OC1IP<2:0> T1IP<2:0> OC2IP<2:0> PMPIF PMPEIF OC4IE CS1IE DMA2IE PMPIE PMPEIE AD1IF IC5EIF IC4IE CS0IE DMA1IE AD1IE IC5EIE CNIF IC4EIF T4IE CTIE DMA0IE CNIE IC4EIE T5IF T1IF DMA4IF INT4IF INT0IF DMA3IF OC4IF CS1IF DMA2IF IC4IF CS0IF DMA1IF T4IF CTIF DMA0IF
1030
IFS0
31:16 15:0 31:16
I2C1MIF INT3IF IC3EIF RTCCIF
I2CSIF OC3IF IC2EIF FSCMIF I2C1SIE OC3IE IC2EIE FSCMIE
I2CBIF IC3IF IC1EIF
SPI1ATXIF SPI1ARXIF SPI1AEIF I2C1AMIF I2C1ASIF T3IF ETHIF INT2IF I2C1ABIF OC2IF U3ATXIF
0000
0000 0000
1040
IFS1
2009 Microchip Technology Inc.
15:0 31:16 15:0
SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF I2C3AMIF I2C2ABIF U1BTXIF IC5IE IC1IE DMA5IE U2AEIE U3BRXIF U1AEIE
0000
1050
IFS2
0000 0000
I2C1BIE IC3IE IC1EIE
U1ATXIE
U3BTXIF U1ARXIE
1060
IEC0
31:16 I2C1MIE 15:0 31:16 INT3IE IC3EIE RTCCIE
SPI1ATXIE SPI1ARXIE SPI1AEIE I2C1AMIE I2C1ASIE T3IE ETHIE INT2IE U3BTXIE INT0IP<2:0> CS0IP<2:0> INT1IP<2:0> IC1IP<2:0> INT2IP<2:0> I2C1ABIE OC2IE U3ATXIE
0000
0000 0000
1070
IEC1
15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE I2C2ASIE U2BTXIE U2BRXIE U2BEIE I2C2ABIE U1BTXIE U3BRXIE U3BEIE
0000
1080 1090 10A0 10B0 Legend: Note
IEC2 IPC0 IPC1 IPC2
0000 0000 0000 0000 0000 0000 0000
INT0IS<1:0> CS0IS<1:0> INT1IS<1:0> IC1IS<1:0> INT2IS<1:0>
CS1IS<1:0> CTIS<1:0> OC1IS<1:0> T1IS<1:0> OC2IS<1:0>
IC2IP<2:0> IC2IS<1:0> T2IP<2:0> T2IS<1:0> 0000 15:0 unknown value Reset; unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-3:
Virtual Address (BF88_#) Range Register Name
INTERRUPT REGISTER PIC32MX675F512H PIC32MX695F512H DEVICES(1) (CONTINUED)
Bits Resets
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
2009 Microchip Technology Inc.
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
10C0 10D0 10E0
IPC3 IPC4 IPC5
31:16 15:0 31:16 15:0 31:16 15:0 31:16
INT3IP<2:0> IC3IP<2:0> INT4IP<2:0> IC4IP<2:0> IC5IP<2:0> AD1IP<2:0> I2C1IP<2:0> U2AIP<2:0>
INT3IS<1:0> IC3IS<1:0> INT4IS<1:0> IC4IS<1:0> IC5IS<1:0> AD1IS<1:0> I2C1IS<1:0> U2AIS<1:0> SPI2AIS<1:0> I2C2AIS<1:0> CMP1IS<1:0> RTCCIS<1:0>
OC3IP<2:0> T3IP<2:0> OC4IP<2:0> T4IP<2:0> OC5IP<2:0> T5IP<2:0> CNIP<2:0> U1AIP<2:0> SPI1AIP<2:0> I2C1AIP<2:0>
OC3IS<1:0> T3IS<1:0> OC4IS<1:0> T4IS<1:0> OC5IS<1:0> T5IS<1:0> CNIS<1:0> U1AIS<1:0> SPI1AIS<1:0> I2C1AIS<1:0> CMP2IS<1:0> PMPIS<1:0> FSCMIS<1:0> U3AIS<1:0> SPI3AIS<1:0> I2C3AIS<1:0> DMA2IS<1:0> DMA0IS<1:0> DMA6IS<1:0> DMA4IS<1:0> FCEIS<1:0> U2BIS<1:0>
10F0
IPC6
15:0
1100
IPC7
31:16 15:0 31:16
SPI2AIP<2:0> I2C2AIP<2:0> CMP1IP<2:0> RTCCIP<2:0> DMA3IP<2:0> DMA1IP<2:0> DMA7IP<2:0> DMA5IP<2:0> USBIP<2:0> U3BIP<2:0>
CMP2IP<2:0> PMPIP<2:0> FSCMIP<2:0> U3AIP<2:0> SPI3AIP<2:0> I2C3AIP<2:0> DMA2IP<2:0> DMA0IP<2:0> DMA6IP<2:0> DMA4IP<2:0> FCEIP<2:0> U2BIP<2:0>
DS61156B-page
PIC32MX5XX/6XX/7XX
1110
IPC8
15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
0000
1120 1130 1140 1150
IPC9 IPC10 IPC11 IPC12
DMA3IS<1:0> DMA1IS<1:0> DMA7IS<1:0> DMA5IS<1:0> USBIS<1:0> U3BIS<1:0>
0000 0000 0000 0000 0000 0000 0000
Legend: Note
U1BIP<2:0> U1BIS<1:0> ETHIP<2:0> ETHIS<1:0> 0000 15:0 unknown value Reset; unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-4:
Virtual Address (BF88_#) Range Register Name
INTERRUPT REGISTER PIC32MX795F512H DEVICE(1)
Bits Resets
DS61156B-page
PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
1000 INTCON 1010 INTSTAT 1020 IPTMR
31:16 15:0 31:16 15:0 31:16 15:0
MVEC
TRC<2:0> RIPL<2:0>
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000 0000 0000 0000 0000 0000
VEC<5:0>
IPTMR<31:0> U1ATXIF U1ARXIF I2C1ASIF INT2IF CAN2IF U3BTXIF U1ARXIE U1AEIF IC2IF USBIF U3ARXIF I2C3ASIF U3BEIF IC2IE USBIE U3ARXIE T2IF FCEIF U3AEIF I2C3ASIF U2BTXIF T2IE FCEIE U3AEIE INT1IF DMA7IF U2ATXIF I2C2AMIF U2BRXIF INT1IE DMA7IE U2ATXIE OC5IF OC1IF DMA6IF U2ARXIF I2C2ASIF U2BEIF OC5IE OC1IE DMA6IE U2ARXIE IC5IF IC1IF DMA5IF U2AEIF CMP2IF U1BRXIF T5IE T1IE DMA4IE CMP2IE U1BRXIE CMP1IF U1BEIF INT4IE INT0IE DMA3IE CMP1IE U1BEIE CS1IP<2:0> CTIP<2:0> OC1IP<2:0> T1IP<2:0> OC2IP<2:0> PMPIF PMPEIF OC4IE CS1IE DMA2IE PMPIE PMPEIE AD1IF IC5EIF IC4IE CS0IE DMA1IE AD1IE IC5EIE CNIF IC4EIF T4IE CTIE DMA0IE CNIE IC4EIE T5IF T1IF DMA4IF INT4IF INT0IF DMA3IF OC4IF CS1IF DMA2IF IC4IF CS0IF DMA1IF T4IF CTIF DMA0IF
1030
IFS0
31:16 15:0 31:16
I2C1MIF INT3IF IC3EIF RTCCIF I2C1MIE INT3IE IC3EIE RTCCIE
I2CSIF OC3IF IC2EIF FSCMIF I2C1SIE OC3IE IC2EIE FSCMIE
I2CBIF IC3IF IC1EIF I2C1BIE IC3IE IC1EIE
SPI1ATXIF SPI1ARXIF SPI1AEIF I2C1AMIF T3IF ETHIF U1ATXIE I2C1ABIF OC2IF CAN1IF U3ATXIF
0000
0000 0000
1040
IFS1
2009 Microchip Technology Inc.
15:0 31:16 15:0 31:16 15:0 31:16
SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF I2C3AMIF I2C2ABIF U1BTXIF IC5IE IC1IE DMA5IE U2AEIE U3BRXIF U1AEIE
0000
1050
IFS2
0000 0000
1060
IEC0
SPI1ATXIE SPI1ARXIE SPI1AEIE I2C1AMIE I2C1ASIE T3IE ETHIE INT2IE CAN2IE U3BTXIE INT0IP<2:0> CS0IP<2:0> INT1IP<2:0> IC1IP<2:0> INT2IP<2:0> I2C1ABIE OC2IE CAN1IE U3ATXIE
0000
0000 0000
1070
IEC1
15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE I2C2ASIE U2BTXIE U2BRXIE U2BEIE I2C2ABIE U1BTXIE U3BRXIE U3BEIE
0000
1080 1090 10A0 10B0 Legend: Note
IEC2 IPC0 IPC1 IPC2
0000 0000 0000 0000 0000 0000 0000
INT0IS<1:0> CS0IS<1:0> INT1IS<1:0> IC1IS<1:0> INT2IS<1:0>
CS1IS<1:0> CTIS<1:0> OC1IS<1:0> T1IS<1:0> OC2IS<1:0>
IC2IP<2:0> IC2IS<1:0> T2IP<2:0> T2IS<1:0> 0000 15:0 unknown value Reset; unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-4:
Virtual Address (BF88_#) Range Register Name
INTERRUPT REGISTER PIC32MX795F512H DEVICE(1) (CONTINUED)
Bits Resets
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
2009 Microchip Technology Inc.
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
10C0 10D0 10E0
IPC3 IPC4 IPC5
31:16 15:0 31:16 15:0 31:16 15:0 31:16
INT3IP<2:0> IC3IP<2:0> INT4IP<2:0> IC4IP<2:0> IC5IP<2:0> AD1IP<2:0> I2C1IP<2:0> U2AIP<2:0>
INT3IS<1:0> IC3IS<1:0> INT4IS<1:0> IC4IS<1:0> IC5IS<1:0> AD1IS<1:0> I2C1IS<1:0> U2AIS<1:0> SPI2AIS<1:0> I2C2AIS<1:0> CMP1IS<1:0> RTCCIS<1:0>
OC3IP<2:0> T3IP<2:0> OC4IP<2:0> T4IP<2:0> OC5IP<2:0> T5IP<2:0> CNIP<2:0> U1AIP<2:0> SPI1AIP<2:0> I2C1AIP<2:0>
OC3IS<1:0> T3IS<1:0> OC4IS<1:0> T4IS<1:0> OC5IS<1:0> T5IS<1:0> CNIS<1:0> U1AIS<1:0> SPI1AIS<1:0> I2C1AIS<1:0> CMP2IS<1:0> PMPIS<1:0> FSCMIS<1:0> U3AIS<1:0> SPI3AIS<1:0> I2C3AIS<1:0> DMA2IS<1:0> DMA0IS<1:0> DMA6IS<1:0> DMA4IS<1:0> CAN1IS<1:0> FCEIS<1:0> U2BIS<1:0>
10F0
IPC6
15:0
1100
IPC7
31:16 15:0 31:16
SPI2AIP<2:0> I2C2AIP<2:0> CMP1IP<2:0> RTCCIP<2:0> DMA3IP<2:0> DMA1IP<2:0> DMA7IP<2:0> DMA5IP<2:0> CAN2IP<2:0> USBIP<2:0> U3BIP<2:0>
CMP2IP<2:0> PMPIP<2:0> FSCMIP<2:0> U3AIP<2:0> SPI3AIP<2:0> I2C3AIP<2:0> DMA2IP<2:0> DMA0IP<2:0> DMA6IP<2:0> DMA4IP<2:0> CAN1IP<2:0> FCEIP<2:0> U2BIP<2:0>
DS61156B-page
PIC32MX5XX/6XX/7XX
1110
IPC8
15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
0000
1120 1130 1140 1150 Legend: Note
IPC9 IPC10 IPC11 IPC12
DMA3IS<1:0> DMA1IS<1:0> DMA7IS<1:0> DMA5IS<1:0> CAN2IS<1:0> USBIS<1:0> U3BIS<1:0>
0000 0000 0000 0000 0000 0000 0000
U1BIP<2:0> U1BIS<1:0> ETHIP<2:0> ETHIS<1:0> 0000 15:0 unknown value Reset; unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-5:
Virtual Address (BF88_#) Range Register Name
INTERRUPT REGISTER PIC32MX575F512L PIC32MX575F256L DEVICES(1)
Bits Resets
DS61156B-page
PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
1000 INTCON 1010 INTSTAT 1020 IPTMR
31:16 15:0 31:16 15:0 31:16 15:0
MVEC
TRC<2:0> RIPL<2:0>
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000 0000 0000 0000 0000 0000
VEC<5:0>
IPTMR<31:0> U1ATXIF U1ARXIF I2C1ASIF INT2IF I2C2BIF U3BTXIF U1ARXIE U1AEIF SPI1TXIF IC2IF USBIF U3ARXIF I2C3ASIF U3BEIF SPI1RXIF T2IF FCEIF U3AEIF I2C3ASIF U2BTXIF SPI1EIF INT1IF DMA7IF U2ATXIF I2C2AMIF U2BRXIF SPI1EIE INT1IE DMA7IE U2ATXIE OC5IF OC1IF DMA6IF U2ARXIF I2C2ASIF U2BEIF OC5IE OC1IE DMA6IE U2ARXIE IC5IF IC1IF DMA5IF U2AEIF CMP2IF U1BRXIF T5IE T1IE DMA4IE CMP2IE U1BRXIE CMP1IF U1BEIF INT4IE INT0IE DMA3IE CMP1IE U1BEIE CS1IP<2:0> CTIP<2:0> OC1IP<2:0> T1IP<2:0> OC2IP<2:0> PMPIF PMPEIF OC4IE CS1IE DMA2IE PMPIE PMPEIE AD1IF IC5EIF IC4IE CS0IE DMA1IE AD1IE IC5EIE CNIF IC4EIF T4IE CTIE DMA0IE CNIE IC4EIE T5IF T1IF DMA4IF INT4IF INT0IF DMA3IF OC4IF CS1IF DMA2IF IC4IF CS0IF DMA1IF T4IF CTIF DMA0IF
1030
IFS0
31:16 15:0 31:16
I2C1MIF INT3IF IC3EIF RTCCIF I2C1MIE INT3IE IC3EIE RTCCIE
I2CSIF OC3IF IC2EIF FSCMIF I2C1SIE OC3IE IC2EIE FSCMIE
I2CBIF IC3IF IC1EIF I2C2MIF I2C1BIE IC3IE IC1EIE I2C2MIE
SPI1ATXIF SPI1ARXIF SPI1AEIF I2C1AMIF T3IF I2C2SIF U1ATXIE I2C1ABIF OC2IF CAN1IF U3ATXIF
0000
0000 0000
1040
IFS1
2009 Microchip Technology Inc.
15:0 31:16 15:0 31:16 15:0 31:16
SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF I2C3AMIF I2C2ABIF U1BTXIF IC5IE IC1IE DMA5IE U2AEIE U3BRXIF U1AEIE SPI1TXIE SPI1RXIE IC2IE USBIE U3ARXIE T2IE FCEIE U3AEIE
0000
1050
IFS2
0000 0000
1060
IEC0
SPI1ATXIE SPI1ARXIE SPI1AEIE I2C1AMIE I2C1ASIE T3IE I2C2SIE INT2IE I2C2BIE U3BTXIE INT0IP<2:0> CS0IP<2:0> INT1IP<2:0> IC1IP<2:0> INT2IP<2:0> I2C1ABIE OC2IE CAN1IE U3ATXIE
0000
0000 0000
1070
IEC1
15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE I2C2ASIE I2C2ABIE U1BTXIE U3BRXIE U3BEIE U2BTXIE U2BRXIE U2BEIE
0000
1080 1090 10A0 10B0 Legend: Note
IEC2 IPC0 IPC1 IPC2
0000 0000 0000 0000 0000 0000 0000
INT0IS<1:0> CS0IS<1:0> INT1IS<1:0> IC1IS<1:0> INT2IS<1:0>
CS1IS<1:0> CTIS<1:0> OC1IS<1:0> T1IS<1:0> OC2IS<1:0>
IC2IP<2:0> IC2IS<1:0> T2IP<2:0> T2IS<1:0> 0000 15:0 unknown value Reset; unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-5:
Virtual Address (BF88_#) Range Register Name
INTERRUPT REGISTER PIC32MX575F512L PIC32MX575F256L DEVICES(1) (CONTINUED)
Bits Resets
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
2009 Microchip Technology Inc.
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
10C0 10D0 10E0
IPC3 IPC4 IPC5
31:16 15:0 31:16 15:0 31:16 15:0 31:16
INT3IP<2:0> IC3IP<2:0> INT4IP<2:0> IC4IP<2:0> SPI1IP<2:0> IC5IP<2:0> AD1IP<2:0> I2C1IP<2:0> U2AIP<2:0>
INT3IS<1:0> IC3IS<1:0> INT4IS<1:0> IC4IS<1:0> SPI1IS<1:0> IC5IS<1:0> AD1IS<1:0> I2C1IS<1:0> U2AIS<1:0> SPI2AIS<1:0> I2C2AIS<1:0> CMP1IS<1:0> RTCCIS<1:0> I2C2IS<1:0> DMA3IS<1:0> DMA1IS<1:0> DMA7IS<1:0> DMA5IS<1:0> USBIS<1:0> U3BIS<1:0>
OC3IP<2:0> T3IP<2:0> OC4IP<2:0> T4IP<2:0> OC5IP<2:0> T5IP<2:0> CNIP<2:0> U1AIP<2:0> SPI1AIP<2:0> I2C1AIP<2:0>
OC3IS<1:0> T3IS<1:0> OC4IS<1:0> T4IS<1:0> OC5IS<1:0> T5IS<1:0> CNIS<1:0> U1AIS<1:0> SPI1AIS<1:0> I2C1AIS<1:0> CMP2IS<1:0> PMPIS<1:0> FSCMIS<1:0> U3AIS<1:0> SPI3AIS<1:0> I2C3AIS<1:0> DMA2IS<1:0> DMA0IS<1:0> DMA6IS<1:0> DMA4IS<1:0> CAN1IS<1:0> FCEIS<1:0> U2BIS<1:0>
10F0
IPC6
15:0
1100
IPC7
31:16 15:0 31:16
SPI2AIP<2:0> I2C2AIP<2:0> CMP1IP<2:0> RTCCIP<2:0> I2C2IP<2:0> DMA3IP<2:0> DMA1IP<2:0> DMA7IP<2:0> DMA5IP<2:0> USBIP<2:0> U3BIP<2:0>
CMP2IP<2:0> PMPIP<2:0> FSCMIP<2:0> U3AIP<2:0> SPI3AIP<2:0> I2C3AIP<2:0> DMA2IP<2:0> DMA0IP<2:0> DMA6IP<2:0> DMA4IP<2:0> CAN1IP<2:0> FCEIP<2:0> U2BIP<2:0>
DS61156B-page
PIC32MX5XX/6XX/7XX
1110
IPC8
15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
0000
1120 1130 1140 1150 Legend: Note
IPC9 IPC10 IPC11 IPC12
0000 0000 0000 0000 0000 0000 0000
U1BIP<2:0> U1BIS<1:0> 0000 15:0 unknown value Reset; unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-6:
Virtual Address (BF88_#) Range Register Name
INTERRUPT REGISTER PIC32MX675F512L PIC32MX695F512L DEVICES(1)
Bits Resets
DS61156B-page
PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
1000 INTCON 1010 INTSTAT 1020 IPTMR
31:16 15:0 31:16 15:0 31:16 15:0
MVEC
TRC<2:0> RIPL<2:0>
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000 0000 0000 0000 0000 0000
VEC<5:0>
IPTMR<31:0> U1ATXIF U1ARXIF U1AEIF SPI1TXIF IC2IF USBIF U3ARXIF I2C3ASIF U3BEIF SPI1RXIF T2IF FCEIF U3AEIF I2C3ASIF U2BTXIF SPI1EIF INT1IF DMA7IF U2ATXIF I2C2AMIF U2BRXIF SPI1EIE INT1IE DMA7IE U2ATXIE OC5IF OC1IF DMA6IF U2ARXIF I2C2ASIF U2BEIF OC5IE OC1IE DMA6IE U2ARXIE IC5IF IC1IF DMA5IF U2AEIF CMP2IF U1BRXIF T5IE T1IE DMA4IE CMP2IE U1BRXIE CMP1IF U1BEIF INT4IE INT0IE DMA3IE CMP1IE U1BEIE CS1IP<2:0> CTIP<2:0> OC1IP<2:0> T1IP<2:0> OC2IP<2:0> PMPIF PMPEIF OC4IE CS1IE DMA2IE PMPIE PMPEIE AD1IF IC5EIF IC4IE CS0IE DMA1IE AD1IE IC5EIE CNIF IC4EIF T4IE CTIE DMA0IE CNIE IC4EIE T5IF T1IF DMA4IF INT4IF INT0IF DMA3IF OC4IF CS1IF DMA2IF IC4IF CS0IF DMA1IF T4IF CTIF DMA0IF
1030
IFS0
31:16 15:0 31:16
I2C1MIF INT3IF IC3EIF RTCCIF I2C1MIE INT3IE IC3EIE RTCCIE
I2CSIF OC3IF IC2EIF FSCMIF I2C1SIE OC3IE IC2EIE FSCMIE
I2CBIF IC3IF IC1EIF I2C2MIF I2C1BIE IC3IE IC1EIE I2C2MIE
SPI1ATXIF SPI1ARXIF SPI1AEIF I2C1AMIF I2C1ASIF T3IF ETHIF I2C2SIF U1ATXIE INT2IF I2C2BIF U3BTXIF U1ARXIE I2C1ABIF OC2IF U3ATXIF
0000
0000 0000
1040
IFS1
2009 Microchip Technology Inc.
15:0 31:16 15:0 31:16 15:0 31:16
SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF I2C3AMIF I2C2ABIF U1BTXIF IC5IE IC1IE DMA5IE U2AEIE U3BRXIF U1AEIE
0000
1050
IFS2
0000 0000
1060
IEC0
SPI1ATXIE SPI1ARXIE SPI1AEIE SPI1TXIE SPI1RXIE I2C1AMIE I2C1ASIE T3IE ETHIE I2C2SIE INT2IE I2C2BIE U3BTXIE INT0IP<2:0> CS0IP<2:0> INT1IP<2:0> IC1IP<2:0> INT2IP<2:0> I2C1ABIE OC2IE U3ATXIE IC2IE USBIE U3ARXIE T2IE FCEIE U3AEIE
0000
0000 0000
1070
IEC1
15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE I2C2ASIE U2BTXIE U2BRXIE U2BEIE I2C2ABIE U1BTXIE U3BRXIE U3BEIE
0000
1080 1090 10A0 10B0 Legend: Note
IEC2 IPC0 IPC1 IPC2
0000 0000 0000 0000 0000 0000 0000
INT0IS<1:0> CS0IS<1:0> INT1IS<1:0> IC1IS<1:0> INT2IS<1:0>
CS1IS<1:0> CTIS<1:0> OC1IS<1:0> T1IS<1:0> OC2IS<1:0>
IC2IP<2:0> IC2IS<1:0> T2IP<2:0> T2IS<1:0> 0000 15:0 unknown value Reset; unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-6:
Virtual Address (BF88_#) Range Register Name
INTERRUPT REGISTER PIC32MX675F512L PIC32MX695F512L DEVICES(1) (CONTINUED)
Bits Resets
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
2009 Microchip Technology Inc.
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
10C0 10D0 10E0
IPC3 IPC4 IPC5
31:16 15:0 31:16 15:0 31:16 15:0 31:16
INT3IP<2:0> IC3IP<2:0> INT4IP<2:0> IC4IP<2:0> SPI1IP<2:0> IC5IP<2:0> AD1IP<2:0> I2C1IP<2:0> U2AIP<2:0>
INT3IS<1:0> IC3IS<1:0> INT4IS<1:0> IC4IS<1:0> SPI1IS<1:0> IC5IS<1:0> AD1IS<1:0> I2C1IS<1:0> U2AIS<1:0> SPI2AIS<1:0> I2C2AIS<1:0> CMP1IS<1:0> RTCCIS<1:0> I2C2IS<1:0> DMA3IS<1:0> DMA1IS<1:0> DMA7IS<1:0> DMA5IS<1:0> USBIS<1:0> U3BIS<1:0>
OC3IP<2:0> T3IP<2:0> OC4IP<2:0> T4IP<2:0> OC5IP<2:0> T5IP<2:0> CNIP<2:0> U1AIP<2:0> SPI1AIP<2:0> I2C1AIP<2:0>
OC3IS<1:0> T3IS<1:0> OC4IS<1:0> T4IS<1:0> OC5IS<1:0> T5IS<1:0> CNIS<1:0> U1AIS<1:0> SPI1AIS<1:0> I2C1AIS<1:0> CMP2IS<1:0> PMPIS<1:0> FSCMIS<1:0> U3AIS<1:0> SPI3AIS<1:0> I2C3AIS<1:0> DMA2IS<1:0> DMA0IS<1:0> DMA6IS<1:0> DMA4IS<1:0> FCEIS<1:0> U2BIS<1:0>
10F0
IPC6
15:0
1100
IPC7
31:16 15:0 31:16
SPI2AIP<2:0> I2C2AIP<2:0> CMP1IP<2:0> RTCCIP<2:0> I2C2IP<2:0> DMA3IP<2:0> DMA1IP<2:0> DMA7IP<2:0> DMA5IP<2:0> USBIP<2:0> U3BIP<2:0>
CMP2IP<2:0> PMPIP<2:0> FSCMIP<2:0> U3AIP<2:0> SPI3AIP<2:0> I2C3AIP<2:0> DMA2IP<2:0> DMA0IP<2:0> DMA6IP<2:0> DMA4IP<2:0> FCEIP<2:0> U2BIP<2:0>
DS61156B-page
PIC32MX5XX/6XX/7XX
1110
IPC8
15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
0000
1120 1130 1140 1150
IPC9 IPC10 IPC11 IPC12
0000 0000 0000 0000 0000 0000 0000
Legend: Note
U1BIP<2:0> U1BIS<1:0> ETHIP<2:0> ETHIS<1:0> 0000 15:0 unknown value Reset; unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-7:
Virtual Address (BF88_#) Range Register Name
INTERRUPT REGISTER PIC32MX795F512L DEVICE(1)
Bits Resets
DS61156B-page
PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
1000 INTCON 1010 INTSTAT 1020 IPTMR
31:16 15:0 31:16 15:0 31:16 15:0
MVEC
TRC<2:0> RIPL<2:0>
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000 0000 0000 0000 0000 0000
VEC<5:0>
IPTMR<31:0> U1ATXIF U1ARXIF I2C1ASIF INT2IF CAN2IF I2C2BIF U3BTXIF U1ARXIE U1AEIF SPI1TXIF IC2IF USBIF U3ARXIF I2C3ASIF U3BEIF SPI1RXIF T2IF FCEIF U3AEIF I2C3ASIF U2BTXIF SPI1EIF INT1IF DMA7IF U2ATXIF I2C2AMIF U2BRXIF SPI1EIE INT1IE DMA7IE U2ATXIE OC5IF OC1IF DMA6IF U2ARXIF I2C2ASIF U2BEIF OC5IE OC1IE DMA6IE U2ARXIE IC5IF IC1IF DMA5IF U2AEIF CMP2IF U1BRXIF T5IE T1IE DMA4IE CMP2IE U1BRXIE CMP1IF U1BEIF INT4IE INT0IE DMA3IE CMP1IE U1BEIE CS1IP<2:0> CTIP<2:0> OC1IP<2:0> T1IP<2:0> OC2IP<2:0> PMPIF PMPEIF OC4IE CS1IE DMA2IE PMPIE PMPEIE AD1IF IC5EIF IC4IE CS0IE DMA1IE AD1IE IC5EIE CNIF IC4EIF T4IE CTIE DMA0IE CNIE IC4EIE T5IF T1IF DMA4IF INT4IF INT0IF DMA3IF OC4IF CS1IF DMA2IF IC4IF CS0IF DMA1IF T4IF CTIF DMA0IF
1030
IFS0
31:16 15:0 31:16
I2C1MIF INT3IF IC3EIF RTCCIF I2C1MIE INT3IE IC3EIE RTCCIE
I2CSIF OC3IF IC2EIF FSCMIF I2C1SIE OC3IE IC2EIE FSCMIE
I2CBIF IC3IF IC1EIF I2C2MIF I2C1BIE IC3IE IC1EIE I2C2MIE
SPI1ATXIF SPI1ARXIF SPI1AEIF I2C1AMIF T3IF ETHIF I2C2SIF U1ATXIE I2C1ABIF OC2IF CAN1IF U3ATXIF
0000
0000 0000
1040
IFS1
2009 Microchip Technology Inc.
15:0 31:16 15:0 31:16 15:0 31:16
SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF I2C3AMIF I2C2ABIF U1BTXIF IC5IE IC1IE DMA5IE U2AEIE U3BRXIF U1AEIE SPI1TXIE SPI1RXIE IC2IE USBIE U3ARXIE T2IE FCEIE U3AEIE
0000
1050
IFS2
0000 0000
1060
IEC0
SPI1ATXIE SPI1ARXIE SPI1AEIE I2C1AMIE I2C1ASIE I2C1ABIE T3IE ETHIE I2C2SIE INT2IE CAN2IE I2C2BIE U3BTXIE INT0IP<2:0> CS0IP<2:0> INT1IP<2:0> IC1IP<2:0> INT2IP<2:0> OC2IE CAN1IE U3ATXIE
0000
0000 0000
1070
IEC1
15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE I2C2ASIE U2BTXIE U2BRXIE U2BEIE I2C2ABIE U1BTXIE U3BRXIE U3BEIE
0000
1080 1090 10A0 10B0 Legend: Note
IEC2 IPC0 IPC1 IPC2
0000 0000 0000 0000 0000 0000 0000
INT0IS<1:0> CS0IS<1:0> INT1IS<1:0> IC1IS<1:0> INT2IS<1:0>
CS1IS<1:0> CTIS<1:0> OC1IS<1:0> T1IS<1:0> OC2IS<1:0>
IC2IP<2:0> IC2IS<1:0> T2IP<2:0> T2IS<1:0> 0000 15:0 unknown value Reset; unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-7:
Virtual Address (BF88_#) Range Register Name
INTERRUPT REGISTER PIC32MX795F512L DEVICE(1) (CONTINUED)
Bits Resets
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
2009 Microchip Technology Inc.
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
10C0 10D0 10E0
IPC3 IPC4 IPC5
31:16 15:0 31:16 15:0 31:16 15:0 31:16
INT3IP<2:0> IC3IP<2:0> INT4IP<2:0> IC4IP<2:0> SPI1IP<2:0> IC5IP<2:0> AD1IP<2:0> I2C1IP<2:0> U2AIP<2:0>
INT3IS<1:0> IC3IS<1:0> INT4IS<1:0> IC4IS<1:0> SPI1IS<1:0> IC5IS<1:0> AD1IS<1:0> I2C1IS<1:0> U2AIS<1:0> SPI2AIS<1:0> I2C2AIS<1:0> CMP1IS<1:0> RTCCIS<1:0> I2C2IS<1:0> DMA3IS<1:0> DMA1IS<1:0> DMA7IS<1:0> DMA5IS<1:0> CAN2IS<1:0> USBIS<1:0> U3BIS<1:0>
OC3IP<2:0> T3IP<2:0> OC4IP<2:0> T4IP<2:0> OC5IP<2:0> T5IP<2:0> CNIP<2:0> U1AIP<2:0> SPI1AIP<2:0> I2C1AIP<2:0>
OC3IS<1:0> T3IS<1:0> OC4IS<1:0> T4IS<1:0> OC5IS<1:0> T5IS<1:0> CNIS<1:0> U1AIS<1:0> SPI1AIS<1:0> I2C1AIS<1:0> CMP2IS<1:0> PMPIS<1:0> FSCMIS<1:0> U3AIS<1:0> SPI3AIS<1:0> I2C3AIS<1:0> DMA2IS<1:0> DMA0IS<1:0> DMA6IS<1:0> DMA4IS<1:0> CAN1IS<1:0> FCEIS<1:0> U2BIS<1:0>
10F0
IPC6
15:0
1100
IPC7
31:16 15:0 31:16
SPI2AIP<2:0> I2C2AIP<2:0> CMP1IP<2:0> RTCCIP<2:0> I2C2IP<2:0> DMA3IP<2:0> DMA1IP<2:0> DMA7IP<2:0> DMA5IP<2:0> CAN2IP<2:0> USBIP<2:0> U3BIP<2:0>
CMP2IP<2:0> PMPIP<2:0> FSCMIP<2:0> U3AIP<2:0> SPI3AIP<2:0> I2C3AIP<2:0> DMA2IP<2:0> DMA0IP<2:0> DMA6IP<2:0> DMA4IP<2:0> CAN1IP<2:0> FCEIP<2:0> U2BIP<2:0>
DS61156B-page
PIC32MX5XX/6XX/7XX
1110
IPC8
15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
0000
1120 1130 1140 1150
IPC9 IPC10 IPC11 IPC12
0000 0000 0000 0000 0000 0000 0000
Legend: Note
U1BIP<2:0> U1BIS<1:0> ETHIP<2:0> ETHIS<1:0> 0000 15:0 unknown value Reset; unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-8:
Virtual Address (BF80_#) Range Register Name
TIMER1-TIMER5 REGISTER MAP(1)
Bits Resets
DS61156B-page
PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
0600 T1CON 0610 0620 TMR1
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
SIDL SIDL SIDL SIDL SIDL
TWDIS
TWIP
TGATE TGATE TGATE TGATE TGATE
TCKPS<2:0> TCKPS<2:0> TCKPS<2:0> TCKPS<2:0>
TSYNC
0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 0000
TCKPS<1:0>
TMR1<15:0> PR1<15:0>
0800 T2CON 0810 0820 TMR2
TMR2<15:0> PR2<15:0>
2009 Microchip Technology Inc.
0A00 T3CON 0A10 0A20 TMR3
TMR3<15:0> PR3<15:0>
0C00 T4CON 0C10 0C20 TMR4
TMR4<15:0> PR4<15:0>
0E00 T5CON 0E10 0E20 Legend: Note TMR5
TMR5<15:0>
15:0 PR5<15:0> FFFF unknown value Reset; unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
2009 Microchip Technology Inc.
TABLE 4-9:
Virtual Address (BF80_#) Range Register Name
INPUT CAPTURE1-INPUT CAPTURE5 REGISTER
Bits Resets
0000 0000 xxxx xxxx ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 xxxx xxxx SIDL ICFEDGE ICC32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 xxxx xxxx SIDL ICFEDGE ICC32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000 0000 xxxx
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
2000 2010 2200 2210 2400 2410
IC1CON(1) IC1BUF IC2CON(1) IC2BUF IC3CON(1) IC3BUF IC4CON(1) IC4BUF IC5CON(1) IC5BUF
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
SIDL
ICFEDGE
ICC32
ICTMR
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
IC1BUF<31:0> SIDL ICFEDGE ICC32 ICTMR
IC2BUF<31:0>
IC3BUF<31:0>
DS61156B-page
2600 2610 2800 2810
IC4BUF<31:0> SIDL ICFEDGE ICC32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>
PIC32MX5XX/6XX/7XX
xxxx 0000 0000
Legend: Note
xxxx IC5BUF<31:0> 15:0 xxxx unknown value Reset; unimplemented, read `0'. Reset values shown hexadecimal. This register corresponding CLR, SET, Registers virtual address, plus offset 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-10:
Virtual Address (BF80_#) Range Register Name
OUTPUT COMPARE 1-OUTPUT COMPARE REGISTER MAP(1)
Bits Resets
DS61156B-page
PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
3000 OC1CON 3010 3020 OC1R OC1RS
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
SIDL
OC32
OCFLT
OCTSEL
OCM<2:0>
0000 0000 xxxx xxxx xxxx xxxx
OC1R<31:0> OC1RS<31:0> SIDL OC32 OCFLT OCTSEL OCM<2:0>
3200 OC2CON 3210 3220 OC2R OC2RS
0000 0000 xxxx xxxx xxxx xxxx
OC2R<31:0> OC2RS<31:0> SIDL OC32 OCFLT OCTSEL OCM<2:0>
2009 Microchip Technology Inc.
3400 OC3CON 3410 3420 OC3R OC3RS
0000 0000 xxxx xxxx xxxx xxxx
OC3R<31:0> OC3RS<31:0> SIDL OC32 OCFLT OCTSEL OCM<2:0>
3600 OC4CON 3610 3620 OC4R OC4RS
0000 0000 xxxx xxxx xxxx xxxx
OC4R<31:0> OC4RS<31:0> SIDL OC32 OCFLT OCTSEL OCM<2:0>
3800 OC5CON 3810 3820 OC5R OC5RS
0000 0000 xxxx xxxx xxxx
OC5R<31:0>
Legend: Note
OC5RS<31:0> 15:0 xxxx unknown value Reset; unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-11:
Virtual Address (BF80_#) Range Register Name
I2C1, I2C1A, I2C2A, I2C3A REGISTER MAP(1)
Bits Resets
0000 0000 0000 0000 0000 0000 RCEN RCEN RSEN RSEN 0000 0000 0000 0000 ACKEN ACKEN 0000 0000 0000 0000 0000 0000 I2CT1DATA<7:0> GCEN IWCOL GCEN STREN I2COV STREN ACKDT ACKDT ADD<9:0> DISSLW SMEN MSK<9:0> I2C1BRG<11:0> STRICT A10M I2CT1DATA<7:0> I2CR1DATA<7:0> I2CR1DATA<7:0>
2009 Microchip Technology Inc.
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
5000 I2C1ACON 5010 I2C1ASTAT 5020 I2C1AADD 5030 I2C1AMSK 5040 I2C1ABRG 5050 I2C1ATRN
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
ACKSTAT ACKSTAT
TRSTAT TRSTAT
SIDL SIDL SIDL
SCLREL SCLREL SCLREL
STRICT STRICT
A10M A10M
DISSLW GCSTAT DISSLW GCSTAT
SMEN ADD10 SMEN ADD10
GCEN IWCOL
STREN I2COV
ACKDT
ACKEN
RCEN
RSEN
ADD<9:0> MSK<9:0> I2C1BRG<11:0>
DS61156B-page
5060 I2C1ARCV 5100 I2C2ACON 5110 I2C2ASTAT 5120 I2C2AADD 5130 I2C2AMSK 5140 I2C2ABRG 5150 I2C2ATRN
PIC32MX5XX/6XX/7XX
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
5160 I2C2ARCV 5200 I2C3ACON 5210 I2C3ASTAT Legend: Note
15:0 ACKSTAT TRSTAT GCSTAT ADD10 IWCOL I2COV 0000 unknown value Reset; unimplemented, read `0'. Reset values shown hexadecimal. registers this table except I2CxRCV have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-11:
Virtual Address (BF80_#) Range Register Name
I2C1, I2C1A, I2C2A, I2C3A REGISTER MAP(1) (CONTINUED)
Bits Resets
DS61156B-page
PIC32MX5XX/6XX/7XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
5220 I2C3AADD 5230 I2C3AMSK 5240 I2C3ABRG 5250 I2C3ATRN
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
ACKSTAT
TRSTAT
SIDL
SCLREL
STRICT
A10M
DISSLW GCSTAT
SMEN ADD10
GCEN IWCOL
STREN I2COV
ACKDT
ACKEN
RCEN
RSEN
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
ADD<9:0> MSK<9:0> I2C1BRG<11:0> I2CT1DATA<7:0> I2CR1DATA<7:0>
5260 I2C3ARCV 5300 5310 5320 5330 5340 5350 5360 I2C1CON I2C1STAT I2C1ADD I2C1MSK I2C1BRG I2C1TRN I2C1RCV
2009 Microchip Technology Inc.
ADD<9:0> MSK<9:0> I2C1BRG<11:0> I2CT1DATA<7:0>
Legend: Note
15:0 I2CR1DATA<7:0> 0000 unknown value Reset; unimplemented, read `0'. Reset values shown hexadecimal. registers this table except I2CxRCV have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
2009 Microchip Technology Inc.
TABLE 4-12:
Virtual Address (BF80_#)
I2C2 REGISTER PIC32MX575F512L, PIC32MX575F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX795F512L DEVICES(1)
Bits Resets
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 I2CT1DATA<7:0>
Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
5400 I2C2CON 5410 I2C2STAT 5420 I2C2ADD 5430 I2C2MSK 5440 I2C2BRG 5450 I2C2TRN
31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
TRSTAT
SIDL
SCLREL
STRICT
A10M
DISSLW GCSTAT
SMEN ADD10
GCEN IWCOL
STREN I2COV
ACKDT
ACKEN
RCEN
RSEN
15:0 ACKSTAT
ADD<9:0> MSK<9:0> I2C2BRG<11:0>
DS61156B-page
5460 I2C2RCV Legend: Note
15:0 I2CR1DATA<7:0> 0000 unknown value Reset; unimplemented, read `0'. Reset values shown hexadecimal. registers this table except I2CxRCV have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
PIC32MX5XX/6XX/7XX
DS61156B-page
PIC32MX5XX/6XX/7XX
TABLE 4-13:
Virtual Address (BF80_#) Register Name
UART1A, UART1B, UART2A, UART2B, UART3A, UART3B REGISTER
Bits Resets
0000 0000 0000 FERR OERR URXDA STSEL URXDA STSEL URXDA STSEL 0110 0000 0000 0000 0000 0000 0000 LPBACK ABAUD ADDEN ABAUD ADDEN ABAUD RXINV RIDLE RXINV RIDLE RXINV BRGH PERR BRGH PERR BRGH 0000 0000 0000 FERR OERR 0110 0000 0000 0000 0000 0000 0000 LPBACK 0000 0000 0000 FERR OERR 0110 0000 0000 0000 0000 0000 0000 LPBACK 0000 0000 0000
Range
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6000 U1AMODE(1) 6010 U1ASTA(1)
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
SIDL UTXINV SIDL UTXINV SIDL UTXINV SIDL
IREN URXEN IREN URXEN IREN URXEN IREN
RTSMD UTXBRK UTXBRK RTSMD UTXBRK
UTXEN UTXEN UTXEN
UTXBF UTXBF UTXBF
ADM_EN TRMT ADM_EN TRMT ADM_EN TRMT ADM_EN
WAKE
LPBACK
ABAUD ADDEN
RXINV RIDLE
BRGH PERR
STSEL
UEN<1:0>
PDSEL<1:0>
ADDR<7:0> URXISEL<1:0> WAKE
UTXISEL<1:0>
6020 U1ATXREG 6030 U1ARXREG 6040 U1ABRG
Transmit Register Receive Register
BRG<15:0> PDSEL<1:0>
6200 U1BMODE(1)
2009 Microchip Technology Inc.
6210
U1BSTA(1)
ADDR<7:0> URXISEL<1:0> WAKE
UTXISEL<1:0>
6220 U1BTXREG 6230 U1BRXREG 6240 U1BBRG(1) 6400 U2AMODE 6410
Transmit Register Receive Register
BRG<15:0> UEN<1:0> PDSEL<1:0>
U2ASTA(1)
ADDR<7:0> URXISEL<1:0> WAKE
UTXISEL<1:0>
6420 U2ATXREG 6430 U2ARXREG 6440 U2ABRG
Transmit Register Receive Register
BRG<15:0> PDSEL<1:0>
6600 U2BMODE(1) 6610 U2BSTA
ADDR<7:0>
Legend: Note
15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110 unknown value Reset; unimplemented, read `0'. Reset values shown hexadecimal. This register corresponding CLR, SET, Registers virtual address, plus offset 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-13:
Virtual Address (BF80_#) Register Name
UART1A, UART1B, UART2A, UART2B, UART3A, UART3B REGISTER (CONTINUED)
Bits Resets
0000 0000 STSEL URXDA STSEL URXDA 0000 0000 0000 0000 LPBACK ABAU
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