PIC24FJ128GA010 Family Silicon Errata Data Sheet Clarification PI
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PIC24FJ128GA010 FAMILY
PIC24FJ128GA010 Family Silicon Errata Data Sheet Clarification
PIC24FJ128GA010 Family devices that have received conform functionally current Device Data Sheet (DS39747D), except anomalies described this document. silicon issues discussed following pages silicon revisions with Device Revision listed Table silicon issues summarized Table errata described this document will addressed future revisions PIC24F128GA010 family silicon. Note: This document summarizes silicon errata issues from revisions silicon, previous well current. Only issues indicated last column Table apply current silicon revision (C2). example, identify silicon revision level using MPLAB conjunction with MPLAB PICkit3: Using appropriate interface, connect device MPLAB programmer/debugger PICkit3. From main menu MPLAB IDE, select Configure>Select Device then select target part number dialog box. Select MPLAB hardware tool (Debugger>Select Tool). Perform "Connect" operation device (Debugger>Connect). Depending development tool used, part number Device Revision value appear Output window. Note: unable extract silicon revision level, please contact your local Microchip sales office assistance.
Data Sheet clarifications corrections start page following discussion silicon issues. silicon revision level identified using current version MPLAB® Microchip's programmers, debuggers emulation tools, which available Microchip corporate site (www.microchip.com).
DEVREV values various PIC24F128GA010 family silicon revisions shown Table
TABLE
SILICON DEVREV VALUES
Device ID(1) 040Dh 040Ch 040Bh 040Ah 0409h 0408h 0407h 0406h 0405h Revision Silicon Revision(2)
Part Number PIC24FJ128GA010 PIC24FJ96GA010 PIC24FJ64GA010 PIC24FJ128GA008 PIC24FJ96GA008 PIC24FJ64GA008 PIC24FJ128GA006 PIC24FJ96GA006 PIC24FJ64GA006 Note
Device (DEVID DEVREV) located last implemented addresses program memory. They shown hexadecimal format "DEVID DEVREV". Refer "PIC24FJXXXGA0XX Flash Programming Specification" (DS39768) detailed information Device Revision your specific device.
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TABLE
Module Core CUART Resets Timers JTAG UART RTCC RTCC UART UART UART UART UART UART UART Interrupts Output Compare Note
SILICON ISSUE SUMMARY
Feature Enhanced mode Programming Master mode Master mode Slave mode Flow Control Auto-Baud Traps INT0 Trigger Framed modes Item Number Affected Revisions(1) Issue Summary write issues Doze mode. Failure lock writes I2CxTRN. Parity failure with values BRG. FSCM clock switch issue. Special Event Trigger failure (Timer2/3). Enhanced Buffer modes unavailable. JTAG device programming compatible with third party solutions. High gain error. Failure detect collision Stop Restart sequences. Erroneous FIFO buffer overflow flag. Master mode reception errors fast rates. Skipped DISI instruction under certain circumstances. PMRD signal absent Master mode under certain conditions. Address increment/decrement failure back-to-back reads Master mode. Missed increments simultaneous register update. Calibration applied every interval. Failure Acknowledge write operation Slave mode. Receive mode enabled outside Idle state. Change Sync Break timing. Reception failures High-Speed mode. UTXISEL0 always reads `0'. UTXSEL mode `10' behaves mode `00'. Hardware flow control unavailable some devices some UARTs. Erroneous baud rate calculations High-Speed mode. Insertion spurious data with auto-baud reception. Failure exit Doze mode certain traps. Single glitch initialization under certain conditions. Device wake when convert INT0 trigger selected. Frame Sync unavailable Master mode under certain conditions.
Only those issues indicated last column apply current silicon revision.
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TABLE
Module Oscillator Core Core Core Ports UART UART UART Output Compare UART RTCC Core Memory RTCC UART UART UART
SILICON ISSUE SUMMARY (CONTINUED)
Feature Slave mode Two-Speed Start-up Reset Traps Resets Slave mode Auto-Baud Auto-Baud mode IrDA® Instruction PORTB Alarm UERIF Interrupt FIFO Error Flags Master mode Item Number Affected Revisions(1) Issue Summary Module Slave mode ignore receive data anyway. Two-Speed Start-up failure when IESO enabled. Unimplemented CLKDIV bits reset `1'. Clock failure trap does vector expected. flags both BOR. OSCO/CLKO/RC15 driven immediately following POR. fails update Slave mode transmissions. Double receive interrupt with auto-baud reception. Auto-baud calculation errors causing transmit receive failures. Erroneous sampling framing errors when using Stop bits. DISSCK does disable clock. Single missed compare events under certain conditions. Improper VWORD Reset FIFO overflow. baud clock only available during transmit. Issues with write operations I2CxSTAT. ACKSTAT prematurely cleared Slave mode. Write errors ALCFGRPT register. Loop count errors with REPEAT instruction R-A-W stalls. False address error traps lower boundary space. open-drain output stays high-impedance state. Decrement alarm repeat counter under certain conditions. UERIF flag with multiple errors. PERR FERR correctly bytes receive FIFO. Does transmit TxREG preloaded. Module respond master transmission slave under certain conditions. Failure respond correctly some reserved addresses 10-bit mode.
Note
Slave mode
Only those issues indicated last column apply current silicon revision.
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TABLE
Module RTCC Pins Core Note
SILICON ISSUE SUMMARY (CONTINUED)
Feature Master mode Alarm Framed modes Enhanced mode Code Protection Item Number Affected Revisions(1) Issue Summary flag error with collisions. Incorrect status timing. toggling error alarm repeat. Spec change VOH. Framed modes supported. Interrupt flag early Enhanced Buffer mode under certain conditions. General code protection disables bootloader functionality.
Only those issues indicated last column apply current silicon revision.
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Silicon Errata Issues
Note: This document summarizes silicon errata issues from revisions silicon, previous well current. Only issues indicated shaded column following tables apply current silicon revision (C2).
Module: UART
With parity option enabled, parity error, indicated with PERR (UxSTA<3>) being set, occur Baud Rate Generator contains value. This affects both even parity options. Work around Load Baud Rate Generator register, UxBRG, with even value disable peripheral's parity option loading either `00' `11' into Parity Data Selection bits, PDSEL<1:0> (UxMODE<2:1>). Affected Silicon Revisions
Module: Core
With Doze mode enabled, DOZEN (CLKDIV<11>) Peripheral Clock Ratio Select bits (CLKDIV<14:12>) configured value except `000', writes locations performed. Work around Disable Doze mode select peripheral clock ratio before modifying stated locations, avoid writing stated locations while Doze mode enabled peripheral clock ratio other than selected. Configure device prior entering Doze mode mode only monitor applications activity. Affected Silicon Revisions
Module: Resets
After oscillator stopped, with Fail-Safe Clock Monitor enabled FCKSM<1:0> Configuration bits (Flash Configuration Word 2<7:6>) programmed `00', system clock source forced FRC. After which, system clock source changed software modifying Oscillator Selection bits, NOSC<2:0> (OSCCON<10:8>), unless device Reset occurs. Work around Upon detecting oscillator failure, determined reading Clock Fail Detect bit, (OSCCON<3>), set, execute RESET instruction prior selecting system clock source using NOSC bits. Affected Silicon Revisions
Module: I2CWriting I2CxTRN during Start transmission generates write collision, indicated IWCOL (I2CxSTAT<7>) being set. this state, additional writes I2CxTRN register should blocked. However, this condition, I2CxTRN register written, although transmissions will occur until IWCOL cleared software. Work around After each write I2CxTRN register, read IWCOL ensure collision occurred. IWCOL set, must cleared software I2CxTRN must rewritten. Affected Silicon Revisions
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Module: Timers
With Timer2 Timer3 configured 32-bit mode setting T2CON<3>, Special Event Trigger start conversion occur when most significant word Period register, PR3, `0'. Work around Either write non-zero value configure Timer3 16-bit operation when generating Special Event Trigger periodic conversions. Affected Silicon Revisions
Module:
Gain error high LSbs external references (VREF+ VREF-) LSbs internal reference (AVDD AVSS). Work around Determine gain error from known reference voltage compensate result software. Affected Silicon Revisions
Module:
module detect collision during Restart Stop sequence. When this occurs, Master Collision Detect bit, (I2CxSTAT<10>), set. will indicate collision, occurs, during Start sequence. This issue only affects multi-master networks. Work around device multi-master network, each master device must detect when Start Stop events occur bus. Start sequence should initiated only after Start Stop event have been detected ensure collision detected. Affected Silicon Revisions
Module: (Enhanced Mode)
Enhanced modes, selected setting Enhanced Buffer Enable bit, SPIBEN (SPIxCON2<0>), available. Work around Standard mode clearing Enhanced Buffer Enable bit, SPIBEN. Affected Silicon Revisions
Module: JTAG (Programming)
current JTAG programming implementation compatible with third party programmers using (Serial Vector Format) description language. JTAG boundary scan supported third party JTAG solutions affected. Work around user program devices with In-Circuit Serial ProgrammingTM. JTAG programming accomplished using custom JTAG software. current implementation supported future PIC24F revisions. JTAG boundary scan supported. Affected Silicon Revisions
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Module: UART
Receive Buffer Overrun Error Status bit, OERR (UxSTA<1>), before UART FIFO overflowed. After fourth byte received UART, FIFO full. OERR should after fifth byte been received UART Shift register. Instead, OERR after fourth received byte with UART Shift register empty. Work around After four bytes have been received UART, UART Receiver Interrupt Flag bit, U1RXIF (IFS0<11>) U2RXIF (IFS1<14>), will set, indicating UART FIFO full. OERR also set. After reading UART Receive Buffer, UxRXREG, four times clear FIFO, clear both OERR UxRXIF bits software. Affected Silicon Revisions
Module:
DISI instruction ignored command executed same instruction cycle when DISICNT register decrements zero. example, DISI instruction performed, DISICNT will decrement zero instruction cycles instruction cycles DISI command plus instruction execution). second DISI command executes same instruction cycle that DISCNT reaches zero, second DISI instruction will ignored. other instruction cycle, second DISI command will perform described product data sheet. Work around disable interrupts using DISI instruction, execute instruction twice. example, disable interrupts five instruction cycles, following: DISI (can value except DISI (number instruction cycles DISI will active) This work around ensures DISI command executed same instruction cycle when DISICNT register decrements zero. Affected Silicon Revisions
Module: (Master Mode)
Master mode receptions using SPI1 SPI2 modules function correctly rates above Mbps master (SPIxCON1<9>) cleared (master samples data middle serial clock period). this case, data transmitted slave received, shifted right bit, master. example, data transmitted slave 0xAAAA, data received master would 0x5555 (0xAAAA shifted right bit). Work around Users module that rate Mbps lower. Alternatively, rate configured higher than Mbps, (SPIxCON1<9>) master must (master samples data serial clock period). Affected Silicon Revisions
Module:
Master mode (MODE<1:0> 10), back-to-back operations cause PMRD signal generated. This limitation occurs when peripheral configured zero Wait states (WAITM<3:0> 0000). Work around PMRD signal will generated correctly minimum instruction cycle delay inserted between back-to-back operations. instruction, other instruction, adequate. Selecting delay other than zero will also permit PMRD signal generated. Affected Silicon Revisions
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Module: (Master Mode)
With Master mode (MODE<1:0> with increment/decrement feature enabled (INCM<1:0> 10), address automatically change when PMDINx register read. This issue occur when multiple back-to-back reads performed. Work around address will generated correctly minimum instruction cycle delay inserted between back-to-back read operations PMDINx register. instruction, other instruction, adequate. Affected Silicon Revisions
Module: (Slave Mode)
Slave mode, peripheral Acknowledge write operation (R/W after Restart been received. This sequence typically used perform slave transmit operation 10-Bit Addressing mode (A10M Attempting perform write operation after Restart cause peripheral generate NACK operation unexpectedly. Work around perform slave transmit, refer Figure 24-27 from Section "Inter-Integrated Circuit(I2CTM)" "PIC24F Family Reference Manual" (DS39702). Affected Silicon Revisions
Module: RTCC
RTCC increment missed RTCC update RTCC increment occur same time, updates disallowed (RTCWREN this condition, RTCC updated since RTCWREN clear. Work around Prior writing RTCVAL registers, verify that RTCSYNC clear RTCWREN set. This ensures that RTCC will updated update will occur during RTCC increment. Affected Silicon Revisions
Module:
Receive mode should enabled (i.e., RCEN should set) only when system Idle (i.e., when ACKEN, RCEN, PEN, RSEN equal zero). should possible RCEN when system Idle; however, RCEN under this circumstance. Work around Wait system become Idle before setting RCEN bit. Verify that following bits clear: ACKEN, RCEN, PEN, RSEN SEN. Affected Silicon Revisions
Module: RTCC
RTCC automatic calibration, stored CAL<7:0> bits, intended applied every minute minute boundary. calibration applied after first minute occur subsequent minute intervals. Work around Read rewrite SECONDS (RTCPTR<1:0> value after each minute. This reinitializes calibration circuit allows calibration applied next minute increment. Affected Silicon Revisions
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Module: UART
timing transmitting Sync Break changed this revision silicon. Sync Break transmitted soon UTXBRK set. dummy write UxTXREG still required must performed before Sync Break finished transmitting. Otherwise, UxTX held active state until write occurred. Work around UTXBRK when Sync Break required perform dummy write UxTXREG immediately following. This sequence will avoid holding UxTX active state. Affected Silicon Revisions
Module: UART
When UTXISEL<1:0> UART interrupt flag should after byte from FIFO transferred Transmit Shift Register (TSR). Instead, interrupt flag only after bytes transferred from FIFO FIFO empty. This behavior similar UTXISEL<1:0> mode. Work around None. Affected Silicon Revisions
Module: UART (Hardware Flow Control)
UART1 UART2 hardware flow control options available 64-pin variants PIC24F128GA010 product family. result, UxCTS UxRTS pins available UEN<1:0> control bits read (unimplemented). UART2 hardware flow control available 80-pin PIC24F128GA010 family variants. Associated pins bits available these devices. Work around None. Affected Silicon Revisions
Module: UART
When UART High-Speed mode, BRGH (UxMODE<3>) set, some optimal UxBRG values cause reception fail. Work around Test UxBRG values application find UxBRG value that works consistently more high-speed applications. user should verify that UxBRG baud rate error does exceed application limits. Affected Silicon Revisions
Module: UART Module: UART
UTXISEL0 (UxSTA<13>) always reads zero regardless value written written either `1', will always read zero. This will affect read-modify-write operations, such bit-wise shift operations. Using read-modify-write instruction UxSTA register will always write UTXISEL0 zero. Work around UTXISEL0 value needed, avoid using read-modify-write instructions UxSTA register. Copy UxSTA register temporary variable UxSTA<13> prior performing read-modify-write operations. Copy value back UxSTA register. Affected Silicon Revisions When UART High-Speed mode (BRGH auto-baud sequence calculate baud rate were Low-Speed mode. Work around calculated baud rate modified following equation: Value (Auto-Baud user should verify that baud rate error does exceed application limits. Affected Silicon Revisions
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Module: UART (Auto-Baud)
With auto-baud feature selected, Sync Break character (0x55) loaded into FIFO data. Work around prevent Sync Break character from being loaded into FIFO, load UxBRG register with either 0x0000 0xFFFF prior enabling auto-baud feature (ABAUD Affected Silicon Revisions
Module: (INT0 Trigger)
With External Interrupt (INT0) selected start conversion (SSRC<2:0> 001), device wake-up from Sleep Idle mode more than conversion selected interrupt (SMPI<3:0> 0000). Interrupts generated correctly device Sleep Idle mode. Work around Configure generate interrupt after every conversion (SMPI<3:0> 0000). another wake-up source, such another interrupt source, exit Sleep Idle mode. Alternatively, perform conversions mode. Affected Silicon Revisions
Module: Interrupts (Traps)
device exit Doze mode certain trap conditions occur. Address error, stack error math error traps affected. Oscillator failure interrupt sources affected cause device correctly exit Doze mode. Work around None. Affected Silicon Revisions
Module: (Framed Modes)
frame synchronization pulse output Master mode pulse selected coincide with first clock (SPIFE SCKx SDOx waveforms affected. Work around Select frame synchronization pulses precede first clock (SPIFE frame pulses will output correctly described product data sheet. Affected Silicon Revisions
Module: Output Compare
output compare module output single glitch after module enabled (OCM<2:0> 000). This issue occurs when output state associated Data Latch register (LATx) opposite state Output Compare mode when peripheral enabled. also occur when switching between Output Compare modes with opposite output states. Work around output glitch must avoided, verify that associated data latch value matches initial state desired Output Compare mode. example, Output Compare configured mode, OCM<2:0> 001, ensure that LATD<4> clear prior writing bits. port latch output value will match initial output state avoid glitch when peripheral enabled. Affected Silicon Revisions
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Module: (Slave Mode)
Slave mode (MSTEN with slave select option enabled (SSEN peripheral accept transfers regardless state. received data SSPxBUF will accurate intended device. Work around Slave select option required (e.g., device multiple slave nodes network), potential work arounds exist: Configure port associated with input periodically read PORT register. read `0', disable peripheral (SPIEN Enable peripheral (SPIEN read logic `1'. Read associated with after transfer complete, indicated SPIxF being set. port read digital `1', read SSPxBUF discard contents. Affected Silicon Revisions
Module: Core (Traps)
clock failure occurs when device Idle mode, oscillator failure trap does vector Trap Service Routine. Instead, device will simply wake-up from Idle mode continue code execution Fail-Safe Clock Monitor (FSCM) enabled. Work around Whenever device wakes from Idle (assuming FSCM enabled), user software should check status OSCFAIL (INTCON1<1>) determine whether clock failure occurred then perform appropriate clock switch operation. Affected Silicon Revisions
Module: Core (Resets)
Brown-out Reset, both bits set. This cause Brown-out Reset condition indistinguishable from Power-on Reset. Work around None. Affected Silicon Revisions
Module: Oscillator (Two-Speed Start-up)
Two-Speed Start-up feature available exit from Sleep mode with IESO (Internal External Switchover mode) enabled. Upon wake-up, device will wait clock source used prior entering Sleep mode become ready. Work around None. Affected Silicon Revisions
Module: Ports
During Power-on Reset (POR), device drive OSCO/CLKO/RC15 clock output approximately During this time, will driven high rather than being high-impedance. This cause issues designs that general purpose I/O. Designs should reviewed ensure that their intended operation will disrupted driven during POR. Work around None. Affected Silicon Revisions
Module: Core (Reset)
CLKDIV register Reset value incorrect. register will reset with unimplemented bits equal Resets. Work around Mask unimplemented bits maintain software compatibility with future device revisions. Affected Silicon Revisions
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Module: (Slave Mode)
During Slave mode transactions, Data/Address bit, D/A, update during data frame. This affects both 10-Bit Addressing modes. slave receptions affected this issue. Work around Read/Write bit, R/W, Transmit Buffer Full Status Bit, TBF, determine whether address data information being received. more information, Figure 24-30 Figure 24-31 Section "Inter-Integrated Circuit(I2CTM)" (DS39702). Affected Silicon Revisions
Module: UART
When UART uses Stop bits (STSEL sample first Stop instead second one. device being communicated with using Stop communications, this lead framing errors. Work around None. Affected Silicon Revisions
Module:
Master mode, Disable SCKx bit, DISSCK, disable clock. result, PIC® microcontroller must provide clock Master mode. Work around None. Affected Silicon Revisions
Module: UART (Auto-Baud)
When auto-baud detected, receive interrupt occur twice. first interrupt occurs beginning Start second after reception Sync field character. Work around receive interrupt occurs, check URXDA (UxSTA<0>) ensure that valid data available. first interrupt, data will present. second interrupt will have Sync field character (55h) receive FIFO. Affected Silicon Revisions
Module: Output Compare (PWM Mode)
mode, output compare module miss compare event when current duty cycle register (OCxRS) value 0x0000 duty cycle) OCxRS register updated with value 0x0001. compare event only missed first time value 0x0001 written OCxRS output remains period. Subsequent high times occur expected. Work around current OCxRS register value 0x0000, avoid writing value 0x0001 OCxRS. Instead, write value 0x0002. this case, however, duty cycle will slightly different from desired value. Affected Silicon Revisions
Module: UART (Auto-Baud)
auto-baud miscalculate certain baud rates clock speed combinations, resulting value that greater less than expected value. When UxBRG less than this result transmission reception failures introducing error greater than Work around Test auto-baud calculations various clock speed baud rate combinations that would used applications. inaccurate UxBRG value generated, manually correct baud rate user code. Affected Silicon Revisions
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Module:
FIFO overflow occurs, VWORD indicator will reset instead `0'. Further writes FIFO will cause VWORD indicator reset after seven writes performed. Work around Poll CRCFUL (CRCCON<7>) ensure that writes performed FIFO when full. Affected Silicon Revisions
Module:
After ACKSTAT set, while receiving NACK from master slave, cleared reception Start Stop bit. Work around Store value ACKSTAT immediately after receiving NACK. Affected Silicon Revisions
Module: RTCC Module: UART (IrDA®)
When UART configured IrDA interface operations (UxMODE<9:8> 11), baud clock signal BCLKx will only present when module transmitting. will Idle other times. Work around Configure output compare modules generate required baud clock signal when UART receiving data Idle state. Affected Silicon Revisions When performing writes ALCFGRPT register, some bits become corrupted. error occurs because desynchronization between clock domain RTCC clock domain. error causes data from instruction following ALCFGRPT instruction overwrite data ALCFGRPT. Work around Always follow writes ALCFGRPT register with additional write same data dummy location. These writes performed locations, registers unimplemented space. optimal perform work around: Read ALCFGRPT into location. Modify ALCFGRPT data, required, RAM. Move value into ALCFGRPT, dummy location, back-to-back instructions. Affected Silicon Revisions
Module:
byte-based operations have intended affect I2CxSTAT register. possible byte operations performed lower byte I2CxSTAT clear (I2CxSTAT<10>). byte operation performed upper byte I2CxSTAT, directly, able clear bit. Work around Modifications I2CxSTAT register should done using word writes only. This done always writing register itself individual bits. example, code: I2C1STAT 0xFBFF forces compiler word-based operation clear bit. assembly, done using BSET BCLR instructions. instructions with modifier. Affected Silicon Revisions
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Module: Core (Instruction Set)
instruction producing read-after-write stall condition executed inside REPEAT loop, instruction will executed fewer times than intended. example, this loop: repeat #0xf [w1],[++w1] will execute less than times. Work around Avoid using REPEAT repetitively execute instructions that create stall condition. Instead, software loop using conditional branches. Affected Silicon Revisions
Module: (PORTB)
When configured open-drain output, remains high-impedance state. settings LATB5 TRISB5 have effect pin's state. Work around open-drain operation required, configure regular (ODCB<5> open-drain operation required, there options: select different open-drain function; place external transistor configure regular I/O. Affected Silicon Revisions
Module: Memory (Program Space Visibility)
When accessing data area data RAM, possible generate false address error trap condition reading data located precisely lower address boundary (8000h). data read using instruction with auto-decrement, resulting address will below boundary (i.e., 7FFEh); this will result address error trap. This false address error also occur 32-bit instruction used read data location 8000h. Work around first location page (address 8000h). Affected Silicon Revisions
Module: RTCC (Alarm)
Under certain circumstances, value Alarm Repeat Counter (ALCFGRPT<7:0>) unexpectedly decremented. This happens only when byte write upper byte ALCFGRPT performed interval between device POR/BOR first edge from RTCC clock source. Work around perform byte writes ALCFGRPT, particularly upper byte. Alternatively, wait until period SOSC completed before performing byte writes ALCFGRPT. Affected Silicon Revisions
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Module: UART (UERIF Interrupt)
UART error interrupt occur, occur incorrect time, multiple errors occur during short period time. Work around Read error flags UxSTA register whenever byte received verify error status. most cases, these bits will correct, even UART error interrupt fails occur. possible exceptions, refer Errata Affected Silicon Revisions
Module: (Master Mode)
Under certain circumstances, module operating Master mode Acknowledge command addressed slave device. This happens when following occurs: 10-Bit Addressing mode used (A10M master same upper address bits (I2CADD<9:8>) addressed slave module. these cases, master also Acknowledges address command generates erroneous slave interrupt, well master interrupt. Work around Several options available: When using 10-Bit Addressing mode, make certain that master slave devices share same MSbs their addresses. this cannot avoided: Clear A10M (I2CxCON<10> prior performing Master mode transmit. Read ADD10 (I2CxSTAT<8>) check full 10-bit match whenever slave interrupt occurs master module. Affected Silicon Revisions
Module: UART (FIFO Error Flags)
Under certain circumstances, PERR FERR error bits correct bytes receive FIFO. This only been observed when both following conditions met: UART receive interrupt occur when FIFO full full (UxSTA<7:6> 1x); more than bytes with error received. these cases, only first bytes with parity framing error will have corresponding bits indicate correctly. error bits will after this. Work around None. Affected Silicon Revisions
Module: (Slave Mode)
Under certain circumstances, module operating Slave mode respond correctly some special addresses reserved protocol. This happens when following occurs: 10-Bit Addressing mode used (A10M A<7:1> bits slave address (I2CADD<7:1>) fall into range reserved 7-bit address ranges: `1111xxx' `0000xxx'. these cases, Slave module Acknowledges command triggers slave interrupt; does copy data into I2CxRCV register bit. Work around bits, A<7:1>, module's slave address equal `1111xxx' `0000xxx'. Affected Silicon Revisions
Module: UART
UART transmit data written TXxREG before module enabled. Work around ensure transmission occurs, always enable UART before buffer loaded. procedure Section 16.2 "Transmitting 8-Bit Data Mode" Section 16.3 "Transmitting 9-Bit Data Mode" device data sheet (DS39747). Affected Silicon Revisions
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Module:
Transmit Buffer Full (TBF) flag (I2CxSTAT<0>) cleared hardware collision occurs before first falling clock edge during transmission. Work around None. Affected Silicon Revisions
Module: (Master Mode)
Master mode, Interrupt Flag (SPIxIF) SPIRBF (SPIxSTAT<0>) both become one-half clock cycle early, instead clock edge. This occurs only under following circumstances: Enhanced Buffer mode disabled (SPIBEN module configured serial data output changes transition from clock active clock Idle state (CKE application using interrupt flag determine when data transmitted written transmit buffer, data currently buffer overwritten. Work around Before writing buffer, check SCKx determine last clock edge passed. Example (below) demonstrates method doing this. this example, functions clock, SCK, which configured Idle low. Affected Silicon Revisions
EXAMPLE
CHECKING STATE SPIxIF AGAINST CLOCK
//wait transmission complete //wait last clock finish //write data buffer
while(IFS0bits.SPI1IF 0){} while(PORTDbits.RD1 1){} SPI1BUF 0xFF;
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Module: RTCC (Alarm)
RTCC alarm repeat will generate incorrect number toggles. repeat count even, will toggle alarm times. repeat count odd, less than toggles will observed Work around None this time. Affected Silicon Revisions
Module: Pins
output, VOL, meets specifications Table below. Work around None. Affected Silicon Revisions
TABLE
CHARACTERISTICS: OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2.0V 3.6V (unless otherwise stated) Operating temperature -40°C +85°C Industrial Typ(1) Units Conditions
CHARACTERISTICS Param DO10 Characteristic Output Voltage Pins
3.6V 3.6V 2.0V 2.0V
Note
Data "Typ" column 3.3V, 25°C unless otherwise stated. Parameters design guidance only tested.
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Module: (Framed Modes)
Framed modes, described device data sheet, supported. When using module, verify FRMEN (SPIxCON2<15>) cleared. other modes function described. Work around None. Affected Silicon Revisions
Module: Core (Code Protection)
When general segment code protection been enabled (GCP Configuration programmed), applications unable write first bytes program memory space (0000h through 0200h). applications that require interrupt vectors changed during time, such bootloaders, modifications interrupt vector tables will possible. Work around Create interrupt vector tables, each AIVT, area program space beyond affected region. addresses vector tables tables. These tables then modified needed actual addresses ISRs. Affected Silicon Revisions
Module: (Enhanced Mode)
operating Enhanced Buffer mode (SPIBEN interrupt flag, SPIxIF, before last been transmitted from shift register. This issue only affects eight interrupt modes, SISEL<2:0> 101, which generates interrupt when last shifted shift register, indicating transfer complete. other interrupt modes Enhanced Buffer mode work described device data sheet. Work around Multiple work arounds available. Select another Buffer Interrupt mode using SISEL<2:0> bits SPIxSTAT register. comparable mode generate interrupt when FIFO empty (SISEL<2:0> 110). Another option monitor SRMPT (SPIxSTAT<7>) determine when shift register empty. Affected Silicon Revisions
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Data Sheet Clarifications
following typographic corrections clarifications noted latest version device data sheet (DS39747D): Note: Corrections shown bold. Where possible, original bold text formatting been removed clarity.
None.
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PIC24FJ128GA010 FAMILY
APPENDIX DOCUMENT REVISION HISTORY
(I2C Master Mode) (I2C Slave Mode) (I2C) (SPI Master Mode) (RTCC- Alarm)* (I/O Pins) (SPI Framed Modes) (SPI- Enhanced Mode)* (Core Code Protection). Document (6/2009) Initial release this document; issued revision Incorporates following current historical silicon issues from revisions (Core)* (I2C) (UART) (Resets) (Timers) (SPI Enhanced Mode)* (JTAG Programming)* (A/D) (I2C) (UART) (SPI Master Mode)* (CPU) 13-14 (PMP Master Mode)* 15-16 (RTCC) (I2C- Slave Mode)* (I2C) 19-22 (UART)* (UART- Hardware Flow Control)* (UART) (UART- Auto-Baud)* (Interrupts Traps)* (Output Compare) (A/D INT0 Trigger)* (SPI Framed Modes)* (SPI Slave Mode) (Oscillator Two-Speed Start-up)* (Core Reset) (Core Traps)* (I/O Ports) (I2C Slave Mode)* 37-38 (UART- Auto-Baud)* (UART) (SPI) (Output Compare Mode)* (CRC) (UART- IrDA) 44-45 (I2C) (RTCC) (Core Instruction Set) (Memory Program Space Visibility) (I/O PORTB) (RTCC- Alarm)* (UART UERIF Interrupt) (UART FIFO Error Flags) (UART)
Issues marked with have additional descriptive text added their titles, otherwise unchanged from original publication. Issues (UART) (I2C) have been revised with updated language that reflects more complete understanding their scope and/or root causes. previous issue from revision (I2C) been deleted duplicate issue This document replaces these errata documents: "PIC24FJ128GA010 Family Rev. Silicon Errata" (DS80275) "PIC24FJ128GA010 Family Rev. Silicon Errata" (DS80295) "PIC24FJ128GA010 Family Rev. Silicon Errata" (DS80330) "PIC24FJ128GA010 Family Rev. Silicon Errata" (DS80422)
DS80471A-page
2009 Microchip Technology Inc.
Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
Code protection constantly evolving. Microchip committed continuously improving code protection features products. Attempts break Microchip's code protection feature violation Digital Millennium Copyright Act. such acts allow unauthorized access your software other copyrighted work, have right relief under that Act.
Information contained this publication regarding device applications like provided only your convenience superseded updates. your responsibility ensure that your application meets with your specifications. MICROCHIP MAKES REPRESENTATIONS WARRANTIES KIND WHETHER EXPRESS IMPLIED, WRITTEN ORAL, STATUTORY OTHERWISE, RELATED INFORMATION, INCLUDING LIMITED CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY FITNESS PURPOSE. Microchip disclaims liability arising from this information use. Microchip devices life support and/or safety applications entirely buyer's risk, buyer agrees defend, indemnify hold harmless Microchip from damages, claims, suits, expenses resulting from such use. licenses conveyed, implicitly otherwise, under Microchip intellectual property rights.
Trademarks Microchip name logo, Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC UNI/O registered trademarks Microchip Technology Incorporated U.S.A. other countries. FilterLab, Hampshire, HI-TECH Linear Active Thermistor, MXDEV, MXLAB, SEEVAL Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, Omniscient Code Generation, PICC, PICC-18, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2009, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
2009 Microchip Technology Inc.
DS80471A-page
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03/26/09
DS80471A-page
2009 Microchip Technology Inc.
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