PIC24FJ64GA004 Family Silicon Errata Data Sheet Clarification PIC
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PIC24FJ64GA004 FAMILY
PIC24FJ64GA004 Family Silicon Errata Data Sheet Clarification
PIC24FJ64GA004 family devices that have received conform functionally current Device Data Sheet (DS39881C), except anomalies described this document. silicon issues discussed following pages silicon revisions with Device Revision listed Table silicon issues summarized Table errata described this document will addressed future revisions PIC24FJ64GA004 family silicon. Note: This document summarizes silicon errata issues from revisions silicon, previous well current. Only issues indicated last column Table apply current silicon revision (B5). example, identify silicon revision level using MPLAB conjunction with MPLAB PICkit3: Using appropriate interface, connect device MPLAB programmer/ debugger PICkit3. From main menu MPLAB IDE, select Configure>Select Device, then select target part number dialog box. Select MPLAB hardware tool (Debugger>Select Tool). Perform "Connect" operation device (Debugger>Connect). Depending development tool used, part number Device Revision value appear Output window. Note: unable extract silicon revision level, please contact your local Microchip sales office assistance.
Data Sheet clarifications corrections start page following discussion silicon issues. silicon revision level identified using current version MPLAB® Microchip's programmers, debuggers, emulation tools, which available Microchip corporate site (www.microchip.com).
DEVREV values various PIC24FJ64GA004 family silicon revisions shown Table
TABLE
SILICON DEVREV VALUES
Device ID(1) 044Fh 044Eh 044Dh 044Ch 0447h 0446h 0445h 0444h 3003h 3042h 3043h Revision Silicon Revision(2) A3/A4
Part Number PIC24FJ64GA004 PIC24FJ48GA004 PIC24FJ32GA004 PIC24FJ16GA004 PIC24FJ64GA002 PIC24FJ48GA002 PIC24FJ32GA002 PIC24FJ16GA002 Note
Device (DEVID DEVREV) located last implemented addresses configuration memory space. They shown hexadecimal format "DEVID DEVREV". Refer "PIC24FJXXXGA0XX Flash Programming Specification" (DS39768) detailed information Device Revision your specific device.
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TABLE
Module JTAG Core Core Core Core UART UART UART UART UART UART
SILICON ISSUE SUMMARY
Feature Idle mode Doze mode Line State (I2C1) Auto-Baud Auto-Baud Auto-Baud Break Character Generation Enhanced Buffer mode Enhanced Buffer mode Slave mode IrDA® UERIF Interrupt Item Number Affected Revisions(1) Issue Summary A3/A4 Persistent pull-up (RA3) when JTAG disabled. interrupt with low-voltage condition Reset. Clock failure trap fails Idle mode. read repeat entering Doze mode. flags both BOR. size implementation some devices. Unimplemented channels selected. Missing midscale conversion code. Device wake when convert INT0 trigger selected. Line state detected correctly. Reception failures High-Speed mode. Erroneous baud rate calculations High-Speed mode. Double receive interrupt with auto-baud reception. Insertion spurious data with auto-baud reception. Auto-baud calculation errors causing transmit receive failures. UART module will generate back-to-back Break characters. Single missed compare events under certain conditions. Some flag bits incorrect times Enhanced Buffer mode. Module Slave mode ignore receive data anyway. interrupt Enhanced Buffer mode under certain conditions. Spec change VOH. OSCO/RA3 driven immediately following POR. Sync loss ICSPmode. Write errors ALCFGRPT register. Slave mode, ACKSTAT state change. Issues with write operations I2CxSTAT. baud clock only available during transmit. Issues with digital signal priorities with RP12 RP18. UERIF flag with multiple errors.
Output Compare JTAG RTCC UART UART Note
Only those issues indicated last column apply current silicon revision.
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TABLE
Module UART Core Core Memory RTCC I2C
SILICON ISSUE SUMMARY (CONTINUED)
Feature FIFO Error Flags Instruction Master mode Master mode Slave mode SOSC Code-Protect IrDA® Item Number Affected Revisions(1) Issue Summary A3/A4 PERR FERR correctly bytes receive FIFO. Spontaneous events with low-range VDD. Loop count errors with REPEAT instruction R-A-W stalls. False address error traps lower boundary space. Decrement Alarm Repeat Counter under certain conditions. SPIIF SPIBEN become early under certain conditions. Module respond Master transmission Slave under certain conditions. Failure respond correctly some reserved addresses 10-bit mode. flag cleared under certain conditions. Erroneous sampling framing errors when using Stop bits. Low-power SOSC unimplemented. Standby mode available. General Code Protection disables bootloader functionality. Interrupts when operating Enhanced Buffer mode. Writes locations when Doze mode enabled. RXINV operation inverted IrDA mode
UART Oscillator Voltage Regulator Core Core UART Note
Only those issues indicated last column apply current silicon revision.
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Silicon Errata Issues
Note: This document summarizes silicon errata issues from revisions silicon, previous well current. Only issues indicated shaded column following tables apply current silicon revision (B5).
Module: Core
clock failure occurs when device Idle mode, oscillator failure trap does vector Trap Service Routine. Instead, device will simply wake-up from Idle mode continue code execution Fail-Safe Clock Monitor (FSCM) enabled. Work around
Module: JTAG
When JTAG disabled, pull-up resistor (pin 35/RA9) will stay enabled 44-pin variants device. This cause device draw extra current when asleep used input held low. Work around: will draw extra current following work around techniques used: used output. driven high input. JTAG enabled. Affected Silicon Revisions
Whenever device wakes from Idle (assuming FSCM enabled), user software should check status OSCFAIL (INTCON1<1>) determine whether clock failure occurred, then perform appropriate clock switch operation. Affected Silicon Revisions
Module: Core
read performed instruction immediately prior enabling Doze mode, then extra read event will occur when Doze mode enabled. most SFRs user space, this will have visible effect. However, this cause registers which perform actions reads, such auto-incrementing decrementing pointer removing data from FIFO buffer, repeat that action, possibly resulting lost data. Work around instruction prior entering Doze mode, sure read register which performs secondary action. Examples this would UART FIFO buffers, RTCVAL registers. easiest ensure this does occur execute instruction before entering Doze mode. Affected Silicon Revisions
Module: Low-Voltage Detect
Low-Voltage Detect interrupt will occur device comes Reset low-voltage state. trigger interrupt, voltage must decrease low-voltage range while device running. Work around None. Affected Silicon Revisions
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Module: Core
Brown-out Reset, both bits set. This cause Brown-out Reset condition indistinguishable from Power-on Reset. Work around None. Affected Silicon Revisions
Module:
module will generate code 511. conversion which should result normally, will instead generate 512. Work around None. Affected Silicon Revisions
Module: Module: Core
PIC24FJ16GA002 PIC24FJ16GA004 devices have data implemented instead This will cause address error trap function addresses between 2000h 27FFh. Work around access beyond address 17FFh maintain software compatibility with future device revisions. Affected Silicon Revisions Affected Silicon Revisions With External Interrupt (INT0) selected start conversion (SSRC<2:0> 001), device wake-up from Sleep Idle mode more than conversion selected interrupt (SMPI<3:0> 0000). Interrupts generated correctly device Sleep Idle mode. Work around Configure generate interrupt after every conversion (SMPI<3:0> 0000). another wake-up source, such another interrupt source, exit Sleep Idle mode. Alternatively, perform conversions mode.
Module:
AD1PCFG AD1CHS registers allow unimplemented channels selected. these channels selected, they will read tied VSS. These channels should disabled. Work around Disable channels, AN13 AN14, AD1PCFG register ensuring that bits cleared. Ensure that bits AD1CHS maintained cleared. these bits set, will cause reference channels AN16-31. Affected Silicon Revisions
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Module: I2C(I2C1, Line State)
When using I2C1, SDA1 line state detected properly unless first held after enabling module. Master mode, this error cause collision occur instead Start transmission. Transmissions after SDA1 been held will occur correctly. Slave mode, device Acknowledge first packet sent after enabling module. this case, will return NACK instead ACK. device will correctly respond packets after detecting level line I2C2 module operates expected does exhibit this issue. Work around Using external device another from microcontroller, drive SDA1 low. external devices additional pins available, sometimes possible perform work around internally, using following steps: With module Master mode, configure output. Clear LATB9 (for default I2C1 assignment) LATB5 (for alternate I2C1 assignment) drive low. Enable I2C1 setting I2CEN (I2C1CON<15>). Note that this action could appear Start slave device RB8/SCL1 driven prior driving RB9/SDA1 low. necessary additional capacitance SDA1 order maintain logic level long enough module detect logic level. Make sure that when adding capacitance, that application does violate timing specifications. Slave mode, master device must either pull SDAx line low, then high again, prior sending first packet device, must resend first packet. Note that absolute maximum time required avoid issue. possible work around issue using shorter delay some devices. Affected Silicon Revisions
Module: UART
When UART High-Speed mode, BRGH (UxMODE<3>) set; some optimal UxBRG values cause reception fail. Work around Test UxBRG values application find UxBRG value that works consistently more high-speed applications. user should verify that UxBRG baud rate error does exceed application limits. possible, recommended comparable baud rate Low-Speed mode. Affected Silicon Revisions
Module: UART
When UART High-Speed mode (BRGH auto-baud sequence calculate baud rate were Low-Speed mode. Work around calculated baud rate modified following equation: Value (Auto-Baud user should verify that baud rate error does exceed application limits. Affected Silicon Revisions
Module: UART
When auto-baud detected, receive interrupt occur twice. first interrupt occurs beginning Start second after reception Sync field character. Work around receive interrupt occurs, check URXDA (UxSTA<0>) ensure that valid data available. first interrupt, data will present. second interrupt will have Sync field character (55h) receive FIFO. Affected Silicon Revisions
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Module: UART
With auto-baud feature selected, Sync field character (0x55) loaded into FIFO data. Work around prevent Sync field character from being loaded into FIFO, load UxBRG register with either 0x0000 0xFFFF prior enabling auto-baud feature (ABAUD Affected Silicon Revisions
Module: Output Compare
mode, output compare module miss compare event when current duty cycle register (OCxRS) value 0x0000 duty cycle) OCxRS register updated with value 0x0001. compare event only missed first time value 0x0001 written OCxRS output remains period. Subsequent high times occur expected. Work around current OCxRS register value 0x0000, avoid writing value 0x0001 OCxRS. Instead, write value 0x0002. this case, however, duty cycle will slightly different from desired value. Affected Silicon Revisions
Module: UART
auto-baud miscalculate certain baud rates clock speed combinations, resulting value that greater less than expected value. When UxBRG less than this result transmission reception failures introducing error greater than Work around Test auto-baud calculations various clock speed baud rate combinations that would used applications. inaccurate UxBRG value generated, manually correct baud rate user code. Affected Silicon Revisions
Module:
When using Enhanced Buffer mode, some indicator bits incorrect times: slave transfers, SRMPT (SPIxSTAT<7>) early, after only periods. Slave Interrupt modes (SISELx there period delay between interrupt event SPIxIF being set. There several instruction cycle delays between FIFO full FIFO empty events interrupt flags indicator bits being set. Work around None this time. Affected Silicon Revisions
Module: UART
UART module will generate consecutive Break characters. Trying perform back-toback Break character transmission will cause UART module transmit dummy character used generate first Break character instead transmitting second Break character. Break characters generated correctly they followed non-Break character transmission. Work around None. Affected Silicon Revisions
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Module:
Slave mode (MSTEN with slave select option enabled (SSEN peripheral accept transfers regardless state. received data SPIxBUF will accurate intended device. Work around There work around using peripheral select feature. external interrupts (INT1 INT2) mapped same signal signal mapped with interrupt-on-change (CNx) functionality. signal changes (active), interrupt flag will set. When data received interrupt occurs, interrupt flag tested. interrupt mapped occur, discard data. Affected Silicon Revisions
Module:
When using Enhanced Buffer mode, interrupt will occur following conditions exist: Buffer Interrupt mode, SISEL<2:0> (SPIxSTAT<4:2>), interrupt when Shift register empty (SISEL<2:0> 101). Slave Select mode enabled (SSEN This only occurs when Enhanced mode, Slave Select mode interrupt Shift register empty enabled. other modes, interrupt will work correctly. Work around When Slave Select mode enabled, interrupting SPIxSR empty empty will occur same time. Therefore, interrupting FIFO empty (SISEL<2:0> 110) used alternative interrupting when Shift register empty (SISEL<2:0> 101). Affected Silicon Revisions
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Module: Ports
outputs, VOH, meet specifications Table below. Work around None. Affected Silicon Revisions
TABLE
CHARACTERISTICS: OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2.0V 3.6V (unless otherwise stated) Operating temperature -40°C +85°C Industrial Typ(1) Units Conditions
CHARACTERISTICS Param DO10 Characteristic Output Voltage Pins
3.6V 3.6V 2.0V 2.0V -3.0 3.6V -6.0 3.6V -1.0 2.0V -3.0 2.0V
DO20
Output High Voltage Pins 1.65
Note
Data "Typ" column 3.3V, 25°C unless otherwise stated. Parameters design guidance only tested.
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Module: Ports
During Power-on Reset (POR), device drive OSCO/RA3 clock output approximately During this time, will driven high rather than being high-impedance. This cause issues designs that general purpose I/O. Designs should reviewed ensure that their intended operation will disrupted driven during POR. Work around None. Affected Silicon Revisions Work around Always follow writes ALCFGRPT register with additional write same data dummy location. These writes performed locations, registers unimplemented space. optimal perform work around: Read ALCFGRPT into location. Modify ALCFGRPT data, required, RAM. Move value into ALCFGRPT, dummy location, back-to-back instructions. Affected Silicon Revisions
Module: JTAG
When entering SHIFT_DR state while ICSPCommunications mode, extra clock edge generated, causing JTAG ICSP communications lose synchronization. This prevents device programming using ICSP over JTAG. JTAG boundary scan affected operates expected. Work around None. Affected Silicon Revisions
Module:
When module operating Slave mode, after ACKSTAT when receiving NACK from master, cleared reception Start Stop bit. this issue, state ACKSTAT after transmission finishes will vary depending device revision. revisions with this issue, ACKSTAT will clear transmission, will remain clear until next NACK received from Master. revisions without issue, ACKSTAT will transmission will remain until receiving from Master. Work around Store value ACKSTAT immediately after receiving NACK from master. Affected Silicon Revisions
Module: RTCC
When performing writes ALCFGRPT register, some bits become corrupted. error occurs because desynchronization between clock domain RTCC clock domain. error causes data, from instruction following ALCFGRPT instruction, overwrite data ALCFGRPT.
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Module:
byte-based operations have intended affect I2CxSTAT register. possible byte operations performed lower byte I2CxSTAT clear (I2CxSTAT<10>). byte operation performed upper byte I2CxSTAT, directly, able clear bit. Work around Modifications I2CxSTAT register should done using word writes only. This done always writing register itself individual bits. example, code, I2C1STAT 0xFBFF, will force compiler word-based operation clear bit. assembly, done using BSET BCLR instructions, instructions with modifier. Affected Silicon Revisions
Module: (Peripheral Select)
remappable functions multiplexed some pins have higher priority than fixed digital signals assigned those pins. design, remapped digital function should always have priority over other fixed digital function same pin. Using these remappable specific fixed digital functions same time cause conflicts unexpected results RP12 PMD0 RP18 PMA2 (40-pin 44-pin devices only) other fixed digital functions affected. Work around affected pins, enable either remappable peripherals, specific fixed digital peripherals, both same time. Affected Silicon Revisions
Module: UART
When UART configured interface operations (UxMODE<9:8> 11), baud clock signal BCLK will only present when module transmitting. will Idle other times. Work around Configure output compare modules generate required baud clock signal when UART receiving data Idle state. Affected Silicon Revisions
Module: UART (UERIF Interrupt)
UART error interrupt occur, occur incorrect time, multiple errors occur during short period time. Work around Read error flags UxSTA register whenever byte received verify error status. most cases, these bits will correct, even UART error interrupt fails occur. possible exceptions, refer Errata Affected Silicon Revisions
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Module: UART (FIFO Error Flags)
Under certain circumstances, PERR FERR error bits correct bytes receive FIFO. This only been observed when both following conditions met: UART receive interrupt occur when FIFO full full (UxSTA<7:6> 1x), more than bytes with error received. these cases, only first bytes, with parity framing error, will have corresponding bits indicate correctly. error bits will after this. Work around None. Affected Silicon Revisions
Module: Core (Instruction Set)
instruction producing read-after-write stall condition executed inside REPEAT loop, instruction will executed fewer times than intended. example, this loop: repeat #0xf [w1],[++w1] will execute less than times. Work around Avoid using REPEAT repetitively execute instructions that create stall condition. Instead, software loop using conditional branches. MPLAB® Compiler will generate REPEAT loops that cause this erratum. Affected Silicon Revisions
Module: Core (BOR)
When on-chip regulator enabled (DISVREG tied VSS), event spontaneously occur under following circumstances: less than 2.5V, internal band reference being used reference with converter (AD1PCFG<15> Work around select internal band reference converter when on-chip regulator Tracking mode (LVDIF (IFS4<8>) Affected Silicon Revisions
Module: Memory (Program Space Visibility)
When accessing data area data RAM, possible generate false address error trap condition reading data located precisely lower address boundary (8000h). data read using instruction with autodecrement, resulting address will below boundary (i.e., 7FFEh); this will result address error trap. This false address error also occur 32-bit instruction used read data location, 8000h. Work around first location page (address 8000h). MPLAB Compiler (v3.11 later) supports option, -merrata=psv_trap, prevent from generating code that would cause this erratum. Affected Silicon Revisions
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Module: RTCC
Under certain circumstances, value Alarm Repeat Counter (ALCFGRPT<7:0>) unexpectedly decremented. This happens only when byte write upper byte ALCFGRPT performed interval between device POR/ first edge from RTCC clock source. Work around perform byte writes ALCFGRPT, particularly upper byte. Alternatively, wait until period SOSC completed before performing byte writes ALCFGRPT. Affected Silicon Revisions
Module: (Master Mode)
Under certain circumstances, module operating Master mode Acknowledge command addressed slave device. This happens when following occurs: 10-Bit Addressing mode used (A10M master same upper address bits (I2CADD<9:8>) addressed slave module. these cases, master also Acknowledges address command generates erroneous slave interrupt, well master interrupt. Work around Several options available: When using 10-Bit Addressing mode, make certain that master slave devices share same MSbs their addresses. this cannot avoided: Clear A10M (I2CxCON<10> prior performing Master mode transmit. Read ADD10 (I2CxSTAT<8>) check full 10-bit match whenever slave interrupt occurs master module. Affected Silicon Revisions
Module: (Master Mode)
Master mode, Interrupt Flag (SPIxIF) SPIRBF (SPIxSTAT<0>) both become one-half clock cycle early, instead clock edge. This occurs only under following circumstances: Enhanced Buffer mode disabled (SPIBEN module configured serial data output changes transition from clock active clock Idle state (CKE application using interrupt flag determine when data transmitted written transmit buffer, data currently buffer overwritten. Work around Before writing buffer, check determine last clock edge passed. Example (below) demonstrates method doing this. this example, functions clock, SCK, which configured Idle low. Affected Silicon Revisions
EXAMPLE
CHECKING STATE SPIxIF AGAINST CLOCK
//wait transmission complete //wait last clock finish //write data buffer
while(IFS0bits.SPI1IF 0){} while(PORTDbits.RD1 1){} SPI1BUF 0xFF;
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Module: (Slave Mode)
Under certain circumstances, module operating Slave mode respond correctly some special addresses reserved protocol. This happens when following occurs: 10-Bit Addressing mode used (A10M bits, A<7:1>, slave address (I2CADD<7:1>) fall into range reserved 7-bit address ranges: `1111xxx' `0000xxx'. these cases, Slave module Acknowledges command triggers slave interrupt; does copy data into I2CxRCV register bit. Work around bits, A<7:1>, module's slave address equal `1111xxx' `0000xxx'. Affected Silicon Revisions
Module: Oscillator (SOSC)
low-power secondary oscillator option, selected SOSCSEL Configuration bits (CW2<12:11>), available this silicon revision. oscillator devices functions Default (High-Gain) mode only. Work around None. Affected Silicon Revisions
Module: Voltage Regulator
Standby mode wake-up option, selected WUTSEL Configuration bits (CW2<14:13>), available this silicon revision. devices default regulator wake-up time Work around None. Affected Silicon Revisions
Module:
Transmit Buffer Full flag, (I2CxSTAT<0>), cleared hardware collision occurs before first falling clock edge during transmission. Work around None. Affected Silicon Revisions
Module: Core (Code Protection)
When General Segment Code Protection been enabled (GCP Configuration programmed), applications unable write first bytes program memory space (0000h through 0200h). applications that require interrupt vectors changed during time, such bootloaders, modifications Interrupt Vector Tables (IVTs) will possible. Work around Create Interrupt Vector Tables, each AIVT, area program space beyond affected region. addresses vector tables tables. These tables then modified needed actual addresses ISRs. Affected Silicon Revisions
Module: UART
When UART operating using Stop bits (STSEL sample first Stop instead second one. device being communicated with using Stop communications, this lead framing errors. Work around None. Affected Silicon Revisions
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Module:
operating Enhanced Buffer mode (SPIBEN interrupt flag, SPIxIF, before last been transmitted from shift register. This issue only affects eight Interrupt modes, SISEL<2:0> 101, which generates interrupt when last shifted shift register, indicating transfer complete. other Interrupt modes Enhanced Buffer mode work described product data sheet. Work around Multiple work arounds available. Select another Buffer Interrupt mode using SISEL<2:0> bits SPIxSTAT register. comparable mode generate interrupt when FIFO empty, SISEL<2:0> 110. Another option monitor SRMPT (SPIxSTAT<7>) determine when shift register empty. Affected Silicon Revisions
Module: UART (IrDA®)
When IrDA reception enabled (UxMODE<12> operation RXINV (UxMODE<4>) opposite description device data sheet (DS39881); that setting configures module logic high Idle state, clearing configures module logic Idle state. Using described data sheet result reception errors. Work around Invert state RXINV bit. Idle state received signal logic high, RXINV Idle state received signal logic low, clear RXINV. Affected Silicon Revisions
Module: Core
With Doze mode enabled, DOZEN (CLKDIV<11>) set, Peripheral Clock Ratio Select bits (CLKDIV<14:12>) configured value except `0b000', writes locations performed. Work around ensure proper Doze mode entry exit, should used before enabling, after disabling doze, when modifying Doze mode clock divider. Affected Silicon Revisions
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Data Sheet Clarifications
following typographic corrections clarifications noted latest version device data sheet (DS39881C): Note: Corrections shown bold. Where possible, original bold text formatting been removed clarity.
Module: Electrical Characteristics
Section 26.1 Characteristics", values parameters DC51b DC51c (Idle Current) reported incorrectly. correct values shown extract from Table 26-5 below (changes bold).
TABLE 26-5:
CHARACTERISTICS: IDLE CURRENT (IIDLE) (PARTIAL REPRESENTATION)
Standard Operating Conditions: 2.0V 3.6V (unless otherwise stated) Operating temperature -40°C +85°C Industrial -40°C +125°C Extended Units Conditions
CHARACTERISTICS Parameter
Typical(1)
Idle Current (IIDLE): Core Off, Clock Base Current, Bits Set(2) DC51 DC51a DC51b DC51c Note -40°C +25°C +85°C +125°C 2.0V(3) LPRC kHz)
Data "Typical" column 3.3V, 25°C unless otherwise stated. Parameters design guidance only tested. Base IIDLE current measured with core off, clock modules Peripheral Module Disable (PMD) bits set. On-chip voltage regulator disabled (DISVREG tied VDD).
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Module: 10-Bit High-Speed Converter
AD1CON3 register been changed reflect current operation Clock Selection Bits (ADSC<7:0>). changes shown Register 20-3, below (updated text bold; bold text original removed clarity).
REGISTER 20-3:
R/W-0 ADRC R/W-0 ADCS7 Legend: Readable Value
AD1CON3: CONTROL REGISTER
R/W-0 SAMC4 R/W-0 SAMC3 R/W-0 SAMC2 R/W-0 SAMC1 R/W-0 SAMC0
R/W-0 ADCS6
R/W-0 ADCS5
R/W-0 ADCS4
R/W-0 ADCS3
R/W-0 ADCS2
R/W-0 ADCS1
R/W-0 ADCS0
Writable
Unimplemented bit, read cleared unknown
ADRC: Conversion Clock Source internal clock Clock derived from system clock Unimplemented: Read SAMC4:SAMC0: Auto-Sample Time bits 11111 00001 00000 (not recommended) ADCS7:ADCS0: Conversion Clock Select bits 11111111 Reserved 01000000 00111111 00000001 00000000
14-13 12-8
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Module: Ports
following section accompanying table have been added immediately after existing Section 9.2.1 "I/O Port Write/Read Timing". current Table subsequent tables sequentially renumbered.
Module: Oscillator Configuration
following section been appended Section "Oscillator Configuration". Additional changes device data sheet related this issue presented Clarification (Special Features).
9.2.2
ANALOG INPUT PINS VOLTAGE CONSIDERATIONS
7.5.1
Note:
Secondary Oscillator Features
SECONDARY OSCILLATOR LOW-POWER OPERATION
This feature implemented only PIC24FJ64GA004 family devices with major silicon revision level later (DEVREV register value 3042h greater).
voltage tolerance pins used device inputs dependent pin's input function. Pins that used digital only inputs able handle voltages 5.5V, level typical digital logic circuits. contrast, pins that also have analog input functions kind only tolerate voltages VDD. Voltage excursions beyond these pins always avoided. Table summarizes input capabilities. Refer Section 26.1 Characteristics" more details.
TABLE 9-1:
Port PORTA<4:0> PORTB<15:12> PORTB<4:0> PORTC<2:0>(1) PORTA<10:7>(1) PORTB<11:5> PORTC<9:3>(1) Note
INPUT VOLTAGE LEVELS
Tolerated Input Description Only input levels tolerated.
Secondary Oscillator (SOSC) operate distinct levels power consumption based device configuration. Low-Power mode, oscillator operates low-gain, low-power state. default, oscillator uses higher gain setting, therefore, requires more power. Secondary Oscillator Mode Selection bits, SOSCSEL<1:0> (CW2<12:11>), determine oscillator's power mode. When Low-Power mode used, care must taken design layout SOSC circuit ensure that oscillator will start oscillate properly. lower gain this mode makes SOSC more sensitive noise requires longer start-up time.
5.5V
Tolerates input levels above VDD, useful most standard logic.
7.5.2
OSCILLATOR LAYOUT
Unavailable 28-pin devices.
count devices, such those PIC24FJ64GA004 family, pinout limitations, SOSC more susceptible noise than other PIC24F devices. Unless proper care taken design layout SOSC circuit, possible inaccuracies introduced into oscillator's period. general, crystal circuit connections should short possible. also good practice surround crystal circuit with ground loop ground plane. more detailed information crystal circuit design, please refer "PIC24F Family Reference Manual", Section "Oscillator" (DS39700) Microchip Application Notes: AN826, "Crystal Oscillator Basics Crystal Selection rfPIC® PICmicro® Devices" (DS00826) AN849, "Basic PICmicro® Oscillator Design" (DS00849).
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Module: Special Features
existing version Section 23.2.5 "Voltage Regulator Standby Mode" modified with following additional material. Changes shown bold. Additional changes device data sheet related this issue presented Clarification (Special Features) Clarification (Electrical Characteristics).
Module: Special Features
Register 23-2 (CW2: Flash Configuration Word been amended SOSCEL WUTSEL Configuration bits. changes shown abbreviated Register 23-2 that follows. Changes shown bold, bold from original been removed clarity. Note: descriptions bits through their corresponding rows unchanged original. They have been removed here sake brevity.
23.2.5
VOLTAGE REGULATOR STANDBY MODE
When enabled, on-chip regulator always consumes small incremental amount current over IDD/IPD, including when device Sleep mode, even though core digital logic does require power. provide additional savings applications where power resources critical, regulator automatically places itself into Standby mode whenever device goes into Sleep mode. This feature controlled VREGS (RCON<8>). default, this cleared which enables Standby mode. select PIC24FJ64GA004 family devices, time required regulator wake-up from Standby mode controlled WUTSEL<1:0> Configuration bits (CW2<14:13>). default wake-up time devices Where WUTSEL Configuration bits implemented, fast wake-up option also available. When WUTSEL<1:0> regulator wake-up time Note: This feature implemented only PIC24FJ64GA004 family devices with major silicon revision level later (DEVREV register value 3042h greater).
When regulator's Standby mode turned (VREGS Flash program memory stays powered Sleep mode device wake-up less than When VREGS set, power consumption while Sleep mode, will approximately higher than power consumption when regulator allowed enter Standby mode.
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REGISTER 23-4:
R/PO-1 IESO R/PO-1 FCKSM1
CW2: FLASH CONFIGURATION WORD (PARTIAL REPRESENTATION)
R/PO-1 FNOSC0 R/PO-1 POSCMD0
R/PO-1 R/PO-1 R/PO-1 R/PO-1 WUTSEL1(1) WUTSEL0(1) SOSCSEL1(1) SOSCSEL0(1)
R/PO-1 FNOSC2
R/PO-1 FNOSC1
R/PO-1 FCKSM0
R/PO-1 OSCIOFCN
R/PO-1 IOL1WAY
R/PO-1 I2C1SEL
R/PO-1 POSCMD1
Legend: Readable Program-once Value when device unprogrammed 23-16
Reserved Unimplemented bit, read cleared
14-13
12-11
10-8
Unimplemented: Read IESO: Internal External Switchover IESO mode (Two-Speed Start-up) enabled IESO mode (Two-Speed Start-up) disabled WUTSEL1:WUTSEL0: Voltage Regulator Standby Mode Wake-up Time Select bits(1) Default regulator start-up time used Fast regulator start-up time used Reserved; SOSCSEL1:SOSCSEL0: Secondary Oscillator Power Mode Select bits(1) Default (High Drive Strength) mode Low-Power (Low Drive Strength) mode Reserved; FNOSC2:FNOSC0: Initial Oscillator Select bits POSCMD1:POSCMD0: Primary Oscillator Configuration bits Primary oscillator disabled Oscillator mode selected Oscillator mode selected Oscillator mode selected These bits implemented only devices with major silicon revision level later (DEVREV register value 3042h greater). Refer Section 27.0 "Packaging Information" device data sheet location interpretation product date codes.
Note
DS80470B-page
2009 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
Module: Electrical Characteristics
Table 26-6 been amended following information (added text bold; bold text original removed clarity).
TABLE 26-6:
CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 2.0V 3.6V (unless otherwise stated) Operating temperature -40°C +85°C Industrial -40°C +125°C Extended Units Conditions
CHARACTERISTICS Parameter Typical(1)
Power-Down Current (IPD): Bits Set, VREGS `0'(2) DC62 DC62a DC62b DC62j DC62c DC62d DC62e DC62k DC62f DC62g DC62h DC62i DC63 DC63a DC63b DC63c DC63d DC63e DC63f DC63g DC63h Note 12.5 10.3 13.4 14.2 -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C 2.0V(3) 2.0V(3) 2.0V(3) 2.5V(3) 2.5V(3) 2.5V(3) 3.3V(4) 3.3V(4) 3.3V(4) RTCC Timer1 w/Low-Power Crystal (SOCSEL<1:0> 01): RTCC ITI32(5) 3.3V(4) 2.5V(3) RTCC Timer1 w/32 Crystal: RTCC ITI32(5) 2.0V(3)
Data Typical column 3.3V, 25°C unless otherwise stated. Parameters design guidance only tested. Base measured with peripherals clocks shut down. I/Os configured inputs pulled high. WDT, etc., switched off. On-chip voltage regulator disabled (DISVREG tied VDD). On-chip voltage regulator enabled (DISVREG tied VSS). Low-Voltage Detect (LVD) Brown-out Detect (BOD) enabled. current additional current consumed when module enabled. This current should added base current.
2009 Microchip Technology Inc.
DS80470B-page
PIC24FJ64GA004 FAMILY
Module: Electrical Characteristics
Table 26-10 Section 26.1 Characteristics" been amended expand definition TVREG, well definition VBG. updated version shown below. Changes shown bold, bold from original been removed clarity.
TABLE 26-10: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40°C +125°C (unless otherwise stated) Param Symbol VRGOUT CEFC Characteristics Regulator Output Voltage Band Reference Voltage External Filter Capacitor Value 1.23 Units Series resistance recommended; required. POR, when VREGS VREGS WUTSEL<1:0> 01(1) VREGS WUTSEL<1:0> 11(2) DISVREG Comments
TVREG
Voltage Regulator Start-up Time
TPWRT Note
Available only devices with major silicon revision level later (DEVREV register value 3042h greater). WUTSEL Configuration bits setting applicable only devices with major silicon revision level later. This specification also applies devices prior revision level whenever VREGS
Module: Electrical Characteristics
Section 26.1 Characteristics", values parameters DO20 DO26 (Output Maximum Voltage) reported incorrectly. correct values shown
extract from Table 26-8 below. Changes shown bold, bold from original been removed clarity.
TABLE 26-8:
CHARACTERISTICS: OUTPUT SPECIFICATIONS (PARTIAL REPRESENTATION)
Standard Operating Conditions: 2.0V 3.6V (unless otherwise stated) Operating temperature -40°C +85°C Industrial -40°C +125°C Extended Typ(1) Units Conditions
CHARACTERISTICS Param
Characteristic Output High Voltage pins pins
DO20 DO26 Note
1.65 1.65
-3.0 3.6V -1.0 2.0V -2.5 3.6V, 125°C -0.5 2.0V, 125°C
Data "Typ" column 25°C unless otherwise stated. Parameters design guidance only tested.
DS80470B-page
2009 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
Module:
following section appended Section "Inter-integrated Circuit (I2C)".
Section 15.5 Acknowledge Status
both Master Slave modes, ACKSTAT only updated when transmitting data resulting reception NACK from another device. check state ACKSTAT when receiving data, either Slave Master. Reading ACKSTAT after receiving address data bytes returns invalid result.
2009 Microchip Technology Inc.
DS80470B-page
PIC24FJ64GA004 FAMILY
APPENDIX DOCUMENT REVISION HISTORY
Document (7/2009) Amended existing silicon revision joint revision A3/A4. Added silicon issue (UART) silicon revision A3/A4. Revised issue (I2C) with additional information, differentiating erroneous behavior from misinterpretation state. Added data sheet clarification (I2C). Document (5/2009) Initial release this document; issued silicon revision Incorporates following current historical silicon issues from revision (JTAG) (Low-Voltage Detect) (Core) (A/D) (I2C I2C1 Line State) 11-16 (UART) (Output Compare) 18-20 (SPI) 21-22 (I/O Ports) (JTAG) (RTCC) 25-26 (I2C) (UART) (I/O Peripheral Select) (UART UERIF Interrupt) (UART FIFO Error Flags) (Core BOR) (Core Instruction Set) (Memory Program Space Visibility) (RTCC) (SPI Master Mode) (I2C Master Mode) (I2C Slave Mode) (I2C) (UART) (Oscillator SOSC) (Voltage Regulator) (Core Code Protection) (SPI) (Core)
data sheet clarifications: Includes Data Sheet Clarifications (Electrical Characteristics), (10-Bit High-Speed Converter), (I/O Ports), (Oscillator Configuration), (Special Features) (Electrical Characteristics). This document replaces these errata documents: "PIC24FJ64GA004 Family Revision Silicon Errata" (DS80316) "PIC24FJ64GA004 Family Revision Silicon Errata" (DS80384) "PIC24FJ64GA004 Family Data Sheet Errata" (DS80333)
DS80470B-page
2009 Microchip Technology Inc.
Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
Code protection constantly evolving. Microchip committed continuously improving code protection features products. Attempts break Microchip's code protection feature violation Digital Millennium Copyright Act. such acts allow unauthorized access your software other copyrighted work, have right relief under that Act.
Information contained this publication regarding device applications like provided only your convenience superseded updates. your responsibility ensure that your application meets with your specifications. MICROCHIP MAKES REPRESENTATIONS WARRANTIES KIND WHETHER EXPRESS IMPLIED, WRITTEN ORAL, STATUTORY OTHERWISE, RELATED INFORMATION, INCLUDING LIMITED CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY FITNESS PURPOSE. Microchip disclaims liability arising from this information use. Microchip devices life support and/or safety applications entirely buyer's risk, buyer agrees defend, indemnify hold harmless Microchip from damages, claims, suits, expenses resulting from such use. licenses conveyed, implicitly otherwise, under Microchip intellectual property rights.
Trademarks Microchip name logo, Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC UNI/O registered trademarks Microchip Technology Incorporated U.S.A. other countries. FilterLab, Hampshire, HI-TECH Linear Active Thermistor, MXDEV, MXLAB, SEEVAL Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2009, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
2009 Microchip Technology Inc.
DS80470B-page
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