PIC24HJ12GP201/202 Family Silicon Errata Data Sheet Clarification

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PIC24HJ12GP201/202 Family Silicon Errata Data Sheet Clarification

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PIC24HJ12GP201/202
PIC24HJ12GP201/202 Family Silicon Errata Data Sheet Clarification
PIC24HJ12GP201/202 family devices that have received conform functionally current Device Data Sheet (DS70282C), except anomalies described this document. silicon issues discussed following pages silicon revisions with Device Revision listed Table silicon issues summarized Table errata described this document will addressed future revisions PIC24HJ12GP201/202 silicon. Note: This document summarizes silicon errata issues from revisions silicon, previous well current. Only issues indicated last column Table apply current silicon revision (A4). example, identify silicon revision level using MPLAB conjunction with MPLAB PICkit3: Using appropriate interface, connect device MPLAB programmer/debugger PICkit From main menu MPLAB IDE, select Configure>Select Device, then select target part number dialog box. Select MPLAB hardware tool (Debugger>Select Tool). Perform "Connect" operation device (Debugger>Connect). Depending development tool used, part number Device Revision value appear Output window. Note: unable extract silicon revision level, please contact your local Microchip sales office assistance.
Data Sheet clarifications corrections start page following discussion silicon issues. silicon revision level identified using current version MPLAB® Microchip's programmers, debuggers emulation tools, which available Microchip corporate site (www.microchip.com).
Device Revision values various PIC24HJ12GP201/202 silicon revisions shown Table
TABLE
SILICON DEVREV VALUES
Part Number Device ID(1) 0x080A 0x080B Revision Silicon Revision(2) 0x3001 0x3002 0x3003
PIC24HJ12GP201 PIC24HJ12GP202 Note
Device Revision (DEVID DEVREV) located last implemented addresses program memory. Refer "dsPIC33F/PIC24H Flash Programming Specification" (DS70152) detailed information Device Revision your specific device.
2009 Microchip Technology Inc.
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PIC24HJ12GP201/202
TABLE
Module JTAG UART UART UART UART UART UART
SILICON ISSUE SUMMARY
Feature Flash Programming High-Speed Mode High-Speed Mode Auto-Baud Auto-Baud Auto-Baud High-Speed Mode Mode Idle Mode Item Number Issue Summary JTAG programming does work. UART receptions corrupted Baud Rate Generator (BRG) mode. auto-baud feature calculate correct baud rate when mode. With auto-baud feature selected, Sync Break character (0x55) loaded into FIFO data. auto-baud feature measures baud rate inaccurately certain baud rate clock speed combinations. When auto-baud detected, receive interrupt occur twice. When UART mode (BRGH using Stop bits (STSEL sample first Stop instead second one. baud clock signal BCLK present only when module transmitting. clock failure occurs when device Idle mode, oscillator failure trap does vector Trap Service Routine (TSR). SPIxCON1 DISSCK does influence port functionality. I2CSTAT only cleared with 16-bit operation, corrupted with 1-bit 8-bit operations I2CSTAT. When module configured 10-bit addressing using same address bits (A10 other devices, bits work expected. Revision devices marked extended temperature range devices only support industrial temperature range (I). UART error interrupt occur, occur incorrect time, multiple errors occur during short period time. When UART module operating 8-bit mode (PDSEL using IrDA® encoder/decoder (IREN module incorrectly transmits data payload 00h. When VREGS (RCON<8>) logic `0', device Reset higher sleep current observed. address error trap occurs certain addressing modes when accessing first four bytes page. When module configured 10-bit slave with address 0x102, I2CxRCV register content lower address byte 0x01 rather than 0x02. With module enabled, port bits external interrupt input functions any) associated with pins reflect actual digital logic levels pins. Affected Revisions(1)
UART Interrupt Controller I2C
SCKx Pins Writes
10-bit Addressing Extended Temperature Interrupts
Product Identification UART
UART
Mode
Internal Voltage Regulator Operations
Sleep Mode
10-bit Addressing
Note
Only those issues indicated last column apply current silicon revision.
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2009 Microchip Technology Inc.
PIC24HJ12GP201/202
TABLE
Module
SILICON ISSUE SUMMARY (CONTINUED)
Feature 10-bit Addressing EXCH Instruction Break Character Generation Item Number Issue Summary 10-bit slave does flag load I2CxRCV register address match Least Significant bits (LSbs) address same 7-bit reserved addresses. After ACKSTAT when receiving NACK, cleared reception Start Stop bit. EXCH instruction does execute correctly enabled. UART module will generate back-to-back Break characters. Affected Revisions(1)
UART
Note
Only those issues indicated last column apply current silicon revision.
2009 Microchip Technology Inc.
DS80466B-page
PIC24HJ12GP201/202
Silicon Errata Issues
Note: This document summarizes silicon errata issues from revisions silicon, previous well current. Only issues indicated shaded column following tables apply current silicon revision (A4).
Module: UART
With auto-baud feature selected, Sync Break character (0x55) loaded into FIFO data. Work around prevent Sync Break character from being loaded into FIFO, load UxBRG register with either 0x0000 0xFFFF prior enabling auto-baud feature (ABAUD Affected Silicon Revisions
Module: JTAG
JTAG programming does work. Work around None. Affected Silicon Revisions
Module: UART
auto-baud feature miscalculate certain baud rate clock speed combinations, resulting value that greater than less than expected value This result reception transmission failures. Work around Test auto-baud rate various clock speed baud rate combinations that would used application. inaccurate value generated, manually correct baud rate user software. Affected Silicon Revisions
Module: UART
UART receptions corrupted Baud Rate Generator mode (BRGH Work around baud rate option (BRGH adjust baud rate accordingly. Affected Silicon Revisions
Module: UART
auto-baud feature calculate correct baud rate when High Baud Rate Enable bit, BRGH, set. With BRGH set, baud rate calculation used same Work around auto-baud feature needed, Baud Rate mode clearing BRGH bit. Affected Silicon Revisions
Module: UART
When auto-baud detected, receive interrupt occur twice. first interrupt occurs beginning Start second after reception Sync field character. Work around extra interrupt detected, ignore additional interrupt. Affected Silicon Revisions
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2009 Microchip Technology Inc.
PIC24HJ12GP201/202
Module: UART
When UART mode (BRGH using Stop bits (STSEL sample first Stop instead second one. This issue does affect other UART configurations. Work around baud rate option (BRGH adjust baud rate accordingly. Affected Silicon Revisions
Module: Interrupt Controller
clock failure occurs when device Idle mode, oscillator failure trap does vector Trap Service Routine. Instead, device will simply wake-up from Idle mode continue code execution Fail-Safe Clock Monitor (FSCM) enabled. Work around Whenever device wakes from Idle (assuming FSCM enabled) user software should check state OSCFAIL (INTCON1<1>) determine whether clock failure occurred, then perform appropriate clock switch operation. Regardless, Trap Service Routine must included user application. Affected Silicon Revisions
Module: UART
When UART configured interface operations (UxMODE<9:8> 11), baud clock signal BCLK present only when module transmitting. idle other times. Work around Configure output compare modules generate required baud clock signal when UART receiving data Idle state. Affected Silicon Revisions
Module:
Setting DISSCK SPIxCON1 register does allow user application General Purpose pin. Work around None. Affected Silicon Revisions
Module:
I2CSTAT cleared only with 16-bit operation, corrupted with 1-bit 8-bit operations I2CSTAT. Work around 16-bit operations clear BCL. Affected Silicon Revisions
2009 Microchip Technology Inc.
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PIC24HJ12GP201/202
Module:
there devices bus, them acting Master receiver other Slave transmitter. both devices configured 10-bit addressing mode, have same value bits their addresses, then when Slave select address sent from Master, both Master Slave acknowledge When Master sends read operation, both Master Slave enter into Read mode both them transmit data. resultant data will ANDing transmissions. Work around devices, addresses well bits should different. Affected Silicon Revisions
Module: UART
When UART operating 8-bit mode (PDSEL using IrDA encoder/decoder (IREN module incorrectly transmits data payload 00h. Work around None. Affected Silicon Revisions
Module: Internal Voltage Regulator
When VREGS (RCON<8>) logic `0', device Reset higher sleep current observed. Work around Ensure VREGS (RCON<8>) logic device Sleep mode operation. Affected Silicon Revisions
Module: Product Identification
Revision devices marked extended temperature range devices only support industrial temperature range (I). Work around Revision newer devices marked extended temperature range devices. Affected Silicon Revisions
Module: UART
UART error interrupt occur, occur incorrect time, multiple errors occur during short period time. Work around Read error flags UxSTA register whenever byte received verify error status. most cases, these bits will correct, even UART error interrupt fails occur. Affected Silicon Revisions
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2009 Microchip Technology Inc.
PIC24HJ12GP201/202
Module: Operations
address error trap occurs certain addressing modes when accessing first four bytes page. This only occurs when using following addressing modes: MOV.D Register Indirect Addressing (word byte mode) with pre/post-decrement Work around perform accesses first four bytes using above addressing modes. applications using language, MPLAB version 3.11 higher, provides following command-line switch that implements work around erratum. -merrata=psv_trap Refer readme.txt file MPLAB v3.11 tool suite further details. Affected Silicon Revisions
Module:
10-bit Addressing mode, some address matches don't flag load receive register, I2CxRCV, lower address byte matches reserved addresses. particular, these include addresses with form XX0000XXXX XX1111XXXX, with following exceptions: 001111000X 011111001X 101111010X 111111011X
Work around Ensure that lower address byte 10-bit Addressing mode does match 7-bit reserved addresses. Affected Silicon Revisions
Module:
When module operating either Master Slave mode, after ACKSTAT when receiving NACK, cleared reception Start Stop bit. Work around Store value ACKSTAT immediately after receiving NACK. Affected Silicon Revisions
Module:
When module configured 10-bit slave with address 0x102, I2CxRCV register content lower address byte 0x01 rather than 0x02; however, module acknowledges both address bytes. Work around None. Affected Silicon Revisions
Module:
With module enabled, port bits external interrupt input functions any) associated with pins reflect actual digital logic levels pins. Work around and/or pins need polled, these pins should connected other port pins order read correctly. This issue does affect operation module. Affected Silicon Revisions
2009 Microchip Technology Inc.
DS80466B-page
PIC24HJ12GP201/202
Module:
EXCH instruction does execute correctly enabled. Work around writing source code assembly, recommended work around replace: EXCH Wsource, Wdestination with: PUSH Wdestination Wsource, Wdestination Wsource using MPLAB compiler, specify compiler option: -merrata=exch (Project Build Options Projects MPLAB Alternate Settings). Affected Silicon Revisions
Module: UART
UART module will generate consecutive break characters. Trying perform back-toback Break character transmission will cause UART module transmit dummy character used generate first Break character instead transmitting second Break character. Break characters generated correctly they followed non-Break character transmission. Work around None. Affected Silicon Revisions
DS80466B-page
2009 Microchip Technology Inc.
PIC24HJ12GP201/202
Data Sheet Clarifications
following typographic corrections clarifications noted latest version device data sheet (DS70282C): Note: Corrections shown bold. Where possible, original bold text formatting been removed clarity.
data sheet clarifications this time.
2009 Microchip Technology Inc.
DS80466B-page
PIC24HJ12GP201/202
APPENDIX REVISION HISTORY
Document (4/2009) Initial release this document; issued revision silicon. Includes silicon issues (JTAG), (UART), (Interrupt Controller), (SPI), 11-12 (I2C), (Product Identification), (UART), (UART), (Internal Voltage Regulator), (PSV Operations), 18-21 (I2C) (CPU). This document replaces following errata document: DS80326, "PIC24HJ12GP201/202 Rev. A2/A3/A4 Silicon Errata" Document (8/2009) Added silicon issue (UART).
DS80466B-page
2009 Microchip Technology Inc.
Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
Code protection constantly evolving. Microchip committed continuously improving code protection features products. Attempts break Microchip's code protection feature violation Digital Millennium Copyright Act. such acts allow unauthorized access your software other copyrighted work, have right relief under that Act.
Information contained this publication regarding device applications like provided only your convenience superseded updates. your responsibility ensure that your application meets with your specifications. MICROCHIP MAKES REPRESENTATIONS WARRANTIES KIND WHETHER EXPRESS IMPLIED, WRITTEN ORAL, STATUTORY OTHERWISE, RELATED INFORMATION, INCLUDING LIMITED CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY FITNESS PURPOSE. Microchip disclaims liability arising from this information use. Microchip devices life support and/or safety applications entirely buyer's risk, buyer agrees defend, indemnify hold harmless Microchip from damages, claims, suits, expenses resulting from such use. licenses conveyed, implicitly otherwise, under Microchip intellectual property rights.
Trademarks Microchip name logo, Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC UNI/O registered trademarks Microchip Technology Incorporated U.S.A. other countries. FilterLab, Hampshire, HI-TECH Linear Active Thermistor, MXDEV, MXLAB, SEEVAL Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2009, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
2009 Microchip Technology Inc.
DS80466B-page
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03/26/09
DS80466B-page
2009 Microchip Technology Inc.

PIC24HJ12GP201/202 Family Silicon Errata Data Sheet Clarification

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