PIC24FJ64GA004 Family Data Sheet Errata PIC24FJ64GA004 Family Dev
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PIC24FJ64GA004 FAMILY
PIC24FJ64GA004 Family Data Sheet Errata
PIC24FJ64GA004 Family Device Data Sheet (DS39881C), following clarifications corrections should noted. silicon issues related these devices will reported separate silicon errata. Please check Microchip site existing issues.
Module: Electrical Characteristics
Section 26.1 Characteristics", values parameters DC51b DC51c (Idle Current) reported incorrectly. correct values shown extract from Table 26-5 below (changes bold).
TABLE 26-5:
CHARACTERISTICS: IDLE CURRENT (IIDLE) (PARTIAL REPRESENTATION)
Standard Operating Conditions: 2.0V 3.6V (unless otherwise stated) Operating temperature -40°C +85°C Industrial -40°C +125°C Extended Units Conditions
CHARACTERISTICS Parameter
Typical(1)
Idle Current (IIDLE): Core Off, Clock Base Current, Bits Set(2) DC51 DC51a DC51b DC51c Note -40°C +25°C +85°C +125°C 2.0V(3) LPRC kHz)
Data "Typical" column 3.3V, 25°C unless otherwise stated. Parameters design guidance only tested. Base IIDLE current measured with core off, clock modules Peripheral Module Disable (PMD) bits set. On-chip voltage regulator disabled (DISVREG tied VDD).
2008 Microchip Technology Inc.
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Module: 10-Bit High-Speed Converter
AD1CON3 register been changed reflect current operation Clock Selection Bits (ADSC7:ADSC0). changes shown Register 20-3, below (updated text bold; bold text original removed clarity).
REGISTER 20-3:
R/W-0 ADRC R/W-0 ADCS7 Legend: Readable Value
AD1CON3: CONTROL REGISTER
R/W-0 SAMC4 R/W-0 SAMC3 R/W-0 SAMC2 R/W-0 SAMC1 R/W-0 SAMC0
R/W-0 ADCS6
R/W-0 ADCS5
R/W-0 ADCS4
R/W-0 ADCS3
R/W-0 ADCS2
R/W-0 ADCS1
R/W-0 ADCS0
Writable
Unimplemented bit, read cleared unknown
ADRC: Conversion Clock Source internal clock Clock derived from system clock Unimplemented: Read SAMC4:SAMC0: Auto-Sample Time bits 11111 00001 00000 (not recommended) ADCS7:ADCS0: Conversion Clock Select bits 11111111 Reserved 01000000 00111111 00000001 00000000
14-13 12-8
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2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
Module: Ports
following section accompanying table have been added immediately after existing Section 9.2.1 "I/O Port Write/Read Timing". current Table subsequent tables sequentially renumbered.
Module: Oscillator Configuration
following section been appended Section "Oscillator Configuration". Additional changes device data sheet related this issue presented Clarification (Special Features).
9.2.2
ANALOG INPUT PINS VOLTAGE CONSIDERATIONS
7.5.1
Note:
Secondary Oscillator Features
SECONDARY OSCILLATOR LOW-POWER OPERATION
This feature implemented only PIC24FJ64GA004 family devices with major silicon revision level later (DEVREV register value 3042h greater).
voltage tolerance pins used device inputs dependent pin's input function. Pins that used digital only inputs able handle voltages 5.5V, level typical digital logic circuits. contrast, pins that also have analog input functions kind only tolerate voltages VDD. Voltage excursions beyond these pins always avoided. Table summarizes input capabilities. Refer Section 26.1 Characteristics" more details.
TABLE 9-1:
Port PORTA<4:0> PORTB<15:12> PORTB<4:0> PORTC<2:0>(1) PORTA<10:7>(1) PORTB<11:5> PORTC<9:3>(1) Note
INPUT VOLTAGE LEVELS
Tolerated Input Description Only input levels tolerated.
Secondary Oscillator (SOSC) operate distinct levels power consumption based device configuration. Low-Power mode, oscillator operates low-gain, low-power state. default, oscillator uses higher gain setting, therefore, requires more power. Secondary Oscillator Mode Selection bits, SOSCSEL1:SOSCSEL0 (CW2<12:11>), determine oscillator's power mode. When Low-Power mode used, care must taken design layout SOSC circuit ensure that oscillator will start oscillate properly. lower gain this mode makes SOSC more sensitive noise requires longer start-up time.
5.5V
Tolerates input levels above VDD, useful most standard logic.
7.5.2
OSCILLATOR LAYOUT
Unavailable 28-pin devices.
count devices, such those PIC24FJ64GA004 family, pinout limitations, SOSC more susceptible noise than other PIC24F devices. Unless proper care taken design layout SOSC circuit, possible inaccuracies introduced into oscillator's period. general, crystal circuit connections should short possible. also good practice surround crystal circuit with ground loop ground plane. more detailed information crystal circuit design, please refer "PIC24F Family Reference Manual", Section "Oscillator" (DS39700) Microchip Application Notes AN826, "Crystal Oscillator Basics Crystal Selection rfPIC® PICmicro® Devices" (DS00826) AN849, "Basic PICmicro® Oscillator Design" (DS00849).
2008 Microchip Technology Inc.
DS80333D-page
PIC24FJ64GA004 FAMILY
Module: Special Features
existing version Section 23.2.5 "Voltage Regulator Standby Mode" modified with following additional material. Changes shown bold. Additional changes device data sheet related this issue presented Clarification (Special Features) Clarification (Electrical Specifications).
Module: Special Features
Register 23-2 (CW2: Flash Configuration Word been amended SOSCEL WUTSEL Configuration bits. changes shown abbreviated Register 23-2 that follows. Changes shown bold, bold from original been removed clarity. Note: descriptions bits through their corresponding rows unchanged original. They have been removed here sake brevity.
23.2.5
VOLTAGE REGULATOR STANDBY MODE
When enabled, on-chip regulator always consumes small incremental amount current over IDD/IPD, including when device Sleep mode, even though core digital logic does require power. provide additional savings applications where power resources critical, regulator automatically places itself into Standby mode whenever device goes into Sleep mode. This feature controlled VREGS (RCON<8>). default, this cleared which enables Standby mode. select PIC24FJ64GA004 family devices, time required regulator wake-up from Standby mode controlled WUTSEL1:WUTSEL0 Configuration bits (CW2<14:13>). default wake-up time devices Where WUTSEL Configuration bits implemented, fast wake-up option also available. When WUTSEL1:WUTSEL0 regulator wake-up time Note: This feature implemented only PIC24FJ64GA004 family devices with major silicon revision level later (DEVREV register value 3042h greater).
When regulator's Standby mode turned (VREGS Flash program memory stays powered Sleep mode device wake-up less than When VREGS set, power consumption while Sleep mode, will approximately higher than power consumption when regulator allowed enter Standby mode.
DS80333D-page
2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 23-2:
R/PO-1 IESO R/PO-1 FCKSM1
CW2: FLASH CONFIGURATION WORD (PARTIAL REPRESENTATION)
R/PO-1 FNOSC0 R/PO-1 POSCMD0
R/PO-1 R/PO-1 R/PO-1 R/PO-1 WUTSEL1(1) WUTSEL0(1) SOSCSEL1(1) SOSCSEL0(1)
R/PO-1 FNOSC2
R/PO-1 FNOSC1
R/PO-1 FCKSM0
R/PO-1 OSCIOFCN
R/PO-1 IOL1WAY
R/PO-1 I2C1SEL
R/PO-1 POSCMD1
Legend: Readable Program-once Value when device unprogrammed 23-16
Reserved Unimplemented bit, read cleared
14-13
12-11
10-8
Unimplemented: Read IESO: Internal External Switchover IESO mode (Two-Speed Start-up) enabled IESO mode (Two-Speed Start-up) disabled WUTSEL1:WUTSEL0: Voltage Regulator Standby Mode Wake-up Time Select bits(1) Default regulator start-up time used Fast regulator start-up time used Reserved; SOSCSEL1:SOSCSEL0: Secondary Oscillator Power Mode Select bits(1) Default (high drive-strength) mode Low-Power (low drive-strength) mode Reserved; FNOSC2:FNOSC0: Initial Oscillator Select bits POSCMD1:POSCMD0: Primary Oscillator Configuration bits Primary oscillator disabled Oscillator mode selected Oscillator mode selected Oscillator mode selected These bits implemented only devices with major silicon revision level later (DEVREV register value 3042h greater). Refer Section 27.0 "Packaging Information" location interpretation product date codes.
Note
2008 Microchip Technology Inc.
DS80333D-page
PIC24FJ64GA004 FAMILY
Module: Electrical Characteristics
Table 26-6 been amended following information (added text bold; bold text original removed clarity).
TABLE 26-6:
CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 2.0V 3.6V (unless otherwise stated) Operating temperature -40°C +85°C Industrial -40°C +125°C Extended Units
CHARACTERISTICS Parameter Typical(1)
Conditions
Power-Down Current (IPD): Bits Set, VREGS DC62 DC62a DC62b DC62j DC62c DC62d DC62e DC62k DC62f DC62g DC62h DC62i DC63 DC63a DC63b DC63c DC63d DC63e DC63f DC63g DC63h Note 12.5 10.3 13.4 14.2 -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C
2.0V(3)
2.5V(3)
RTCC Timer1 w/32 Crystal: RTCC ITI32(5)
3.3V(4)
2.0V(3) 2.0V(3) 2.0V(3) 2.5V(3) 2.5V(3) 2.5V(3) 3.3V(4) 3.3V(4) 3.3V(4) RTCC Timer1 w/Low-Power Crystal (SOCSEL<1:0> 01): RTCC ITI32(5)
Data Typical column 3.3V, 25°C unless otherwise stated. Parameters design guidance only tested. Base measured with peripherals clocks shut down. I/Os configured inputs pulled high. WDT, etc., switched off. On-chip voltage regulator disabled (DISVREG tied VDD). On-chip voltage regulator enabled (DISVREG tied VSS). Low-Voltage Detect (LVD) Brown-out Detect (BOD) enabled. current additional current consumed when module enabled. This current should added base current.
DS80333D-page
2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
Module: Electrical Specifications
Table 26-10 Section 26.1 Specifications" been amended expand definition TVREG, well definition VBG. updated version shown below. Changes shown bold, bold from original been removed clarity.
TABLE 26-10: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40°C +125°C (unless otherwise stated) Param Symbol VRGOUT CEFC Characteristics Regulator Output Voltage Band Reference Voltage External Filter Capacitor Value 1.23 Units Series resistance recommended; required. POR, when VREGS VREGS WUTSEL1:WUTSEL0 01(1) VREGS WUTSEL1:WUTSEL0 11(2) DISVREG Comments
TVREG
Voltage Regulator Start-up Time
TPWRT Note
Available only devices with major silicon revision level later (DEVREV register value 3042h greater). WUTSEL Configuration setting applicable only devices with major silicon revision level later. This specification also applies devices prior revision level whenever VREGS
Module: Electrical Characteristics
Section 26.1 Characteristics", values parameters DO20 DO26 (Output Maximum Voltage) reported incorrectly. correct values shown
extract from Table 26-8 below. Changes shown bold, bold from original been removed clarity.
TABLE 26-8:
CHARACTERISTICS: OUTPUT SPECIFICATIONS (PARTIAL REPRESENTATION)
Standard Operating Conditions: 2.0V 3.6V (unless otherwise stated) Operating temperature -40°C +85°C Industrial -40°C +125°C Extended Typ(1) Units Conditions
CHARACTERISTICS Param
Characteristic Output High Voltage pins pins
DO20 DO26 Note
1.65 1.65
-3.0 3.6V -1.0 2.0V -2.5 3.6V, 125°C -0.5 2.0V, 125°C
Data "Typ" column 25°C unless otherwise stated. Parameters design guidance only tested.
2008 Microchip Technology Inc.
DS80333D-page
PIC24FJ64GA004 FAMILY
REVISION HISTORY
Document (7/2007) Initial release this document. Includes Data Sheet Clarification (Special Functions Registers), (Pin Diagrams), (Memory Organization), (Flash Program Memory), (Oscillator Configuration), (I/O Ports), 7-11 (Output Compare), 12-13 (Special Peripheral Interface), 14-15 (Inter-Intergrated Circuit- I2CTM), 16-18 (Universal Asynchronous Receiver Transmitter UART), 19-20 (10-Bit High-Speed Converter), 21-22 (Special Features) 23-26 (Electrical Characteristics). Document (1/2008) Removed previous Data Sheet Clarifications added Data Sheet Clarification (Electrical Characteristics). Document (7/2008) Added Data Sheet Clarifications (10-Bit HighSpeed Converter), (I/O Ports), (Oscillator Configuration), (Special Features) (Electrical Specifications). Document (10/2008) Added Data Sheet Clarifications (Electrical Specifications).
DS80333D-page
2008 Microchip Technology Inc.
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