PIC24HJXXXGPX06/X08/X10 Rev. A2/A3/A4 Silicon Errata PIC24H (Rev.
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PIC24HJXXXGPX06/X08/X10
PIC24HJXXXGPX06/X08/X10 Rev. A2/A3/A4 Silicon Errata
PIC24H (Rev. A2/A3/A4) devices received were found conform specifications functionality described following documents: DS70175 "PIC24H Family Data Sheet" DS70157 "dsPIC30F/33F Programmer's Reference Manual" DS70046 "dsPIC30F Family Reference Manual" exceptions specifications documents listed above described this section. specific devices which these exceptions described listed below: PIC24HJ64GP206 PIC24HJ64GP210 PIC24HJ64GP506 PIC24HJ64GP510 PIC24HJ128GP206 PIC24HJ128GP210 PIC24HJ128GP306 PIC24HJ128GP310 PIC24HJ128GP506 PIC24HJ128GP510 PIC24HJ256GP206 PIC24HJ256GP210 PIC24HJ256GP610
Silicon Errata Summary
following list summarizes errata described further detail through remainder this document: Doze Mode When Doze mode enabled, writes peripheral cause other updates that register cease function duration current clock cycle. 12-bit Analog-to-Digital Module Converter (ADC)
this revision silicon, 12-bit module INL, signal acquisition time parameters within published data sheet specifications. 10-bit Module this revision silicon, 10-bit module DNL, conversion speed signal acquisition time parameters within published data sheet specifications. Module: Interaction with EXCH Instruction EXCH instruction does execute correctly when operands contains value equal address DMAC SFRs. DISI Instruction DISI instruction will disable interrupts DISI instruction executed same instruction cycle that DISI counter decrements zero. Output Compare Module Mode output compare module will miss compare event when duty cycle register value updated from 0x0000 0x0001. Module Frame Master Mode module will fail generate frame synchronization pulses Frame Master mode FRMDLY Module Slave Select Mode module Slave Select functionality will work correctly. Module does have effect when module configured prescale factor Master mode.
PIC24H Rev. A2/A3/A4 silicon identified performing "Reset Connect" operation device using MPLAB® with MPLAB v7.40 later. output window will show successful connection device specified Configure>Select Device. resulting DEVREV register values Rev. A2/A3/A4 silicon 0x3002, 0x3004, 0x3040, respectively. errata described this document will addressed future revisions silicon.
2008 Microchip Technology Inc.
DS80280G-page
PIC24HJXXXGPX06/X08/X10
ECANModule ECAN transmissions incorrect multiple transmit buffers simultaneously queued transmission. ECAN Module Under specific conditions, first five bits transmitted identifier match value transmit buffer register. ECAN Module Loopback Mode ECAN module (ECAN1 ECAN2) does function correctly Loopback mode. I2CModule Collision Status does when collision occurs during Restart Stop event. INT0, Sleep/Idle Mode event triggers from INT0 will wake-up device from Sleep Idle mode SMPI bits non-zero. Doze Mode Traps address error trap, stack error trap, math error trap error trap will wake-up device from Doze mode. JTAG Programming JTAG programming does work. UART With parity option enabled, parity error occur Baud Rate Generator (BRG) contains value. UART Receive Buffer Overrun Error Status before UART FIFO overflowed. UART UART receptions corrupted mode. UART UTXISEL0 always read back zero. UART auto-baud feature calculate correct baud rate when mode. UART With auto-baud feature selected, sync break character (0x55) loaded into FIFO data. Module write collision does prevent transmit register from being written. Module ACKSTAT only reflects received ACK/NACK status Master transmissions, Slave transmissions. Module Status does slave write transmit register. Traps Idle Mode clock failure occurs when device Idle mode, oscillator failure trap does vector Trap Service Routine (TSR). MCLR Wake-up from Sleep Mode MCLR wake-up from Sleep mode does wait on-chip voltage regulator power-up. ECAN Module C1RXOVF2 C2RXOVF2 registers always read back 0x0000. Oscillator Internal accuracy parameters within published data sheet specifications. Module SPI1 functionality (U1RX/SDI1/RF2) erroneously enabled SPI2 module. UART auto-baud feature measures baud rate inaccurately certain baud rate clock speed combinations. Device Register content Device register changes from factory programmed value. Module data transfers that active Single-Shot mode while device Sleep Idle mode result more data transfers than expected. Doze Mode Traps error trap generated when device Doze mode. Output Compare Module Dual Compare Match mode, output reset when OCxR OCxRS registers loaded with values having difference UART When UART mode (BRGH using Stop bits (STSEL sample first Stop instead second one. UART When auto-baud detected, receive interrupt occur twice.
DS80280G-page
2008 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
NULL Data Peripheral Write mode channel does function. request Fault condition does generate error trap. channel writes additional NULL value peripheral register. REPEAT Instruction instruction executed inside REPEAT loop that produces Read-After-Write stall condition, results instruction being executed fewer times than intended. Oscillator certain values TUN<5:0> bits (OSCTUN<5:0>), resultant frequencies incorrect. UART Module baud clock signal BCLK present only when module transmitting. Module SPIxCON1 DISSCK does influence port functionality. Module I2CSTAT cleared only with 16-bit operation corrupted with 1-bit 8-bit operations I2CSTAT. Module: 10-bit addressing mode When module configured 10-bit addressing using same address bits (A10 other devices, bits work expected. Module: 10-bit Addressing Mode When module configured 10-bit slave with address 0x102, I2CxRCV register content lower address byte 0x01 rather than 0x02. Module With module enabled, PORT bits external Interrupt Input functions any) associated with pins will reflect actual digital logic levels pins. Module: 10-bit Addressing Mode 10-bit slave does flag load I2CxRCV register address match Least Significant bits address same 7-bit reserved addresses. Internal Voltage Regulator When VREGS (RCON<8>) logic `0', higher sleep current observed. ECAN Module ECAN module does generate event interrupt when coming Disable mode wake-up activity even WAKIE CiINTE register set. Operations address error trap occurs certain addressing modes when accessing first four bytes page. UART (UxE Interrupt) UART error interrupt occur, occur incorrect time, multiple errors occur during short period time. UART Module When UART module operating 8-bit mode (PDSEL using IrDA® encoder/decoder (IREN module incorrectly transmits data payload 00h. following sections describe errata work around these errata, where they apply.
2008 Microchip Technology Inc.
DS80280G-page
PIC24HJXXXGPX06/X08/X10
Module: Doze Mode
Enabling Doze mode slows down allows peripherals full speed. When clock slowed down enabling Doze mode (CLKDIV<11> writes peripheral cause other updates that register cease function duration current clock cycle. This only issue attempts write same register peripheral while Doze mode. instance, module active Doze mode enabled, main program should avoid writing ADCCONx registers because these registers being used module. does make writes before module does, then attempts module write these registers will fail. Work around Doze mode, avoid writing code that will modify SFRs which written enabled peripherals.
DS80280G-page
2008 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
Module: 12-bit
When module configured 12-bit operation, specifications data sheets met. Work around Implement module 11-bit with maximum conversion rate ksps. specifications Table reflect 11-bit operation. source impedance recommended ohms sample time recommended ensure compatibility future enhanced modules. Missing codes possible every codes. When used 10-bit ADC, Least Significant Bytes (LSBs), with missing codes. Maximum conversion rate ksps.
TABLE
Param AD17 AD20a AD21a AD22a AD23a AD24a AD21aa AD22aa AD23aa AD24aa AD33a AD34a AD56a AD57a
PERFORMANCE (11-BIT OPERATION)
Symbol GERR EOFF GERR EOFF FNYQ ENOB FCNV TSAMP -1.5 -1.5 Typical bits 10.4 Units Bits Bits ksps Conditions 12-bit
Accuracy Measurements taken with External VREF+/VREF-
Accuracy Measurements taken with Internal VREF+/VREF-
Dynamic Performance
Conversion Rate
2008 Microchip Technology Inc.
DS80280G-page
PIC24HJXXXGPX06/X08/X10
Module: 10-bit
When module configured 10-bit operation, specifications data sheet operation above ksps. ksps, module meets specifications except Gain Offset parameters AD23bb AD24bb. ksps operation, module specifications shown Table Work around None. Future versions silicon will support performance stated data sheet.
TABLE
Param AD17 AD20b AD21b AD22b AD23b AD24b AD21bb AD22bb AD23bb AD24bb AD33b AD34b AD56b AD57b
KSPS OPERATION
Symbol GERR EOFF GERR EOFF FNYQ ENOB FCNV TSAMP -1.5 -1.5 Typical bits Dynamic Performance Conversion Rate ksps Bits Units Bits Conditions 10-bit
Accuracy Measurements taken with External VREF+/VREF-
Accuracy Measurements taken with Internal VREF+/VREF-
DS80280G-page
2008 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
Module: Module: Interaction with EXCH Instruction
EXCH instruction does execute correctly when either operands numerically equal address DMAC SFRs this revision silicon. Work around writing source code assembly, recommended replace: EXCH Wsource, Wdestination with: PUSH Wdestination Wsource, Wdestination Wsource using MPLAB compiler, specify compiler option, -merrata=exch (Project>Build Options>Projects>MPLAB C30>Use Alternate Settings)
Module: Output Compare Module Mode
Output Compare module will miss compare event when current duty cycle register (OCxRS) value 0x0000 duty cycle), OCxRS register updated with value 0x0001. compare event only missed first time value 0x0001 written OCxRS, output remains period. Subsequent high times occur expected. Work around None. current OCxRS register value 0x0000, avoid writing value 0x0001 OCxRS. Instead, write value 0x0002; however, this case duty cycle will slightly different from desired value.
Module: Module Frame Master Mode
module will fail generate frame synchronization pulses when configured Frame Master mode start data selected coincide with start frame synchronization pulse (FRMEN SPIFSD FRMDLY However, module functions correctly Frame Slave mode, also Frame Maser mode FRMDLY Work around being used, manually drive high using associated PORT register, then drive after required bit-time pulse-width. This operation needs performed when transmit buffer written. being used, other peripheral modules using transfers, Timer interrupt periodically generate frame synchronization pulse (using method described above) after every 16-bit periods (depending data word size, configured using MODE 16-bit). FRMDLY work around needed.
Module: DISI Instruction
When user executes DISI example, this will disable interrupts cycles DISI instruction itself). this case, DISI instruction uses counter which counts down from counter loaded with DISI instruction. user code executes another DISI instruction cycle where DISI counter become zero, DISI count loaded, DISI state machine does properly re-engage continue disable interrupts. this point, interrupts enabled. next time user code executes DISI instruction, feature will normally block interrupts. summary, only when DISI execution coincident with current DISI count that issue occurs. Executing DISI instruction before DISI counter reaches zero will produce this error. this case, DISI counter loaded with value, interrupts remain disabled until counter becomes zero. Work around When executing multiple DISI instructions within source code, make sure that subsequent DISI instructions have least instruction cycle between time that DISI counter decrements zero next DISI instruction. Alternatively, make sure that subsequent DISI instructions called before DISI counter decrements zero.
2008 Microchip Technology Inc.
DS80280G-page
PIC24HJXXXGPX06/X08/X10
Module: Slave Select Mode
module Slave Select functionality (enabled setting SSEN will function correctly. Whether high low, data transfer will completed interrupt will generated. Work around being used, poll state using Change Notification (CN) associated follows: Disable SPIx module clearing SPIEN SPIxSTAT register. Clear SSEN SPIxCON1 register allow port control pin. Ensure that configured digital input setting associated TRISx register. Enable interrupts selected setting appropriate bits CNEN1 CNEN2 registers. Turn weak pull-up device selected pins setting appropriate bits CNPU1 CNPU2 registers. Clear CNIF interrupt flag IFSx register. Select desired interrupt priority interrupts using CNIP<2:0> control bits IPCx register. Enable interrupts using CNIE control IECx register. Interrupt Service Routine, read PORTx register associated pin: PORTx `0', then enable SPIx module setting SPIEN perform required data read/write. PORTx `1', then disable SPIx module setting SPIEN bit, clear interrupt flag (SPIxIF), perform dummy read SPIxBUF register return from Interrupt Service Routine (ISR). being used, work around exists.
Module:
(SPIxCON1<9>, where does have effect when module configured prescale factor Master mode. this mode, whether cleared, data always sampled data output time. Work around sampling middle data output time required, then configure module clock prescale factor other than using PPRE<1:0> SPRE<2:0> bits SPIxCON1 register.
Module: ECAN
multiple ECAN transmit buffers enabled (multiple TXREQ TXEN bits simultaneously), then message transmissions from enabled buffers interfere with another. result, incorrect data transmissions will occur intermittently. Work around Enable only Buffer transmission given time. user application, this ensured checking that other TXREQn TXENn bits clear, before setting TXREQn TXENn Buffer
Module: ECAN
Under specific conditions, first five bits transmitted identifier match value transmit buffer SID. ECAN module detects Start-of-Frame (SOF) third interframe space message transmitted pending, first five bits transmitted identifier corrupted. Work around None.
Module: ECAN Loopback Mode
ECAN module (ECAN1 ECAN2) does function correctly Loopback mode. Work around Loopback mode.
DS80280G-page
2008 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
Module:
Collision Status (BCL) does when collision occurs during Restart Stop event. However, gets when collision occurs during Start event. Work around None.
Module: UART
Receive Buffer Overrun Error Status bit, OERR (UxSTA<1>), before UART FIFO overflowed. After fourth byte received UART, FIFO full. OERR should after fifth byte been received UART shift register. Instead, OERR after fourth received byte with UART Shift register empty. Work around After four bytes have been received UART, UART Receiver Interrupt Flag bit, U1RXIF (IFS0<11>) U2RXIF (IFS1<14>), will set, indicating UART FIFO full. OERR also set. After reading UART receive buffer, UxRXREG, four times clear FIFO, clear both OERR UxRXIF bits software.
Module: INT0, Sleep/Idle Mode
event triggers from INT0 will wake-up device from Sleep Idle mode SMPI bits non-zero. This means that configured generate interrupt after certain number INT0 triggered conversions, conversions will triggered device will remain Sleep. will perform conversions wake-up device only configured generate interrupt after each INT0 triggered conversion (SMPI<3:0> 0000). Work around None. event trigger from INT0 required, initialize SMPI<3:0> `0000' (interrupt every conversion).
Module: UART
UART receptions corrupted Baud Rate Generator mode (BRGH Work around baud rate option (BRGH adjust baud rate accordingly.
Module: Doze Mode Traps
address error trap, stack error trap, math error trap error trap will wake-up device from Doze mode. Work around None.
Module: UART
UTXISEL0 (UxSTA<13>) always read zero regardless value written written either `1', will always read zero. This will affect read-modify-write operations such bitwise shift operations. Using read-modify-write instruction UxSTA register (e.g., BSET, BLCR) will always write UTXISEL0 zero. Work around UTXISEL0 value needed, avoid using read-modify-write instructions UxSTA register. Copy UxSTA register temporary variable UxSTA<13> prior performing read-modify-write operations. Copy value back UxSTA register.
Module: JTAG Programming
JTAG programming does work. Work around None.
Module: UART
With parity option enabled, parity error, indicated PERR (UxSTA<3>) being set, occur Baud Rate Generator contains value. This affects both even parity options. Work around Load Baud Rate Generator register, UxBRG, with even value, disable peripheral's parity option loading either 0b00 0b11 into Parity Data Selection bits, PDSEL<1:0> (UxMODE<2:1>).
Module: UART
auto-baud feature calculate correct baud rate when High Baud Rate Enable bit, BRGH, set. With BRGH set, baud rate calculation used same Work around auto-baud feature needed, Baud Rate mode clearing BRGH bit.
2008 Microchip Technology Inc.
DS80280G-page
PIC24HJXXXGPX06/X08/X10
Module: UART
With auto-baud feature selected, sync break character (0x55) loaded into FIFO data. Work around prevent sync break character from being loaded into FIFO, load UxBRG register with either 0x0000 0xFFFF prior enabling auto-baud feature (ABAUD
Module: Traps Idle Mode
clock failure occurs when device Idle mode, oscillator failure trap does vector Trap Service Routine. Instead, device will simply wake-up from Idle mode continue code execution Fail-Safe Clock Monitor (FSCM) enabled. Work around Whenever device wakes from Idle (assuming FSCM enabled) user software should check state OSCFAIL (INTCON1<1>) determine whether clock failure occurred, then perform appropriate clock switch operation. Regardless, Trap Service Routine must included user application.
Module:
Writing I2CxTRN during Start transmission generates write collision, indicated IWCOL (I2CxSTAT<7>) being set. this state, additional writes I2CxTRN register should blocked. However, this condition, I2CxTRN register written, although transmissions will occur until IWCOL cleared software. Work around After each write I2CxTRN register, read IWCOL ensure collision occurred. IWCOL set, must cleared software I2CxTRN register must rewritten.
Module: MCLR Wake-up from Sleep Mode
MCLR reset pulse causes device wake-up from Sleep mode, device wakes without waiting on-chip voltage regulator power-up. This will subsequently result Brown-out Reset (BOR). Work around None.
Module:
ACKSTAT (I2CxSTAT<15>) only reflects received ACK/NACK status Master transmissions, Slave transmissions. result, Slave cannot this determine received NACK from Master. future silicon revisions, ACKSTAT will reflect received ACK/NACK status both Master Slave transmissions. Work around should connected other available device. After transmitting byte, Slave should poll line (subject time-out period dependent application) determine (`0') NACK (`1') received.
Module: ECAN
C1RXOVF2 C2RXOVF2 registers non-functional. They always read back 0x0000, even when receive overflow occurred. Work around None.
Module:
Status (I2CxSTAT<5>) gets slave data reception I2CxRCV register, does slave write I2CxTRN register. future silicon revisions, will slave write I2CxTRN register. Work around Status only determining slave reception status slave transmission status.
DS80280G-page
2008 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
Module: Oscillator
device does meet internal accuracy specifications data sheet (Table 23-18 "PIC24H Family Data Sheet" (DS70175)). actual accuracy specifications shown Table Work around None.
TABLE
INTERNAL ACCURACY
Standard Operating Conditions: 3.0V 3.6V (unless otherwise stated) Operating temperature -40°C +85°C industrial Typical Units MHz(1,2) Conditions -40°C +85°C 3.0-3.6V Internal Accuracy Frequency 7.37
Characteristics Parameter Characteristic Note
Frequency calibrated 25°C 3.3V. bits used compensate temperature drift. Devices initial frequency 7.37 (±2%) 25°C.
2008 Microchip Technology Inc.
DS80280G-page
PIC24HJXXXGPX06/X08/X10
Module:
SPI1 functionality (U1RX/SDI1/RF2) enabled SPI2 module. result, side effects occur: functionality disabled SPI2 module enabled. This will function SDI1 SPI1 module enabled. This issue affects 64-pin devices only: PIC24HJ64GP206 PIC24HJ128GP206 PIC24HJ256GP206 PIC24HJ128GP306 PIC24HJ64GP506 PIC24HJ128GP506
Module: Device Register
devices, content Device register change from factory programmed default value immediately after RTSP ICSPFlash programming. result, development tools will recognize these devices will generate error message indicating that device device part number match. Additionally, some peripherals will reconfigured will function described device data sheet. Refer Section "Flash Programming" (DS70191), "dsPIC33F Family Reference Manual" explanation RTSP ICSP Flash programming. Work around RTSP ICSP Flash programming routines must modified follows: word programming allowed. word programming must replaced with programming. During programming, load write latches described 5.4.2.3 "Loading Write Latches" Section "Flash Programming" (DS70191). After latches loaded, reload latch location given row) that 0x18, with original data. example, reload following latch locations with desired data: 0xXXXX18, 0xXXXX38, 0xXXXX58, 0xXXXX78, 0xXXXX98, 0xXXXXB8, 0xXXXXD8, 0xXXXXF8 Start programming setting NVMOP<3:0> `0001' (memory program operation) NVMCON register. After programming complete, verify contents Flash memory. Flash verification errors found, repeat steps through Flash verification errors found after second iteration, report this problem Microchip. Steps through work around implemented MPLAB version 8.00 higher MPLAB MPLAB REAL ICEin-circuit emulator tools.
Work around conditions apply: SPI2 module used, cannot used (RF2). recommended another pin. SPI1 module used, SPI2 module must also enabled gain SDI1 functionality alternative, (RF2) configured input, which will allow function SDI1.
Module: UART
auto-baud feature miscalculate certain baud rate clock speed combinations, resulting value that greater than less than expected value This result reception transmission failures. Work around Test auto-baud rate various clock speed baud rate combinations that would used application. inaccurate value generated, manually correct baud rate user software.
DS80280G-page
2008 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
Module:
When channel enabled Single-Shot mode while device Idle mode, corresponding peripheral active configured operate during Idle mode, channel become disabled immediately upon transferring required amount data. result, number bytes words data transferred exceed transfer count specified DMAxCNT register. example, transfers active both byte transmissions receptions, only receive channel interrupt enabled waking device from Idle mode, extra byte will transmitted time device wakes from Idle mode. Work around None.
Module: UART
When UART mode (BRGH using Stop bits (STSEL sample first Stop instead second one. This issue does affect other UART configurations. Work around baud rate option (BRGH adjust baud rate accordingly.
Module: UART
When auto-baud detected, receive interrupt occur twice. first interrupt occurs beginning Start second after reception Sync field character. Work around extra interrupt detected, ignore additional interrupt.
Module: Doze Mode Traps
error trap generated when device Doze mode. Work around None.
Module:
When channel configured NULL Data Peripheral Write mode (DMAxCON<11> does execute null (all zeros) write peripheral address. Work around channels receive data from peripheral module. channel must configured transfer data from peripheral RAM, while another channel must configured transfer dummy data from peripheral. Both channels must setup same request.
Module: Output Compare
When Output Compare module operated Dual Compare Match mode, timer compare match with value OCxR register sets output producing rising edge pin. Then, when timer compare match with value OCxRS register occurs, output reset producing falling edge pin. above statement applies conditions except when difference between OCxR OCxRS this case, Output Compare module miss reset compare event, cause remain continuously high. This condition will remain until difference between values OCxR OCxRS registers made greater than Work around Ensure software that difference between values OCxR OCxRS registers maintained greater than
Module:
priority channel request pre-empted higher priority channel request. example, Channel higher priority than Channel request channel will pending while Channel processing request. Channel receives another request while pending request state, module does generate error trap event. Work around None. Using higher priority channels servicing sources frequent requests significantly reduces possibility condition described above occurring, does completely eliminate
2008 Microchip Technology Inc.
DS80280G-page
PIC24HJXXXGPX06/X08/X10
Module:
When channel configured Shot mode with NULL write enabled, channel will write extra NULL peripheral register after completing last transfer. case module SPIxBUF register, this would cause module perform extra receive operation. Work around None. case using NULL write with module, perform dummy read SPIxBUF register after transfer completed clear SPIRBF flag prevent un-expected overflow condition next receive operation.
Module: REPEAT Instruction
instruction executed inside REPEAT loop, which produces Read-After-Write stall condition, results instruction being executed fewer times than intended. example such code repeat #0xf [w1],[++w1] Work around Avoid repeating instruction that creates stall using REPEAT instruction. Instead, software loop using conditional branches.
DS80280G-page
2008 Microchip Technology Inc.
PIC24HJXXXGPX06/X08/X10
Module: Oscillator
certain values TUN<5:0> bits (OSCTUN<5:0>), resultant frequencies match expected values. shown Table actual frequencies obtained different values TUN<5:0> bits listed terms percentage change relative center frequency 7.3728 MHz. frequency errors listed table approximate vary slightly from device device. recommended that user application include some means measuring exact oscillator frequency order verify frequencies listed below. Work around Configure your peripherals other system parameters based actual frequencies listed Table
TABLE
TUN<5:0> 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 Expected Change from 7.3728 +0.375% +0.75% +1.125% +1.5% +1.875% +2.25% +2.625% +3.375% +3.75% +4.125% +4.5% +4.875% +5.25% +5.625% +6.375% +6.75% +7.125% +7.5% +7.875% +8.25% +8.625% +9.375% +9.75% +10.125% +10.5% +10.875% +11.25% +11.625% Actual Change from 7.3728 +0.375% +0.75% +1.125% +1.5% +1.875% +2.25% +2.625% +3.375% +3.75% +4.125% +4.5% +4.875% +5.25% +5.625% +8.325% +8.7% +9.075% +9.45% +9.825% +10.2% +10.575% +10.95% +11.325% +11.7% +12.075% +12.45% +12.825% +13.2% +13.575% +13.95%
TABLE
TUN<5:0> 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111
(CONTINUED)
Expected Change from 7.3728 -12% -11.625% -11.25% -10.875% -10.5% -10.125% -9.75% -9.375% -8.625% -8.25% -7.875% -7.5% -7.125% -6.75% -6.375% -5.625% -5.25% -4.875% -4.5% -4.125% -3.75% -3.375% -2.625% -2.25% -1.875% -1.5% -1.125% -0.75% -0.375% Actual Change from 7.3728 -12% -11.625% -11.25% -10.875% -10.5% -10.125% -9.75% -9.375% -8.625% -8.25% -7.875% -7.5% -7.125% -6.75% -6.375% -3.675% -3.3% -2.925% -2.55% -2.175% -1.8% -1.425% -1.05% -0.675% -0.3% +0.075% +0.45% +0.825% +1.2% +1.575% +1.95%
2008 Microchip Technology Inc.
DS80280G-page
PIC24HJXXXGPX06/X08/X10
Module: UART
When UART configured interface operations (UxMODE<9:8> 11), baud clock signal BCLK present only when module transmitting. idle other times. Work around Configure output compare modules generate required baud clock signal when UART receiving data idle state.
Module:
With module enabled, PORT bits external interrupt input functions any) associated with pins reflect actual digital logic levels pins. Work around and/or pins need polled, these pins should connected other port pins order read correctly. This issue does affect operation module.
Module:
Setting DISSCK SPIxCON1 register does allow user application general purpose pin. Work around None.
Module:
10-bit Addressing mode, some address matches don't flag load receive register I2CxRCV, lower address byte matches reserved addresses. particular, these include addresses with form XX0000XXXX XX1111XXXX, with following exceptions: 001111000X 011111001X 101111010X 111111011X
Module:
I2CSTAT cleared only with 16-bit operation corrupted with 1-bit 8-bit operations I2CSTAT. Work around 16-bit operations clear BCL.
Work around Ensure that lower address byte 10-bit Addressing mode does match 7-bit reserved addresses.
Module:
there devices bus, them acting Master receiver other Slave transmitter. both devices configured 10-bit addressing mode, have same value bits their addresses, then when Slave select address sent from Master, both Master Slave acknowledge When Master sends read operation, both Master Slave enter into Read mode both them transmit data. resultant data will ANDing transmissions. Work around devices, addresses well bits should different.
Module: Internal Voltage Regulator
When VREGS (RCON<8>) logic `0', higher sleep current observed. Work around Ensure VREGS (RCON<8>) logic device Sleep mode operation.
Module: ECAN
ECAN module does generate event interrupt when coming Disable mode wake-up activity even WAKIE CiINTE register set. WAKIF CiINTF register will reflect correct status. event interrupt occurs only device Sleep mode when wake-up activity occurred. Work around When placing ECAN module Disable mode, place device Sleep mode able generate event interrupt wake-up activity. possible place device Sleep mode, poll WAKIF CiINTF register track wake-up activity.
Module:
When module configured 10-bit slave with address 0x102, I2CxRCV register content lower address byte 0x01 rather than 0x02; however, module acknowledges both address bytes. Work around None.
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2008 Microchip Technology Inc.
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Module: Operations
address error trap occurs certain addressing modes when accessing first four bytes page. This only occurs when using following addressing modes: MOV.D Register Indirect Addressing (word byte mode) with pre/post-decrement Work around perform accesses first four bytes using above addressing modes. applications using language, MPLAB version 3.11 higher, provides following command-line switch that implements work around erratum. -merrata=psv_trap Refer readme.txt file MPLAB v3.11 tool suite further details.
Module: UART (UxE Interrupt)
UART error interrupt occur, occur incorrect time, multiple errors occur during short period time. Work around Read error flags UxSTA register whenever byte received verify error status. most cases, these bits will correct, even UART error interrupt fails occur.
Module: UART (IrDA)
When UART operating 8-bit mode (PDSEL using IrDA encoder/decoder (IREN module incorrectly transmits data payload 00h. Work around None.
2008 Microchip Technology Inc.
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PIC24HJXXXGPX06/X08/X10
APPENDIX
Revision (6/2006) Initial release document. Revision (12/2006) Added issues Revision (3/2007) Changed document title, updated issue added issues Revision (6/2007) Added following silicon issues: (SPI), (UART), (Device Register), (DMA), (Doze Mode Traps) (DCI). Revision (10/2007) Removed issue (Output Compare) issue (DCI). Updated silicon issue (Traps Idle Mode). Added silicon issues (ECAN), (Output Compare), 38-39 (UART), 40-42 (DMA), (REPEAT Instruction), (FRC Oscillator). Revision (4/2008) Updated silicon issues (DMA Module: Interaction with EXCH Instruction) (ECAN). Removed silicon issue (ECAN). Added silicon issues (UART), (SPI) 46-47 (I2C). Revision (9/2008) Added reference silicon revision Updated issue (SPI Slave Select Mode) (I2C). Removed issue (ECAN). Added silicon issues 47-49 (I2C), (Internal Voltage Regulator), (ECAN), (PSV Operations), (UART (UxE Interrupt)) (UART (IrDA)).
REVISION HISTORY
DS80280G-page
2008 Microchip Technology Inc.
Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
Code protection constantly evolving. Microchip committed continuously improving code protection features products. Attempts break Microchip's code protection feature violation Digital Millennium Copyright Act. such acts allow unauthorized access your software other copyrighted work, have right relief under that Act.
Information contained this publication regarding device applications like provided only your convenience superseded updates. your responsibility ensure that your application meets with your specifications. MICROCHIP MAKES REPRESENTATIONS WARRANTIES KIND WHETHER EXPRESS IMPLIED, WRITTEN ORAL, STATUTORY OTHERWISE, RELATED INFORMATION, INCLUDING LIMITED CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY FITNESS PURPOSE. Microchip disclaims liability arising from this information use. Microchip devices life support and/or safety applications entirely buyer's risk, buyer agrees defend, indemnify hold harmless Microchip from damages, claims, suits, expenses resulting from such use. licenses conveyed, implicitly otherwise, under Microchip intellectual property rights.
Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt UNI/O registered trademarks Microchip Technology Incorporated U.S.A. other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2008, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
2008 Microchip Technology Inc.
DS80280G-page
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01/02/08
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2008 Microchip Technology Inc.
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