PIC24H Engineering Samples Rev. A0/A1 Silicon Errata PIC24HJXXXGP

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PIC24H Engineering Samples Rev. A0/A1 Silicon Errata PIC24HJXXXGP

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PIC24H Engineering Samples Rev. A0/A1 Silicon Errata
PIC24HJXXXGPXXX, (Rev. A0/A1) Silicon Errata
PIC24H Engineering Samples (Rev. A0/A1) received were found conform specifications functionality described following documents: DS70175 "PIC24H Family Data Sheet" DS70157 "dsPIC30F/33F Programmer's Reference Manual" DS70046 "dsPIC30F Family Reference Manual" exceptions specifications documents listed above described this section. specific devices which these exceptions described listed below: PIC24HJ128GP506-PT PIC24HJ256GP206-PT PIC24HJ256GP610-PF PIC24HJ256GP610-PT
Silicon Errata Summary
following list summarizes errata described further detail through remainder this document: with Prescaler modules function correctly when clock prescale ratio 1:1. Master Reception Rates above Mbps Master reception does function correctly rates higher than Mbps, data sampled middle serial clock period. with Sample/Hold Sample/Hold amplifier does function correctly Analog-to-Digital Converter modules. LATC LATD Reads LATC LATD register reads function. Single-Shot Mode Direct Memory Access Single-Shot mode does function correctly. Windowed Watchdog Timer When Windowed option enabled disabled, time will occur. Timer3 Conversion Trigger Source Timer2 Timer3, when configured single 32-bit timer, initiate conversion register Timer3 selected conversion trigger source. UART Auto-Baud UART FIFO will loaded with incorrect data UxBRG register initialized specific value. Doze Mode When Doze mode enabled, writes peripheral cause other updates that register cease function duration current clock cycle.
PIC24H Rev. A0/A1 silicon identified performing "Reset Connect" operation device using MPLAB® with MPLAB v7.31.01 later. output window will show either: successful connection device specified Configure>Select Device Warning message Warn0020: Invalid target device this message received, consult "dsPIC33F Flash Programming Specification" (DS70152) verify device This document contains device both dsPIC33F PIC24H devices. This device mismatch will fixed future revisions MPLAB IDE. errata described this section will addressed future revisions silicon.
2006 Microchip Technology Inc.
DS80260B-page
PIC24H ENGINEERING SAMPLES
12-bit Module this revision silicon, 12-bit module DNL, conversion speed signal acquisition time parameters within published data sheet specifications. 10-bit Module this revision silicon, 10-bit module INL, signal acquisition time parameters within published data sheet specifications. Module: Interaction with EXCH Instruction EXCH instruction does execute correctly when operands contains value equal address DMAC SFRs. DISI Instruction DISI instruction will disable interrupts DISI instruction executed same instruction cycle that DISI counter decrements zero. JTAG Programming JTAG programming will work silicon revision A0/A1. Internal Oscillator internal oscillator calibrated silicon revision A0/A1. ECANLoopback Mode ECAN module (ECAN1 ECAN2) does function correctly Loopback mode. Clock Switch From Fail-Safe Clock Source Once clock fail interrupt occurred, clock source cannot switched from fail-safe clock source. I2CModule module does wake-up from Sleep when detects activity. following sections will describe errata work around these errata, where they apply.
DS80260B-page
2006 Microchip Technology Inc.
PIC24H ENGINEERING SAMPLES
Module: with Prescaler
SPI1 SPI2 modules generate serial clock signals and, therefore, function correctly following values PPRE<1:0> (SPIxCON1<1:0>) SPRE<2:0> (SPIxCON1<4:2>) bits: PPRE SPRE Work around Users module with prescale ratio other than 1:1.
Module: LATC LATD Reads
LATC LATD register reads function. Performing read read-modify-write operation LATC register LATD register will function. perform read read-modify-write operations LATC LATD registers. Inspect disassembly listing user application software that accessing LATC LATD register, ensure that read read-modify-write operations being performed these registers. verify contents LATC register, perform following steps: Write LATC Make PORTC output Read PORTC register same steps performed verify contents LATD register. Note: Port state, therefore read value, depends load attached Port pin.
Module: Master Reception Rates above Mbps
Master mode receptions using SPI1 SPI2 module function correctly rates above Mbps Master (SPIxCON1<9>) cleared (Master samples data middle serial clock period). this case, data transmitted Slave received shifted right Master. example, data transmitted Slave 0xAAAA, data received Master would 0x5555 (0xAAAA shifted right bit). Work around Users module that rate Mbps lower. Alternatively, rate configured higher than Mbps, (SPIxCON1<9>) Master must (Master samples data serial clock period).
Module: Single-Shot Mode
Single-Shot mode does function correctly more than block transfer. After block transfer, channel becomes unusable until device reset occurs. Work around more than data block transfers required during entire program execution, user application required channel operate Continuous mode, disable channel every time corresponding interrupt occurred. However, only data block transfer required particular channel during entire program execution, Single-Shot mode used.
Module: with Sample/Hold
Sample/Hold amplifier does function correctly when used with Analog-to-Digital Converter (ADC) modules. corresponding conversion result always read 0x0000. Work around Sample/Hold amplifier with ADC1 ADC2 module. CH0, CH2.
Module: Watchdog Timer
When disabled Window enabled, time will occur. This will cause device reset unexpectedly. disabled clearing FWDTEN (FWDT<7>). Window feature enabled clearing WINDIS (FWDT<6>). Work around order prevent unexpected time when disabled, disable Window feature setting WINDIS (FWDT<6>).
2006 Microchip Technology Inc.
DS80260B-page
PIC24H ENGINEERING SAMPLES
Module: with Timer Conversion Trigger Source
module configured that Timer3 ends sampling starts conversion (ADCON<7:5> 010). PR3, Timer3 period register, loaded with value that compared TMR3. mode described, when TMR3 equal PR3, conversion initiated. Timer3 also initiate conversion when Timer2 Timer3 configured single 32bit timer. However, when Timer2 Timer3 configured single 32-bit timer, conversion initiated register `0'. Work around When Timer3 selected trigger initiating conversion (i.e. ADCON<7:5> 010), make sure that non-zero.
Module: 12-bit
When module configured 12-bit operation, LSBs LSB. conversion speed limited Ksps requires minimum signal acquisition time Work around Implement module either 11-bit Converter. When used 10-bit ADC, LSBs, with missing codes. When used 11-bit ADC, LSBs with missing codes each power boundary. monotonicity still realized missing codes ignored. Future versions silicon will support full 12-bit operation with LSBs DNL, Ksps conversion rate signal acquisition time.
Module: UART Auto-Baud
When auto-baud enabled (UxMODE<5> set), UART FIFO will loaded with incorrect data unless UxBRG register initialized 0xFFFF. Work around Initialize UxBRG register 0xFFFF anytime auto-baud enabled.
Module: 10-bit
module LSBs LSB. Work around None. Future versions silicon will support LSBs specifications, signal acquisition time.
Module: Oscillator: Doze Mode
Enabling Doze mode slows down allows peripherals full speed. When clock slowed down enabling Doze mode (CLKDIV<11> writes peripheral cause other updates that register cease function duration current clock cycle. This only issue attempts write same register peripheral while Doze mode. instance, module active Doze mode enabled, main program should avoid writing ADCCONx registers because these registers being used module. does make writes before module does, then attempts module write these registers will fail. Work around Doze mode, avoid writing code that will modify SFRs which written enabled peripherals.
DS80260B-page
2006 Microchip Technology Inc.
PIC24H ENGINEERING SAMPLES
Module: Module: Interaction with EXCH Instruction
EXCH instruction does execute correctly when either operands numerically equal address DMAC SFRs this revision silicon. Work around writing source code assembly, recommended replace: EXCH Wsource, Wdestination with: PUSH Wdestination Wsource, Wdestination Wsource using MPLAB compiler, check disassembly listing (View>Disassembly Listing) EXCH instruction. used, make sure operands equivalent SFRs' addresses.
Module: JTAG Programming
JTAG programming does work silicon revision A0/A1. Work around None.
Module: Internal Oscillator
internal oscillator calibrated silicon revision A0/A1. Work around user calibrate internal oscillator manually modifying OSCTUN bits. This done using waveform generator other external source generate square wave known frequency input capture pins. Configure corresponding Input Capture module measure square wave period. Calculate value that input capture module should generate based nominal internal oscillator frequency 7.37 MHz. Adjust OSCTUN bits until measured input capture value matches calculated value.
Module: DISI Instruction
When user executes DISI example, this will disable interrupts cycles DISI instruction itself). this case, DISI instruction uses counter which counts down from counter loaded with DISI instruction. user code executes another DISI instruction cycle where DISI counter become zero, DISI count loaded, DISI state machine does properly reengage continue disable interrupts. this point, interrupts enabled. next time user code executes DISI instruction, feature will normally block interrupts. summary, only when DISI execution coincident with current DISI count that issue occurs. Executing DISI instruction before DISI counter reaches zero will produce this error. this case, DISI counter loaded with value, interrupts remain disabled until counter becomes zero. Work around When executing multiple DISI instructions within source code, make sure that subsequent DISI instructions have least instruction cycle between time that DISI counter decrements zero next DISI instruction. Alternatively, make sure that subsequent DISI instructions called before DISI counter decrements zero.
Module: ECAN Loopback Mode
ECAN module (ECAN1 ECAN2) does function correctly Loopback mode. Work around Loopback mode.
Module: Oscillator Configuration Block
fail-safe clock monitoring function enabled, during failure external oscillator, device will automatically switch internal oscillator. clock failure trap event also generated. revision A0/A1 parts, once this interrupt occurs, clock source cannot switched from internal oscillator. Work around user must issue Reset before attempting change clock sources after clock fail event.
Module:
module does wake-up from Sleep when detects activity. Work around None.
2006 Microchip Technology Inc.
DS80260B-page
PIC24H ENGINEERING SAMPLES
APPENDIX
Revision (2/2006) First release document. Revision (5/2006) Added silicon issues (Windowed Watchdog Timer, (Timer3 Conversion Trigger Source), (UART Auto-Baud), (Doze Mode), (12-bit ADC), (10-bit ADC), (DMA Module: Interaction with EXCH Instruction), (DISI Instruction), (JTAG Programming), (Internal Oscillator), (ECAN Loopback Mode), (Clock Switch from Fail-Safe Clock Source) (I2C Module).
REVISION HISTORY
DS80260B-page
2006 Microchip Technology Inc.
Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
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Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, MATE, PowerSmart, rfPIC, SmartShunt registered trademarks Microchip Technology Incorporated U.S.A. other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2006, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona, Gresham, Oregon Mountain View, California. Company's quality system processes procedures PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
2006 Microchip Technology Inc.
DS80260B-page
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02/16/06
DS80260B-page
2006 Microchip Technology Inc.

PIC24H Engineering Samples Rev. A0/A1 Silicon Errata PIC24HJXXXGP

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