High-Performance, 16-bit Microcontrollers 2009 Microchip Technolo
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PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 Data Sheet
High-Performance, 16-bit Microcontrollers
2009 Microchip Technology Inc.
DS70293C
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DS70293C-page
2009 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 High-Performance, 16-bit Microcontrollers
Operating Range:
MIPS operation 3.0-3.6V): Industrial temperature range (-40°C +85°C) Extended temperature range (-40°C +125°C)
Timers/Capture/Compare/PWM:
Timer/Counters, five 16-bit timers: pair make 32-bit timers timer runs Real-Time Clock with external 32.768 oscillator Programmable prescaler Input Capture four channels): Capture down both edges 16-bit capture input functions 4-deep FIFO each capture Output Compare four channels): Single Dual 16-bit Compare mode 16-bit Glitchless mode Hardware Real-Time Clock/Calendar (RTCC): Provides clock, calendar, alarm functions
High-Performance CPU:
Modified Harvard architecture compiler optimized instruction 16-bit wide data path 24-bit wide instructions Linear program memory addressing instruction words Linear data memory addressing Kbytes base instructions: mostly word/1 cycle Flexible powerful addressing modes Software stack multiply operations 32/16 16/16 divide operations ±16-bit shifts 40-bit data
Interrupt Controller:
5-cycle latency available interrupt sources three external interrupts Seven programmable priority levels Five processor exceptions
Direct Memory Access (DMA):
8-channel hardware Kbytes dual ported buffer area (DMA RAM) store data transferred DMA: Allows data transfer between peripheral while executing code cycle stealing) Most peripherals support
Digital I/O:
Peripheral Select functionality programmable digital pins Wake-up/Interrupt-on-Change pins Output pins drive from 3.0V 3.6V output with open drain configuration digital input pins tolerant sink pins
On-Chip Flash SRAM:
Flash program memory Kbytes) Data SRAM Kbytes) Boot, Secure, General Security program Flash
2009 Microchip Technology Inc.
DS70293C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
Communication Modules:
4-wire modules): Framing supports interface simple codecs Supports 8-bit 16-bit data Supports serial clock formats sampling modes I2CTM: Full Multi-Master Slave mode support 7-bit 10-bit addressing collision detection arbitration Integrated signal conditioning Slave address masking UART modules): Interrupt address detect Interrupt UART error Wake-up Start from Sleep mode 4-character FIFO buffers support IrDA® encoding decoding hardware High-Speed Baud mode Hardware Flow Control with Enhanced (ECANmodule) 2.0B active: eight transmit receive buffers receive filters three masks Loopback, Listen Only Listen Messages modes diagnostics monitoring Wake-up message Automatic processing Remote Transmission Requests FIFO mode using DeviceNetaddressing support Parallel Master Slave Port (PMP/EPSP): Supports 8-bit 16-bit data Supports address lines Programmable Cyclic Redundancy Check (CRC): Programmable length generator polynomial 16-bit length) 8-deep, 16-bit 16-deep, 8-bit FIFO data input
System Management:
Flexible clock options: External, crystal, resonator internal Fully integrated Phase-Locked Loop (PLL) Extremely jitter Power-Up Timer Oscillator Start-up Timer/Stabilizer Watchdog Timer with oscillator Fail-Safe Clock Monitor Reset multiple sources
Power Management:
On-chip 2.5V voltage regulator Switch between clock sources real time Idle, Sleep Doze modes with fast wake-up
Analog-to-Digital Converters (ADCs):
10-bit, Msps 12-bit, Ksps conversion: four simultaneous samples (10-bit ADC) input channels with auto-scanning Conversion start manual synchronized with four trigger sources Conversion possible Sleep mode integral nonlinearity differential nonlinearity
Comparator Module:
analog comparators with programmable input/output configuration
CMOS Flash Technology:
Low-power, high-speed Flash technology Fully static design 3.3V (±10%) operating voltage Industrial Extended temperature power consumption
Packaging:
28-pin SDIP/SOIC/QFN-S 44-pin TQFP/QFN Note: device variant tables exact peripheral features device.
DS70293C-page
2009 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 PRODUCT FAMILIES
device names, counts, memory sizes peripheral availability each device listed below. following pages show their pinout diagrams.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 Controller Families
Analog Comparator Channels/Voltage Regulator) Remappable Peripheral Program Flash Memory (Kbyte) 8-bit Parallel Master Port (Address Lines)
External Interrupts(3)
Remappable Pins
Output Compare Standard
16-bit Timer(2)
10-bit/12-bit (Channels)
Input Capture
I2CCRC Generator
(Kbyte)(1)
UART
PIC24HJ128GP504 PIC24HJ128GP502
Device
ECAN
TQFP SDIP SOIC QFN-S TQFP SDIP SOIC QFN-S TQFP SDIP SOIC QFN-S TQFP SDIP SOIC QFN-S TQFP
PIC24HJ128GP204 PIC24HJ128GP202
PIC24HJ64GP504 PIC24HJ64GP502
PIC24HJ64GP204 PIC24HJ64GP202
PIC24HJ32GP304 PIC24HJ32GP302
Note
SDIP SOIC QFN-S size inclusive Kbytes devices except PIC24HJ32GP302/304, which include Kbyte RAM. Only four five timers remappable. Only three interrupts remappable.
2009 Microchip Technology Inc.
DS70293C-page
Packages
Pins
RTCC
Pins
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
Diagrams
28-Pin SDIP, SOIC
MCLR AN0/VREF+/CN2/RA0 AN1/VREF-/CN3/RA1 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 PGEC1/ AN3/C2IN+/RP1(1)/CN5/RB1 AN4/C1IN-/RP2 /CN6/RB2 AN5/C1IN+/RP3(1)/CN7/RB3 OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/PMA0/RA3 SOSCI/RP4(1)/CN1/PMBE/RB4 SOSCO/T1CK/CN0/PMA1/RA4
Pins tolerant
PIC24HJ32GP302 PIC24HJ64GP202 PIC24HJ64GP502 PIC24HJ128GP202 PIC24HJ128GP502 AVDD AVSS AN9/RP15(1)/CN11/PMCS1/RB15 AN11/RP13(1)/CN13/PMRD/RB13 AN12/RP12(1)/CN14/PMD0/RB12 VCAP/VDDCORE TDO/SDA1/RP9(1)/CN21/PMD3/RB9 TCK/SCL1/RP8(1)/CN22/PMD4/RB8 INT0/RP7(1)/CN23/PMD5/RB7
28-Pin QFN-S(2)
AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AVDD AVSS AN9/RP15/CN11/PMCS1/RB15 AN10/RTCC/RP14/CN12/PMWR/RB14
Pins tolerant
PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 AN4/C1IN-/RP2(1)/CN6/RB2 AN5/C1IN+/RP3(1)/CN7/RB3 OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/PMA0/RA3
PIC24HJ32GP302 PIC24HJ64GP202 PIC24HJ64GP502 PIC24HJ128GP202 PIC24HJ128GP502
AN11/RP13(1)/CN13/PMRD/RB13 AN12/RP12(1)/CN14/PMD0/RB12 VCAP/VDDCORE TDO/SDA1/RP9(1)/CN21/PMD3/RB9
Note
pins used remappable peripheral. table "PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 Controller Families" this section list available peripherals. metal plane bottom device connected pins recommended connected externally.
SOSCI/RP4(1)/CN1/PMBE/RB4 SOSCO/T1CK/CN0/PMA1/RA4 INT0/RP7(1)/CN23/PMD5/RB7 TCK/SCL1/RP8(1)/CN22/PMD4/RB8
DS70293C-page
2009 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
Diagrams (Continued)
44-Pin QFN(2)
Pins tolerant
PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AVDD AVSS AN9/RP15(1)/CN11/PMCS1/RB15 TCK/PMA7/RA7 TMS/PMA10/RA10
AN5/C1IN+/RP3(1)/CN7/RB3 AN6/RP16(1)/CN8/RC0 AN7/RP17(1)/CN9/RC1 AN8/CVREF/RP18(1)/PMA2/CN10/RC2 OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 TDO/PMA8/RA8 SOSCI/RP4(1)/CN1/RB4
AN4/C1IN-/RP2(1)/CN6/RB2
AN11/RP13(1)/CN13/PMRD/RB13 AN12/RP12(1)/CN14/PMD0/RB12 PGEC2/RP11(1)/CN15/PMD1/RB11 PGED2/RP10(1)/CN16/PMD2/RB10 VCAP/VDDCORE RP25(1)/CN19/PMA6/RC9 RP24(1)/CN20/PMA5/RC8 RP23(1)/CN17/PMA0/RC7 RP22(1)/CN18/PMA1/RC6 SDA1/RP9(1)/CN21/PMD3/RB9
PIC24HJ32GP304 PIC24HJ64GP204 PIC24HJ64GP504 PIC24HJ128GP204 PIC24HJ128GP504
Note
pins used remappable peripheral. table "PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 Controller Families" this section list available peripherals. metal plane bottom device connected pins recommended connected externally.
2009 Microchip Technology Inc.
SOSCO/T1CK/CN0/RA4 TDI/PMA9/RA9 RP19(1)/CN28/PMBE/RC3 RP20(1)/CN25/PMA4/RC4 RP21(1)/CN26/PMA3/RC5 INT0/RP7(1)/CN23/PMD5/RB7 SCL1/RP8(1)/CN22/PMD4/RB8
DS70293C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
Diagrams (Continued)
44-Pin TQFP
PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AVDD AVSS AN9/RP15(1)/CN11/PMCS1/RB15 TCK/PMA7/RA7 TMS/PMA10/RA10
Pins tolerant
Note
pins used remappable peripheral. table "PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 Controller Families" this section list available peripherals.
SOSCO/T1CK/CN0/RA4 TDI/PMA9/RA9 RP19(1)/CN28/PMBE/RC3 (1)/CN25/PMA4/RC4 RP20 RP21(1)/CN26/PMA3/RC5 INT0/RP7(1)/CN23/PMD5/RB7 SCL1/RP8(1)/CN22/PMD4/RB8
AN4/C1IN-/RP2(1)/CN6/RB2 AN5/C1IN+/RP3(1)/CN7/RB3 AN6/RP16(1)/CN8/RC0 AN7/RP17(1)/CN9/RC1 AN8/CVREF/RP18(1)/PMA2/CN10/RC2 OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 TDO/PMA8/RA8 SOSCI/RP4(1)/CN1/RB4
PIC24HJ32GP304 PIC24HJ64GP204 PIC24HJ64GP504 PIC24HJ128GP204 PIC24HJ128GP504
AN11/RP13(1)/CN13/PMRD/RB13 AN12/RP12(1)/CN14/PMD0/RB12 PGEC2/RP11(1)/CN15/PMD1/RB11 VCAP/VDDCORE RP25(1)/CN19/PMA6/RC9 RP24(1)/CN20/PMA5/RC8 RP23(1)/CN17/PMA0/RC7 RP22(1)/CN18/PMA1/RC6 SDA1/RP9(1)/CN21/PMD3/RB9
DS70293C-page
2009 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
Table Contents
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 Product Families Device Overview Guidelines Getting Started with 16-bit Microcontrollers CPU. Memory Organization Flash Program Memory. Resets Interrupt Controller Direct Memory Access (DMA) Oscillator Configuration 10.0 Power-Saving Features. 11.0 Ports 12.0 Timer1 13.0 Timer2/3 TImer4/5 feature 14.0 Input Capture. 15.0 Output Compare. 16.0 Serial Peripheral Interface (SPI). 17.0 Inter-Integrated Circuit (I2CTM) 18.0 Universal Asynchronous Receiver Transmitter (UART) 19.0 Enhanced (ECANTM) Module. 20.0 10-bit/12-bit Analog-to-Digital Converter (ADC1) 21.0 Comparator Module. 22.0 Real-Time Clock Calendar (RTCC) 23.0 Programmable Cyclic Redundancy Check (CRC) Generator 24.0 Parallel Master Port (PMP). 25.0 Special Features 26.0 Instruction Summary 27.0 Development Support. 28.0 Electrical Characteristics 29.0 Packaging Information. Appendix Revision History. Index Microchip Site Customer Change Notification Service Customer Support Reader Response Product Identification System
2009 Microchip Technology Inc.
DS70293C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 VALUED CUSTOMERS
intention provide valued customers with best documentation possible ensure successful your Microchip products. this end, will continue improve publications better suit your needs. publications will refined enhanced volumes updates introduced. have questions comments regarding this publication, please contact Marketing Communications Department E-mail docerrors@microchip.com Reader Response Form back this data sheet (480) 792-4150. welcome your feedback.
Most Current Data Sheet
obtain most up-to-date version this data sheet, please register Worldwide site http://www.microchip.com determine version data sheet examining literature number found bottom outside corner page. last character literature number version number, (e.g., DS30000A version document DS30000).
Errata
errata sheet, describing minor operational differences from data sheet recommended workarounds, exist current devices. device/documentation issues become known will publish errata sheet. errata will specify revision silicon revision document which applies. determine errata sheet exists particular device, please check with following: Microchip's Worldwide site; http://www.microchip.com Your local Microchip sales office (see last page) When contacting sales office, please specify which device, revision silicon data sheet (include literature number) using.
Customer Notification System
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DS70293C-page
2009 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
Note:
DEVICE OVERVIEW
This data sheet summarizes features PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 families devices. intended comprehensive reference source. complement information this data sheet, refer related section PIC24H Family Reference Manual, which available from Microchip website (www.microchip.com)
This document contains device specific information PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 devices. Figure shows general block diagram core peripheral modules PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 families devices. Table lists functions various pins shown pinout diagrams.
2009 Microchip Technology Inc.
DS70293C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
FIGURE 1-1:
Table Data Access Control Block Interrupt Controller Program Counter Loop Stack Control Control Logic Logic Address Latch
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 BLOCK DIAGRAM
Data Data Latch
PORTA
PORTB
Address Generator Units
Controller
PORTC
Address Latch
Program Memory Data Latch Latch
Literal Data Remappable Pins
Instruction Decode Control Control Signals Various Blocks
OSC2/CLKO OSC1/CLKI Timing Generation FRC/LPRC Oscillators Precision Band Reference Voltage Regulator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset
Instruction
Multiplier Register Array
Divide Support
16-bit
VCAP/VDDCORE
VDD,
MCLR
PMP/ EPSP
Comparator
ECAN1
Timers
UART1,
ADC1
PWM1-4
RTCC
SPI1,
IC1,
I2C1
Note:
pins features implemented device pinout configurations. pinout diagrams specific pins features present each device.
DS70293C-page
2009 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
TABLE 1-1:
Name AN0-AN12 CLKI
PINOUT DESCRIPTIONS
Type Buffer Type Analog ST/CMOS Analog input channels. External clock source input. Always associated with OSC1 function. Oscillator crystal output. Connects crystal resonator Crystal Oscillator mode. Optionally functions CLKO modes. Always associated with OSC2 function. Oscillator crystal input. buffer when configured mode; CMOS otherwise. Oscillator crystal output. Connects crystal resonator Crystal Oscillator mode. Optionally functions CLKO modes. 32.768 low-power oscillator crystal input; CMOS otherwise. 32.768 low-power oscillator crystal output. Change notification inputs. software programmed internal weak pull-ups inputs. Capture inputs Capture inputs 7/8. Compare Fault input (for Compare Channels Compare outputs through External interrupt External interrupt External interrupt PORTA bidirectional port. PORTA bidirectional port. PORTB bidirectional port. PORTC bidirectional port. Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. Timer4 external clock input. Timer5 external clock input. UART1 clear send. UART1 ready send. UART1 receive. UART1 transmit. UART2 clear send. UART2 ready send. UART2 receive. UART2 transmit. Synchronous serial clock input/output SPI1. SPI1 data SPI1 data out. SPI1 slave synchronization frame pulse I/O. Synchronous serial clock input/output SPI2. SPI2 data SPI2 data out. SPI2 slave synchronization frame pulse I/O. Analog Analog input Output input buffer Power Input Description
CLKO OSC1 OSC2 SOSCI SOSCO CN0-CN30 IC1-IC2 IC7-IC8 OCFA OC1-OC4 INT0 INT1 INT2 RA0-RA4 RA7-RA10 RB0-RB15 RC0-RC9 T1CK T2CK T3CK T4CK T5CK U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX SCK1 SDI1 SDO1 SCK2 SDI2 SDO2
ST/CMOS ST/CMOS
Legend: CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Peripheral Select
2009 Microchip Technology Inc.
DS70293C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
TABLE 1-1:
Name SCL1 SDA1 ASCL1 ASDA1 C1RX C1TX RTCC CVREF C1INC1IN+ C1OUT C2INC2IN+ C2OUT PMA0 PMA1 PMA2 -PMPA10 PMBE PMCS1 PMD0-PMPD7 PMRD PMWR PGED1 PGEC1 PGED2 PGEC2 PGED3 PGEC3 MCLR AVDD AVSS VCAP/VDDCORE VREF+ VREF-
PINOUT DESCRIPTIONS (CONTINUED)
Type Buffer Type TTL/ST TTL/ST TTL/ST Analog Analog Description Synchronous serial clock input/output I2C1. Synchronous serial data input/output I2C1. Alternate synchronous serial clock input/output I2C1. Alternate synchronous serial data input/output I2C1. JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin. ECAN1 receive pin. ECAN1 transmit pin. Real-Time Clock Alarm Output. Comparator Voltage Reference Output. Comparator Negative Input. Comparator Positive Input. Comparator Output. Comparator Negative Input. Comparator Positive Input. Comparator Output. Parallel Master Port Address Input (Buffered Slave modes) Output (Master modes). Parallel Master Port Address Input (Buffered Slave modes) Output (Master modes). Parallel Master Port Address (Demultiplexed Master Modes). Parallel Master Port Byte Enable Strobe. Parallel Master Port Chip Select Strobe. Parallel Master Port Data (Demultiplexed Master mode) Address/ Data (Multiplexed Master modes). Parallel Master Port Read Strobe. Parallel Master Port Write Strobe. Data programming/debugging communication channel Clock input programming/debugging communication channel Data programming/debugging communication channel Clock input programming/debugging communication channel Data programming/debugging communication channel Clock input programming/debugging communication channel Master Clear (Reset) input. This active-low Reset device. Positive supply analog modules. This must connected times. Ground reference analog modules. Positive supply peripheral logic pins. logic filter capacitor connection. Ground reference logic pins. Analog voltage reference (high) input. Analog voltage reference (low) input. Analog Analog input Output input buffer Power Input
Legend: CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Peripheral Select
DS70293C-page
2009 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 GUIDELINES GETTING STARTED WITH 16-BIT MICROCONTROLLERS
This data sheet summarizes features PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 family devices. intended comprehensive reference source. complement information this data sheet, refer "PIC24H Family Reference Manual", which available from Microchip website (www.microchip.com).
Decoupling Capacitors
Note:
decoupling capacitors every pair power supply pins, such VDD, VSS, AVDD AVSS required. Consider following criteria when using decoupling capacitors: Value type capacitor: Recommendation (100 nF), 10-20V. This capacitor should low-ESR have resonance frequency range higher. recommended that ceramic capacitors used. Placement printed circuit board: decoupling capacitors should placed close pins possible. recommended place capacitors same side board device. space constricted, capacitor placed another layer using via; however, ensure that trace length from capacitor within one-quarter inch length. Handling high frequency noise: board experiencing high frequency noise, upward tens MHz, second ceramic-type capacitor parallel above described decoupling capacitor. value second capacitor range 0.01 0.001 Place this second capacitor next primary decoupling capacitor. high-speed circuit designs, consider implementing decade pair capacitances close power ground pins possible. example, parallel with 0.001 Maximizing performance: board layout from power supply circuit, power return traces decoupling capacitors first, then device pins. This ensures that decoupling capacitors first power chain. Equally important keep trace length between capacitor power pins minimum thereby reducing track inductance.
Basic Connection Requirements
Getting started with PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 family 16-bit Microcontrollers (MCU) requires attention minimal device connections before proceeding with development. following list names, which must always connected: pins (see Section "Decoupling Capacitors") AVDD AVSS pins (regardless module used) (see Section "Decoupling Capacitors") VCAP/VDDCORE (see Section "Capacitor Internal Voltage Regulator (Vcap/Vddcore)") MCLR (see Section "Master Clear (MCLR) Pin") PGECx/PGEDx pins used In-Circuit Serial Programming(ICSPTM) debugging purposes (see Section "ICSP Pins") OSC1 OSC2 pins when external oscillator source used (see Section "External Oscillator Pins") Additionally, following pins required: VREF+/VREF- pins used when external voltage reference module implemented Note: AVDD AVSS pins must connected independent voltage reference source.
2009 Microchip Technology Inc.
DS70293C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION
Ceramic
Master Clear (MCLR)
MCLR provides specific device functions: Device Reset Device programming debugging. During device programming debugging, resistance capacitance that added must considered. Device programmers debuggers drive MCLR pin. Consequently, specific voltage levels (VIH VIL) fast signal transitions must adversely affected. Therefore, specific values will need adjusted based application requirements.
MCLR
VCAP/VDDCORE
PIC24H
AVDD AVSS
Ceramic
Ceramic
Ceramic
Ceramic
example, shown Figure 2-2, recommended that capacitor isolated from MCLR during programming debugging operations. Place components shown Figure within one-quarter inch from MCLR pin.
2.2.1
TANK CAPACITORS
FIGURE 2-2:
boards with power traces running longer than inches length, suggested tank capacitor integrated circuits including MCUs supply local power source. value tank capacitor should determined based trace resistance that connects power supply source device, maximum current drawn device application. other words, select tank capacitor that meets acceptable voltage device. Typical values range from
EXAMPLE MCLR CONNECTIONS
MCLR PIC24H
Capacitor Internal Voltage Regulator (VCAP/VDDCORE)
Note
low-ESR Ohms) capacitor required VCAP/VDDCORE pin, which used stabilize voltage regulator output voltage. VCAP/VDDCORE must connected VDD, must have capacitor between connected ground. type ceramic tantalum. Refer Section 28.0 "Electrical Characteristics" additional information. placement this capacitor should close VCAP/VDDCORE. recommended that trace length exceed one-quarter inch mm). Refer Section 25.2 "On-Chip Voltage Regulator" details.
recommended. suggested starting value Ensure that MCLR specifications met. will limit current flowing into MCLR from external capacitor event MCLR breakdown, Electrostatic Discharge (ESD) Electrical Overstress (EOS). Ensure that MCLR specifications met.
DS70293C-page
2009 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
ICSP Pins External Oscillator Pins
PGECx PGEDx pins used In-Circuit Serial Programming(ICSPTM) debugging purposes. recommended keep trace length between ICSP connector ICSP pins device short possible. ICSP connector expected experience event, series resistor recommended, with value range tens Ohms, exceed Ohms. Pull-up resistors, series diodes, capacitors PGECx PGEDx pins recommended they will interfere with programmer/debugger communications device. such discrete components application requirement, they should removed from circuit during programming debugging. Alternatively, refer AC/DC characteristics timing requirements information respective device Flash programming specification information capacitive loading limits input voltage high (VIH) input (VIL) requirements. Ensure that "Communication Channel Select" (i.e., PGECx/PGEDx pins) programmed into device matches physical connections ICSP MPLAB® MPLAB® MPLAB® REAL ICETM. more information REAL connection requirements, refer following documents that available Microchip website. "MPLAB In-Circuit Debugger User's Guide" DS51331 "Using MPLAB® (poster) DS51265 "MPLAB® Design Advisory" DS51566 "Using MPLAB® (poster) DS51765 "MPLAB® Design Advisory" DS51764 "MPLAB® REAL ICEIn-Circuit Debugger User's Guide" DS51616 "Using MPLAB® REAL ICETM" (poster) DS51749
Many MCUs have options least oscillators: high-frequency primary oscillator low-frequency secondary oscillator (refer Section "Oscillator Configuration" details). oscillator circuit should placed same side board device. Also, place oscillator circuit close respective oscillator pins, exceeding one-half inch distance between them. load capacitors should placed next oscillator itself, same side board. grounded copper pour around oscillator circuit isolate them from surrounding circuits. grounded copper pour should routed directly ground. signal traces power traces inside ground pour. Also, using two-sided board, avoid traces other side board where crystal placed. suggested layout shown Figure 2-3.
FIGURE 2-3:
SUGGESTED PLACEMENT OSCILLATOR CIRCUIT
Main Oscillator Guard Ring Guard Trace Secondary Oscillator
2009 Microchip Technology Inc.
DS70293C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
Oscillator Value Conditions Device Start-up Unused I/Os
target device enabled configured device start-up oscillator, maximum oscillator source frequency must limited comply with device start-up conditions. This means that external oscillator frequency outside this range, application must start-up mode first. default settings after with oscillator frequency outside this range will violate device operating speed. Once device powers application firmware initialize SFRs, CLKDIV, PLLDBF suitable value, then perform clock switch Oscillator clock source. Note that clock switching must enabled device Configuration word.
Unused pins should configured outputs driven logic-low state. Alternatively, connect resistor unused pins drive output logic low.
Configuration Analog Digital Pins During ICSP Operations
MPLAB REAL selected debugger, automatically initializes input pins (ANx) "digital" pins, setting bits AD1PCFGL register. bits this register that correspond pins that initialized MPLAB REAL ICE, must cleared user application firmware; otherwise, communication errors will result between debugger device. your application needs certain pins analog input pins during debug session, user application must clear corresponding bits AD1PCFGL register during initialization module. When MPLAB REAL used programmer, user application firmware must correctly configure AD1PCFGL register. Automatic initialization this register only done during debugger operation. Failure correctly configure register(s) will result pins being recognized analog input pins, resulting port value being read logic '0', which affect user application functionality.
DS70293C-page
2009 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
Note:
This data sheet summarizes features PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 families devices. intended comprehensive reference source. complement information this data sheet, refer "PIC24H Family Reference Manual", Section "CPU" (DS70245), which available from Microchip website (www.microchip.com).
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 instruction includes many addressing modes designed optimum compiler efficiency. most instructions, PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 capable executing data program data) memory read, working register (data) read, data memory write program (instruction) memory read instruction cycle. result, three parameter instructions supported, allowing operations executed single cycle. block diagram shown Figure 3-1, programmer's model PIC24HJ32GP302/ 304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 shown Figure 3-2.
Overview
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 module 16-bit (data) modified Harvard architecture with enhanced instruction addressing modes. 24-bit instruction word with variable length opcode field. Program Counter (PC) bits wide addresses bits user program memory space. actual amount program memory implemented varies device. single-cycle instruction prefetch mechanism used help maintain throughput provides predictable execution. instructions execute single cycle, with exception instructions that change program flow, double word move (MOV.D) instruction table instructions. Overhead-free, single-cycle program loop constructs supported using REPEAT instruction, which interruptible point. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 devices have sixteen, 16-bit working registers programmer's model. Each working registers serve data, address address offset register. 16th working register (W15) operates software Stack Pointer (SP) interrupts calls.
Data Addressing Overview
data space linearly addressed words Kbytes using Address Generation Unit (AGU). upper Kbytes data space memory optionally mapped into program space program word boundary defined 8-bit Program Space Visibility Page (PSVPAG) register. program data space mapping feature lets instruction access program space were data space. data space also includes Kbytes RAM, which primarily used data transfers, used general purpose RAM.
2009 Microchip Technology Inc.
DS70293C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
Special Features
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 devices support 16/16 32/16 integer divide operations. divide instructions iterative operations. They must executed within REPEAT loop, resulting total execution time instruction cycles. divide operation interrupted during those cycles without loss data. multi-bit data shifter used perform 16-bit, left right shift single cycle.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 features 17-bit 17bit, single-cycle multiplier. multiplier perform signed, unsigned mixed-sign multiplication. Using 17-bit 17-bit multiplier 16-bit 16-bit multiplication makes mixed-sign multiplication possible.
FIGURE 3-1:
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 CORE BLOCK DIAGRAM
Table Data Access Control Block Interrupt Controller Program Counter Loop Stack Control Control Logic Logic Data
Data Latch Address Latch
Address Latch Address Generator Units Controller
Program Memory Data Latch Latch Literal Data
Instruction Decode Control
Instruction
Control Signals Various Blocks
Multiplier Register Array
Divide Support
16-bit
Peripheral Modules
DS70293C-page
2009 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
FIGURE 3-2: PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 PROGRAMMER'S MODEL
W0/WREG W14/Frame Pointer W15/Stack Pointer SPLIM Stack Pointer Limit Register Working Registers
PUSH.S Shadow
Legend
PC22 TBLPAG PSVPAG Data Table Page Address
Program Counter
Program Space Visibility Page Address RCOUNT REPEAT Loop Counter
CORCON
Core Configuration Register
IPL2 IPL1 IPL0
STATUS Register
2009 Microchip Technology Inc.
DS70293C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
Control Registers
STATUS REGISTER
R/W-0 R/W-0(2) IPL<2:0> Legend: Clear only only 15-9 Readable Writable cleared Unimplemented: Read Half Carry/Borrow carry-out from low-order (for byte-sized data) low-order (for word-sized data) result occurred carry-out from low-order (for byte-sized data) low-order (for word-sized data) result occurred IPL<2:0>: Interrupt Priority Level Status bits(2) Interrupt Priority Level (15), user interrupts disabled Interrupt Priority Level (14) Interrupt Priority Level (13) Interrupt Priority Level (12) Interrupt Priority Level (11) Interrupt Priority Level (10) Interrupt Priority Level Interrupt Priority Level REPEAT Loop Active REPEAT loop progress REPEAT loop progress Negative Result negative Result non-negative (zero positive) Overflow This used signed arithmetic (two's complement). indicates overflow magnitude that causes sign change state. Overflow occurred signed arithmetic this arithmetic operation) overflow occurred Zero operation that affects some time past most recent operation that affects cleared (i.e., non-zero result) Carry/Borrow carry-out from Most Significant result occurred carry-out from Most Significant result occurred Unimplemented bit, read Value unknown
REGISTER 3-1:
R/W-0(1)
R/W-0(2)
R/W-0
R/W-0
R/W-0
R/W-0
Note IPL<2:0> bits concatenated with IPL<3> (CORCON<3>) form Interrupt Priority Level. value parentheses indicates IPL<3> User interrupts disabled when IPL<3> IPL<2:0> Status bits read only when NSTDIS (INTCON1<15>).
DS70293C-page
2009 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
REGISTER 3-2:
Legend: Readable cleared 15-4 Clear only Writable unknown
CORCON: CORE CONTROL REGISTER
R/C-0 IPL3(1) R/W-0
Value Unimplemented bit, read
Unimplemented: Read IPL3: Interrupt Priority Level Status 3(1) interrupt priority level greater than interrupt priority level less PSV: Program Space Visibility Data Space Enable Program space visible data space Program space visible data space Unimplemented: Read
Note IPL3 concatenated with IPL<2:0> bits (SR<7:5>) form interrupt priority level.
2009 Microchip Technology Inc.
DS70293C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
Arithmetic Logic Unit (ALU)
3.5.2 DIVIDER
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 bits wide capable addition, subtraction, shifts logic operations. Unless otherwise mentioned, arithmetic operations two's complement nature. Depending operation, affect values Carry (C), Zero (Z), Negative (N), Overflow (OV) Digit Carry (DC) Status bits register. Status bits operate Borrow Digit Borrow bits, respectively, subtraction operations. perform 8-bit 16-bit operations, depending mode instruction that used. Data operation come from register array data memory, depending addressing mode instruction. Likewise, output data from written register array data memory location. Refer "dsPIC30F/33F Programmer's Reference Manual" (DS70157) information bits affected each instruction. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 incorporates hardware support both multiplication division. This includes dedicated hardware multiplier support hardware 16-bit-divisor division.
divide block supports 32-bit/16-bit 16-bit/16-bit signed unsigned integer divide operations with following data sizes: 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide
quotient divide instructions ends remainder 16-bit signed unsigned instructions specify register both 16-bit divisor (Wn) register (aligned) pair (W(m 1):Wm) 32-bit dividend. divide algorithm takes cycle divisor, both 32-bit/16-bit 16-bit/16-bit instructions take same number cycles execute.
3.5.3
MULTI-BIT DATA SHIFTER
multi-bit data shifter capable performing 16-bit arithmetic logic right shifts, 16-bit left shifts single cycle. source either working register memory location. shifter requires signed binary value determine both magnitude (number bits) direction shift operation. positive value shifts operand right. negative value shifts operand left. value does modify operand.
3.5.1
MULTIPLIER
Using high-speed 17-bit 17-bit multiplier, supports unsigned, signed mixed-sign operation several multiplication modes: 16-bit 16-bit signed 16-bit 16-bit unsigned 16-bit signed 5-bit (literal) unsigned 16-bit unsigned 16-bit unsigned 16-bit unsigned 5-bit (literal) unsigned 16-bit unsigned 16-bit signed 8-bit unsigned 8-bit unsigned
DS70293C-page
2009 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
Note:
MEMORY ORGANIZATION
This data sheet summarizes features PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 families devices. intended comprehensive reference source. complement information this data sheet, refer "PIC24H Family Reference Manual", Section "Program Memory" (DS70238), which available from Microchip website (www.microchip.com).
Program Address Space
program address memory space PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 devices instructions. space addressable 24-bit value derived either from 23-bit Program Counter (PC) during program execution, from table operation data space remapping described Section "Interfacing Program Data Memory Spaces". User application access program memory space restricted lower half address range (0x000000 0x7FFFFF). exception TBLRD/TBLWT operations, which TBLPAG<7> permit access Configuration bits Device sections configuration memory space. memory PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 devices shown Figure 4-1.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 architecture features separate program data memory spaces buses. This architecture also allows direct access program memory from data space during code execution.
FIGURE 4-1:
PROGRAM MEMORY PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 DEVICES
PIC24HJ64GPX02/X04 GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table PIC24HJ128GPX02/X04 GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table 0x000000 0x000002 0x000004 0x0000FE 0x000100 0x000104 0x0001FE 0x000200
PIC24HJ32GP302/304 GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Program Flash Memory (11264 instructions)
User Memory Space
User Program Flash Memory (22016 instructions)
User Program Flash Memory (44032 instructions)
0x0057FE 0x005800
0x00ABFE 0x00AC00 Unimplemented (Read `0's) Unimplemented (Read `0's) Unimplemented (Read `0's) 0x7FFFFE 0x800000 Reserved Reserved Reserved 0x0157FE 0x015800
Configuration Memory Space
Device Configuration Registers
Device Configuration Registers
Device Configuration Registers
0xF7FFFE 0xF80000 0xF80017 0xF80018
Reserved
Reserved
Reserved 0xFEFFFE 0xFF0000 0xFF0002 0xFFFFFE
DEVID Reserved
DEVID Reserved
DEVID Reserved
Note:
Memory areas shown scale.
2009 Microchip Technology Inc.
DS70293C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.2 INTERRUPT TRAP VECTORS
program memory space organized word-addressable blocks. Although treated bits wide, more appropriate think each address program memory lower upper word, with upper byte upper word being unimplemented. lower word always even address, while upper word address (Figure 4-2). Program memory addresses always word-aligned lower word, addresses incremented decremented during code execution. This arrangement provides compatibility with data memory space addressing makes data program memory space accessible.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 devices reserve addresses between 0x00000 0x000200 hard-coded program execution vectors. hardware Reset vector provided redirect code execution from default value device Reset actual start code. GOTO instruction programmed user application 0x000000, with actual address start code 0x000002. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 devices also have interrupt vector tables, located from 0x000004 0x0000FF 0x000100 0x0001FF. These vector tables allow each device interrupt sources handled separate Interrupt Service Routines (ISRs). more detailed discussion interrupt vector tables provided Section "Interrupt Vector Table".
FIGURE 4-2:
Address 0x000001 0x000003 0x000005 0x000007
PROGRAM MEMORY ORGANIZATION
most significant word 00000000 00000000 00000000 00000000 Program Memory `Phantom' Byte (read `0') Instruction Width least significant word 0x000000 0x000002 0x000004 0x000006 Address (lsw Address)
DS70293C-page
2009 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
Data Address Space
word accesses must aligned even address. Misaligned word data fetches supported, care must taken when mixing byte word operations, translating from 8-bit code. misaligned read write attempted, address error trap generated. error occurred read, instruction underway completed. error occurred write, instruction executed write does occur. either case, trap then executed, allowing system and/or user application examine machine state prior execution address Fault. byte loads into register loaded into Least Significant Byte. Most Significant Byte modified. sign-extend instruction (SE) provided allow user applications translate 8-bit signed data 16-bit signed values. Alternatively, 16-bit unsigned data, user applications clear register executing zero-extend (ZE) instruction appropriate address.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 separate 16-bit-wide data memory space. data space accessed using separate Address Generation Units (AGUs) read write operations. data memory maps shown Figure Figure 4-4. Effective Addresses (EAs) data memory space bits wide point bytes within data space. This arrangement gives data space address range Kbytes words. lower half data memory space (that when EA<15> used implemented memory addresses, while upper half (EA<15> reserved Program Space Visibility area (see Section 4.4.3 "Reading Data From Program Memory Using Program Space Visibility"). PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 devices implement Kbytes data memory. Should point location outside this area, all-zero word byte returned.
4.2.1
DATA SPACE WIDTH
4.2.3
SPACE
data memory space organized byte addressable, 16-bit wide blocks. Data aligned data memory registers 16-bit words, data space resolve bytes. Least Significant Bytes (LSBs) each word have even addresses, while Most Significant Bytes (MSBs) have addresses.
first Kbytes Near Data Space, from 0x0000 0x07FF, primarily occupied Special Function Registers (SFRs). These used PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 core peripheral modules controlling operation device. SFRs distributed among modules that they control, generally grouped together module. Much space contains unused addresses; these read `0'. Note: actual peripheral features interrupts varies device. Refer corresponding device tables pinout diagrams device-specific information.
4.2.2
DATA MEMORY ORGANIZATION ALIGNMENT
maintain backward compatibility with PIC® devices improve data space memory usage efficiency, PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 instruction supports both word byte operations. consequence byte accessibility, effective address calculations internally scaled step through word-aligned memory. example, core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] results value byte operations word operations. data byte read, reads complete word that contains byte, using determine which byte select. selected byte placed onto data path. That data memory registers organized parallel byte-wide entities with shared (word) address decode separate write lines. Data byte writes only write corresponding side array register that matches byte address.
4.2.4
NEAR DATA SPACE
Kbyte area between 0x0000 0x1FFF referred near data space. Locations this space directly addressable 13-bit absolute address field within memory direct instructions. Additionally, whole data space addressable using instructions, which support Memory Direct Addressing mode with 16-bit address field, using Indirect Addressing mode using working register address pointer.
2009 Microchip Technology Inc.
DS70293C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
4.2.5
When controller attempt concurrently write same location, hardware ensures that given precedence accessing location. Therefore, provides reliable means transferring data without ever having stall CPU. Note: used general purpose data storage function required application.
PIC24HJ32GP302/304 devices contain Kbytes dual ported located data space. PIC24HJ64GPX02/X04 PIC24HJ128GPX02/X04 devices contain Kbytes dual ported located data space, part data space. Memory locations space accessible simultaneously controller module. utilized controller store data transferred various peripherals using DMA, well data transferred from various peripherals using DMA. accessed controller without having steal cycles from CPU.
FIGURE 4-3:
DATA MEMORY PIC24HJ32GP302/304 DEVICES WITH
Address 0x0000 Space 0x07FF 0x0801 0x07FE 0x0800 Kbyte Near Data Space 0x13FE 0x1400 0x17FE 0x1800 bits 0x0000 Address
Kbyte Space
Data Kbyte SRAM Space
0x13FF 0x1401 0x17FF 0x1801 0x8001
0x8000
Optionally Mapped into Program Memory
Data Unimplemented
0xFFFF
0xFFFE
DS70293C-page
2009 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
FIGURE 4-4: DATA MEMORY PIC24HJ128GP202/204, PIC24HJ64GP202/204, PIC24HJ128GP502/504, PIC24HJ64GP502/504 DEVICES WITH
Address Kbyte Space 0x0001 Space 0x07FF 0x0801 Data Kbyte SRAM Space 0x1FFF 0x2001 0x27FF 0x2801 0x1FFE 0x2000 0x27FE 0x2800 0x07FE 0x0800 Kbyte Near Data Space bits 0x0000 Address
0x8001
0x8000
Optionally Mapped into Program Memory
Data Unimplemented
0xFFFF
0xFFFE
2009 Microchip Technology Inc.
DS70293C-page
DS70293C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
TABLE 4-1:
Name WREG0 WREG1 WREG2 WREG3 WREG4 WREG5 WREG6 WREG7 WREG8 WREG9 WREG10 WREG11 WREG12 WREG13 WREG14 WREG15 SPLIM TBLPAG PSVPAG RCOUNT CORCON DISICNT Legend: Addr 0000 0002 0004 0006 0008 000A 000C 000E 0010 0012 0014 0016 0018 001A 001C 001E 0020 002E 0030 0032 0034 0036 0042 0044 0052
CORE REGISTERS
Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 xxxx 0000 Program Counter High Byte Register Table Page Address Pointer Register Program Memory Visibility Page Address Pointer Register IPL2 IPL1 IPL0 IPL3 0000 0000 0000 xxxx 0000 0000 xxxx
Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Stack Pointer Limit Register Program Counter Word Register Repeat Loop Counter Register
2009 Microchip Technology Inc.
Disable Interrupts Counter Register
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
2009 Microchip Technology Inc.
TABLE 4-2:
Name CNEN1 CNEN2 CNPU1 CNPU2 Legend: Addr 0060 0062 0068 006A
CHANGE NOTIFICATION REGISTER PIC24HJ128GP202/502, PIC24HJ64GP202/502, PIC24HJ32GP302
CN15IE CN14IE CN30IE CN13IE CN29IE CN12IE CN11IE CN27IE CN24IE CN7IE CN23IE CN7PUE CN6IE CN22IE CN6PUE CN5IE CN21IE CN5PUE CN4IE CN4PUE CN3IE CN3PUE CN2IE CN2PUE CN1IE CN1PUE CN0IE CN16IE CN0PUE CN16PUE Resets 0000 0000 0000 0000
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN30PUE CN29PUE CN27PUE
CN24PUE CN23PUE CN22PUE CN21PUE
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-3:
Name CNEN1 Addr 0060
CHANGE NOTIFICATION REGISTER PIC24HJ128GP204/504, PIC24HJ64GP204/504, PIC24HJ32GP304
CN15IE CN14IE CN30IE CN13IE CN29IE CN12IE CN28IE CN11IE CN27IE CN10IE CN26IE CN9IE CN25IE CN9PUE CN8IE CN24IE CN8PUE CN7IE CN23IE CN7PUE CN6IE CN22IE CN6PUE CN5IE CN21IE CN5PUE CN4IE CN20IE CN4PUE CN3IE CN19IE CN3PUE CN2IE CN18IE CN2PUE CN1IE CN17IE CN1PUE CN0IE CN16IE CN0PUE Resets 0000 0000 0000 0000
CNEN2 00C2 CNPU1 0068
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE
CNPU2 006A
CN30PUE CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE
DS70293C-page
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
DS70293C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
TABLE 4-4:
Name INTCON1 INTCON2 IFS0 IFS1 IFS2 IFS3 IFS4 IEC0 IEC1 IEC2 IEC3 IEC4 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC9 IPC11 IPC15 IPC16 IPC17 Legend: Note Addr 0080 0082 0084 0086 0088 008A 008C 0094 0096 0098 009A 009C 00A4 00A6 00A8 00AA 00AC 00AE 00B0 00B2 00B4 00B6 00BA 00C2 00C4 00C6
INTERRUPT CONTROLLER REGISTER
NSTDIS ALTIVT U2TXIF U2TXIE DISI DMA1IF U2RXIF DMA4IF RTCIF DMA1IE U2RXIE DMA4IE RTCIE AD1IF INT2IF PMPIF DMA5IF AD1IE INT2IE PMPIE DMA5IE T1IP<2:0> T2IP<2:0> U1RXIP<2:0> CNIP<2:0> IC8IP<2:0> T4IP<2:0> U2TXIP<2:0> C1IP<2:0>(1) CRCIP<2:0> U1TXIF T5IF U1TXIE T5IE U1RXIF T4IF U1RXIE T4IE SPI1IF OC4IF SPI1IE OC4IE SPI1EIF OC3IF SPI1EIE OC3IE OC1IP<2:0> OC2IP<2:0> SPI1IP<2:0> DMA1IP<2:0> CMIP<2:0> IC7IP<2:0> OC4IP<2:0> U2RXIP<2:0> C1RXIP<2:0>(1) DMA4IP<2:0> RTCIP<2:0> U2EIP<2:0> C1TXIP<2:0>(1) ILR<3:0>> T3IF DMA2IF T3IE DMA2IE T2IF IC8IF T2IE IC8IE INT0EP INT0IF SPI2EIF INT0IE SPI2EIE Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4444 4444 0444 4444 4404 4444 4444 4444 0004 0440 0440 4440 0444 4444
DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL OC2IF IC7IF C1TXIF(1) OC2IE IC7IE C1TXIE(1) IC2IF DMA7IF IC2IE DMA7IE IC1IP<2:0> IC2IP<2:0> SPI1EIP<2:0> AD1IP<2:0> MI2C1IP<2:0> OC3IP<2:0> INT2IP<2:0> SPI2IP<2:0> PMPIP<2:0> DMA5IP<2:0> U1EIP<2:0> DMA7IP<2:0> DMA0IF INT1IF DMA3IF DMA6IF DMA0IE INT1IE DMA3IE DMA6IE T1IF CNIF C1IF(1) CRCIF T1IE CNIE C1IE(1) CRCIE VECNUM<6:0> INT2EP OC1IF CMIF C1RXIF(1) U2EIF OC1IE CMIE C1RXIE(1) U2EIE INT1EP IC1IF SPI2IF U1EIF IC1IE SPI2IE U1EIE INT0IP<2:0> DMA0IP<2:0> T3IP<2:0> U1TXIP<2:0> SI2C1IP<2:0> INT1IP<2:0> DMA2IP<2:0> T5IP<2:0> SPI2EIP<2:0> DMA3IP<2:0> DMA6IP<2:0>
MI2C1IF SI2C1IF
MI2C1IE SI2C1IE
2009 Microchip Technology Inc.
INTTREG 00E0
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. Interrupts disabled devices without ECANmodules.
2009 Microchip Technology Inc.
TABLE 4-5:
Name TMR1 T1CON TMR2 TMR3HLD TMR3 T2CON T3CON TMR4 TMR5HLD TMR5 T4CON T5CON Legend: Addr 0100 0102 0104 0106 0108 010A 010C 010E 0110 0112 0114 0116 0118 011A 011C 011E 0120
TIMER REGISTER
Resets xxxx FFFF TGATE TCKPS<1:0> TSYNC 0000 xxxx xxxx xxxx FFFF FFFF TGATE TGATE TCKPS<1:0> TCKPS<1:0> 0000 0000 xxxx xxxx xxxx FFFF FFFF TGATE TGATE TCKPS<1:0> TCKPS<1:0> 0000 0000
Timer1 Register Period Register TSIDL Timer2 Register Timer3 Holding Register (for 32-bit timer operations only) Timer3 Register Period Register Period Register TSIDL TSIDL
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
Timer4 Register Timer5 Holding Register (for 32-bit timer operations only) Timer5 Register Period Register Period Register TSIDL TSIDL
DS70293C-page
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-6:
Name IC1BUF IC1CON IC2BUF IC2CON IC7BUF IC7CON IC8BUF IC8CON Legend: Addr 0140 0142 0144 0146 0158 015A 015C 015E
INPUT CAPTURE REGISTER
Resets xxxx ICI<1:0> ICI<1:0> ICI<1:0> ICI<1:0> ICOV ICOV ICOV ICOV ICBNE ICBNE ICBNE ICBNE ICM<2:0> ICM<2:0> ICM<2:0> ICM<2:0> 0000 xxxx 0000 xxxx 0000 xxxx 0000
Input Capture Register ICSIDL ICSIDL ICSIDL ICSIDL ICTMR ICTMR ICTMR ICTMR Input Capture Register Input Capture Register Input 8Capture Register
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
DS70293C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
TABLE 4-7:
Name OC1RS OC1R OC1CON OC2RS OC2R OC2CON OC3RS OC3R OC3CON OC4RS OC4R OC4CON Legend: Addr 0180 0182 0184 0186 0188 018A 018C 018E 0190 0192 0194 0196
OUTPUT COMPARE REGISTER
Resets xxxx xxxx OCFLT OCTSEL OCM<2:0> 0000 xxxx xxxx OCFLT OCTSEL OCM<2:0> 0000 xxxx xxxx OCFLT OCTSEL OCM<2:0> 0000 xxxx xxxx OCFLT OCTSEL OCM<2:0> 0000
Output Compare Secondary Register Output Compare Register OCSIDL Output Compare Secondary Register Output Compare Register OCSIDL Output Compare Secondary Register Output Compare Register OCSIDL Output Compare Secondary Register Output Compare Register OCSIDL
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
2009 Microchip Technology Inc.
TABLE 4-8:
Name I2C1RCV I2C1TRN I2C1BRG I2C1CON I2C1STAT I2C1ADD I2C1MSK Legend: Addr 0200 0202 0204 0206 0208 020A 020C
I2C1 REGISTER
I2CEN ACKSTAT TRSTAT I2CSIDL SCLREL IPMIEN A10M DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV ACKDT Resets 0000 00FF 0000 RSEN 1000 0000 0000 0000
Receive Register Transmit Register Baud Rate Generator Register ACKEN RCEN
Address Register Address Mask Register
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-9:
Name U1MODE U1STA U1TXREG U1RXREG U1BRG Legend: Addr 0220 0222 0224 0226 0228
UART1 REGISTER
UARTEN UTXISEL1 UTXINV USIDL UTXISEL0 IREN RTSMD UTXBRK UTXEN UEN1 UTXBF UEN0 TRMT UTX8 URX8 Baud Rate Generator Prescaler WAKE LPBACK ABAUD ADDEN URXINV RIDLE BRGH PERR STSEL URXDA Resets 0000 0110 xxxx 0000 0000
PDSEL<1:0> FERR OERR
URXISEL<1:0>
UART Transmit Register UART Received Register
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
2009 Microchip Technology Inc.
TABLE 4-10:
Name U2MODE U2STA U2TXREG U2RXREG U2BRG Legend: Addr 0230 0232 0234 0236 0238
UART2 REGISTER
UARTEN UTXISEL1 UTXINV USIDL UTXISEL0 IREN RTSMD UTXBRK UTXEN UEN1 UTXBF UEN0 TRMT UTX8 URX8 Baud Rate Generator Prescaler WAKE LPBACK ABAUD ADDEN URXINV RIDLE BRGH PERR STSEL URXDA Resets
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
PDSEL<1:0> FERR OERR
0000 0110 xxxx 0000 0000
URXISEL<1:0>
UART Transmit Register UART Receive Register
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-11:
Name SPI1STAT SPI1CON1 SPI1CON2 Addr 0240 0242 0244 0248
SPI1 REGISTER
SPIEN FRMEN SPIFSD SPISIDL FRMPOL DISSCK DISSDO MODE16 SSEN SPIROV MSTEN SPRE<2:0> SPITBF FRMDLY SPIRBF Resets 0000 0000 0000 0000
PPRE<1:0>
DS70293C-page
SPI1BUF Legend:
SPI1 Transmit Receive Buffer Register
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-12:
Name SPI2STAT SPI2CON1 SPI2CON2 SPI2BUF Legend: Addr 0260 0262 0264 0268
SPI2 REGISTER
SPIEN FRMEN SPIFSD SPISIDL FRMPOL DISSCK DISSDO MODE16 SSEN SPIROV MSTEN SPRE<2:0> SPITBF FRMDLY SPIRBF Resets 0000 0000 0000 0000
PPRE<1:0>
SPI2 Transmit Receive Buffer Register
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
DS70293C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
TABLE 4-13:
File Name ADC1BUF0 AD1CON1 AD1CON2 AD1CON3 AD1CHS123 AD1CHS0 AD1PCFGL AD1CSSL AD1CON4 Legend: Addr 0300 0320 0322 0324 0326 0328 032C 0330 0332
ADC1 REGISTER PIC24HJ64GP202/502, PIC24HJ128GP202/502 PIC24HJ32GP302
Resets xxxx SSRC<2:0> BUFS CH0NA PCFG9 CSS9 PCFG5 CSS5 PCFG4 CSS4 PCFG3 CSS3 SIMSAM ASAM SAMP BUFM CH123NA<1:0> CH0SA<4:0> PCFG2 CSS2 PCFG1 CSS1 DMABL<2:0> PCFG0 CSS0 DONE ALTS CH123SA 0000 0000 0000 0000 0000 0000 0000 0000 SMPI<3:0> ADCS<7:0> CH123SB
Data Buffer ADON ADRC CH0NB VCFG<2:0> PCFG12 CSS12 ADSIDL ADDMABM AD12B CSCNA SAMC<4:0> CH123NB<1:0> CH0SB<4:0> PCFG11 PCFG10 CSS11 CSS10 FORM<1:0> CHPS<1:0>
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-14:
File Name Addr 0300 0320 0322 0324 0326 0328 032C 0330 0332
ADC1 REGISTER PIC24HJ64GP204/504, PIC24HJ128GP204/504 PIC24HJ32GP304
Resets xxxx SSRC<2:0> BUFS CH0NA PCFG9 CSS9 PCFG8 CSS8 PCFG7 CSS7 PCFG6 CSS6 PCFG5 CSS5 PCFG4 CSS4 PCFG3 CSS3 SIMSAM ASAM SAMP BUFM CH123NA<1:0> CH0SA<4:0> PCFG2 CSS2 PCFG1 CSS1 DMABL<2:0> PCFG0 CSS0 DONE ALTS CH123SA 0000 0000 0000 0000 0000 0000 0000 0000 SMPI<3:0> ADCS<7:0> CH123SB
2009 Microchip Technology Inc.
ADC1BUF0 AD1CON1 AD1CON2 AD1CON3 AD1CHS123 AD1CHS0 AD1PCFGL AD1CSSL AD1CON4 Legend:
Data Buffer ADON ADRC CH0NB VCFG<2:0> PCFG12 CSS12 ADSIDL ADDMABM AD12B CSCNA SAMC<4:0> CH123NB<1:0> CH0SB<4:0> PCFG11 PCFG10 CSS11 CSS10 FORM<1:0> CHPS<1:0>
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
2009 Microchip Technology Inc.
TABLE 4-15:
File Name DMA0CON DMA0REQ DMA0STA DMA0STB DMA0PAD DMA0CNT DMA1CON DMA1REQ DMA1STA DMA1STB DMA1PAD DMA1CNT DMA2CON DMA2REQ DMA2STA DMA2STB DMA2PAD DMA2CNT DMA3CON DMA3REQ DMA3STA DMA3STB DMA3PAD DMA3CNT DMA4CON DMA4REQ DMA4STA DMA4STB DMA4PAD DMA4CNT Addr 0380 0382 0384 0386 0388 038A 038C 038E 0390 0392 0394 0396 0398 039A 039C 039E 03A0 03A2 03A4 03A6 03A8 03AA 03AC 03AE 03B0 03B2 03B4 03B6 03B8 03BA 03BC 03BE 03C0 03C2
REGISTER
CHEN FORCE SIZE HALF NULLW STA<15:0> STB<15:0> PAD<15:0> CHEN FORCE SIZE HALF NULLW STA<15:0> STB<15:0> PAD<15:0> CHEN FORCE SIZE HALF NULLW STA<15:0> STB<15:0> PAD<15:0> CHEN FORCE SIZE HALF NULLW STA<15:0> STB<15:0> PAD<15:0> CHEN FORCE SIZE HALF NULLW STA<15:0> STB<15:0> PAD<15:0> CHEN FORCE SIZE HALF NULLW STA<15:0> STB<15:0> CNT<9:0> AMODE<1:0> IRQSEL<6:0> MODE<1:0> CNT<9:0> AMODE<1:0> IRQSEL<6:0> MODE<1:0> CNT<9:0> AMODE<1:0> IRQSEL<6:0> MODE<1:0> CNT<9:0> AMODE<1:0> IRQSEL<6:0> MODE<1:0> CNT<9:0> AMODE<1:0> IRQSEL<6:0> MODE<1:0> IRQSEL<6:0> Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
AMODE<1:0>
MODE<1:0>
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
DS70293C-page
DMA5CON DMA5REQ DMA5STA DMA5STB Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-15:
File Name DMA5PAD DMA5CNT DMA6CON DMA6REQ DMA6STA DMA6STB DMA6PAD DMA6CNT DMA7CON DMA7REQ DMA7STA DMA7STB DMA7PAD DMA7CNT DMACS0 DMACS1 DSADR Legend: Addr 03C4 03C6 03C8 03CA 03CC 03CE 03D0 03D2 03D4 03D6 03D8 03DA 03DC 03DE 03E0 03E2 03E4
REGISTER (CONTINUED)
PAD<15:0> CHEN FORCE SIZE HALF NULLW STA<15:0> STB<15:0> PAD<15:0> CHEN FORCE SIZE HALF NULLW STA<15:0> STB<15:0> PAD<15:0> XWCOL7 PPST7 DSADR<15:0> XWCOL6 PPST6 LSTCH<3:0> CNT<9:0> XWCOL5 PPST5 XWCOL4 PPST4 XWCOL3 PPST3 XWCOL2 PPST2 XWCOL1 PPST1 XWCOL0 PPST0 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0 CNT<9:0> AMODE<1:0> IRQSEL<6:0> MODE<1:0> CNT<9:0> AMODE<1:0> IRQSEL<6:0> MODE<1:0> Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
DS70293C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
2009 Microchip Technology Inc.
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-16:
File Name C1CTRL1 C1CTRL2 C1VEC C1FCTRL C1FIFO C1INTF C1INTE C1EC C1CFG1 C1CFG2 C1FEN1 C1FMSKSEL1 C1FMSKSEL2 Legend:
ECAN1 REGISTER WHEN C1CTRL1.WIN (FOR PIC24HJ128GP502/504 PIC24HJ64GP502/504)
FLTEN15 DMABS<2:0> WAKFIL FLTEN14 TXBO FLTEN13 TXBP FLTEN12 CSIDL FBP<5:0> RXBP FLTEN11 F5MSK<1:0> F13MSK<1:0> TXWAR FLTEN10 RXWAR SEG2PH<2:0> FLTEN9 FLTEN8 F4MSK<1:0> F12MSK<1:0> EWARN ABAT FILHIT<4:0> REQOP<2:0> IVRIF IVRIE WAKIF WAKIE ERRIF ERRIE FIFOIF FIFOIE OPMODE<2:0> CANCAP ICODE<6:0> FSA<4:0> FNRB<5:0> RBOVIF RBOVIE RBIF RBIE TBIF TBIE Resets 0480
2009 Microchip Technology Inc.
Addr 0400 0402 0404 0406 0408 040A 040C 040E 0410 0412 0414 0418 041A
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
DNCNT<4:0>
0000 0000 0000 0000 0000 0000 0000 0000
TERRCNT<7:0> SJW<1:0> SEG2PHTS FLTEN7 FLTEN6
RERRCNT<7:0> BRP<5:0> SEG1PH<2:0> FLTEN5 FLTEN4 FLTEN3 F2MSK<1:0> F10MSK<1:0> F1MSK<1:0> F9MSK<1:0> PRSEG<2:0> FLTEN2 FLTEN1 FLTEN0 F0MSK<1:0> F8MSK<1:0>
0000 FFFF 0000 0000
F7MSK<1:0> F15MSK<1:0>
F6MSK<1:0> F14MSK<1:0>
F3MSK<1:0> F11MSK<1:0>
unimplemented, read `0'. Reset values shown hexadecimal.
DS70293C-page
TABLE 4-17:
File Name Addr 0400041E C1RXFUL1 C1RXFUL2 C1RXOVF1 C1RXOVF2 0420 0422 0428
ECAN1 REGISTER WHEN C1CTRL1.WIN (FOR PIC24HJ128GP502/504 PIC24HJ64GP502/504)
Resets
definition when RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 RXOVF8 RXFUL7 RXOVF7 TXEN0 TXEN2 TXEN4 TXEN6 RXFUL6 RXOVF6 TXABT0 TXABT2 TXABT4 TXABT6 RXFUL5 RXOVF5 TXLARB0 TXLARB2 TXLARB4 TXLARB6 RXFUL4 RXOVF4 TXERR0 TXERR2 TXERR4 TXERR6 RXFUL3 RXOVF3 TXREQ0 TXREQ2 TXREQ4 TXREQ6 RXFUL2 RXOVF2 RTREN0 RTREN2 RTREN4 RTREN6 RXFUL1 RXOVF1 RXFUL0 RXOVF0 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx
RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 TXEN1 TXEN3 TXEN5 TXEN7 TXABT1 TXABT3 TXABT5 TXABT7 TXLARB1 TXLARB3 TXLARB5 TXLARB7 TXERR1 TXERR3 TXERR5 TXERR7 TXREQ1 TXREQ3 TXREQ5 TXREQ7 RTREN1 RTREN3 RTREN5 RTREN7
042A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 TX1PRI<1:0> TX3PRI<1:0> TX5PRI<1:0> TX7PRI<1:0> TX0PRI<1:0> TX2PRI<1:0> TX4PRI<1:0> TX6PRI<1:0>
C1TR01CON 0430 C1TR23CON 0432 C1TR45CON 0434 C1TR67CON 0436 C1RXD C1TXD Legend: 0440 0442
Received Data Word Transmit Data Word
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
DS70293C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
TABLE 4-18:
File Name
ECAN1 REGISTER WHEN C1CTRL1.WIN (FOR PIC24HJ128GP502/504 PIC24HJ64GP502/504)
Resets
Addr 0400041E
definition when F3BP<3:0> F7BP<3:0> F11BP<3:0> F15BP<3:0> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> F2BP<3:0> F6BP<3:0> F10BP<3:0> F14BP<3:0> F1BP<3:0> F5BP<3:0> F9BP<3:0> F13BP<3:0> SID<2:0> MIDE MIDE MIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EID<7:0> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0> F0BP<3:0> F4BP<3:0> F8BP<3:0> F12BP<3:0> EID<17:16> 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
C1BUFPNT1 C1BUFPNT2 C1BUFPNT3 C1BUFPNT4 C1RXM0SID C1RXM0EID C1RXM1SID C1RXM1EID C1RXM2SID C1RXM2EID C1RXF0SID C1RXF0EID C1RXF1SID C1RXF1EID C1RXF2SID C1RXF2EID C1RXF3SID C1RXF3EID C1RXF4SID C1RXF4EID C1RXF5SID C1RXF5EID C1RXF6SID C1RXF6EID
0420 0422 0424 0426 0430 0432 0434 0436 0438 043A 0440 0442 0444 0446 0448 044A 044C 044E 0450 0452 0454 0456 0458 045A 045C 045E 0460 0462 0464 0466 0468 046A
2009 Microchip Technology Inc.
C1RXF7SID C1RXF7EID C1RXF8SID C1RXF8EID C1RXF9SID C1RXF9EID C1RXF10SID C1RXF10EID Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-18:
File Name C1RXF11SID C1RXF11EID C1RXF12SID C1RXF12EID C1RXF13SID C1RXF13EID C1RXF14SID C1RXF14EID C1RXF15SID C1RXF15EID Legend:
ECAN1 REGISTER WHEN C1CTRL1.WIN (FOR PIC24HJ128GP502/504 PIC24HJ64GP502/504) (CONTINUED)
SID<2:0> SID<2:0> SID<2:0> SID<2:0> SID<2:0> EXIDE EXIDE EXIDE EXIDE EXIDE Resets xxxx
2009 Microchip Technology Inc.
Addr 046C 046E 0470 0472 0474 0476 0478 047A 047C 047E
SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8> SID<10:3> EID<15:8>
EID<17:16> EID<17:16> EID<17:16> EID<17:16> EID<17:16>
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
EID<7:0> EID<7:0> EID<7:0> EID<7:0> EID<7:0>
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-19:
File Name RPINR0 RPINR1 RPINR3 RPINR4 RPINR7 RPINR10 RPINR11 RPINR18 RPINR19 RPINR20 RPINR21 RPINR22 RPINR23 RPINR26(1) Addr 0680 0682 0686 0688 068E 0694 0696 06A4 06A6 06A8 06AA 06AC 06AE 06B4
PERIPHERAL SELECT INPUT REGISTER
INT1R<4:0> T3CKR<4:0> T5CKR<4:0> IC2R<4:0> IC8R<4:0> U1CTSR<4:0> U2CTSR<4:0> SCK1R<4:0> SCK2R<4:0> INT2R<4:0> T2CKR<4:0> T4CKR<4:0> IC1R<4:0> IC7R<4:0> OCFAR<4:0> U1RXR<4:0> U2RXR<4:0> SDI1R<4:0> SS1R<4:0> SDI2R<4:0> SS2R<4:0> C1RXR<4:0> Resets 1F00 001F 1F1F 1F1F 1F1F 1F1F 001F 1F1F 1F1F 1F1F 001F 1F1F 001F 001F
DS70293C-page
Legend: Note
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. This register present PIC24HJ128GP502/504 PIC24HJ64GP502/504 devices only.
DS70293C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
TABLE 4-20:
File Name RPOR0 RPOR1 RPOR2 RPOR3 RPOR4 RPOR5 RPOR6 RPOR7 Legend: Addr 06C0 06C2 06C4 06C6 06C8 06CA 06CC 06CE
PERIPHERAL SELECT OUTPUT REGISTER PIC24HJ128GP202/502, PIC24HJ64GP202/502 PIC24HJ32GP302
RP1R<4:0> RP3R<4:0> RP5R<4:0> RP7R<4:0> RP9R<4:0> RP11R<4:0> RP13R<4:0> RP15R<4:0> RP0R<4:0> RP2R<4:0> RP4R<4:0> RP6R<4:0> RP8R<4:0> RP10R<4:0> RP12R<4:0> RP14R<4:0> Resets 0000 0000 0000 0000 0000 0000 0000 0000
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-21:
PERIPHERAL SELECT OUTPUT REGISTER PIC24HJ128GP204/504, PIC24HJ64GP204/504 PIC24HJ32GP304
RP1R<4:0> RP3R<4:0> RP5R<4:0> RP7R<4:0> RP9R<4:0> RP11R<4:0> RP13R<4:0> RP15R<4:0> RP17R<4:0> RP19R<4:0> RP21R<4:0> RP23R<4:0> RP25R<4:0> RP0R<4:0> RP2R<4:0> RP4R<4:0> RP6R<4:0> RP8R<4:0> RP10R<4:0> RP12R<4:0> RP14R<4:0> RP16R<4:0> RP18R<4:0> RP20R<4:0> RP22R<4:0> RP24R<4:0> Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
2009 Microchip Technology Inc.
File Name RPOR0 RPOR1 RPOR2 RPOR3 RPOR4 RPOR5 RPOR6 RPOR7 RPOR8 RPOR9 RPOR10 RPOR11 RPOR12 Legend:
Addr 06C0 06C2 06C4 06C6 06C8 06CA 06CC 06CE 06D0 06D2 06D4 06D6 06D8
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
2009 Microchip Technology Inc.
TABLE 4-22:
File Name PMCON PMMODE PMADDR PMDOUT1 PMDOUT2 PMDIN1 PMPDIN2 PMAEN PMSTAT Legend: Addr 0600 0602 0604 0606 0608 060A 060C 060E
PARALLEL MASTER/SLAVE PORT REGISTER PIC24HPIC24HJ128GP202/502, PIC24HJ64GP202/502 PIC24HJ32GP302
PMPEN BUSY ADDR15 PSIDL PTBEEN MODE16 CSF1 CSF0 CS1P WRSP RDSP Resets
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
ADRMUX<1:0> INCM<1:0>
PTWREN PTRDEN MODE<1:0>
0000 0000 0000 0000 0000 0000 0000
IRQM<1:0>
WAITB<1:0> ADDR<13:0>
WAITM<3:0>
WAITE<1:0>
Parallel Port Data Register (Buffers Parallel Port Data Register (Buffers Parallel Port Data Register (Buffers Parallel Port Data Register (Buffers PTEN14 IBOV IB3F IB2F IB1F IB0F OBUF OB3E OB2E PTEN<1:0> OB1E OB0E
0000 0000
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-23:
PARALLEL MASTER/SLAVE PORT REGISTER PIC24HJ128GP204/504, PIC24HJ64GP204/504 PIC24HJ32GP304
PMPEN BUSY ADDR15 PSIDL PTBEEN MODE16 CSF1 CSF0 CS1P WRSP RDSP Resets 0000 0000 0000 0000 0000 0000 0000 0000 OB3E OB2E OB1E OB0E 0000
DS70293C-page
File Name PMCON PMMODE PMADDR PMDOUT1 PMDOUT2 PMDIN1 PMPDIN2 PMAEN PMSTAT Legend:
Addr 0600 0602 0604 0606 0608 060A 060C 060E
ADRMUX<1:0> INCM<1:0>
PTWREN PTRDEN MODE<1:0>
IRQM<1:0>
WAITB<1:0> ADDR<13:0>
WAITM<3:0>
WAITE<1:0>
Parallel Port Data Register (Buffers Parallel Port Data Register (Buffers Parallel Port Data Register (Buffers Parallel Port Data Register (Buffers PTEN14 IBOV IB3F IB2F IB1F IB0F OBUF PTEN<10:0>
unimplemented, read `0'. Reset values shown hexadecimal.
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PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
TABLE 4-24:
File Name ALRMVAL ALCFGRPT RTCVAL RCFGCAL Legend: Addr 0620 0622 0624 0626
REAL-TIME CLOCK CALENDAR REGISTER
Resets xxxx ARPT<7:-0> CAL<7:0> 0000 xxxx 0000
Alarm Value Register Window based APTR<1:0> ALRMEN RTCEN CHIME AMASK<3:0> RTCWREN RTCSYNC HALFSEC RTCOE ALRMPTR<1:0> RTCC Value Register Window based RTCPTR<1:0> RTCPTR<1:0>
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-25:
File Name CRCCON CRCXOR CRCDAT CRCWDAT Legend: Addr 0640 0642 0644 0646
REGISTER
CSIDL VWORD<4:0> CRCFUL X<15:0> Data Input Register Result Register CRCMPT CRCGO Resets 0000 0000 0000 0000
PLEN<3:0>
unimplemented, read `0'. Reset values shown hexadecimal.
2009 Microchip Technology Inc.
TABLE 4-26:
File Name CMCON CVRCON Legend: Addr 0630 0632
DUAL COMPARATOR REGISTER
CMIDL C2EVT C1EVT C2EN C1EN C2OUTEN C1OUTEN C2OUT CVREN C1OUT CVROE C2INV CVRR C1INV CVRSS C2NEG C2POS C1NEG C1POS Resets 0000 0000
CVR<3:0>
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-27:
File Name TRISA PORTA LATA ODCA Legend: Addr 02C0 02C2 02C4 02C6
PORTA REGISTER PIC24HJ128GP202/502, PIC24HJ64GP202/502 PIC24HJ32GP302
TRISA4 LATA4 TRISA3 LATA3 TRISA2 LATA2 TRISA1 LATA1 TRISA0 LATA0 Resets 079F xxxx xxxx 0000
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
2009 Microchip Technology Inc.
TABLE 4-28:
File Name TRISA PORTA LATA ODCA Legend: Addr 02C0 02C2 02C4 02C6
PORTA REGISTER PIC24HJ128GP204/504, PIC24HJ64GP204/504 PIC24HJ32GP304
TRISA10 RA10 LATA10 ODCA10 TRISA9 LATA9 ODCA9 TRISA8 LATA8 ODCA8 TRISA7 LATA7 ODCA7 TRISA4 LATA4 TRISA3 LATA3 TRISA2 LATA2 TRISA1 LATA1 TRISA0 LATA0 Resets 079F xxxx xxxx 0000
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-29:
File Name TRISB PORTB LATB ODCB Legend: Addr 02C8 02CA 02CC 02CE
PORTB REGISTER
TRISB15 RB15 LATB15 TRISB14 RB14 LATB14 TRISB13 RB13 LATB13 TRISB12 RB12 LATB12 TRISB11 RB11 LATB11 ODCB11 TRISB10 RB10 LATB10 ODCB10 TRISB9 LATB9 ODCB9 TRISB8 LATB8 ODCB8 TRISB7 LATB7 ODCB7 TRISB6 LATB6 ODCB6 TRISB5 LATB5 ODCB5 TRISB4 LATB4 TRISB3 LATB3 TRISB2 LATB2 TRISB1 LATB1 TRISB0 LATB0 Resets FFFF xxxx xxxx 0000
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
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TABLE 4-30:
File Name TRISC PORTC LATC ODCC Legend: Addr 02D0 02D2 02D4 02D6
PORTC REGISTER PIC24HJ128GP204/504, PIC24HJ64GP204/504 PIC24HJ32GP304
TRISC9 LATC9 ODCC9 TRISC8 LATC8 ODCC8 TRISC7 LATC7 ODCC7 TRISC6 LATC6 ODCC6 TRISC5 LATC5 ODCC5 TRISC4 LATC4 ODCC4 TRISC3 LATC3 ODCC3 TRISC2 LATC2 TRISC1 LATC1 TRISC0 LATC0 Resets 03FF xxxx xxxx 0000
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-31:
File Name RCON OSCCON CLKDIV PLLFBD OSCTUN Legend: Note Addr 0740 0742 0744 0746 0748
SYSTEM CONTROL REGISTER
TRAPR IOPUWR COSC<2:0> DOZE<2:0> DOZEN NOSC<2:0> FRCDIV<2:0> VREGS EXTR CLKLOCK IOLOCK SWDTEN LOCK PLLDIV<8:0> TUN<5:0> WDTO SLEEP IDLE PLLPRE<4::0> LPOSCEN OSWEN Resets xxxx(1) 0300(2) 3040 0030 0000
PLLPOST<1:0>
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. RCON register Reset values dependent type Reset. OSCCON register Reset values dependent FOSC Configuration bits type Reset.
TABLE 4-32:
File Name BSRAM SSRAM Legend: Note Addr 0750 0752
SECURITY REGISTER MAP(1)
IW_BSR IR_BSR IR_SSR RL_BSR RL_SSR Resets 0000 0000
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unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. This register present devices with Flash (PIC24HJ32GP302/304).
TABLE 4-33:
File Name NVMCON NVMKEY Legend: Addr 0760 0766
REGISTER
WREN WRERR ERASE NVMKEY<7:0> Resets 0000 0000
NVMOP<3:0>
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-34:
File Name PMD1 PMD2 PMD3 Legend: Addr 0770 0772 0774
REGISTER
T5MD IC8MD T4MD IC7MD T3MD T2MD T1MD CMPMD IC2MD RTCCMD IC1MD PMPMD I2C1MD CRCMD U2MD U1MD SPI2MD SPI1MD OC4MD OC3MD C1MD OC2MD AD1MD OC1MD Resets 0000 0000 0000
2009 Microchip Technology Inc.
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
4.2.6 SOFTWARE STACK 4.2.7 DATA PROTECTION FEATURE
addition working register, register PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 devices also used software Stack Pointer. Stack Pointer always points first available free word grows from lower higher addresses. pre-decrements stack pops post-increments stack pushes, shown Figure 4-5. push during CALL instruction, zero-extended before push, ensuring that always clear. Note: push during exception processing concatenates register prior push.
PIC24H product family supports Data protection features that enable segments protected when used conjunction with Boot Secure Code Segment Security. BSRAM (Secure segment accessible only from Boot Segment Flash code when enabled. SSRAM (Secure segment RAM) accessible only from Secure Segment Flash code when enabled. Table overview BSRAM SSRAM SFRs.
Instruction Addressing Modes
Stack Pointer Limit register (SPLIM) associated with Stack Pointer sets upper address boundary stack. SPLIM uninitialized Reset. case Stack Pointer, SPLIM<0> forced because stack operations must word aligned. Whenever generated using source destination pointer, resulting address compared with value SPLIM. contents Stack Pointer (W15) SPLIM register equal push operation performed, stack error trap does occur. stack error trap occurs subsequent push operation. example, cause stack error trap when stack grows beyond address 0x2000 RAM, initialize SPLIM with value 0x1FFE. Similarly, Stack Pointer underflow (stack error) trap generated when Stack Pointer address found less than 0x0800. This prevents stack from interfering with Special Function Register (SFR) space. write SPLIM register should immediately followed indirect read operation using W15.
addressing modes shown Table 4-35 form basis addressing modes optimized support specific features individual instructions. addressing modes provided class instructions differ from those other instruction types.
4.3.1
FILE REGISTER INSTRUCTIONS
Most file register instructions 13-bit address field directly address data present first 8192 bytes data memory (near data space). Most file register instructions employ working register, which denoted WREG these instructions. destination typically either same file register WREG (with exception instruction), which writes result register register pair. instruction allows additional flexibility access entire data space.
4.3.2
INSTRUCTIONS
three-operand instructions form: Operand Operand <function> Operand where Operand always working register (that addressing mode only register direct), which referred Operand register, fetched from data memory, 5-bit literal. result location either register data memory location. following addressing modes supported instructions: Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified 5-bit 10-bit Literal Note: instructions support addressing modes given above. Individual instructions support different subsets these addressing modes.
FIGURE 4-5:
0x0000
CALL STACK FRAME
Stack Grows Toward Higher Address
PC<15:0> 000000000 PC<22:16> <Free Word>
(before CALL) (after CALL) [-W15] PUSH [W15++]
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TABLE 4-35: FUNDAMENTAL ADDRESSING MODES SUPPORTED
Description address file register specified explicitly. contents register accessed directly. contents forms Effective Address (EA). contents forms post-modified (incremented decremented) constant value. pre-modified (incremented decremented) signed constant value form
Addressing Mode File Register Direct Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified
Register Indirect with Register Offset forms (Register Indexed) Register Indirect with Literal Offset literal forms
4.3.3
MOVE (MOV) INSTRUCTION
Move instructions provide greater degree addressing flexibility than other instructions. addition Addressing modes supported most instructions, instructions also support Register Indirect with Register Offset Addressing mode, also referred Register Indexed mode. Note: instructions, addressing mode specified instruction differ source destination However, 4-bit (Register Offset) field shared both source destination (but typically only used one).
summary, following addressing modes supported move instructions: Register Direct Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset (Indexed) Register Indirect with Literal Offset 8-bit Literal 16-bit Literal Note: instructions support addressing modes given above. Individual instructions support different subsets these addressing modes.
4.3.4
OTHER INSTRUCTIONS
Besides addressing modes outlined previously, some instructions literal constants various sizes. example, (branch) instructions 16-bit signed literals specify branch destination directly, whereas DISI instruction uses 14-bit unsigned literal field. some instructions, such Acc, source operand result implied opcode itself. Certain operations, such NOP, have operands.
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Interfacing Program Data Memory Spaces
4.4.1 ADDRESSING PROGRAM SPACE
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 architecture uses 24-bit-wide program space 16-bit-wide data space. architecture also modified Harvard scheme, meaning that data also present program space. this data successfully, must accessed that preserves alignment information both spaces. Aside from normal execution, PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 architecture provides methods which program space accessed during operation: Using table instructions access individual bytes words anywhere program space Remapping portion program space into data space (Program Space Visibility) Table instructions allow application read write small areas program memory. This capability makes method ideal accessing data tables that need updated periodically. also allows access bytes program word. remapping method allows application access large block data read-only basis, which ideal look-ups from large table static data. application only access least significant word program word.
Since address ranges data program spaces bits, respectively, method needed create 23-bit 24-bit program address from 16-bit data registers. solution depends interface method used. table operations, 8-bit Table Page register (TBLPAG) used define word region within program space. This concatenated with 16-bit arrive full 24-bit program space address. this format, Most Significant TBLPAG used determine operation occurs user memory (TBLPAG<7> configuration memory (TBLPAG<7> remapping operations, 8-bit Program Space Visibility register (PSVPAG) used define word page program space. When Most Significant `1', PSVPAG concatenated with lower bits form 23-bit program space address. Unlike table operations, this limits remapping operations strictly user memory area. Table 4-36 Figure show program created table operations remapping accesses from data Here, P<23:0> refers program space word, D<15:0> refers data space word.
TABLE 4-36:
PROGRAM SPACE ADDRESS CONSTRUCTION
Access Space User User Configuration Program Space Address <23> TBLPAG<7:0> 0xxx xxxx TBLPAG<7:0> 1xxx xxxx PSVPAG<7:0> xxxx xxxx <22:16> <15> PC<22:1> xxxx xxxx xxxx xxxx xxx0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<14:0>(1) xxxx xxxx xxxx <14:1>
Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write)
Program Space Visibility (Block Remap/Read) Note
User
Data EA<15> always this case, used calculating program space address. address PSVPAG<0>.
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FIGURE 4-6: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter bits
Table Operations(2)
TBLPAG bits bits bits
Select Program Space Visibility(1) (Remapping) PSVPAG bits
bits bits
User/Configuration Space Select
Byte Select
Note Least Significant (LSb) program space addresses always fixed maintain word alignment data program data spaces. Table operations required word aligned. Table read operations permitted configuration memory space.
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PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
4.4.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS
Byte mode, either upper lower byte lower program word mapped lower byte data address. upper byte selected when Byte Select `1'; lower byte selected when `0'. TBLRDH (Table Read High): Word mode, this instruction maps entire upper word program address (P<23:16>) data address. `phantom' byte (D<15:8>), always `0'. Byte mode, this instruction maps upper lower byte program word D<7:0> data address, TBLRDL instruction. data always when upper `phantom' byte selected (Byte Select similar fashion, table instructions, TBLWTH TBLWTL, used write individual bytes words program space address. details their operation explained Section "Flash Program Memory". table operations, area program memory space accessed determined Table Page register (TBLPAG). TBLPAG covers entire program memory space device, including user application configuration spaces. When TBLPAG<7> table page located user memory space. When TBLPAG<7> page located configuration space.
TBLRDL TBLWTL instructions offer direct method reading writing lower word address within program space without going through data space. TBLRDH TBLWTH instructions only method read write upper bits program space word data. incremented each successive 24-bit program word. This allows program memory addresses directly data space addresses. Program memory thus regarded 16-bit-wide word address spaces, residing side side, each with same address range. TBLRDL TBLWTL access space that contains least significant data word. TBLRDH TBLWTH access space that contains upper data byte. table instructions provided move byte word-sized (16-bit) data from program space. Both function either byte word operations. TBLRDL (Table Read Low): Word mode, this instruction maps lower word program space location (P<15:0>) data address (D<15:0>).
FIGURE 4-7:
TBLPAG
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
0x000000
00000000 00000000 00000000 00000000
0x020000 0x030000
`Phantom' Byte
TBLRDH.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.W
address table operation determined data within page defined TBLPAG register. Only read operations shown; write operations also valid user memory area.
0x800000
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PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
4.4.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY
24-bit program word used contain data. upper bits program space location used data should programmed with `1111 1111' `0000 0000' force NOP. This prevents possible issues should area code ever accidentally executed. Note: access temporarily disabled during table reads/writes.
upper Kbytes data space optionally mapped into word page program space. This option provides transparent access stored constant data from data space without need special instructions (such TBLRDL/H). Program space access through data space occurs Most Significant data space program space visibility enabled setting Core Control register (CORCON<2>). location program memory space mapped into data space determined Program Space Visibility Page register (PSVPAG). This 8-bit register defines possible pages words program space. effect, PSVPAG functions upper bits program memory address, with bits functioning lower bits. incrementing each program memory word, lower bits data space addresses directly lower bits corresponding program space addresses. Data reads this area cycle instruction being executed, since program memory fetches required. Although each data space address 8000h higher maps directly into corresponding program memory address (see Figure 4-8), only lower bits
operations that executed outside REPEAT loop, MOV.D instructions require instruction cycle addition specified execution time. other instructions require instruction cycles addition specified execution time. operations that PSV, executed inside REPEAT loop, these instances require instruction cycles addition specified execution time instruction: Execution first iteration Execution last iteration Execution prior exiting loop interrupt Execution upon re-entering loop after interrupt serviced other iteration REPEAT loop allows instruction using access data, execute single cycle.
FIGURE 4-8:
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> EA<15>
Program Space
PSVPAG 0x000000 0x010000 0x018000 data page designated PSVPAG mapped into upper half data memory space.
Data Space
0x0000 Data EA<14:0>
0x8000
Area .while lower bits specify exact address within 0xFFFF area. This corresponds exactly same lower bits actual program space address.
0x800000
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PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
Note:
FLASH PROGRAM MEMORY
This data sheet summarizes features PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 families devices. intended comprehensive reference source. complement information this data sheet, refer "PIC24H Family Reference Manual", Section "Flash Programming" (DS70228), which available from Microchip website (www.microchip.com).
with unprogrammed devices then program microcontroller just before shipping product. This also allows most recent firmware custom firmware programmed. RTSP accomplished using TBLRD (table read) TBLWT (table write) instructions. With RTSP, user application write program memory data either blocks `rows' instructions (192 bytes) time single program memory word, erase program memory blocks `pages' instructions (1536 bytes) time.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 devices contain internal Flash program memory storing executing application code. memory readable, writable erasable during normal operation over entire range. Flash memory programmed ways: In-Circuit Serial Programming(ICSPTM) programming capability Run-Time Self-Programming (RTSP) ICSP allows PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 devices serially programmed while application circuit. This done with lines programming clock programming data (one alternate programming pairs: PGEC1/PGED1, PGEC2/PGED2 PGEC3/PGED3), three other lines power (VDD), ground (VSS) Master Clear (MCLR). This allows customers manufacture boards
Table Instructions Flash Programming
Regardless method used, programming Flash memory done with table read table write instructions. These allow direct read write access program memory space from data memory while device normal operating mode. 24-bit target address program memory formed using bits <7:0> TBLPAG register Effective Address (EA) from register specified table instruction, shown Figure 5-1. TBLRDL TBLWTL instructions used read write bits <15:0> program memory. TBLRDL TBLWTL access program memory both Word Byte modes. TBLRDH TBLWTH instructions used read write bits <23:16> program memory. TBLRDH TBLWTH also access program memory Word Byte mode.
FIGURE 5-1:
ADDRESSING TABLE REGISTERS
bits Using Program Counter Program Counter
Working Using Table Instruction TBLPAG bits bits
User/Configuration Space Select
24-bit
Byte Select
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RTSP Operation Programming Operations
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 Flash program memory array organized into rows instructions bytes. RTSP allows user application erase page memory, which consists eight rows (512 instructions) time, program word time. Table 28-12 shows typical erase programming times. 8-row erase pages single write rows edge-aligned from beginning program memory, boundaries 1536 bytes bytes, respectively. program memory implements holding buffers that contain instructions programming data. Prior actual programming operation, write data must loaded into buffers sequentially. instruction words loaded must always from group boundary. basic sequence RTSP programming Table Pointer, then series TBLWT instructions load buffers. Programming performed setting control bits NVMCON register. total TBLWTL TBLWTH instructions required load instructions. table write operations single-word writes (two instruction cycles) because only buffers written. programming cycle required programming each row.
complete programming sequence necessary programming erasing internal Flash RTSP mode. processor stalls (waits) until programming operation finished. programming time depends accuracy (see Table 28-19) value Oscillator Tuning register (see Register 9-4). following formula calculate minimum maximum values Write Time, Page Erase Time, Word Write Cycle Time parameters (see Table 28-12).
EQUATION 5-1:
PROGRAMMING TIME
-7.37 Accuracy Tuning example, device operating +125°C, accuracy will ±5%. TUN<5:0> bits (see Register 9-4) `b111111, Minimum Write Time 11064 Cycles 1.435ms 7.37 0.05 0.00375 and, Maximum Write Time 11064 Cycles 1.586ms 7.37 0.05 0.00375 Setting (NVMCON<15>) starts operation, automatically cleared when operation finished.
Control Registers
SFRs used read write program Flash memory: NVMCON NVMKEY. NVMCON register (Register 5-1) controls which blocks erased, which memory type programmed start programming cycle. NVMKEY (Register 5-2) write-only register that used write protection. start programming erase sequence, user application must consecutively write 0x55 0xAA NVMKEY register. Refer Section "Programming Operations" further details.
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REGISTER 5-1:
R/SO-0(1) Legend: Readable Value Settable only Writable Unimplemented bit, read cleared unknown R/W-0(1) ERASE R/W-0(1) R/W-0(1) R/W-0(1)
NVMCON: FLASH MEMORY CONTROL REGISTER
R/W-0(1) WREN R/W-0(1) WRERR R/W-0(1)
NVMOP<3:0>(2)
Write Control Initiates Flash memory program erase operation. operation self-timed cleared hardware once operation complete Program erase operation complete inactive WREN: Write Enable Enable Flash program/erase operations Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag improper program erase sequence attempt termination occurred (bit automatically attempt bit) program erase operation completed normally Unimplemented: Read ERASE: Erase/Program Enable Perform erase operation specified NVMOP<3:0> next command Perform program operation specified NVMOP<3:0> next command Unimplemented: Read NVMOP<3:0>: Operation Select bits(2) ERASE 1111 Memory bulk erase operation 1110 Reserved 1101 Erase General Segment 1100 Erase Secure Segment 1011 Reserved 0011 operation 0010 Memory page erase operation 0001 operation 0000 Erase single Configuration register byte ERASE 1111 operation 1110 Reserved 1101 operation 1100 operation 1011 Reserved 0011 Memory word program operation 0010 operation 0001 Memory program operation 0000 Program single Configuration register byte
12-7
Note These bits only reset POR. other combinations NVMOP<3:0> unimplemented.
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REGISTER 5-2:
Legend: Readable Value 15-8
NVMKEY: NONVOLATILE MEMORY REGISTER
NVMKEY<7:0>
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read NVMKEY<7:0>: Register (write-only) bits
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5.4.1 PROGRAMMING ALGORITHM FLASH PROGRAM MEMORY
Write first instructions from data into program memory buffers (see Example 5-2). Write program block Flash memory: NVMOP bits `0001' configure programming. Clear ERASE WREN bit. Write 0x55 NVMKEY. Write 0xAA NVMKEY. bit. programming cycle begins stalls duration write cycle. When write Flash memory done, cleared automatically. Repeat steps using next available instructions from block data incrementing value TBLPAG, until instructions written back Flash memory.
Programmers program program Flash memory time. this, necessary erase 8-row erase page that contains desired row. general process Read eight rows program memory (512 instructions) store data RAM. Update program data with desired data. Erase block (see Example 5-1): NVMOP bits (NVMCON<3:0>) `0010' configure block erase. ERASE (NVMCON<6>) WREN (NVMCON<14>) bits. Write starting address page erased into TBLPAG registers. Write 0x55 NVMKEY. Write 0xAA NVMKEY. (NVMCON<15>). erase cycle begins stalls duration erase cycle. When erase done, cleared automatically.
protection against accidental operations, write initiate sequence NVMKEY must used allow erase program operation proceed. After programming command been executed, user application must wait programming time until programming complete. instructions following start programming sequence should NOPs, shown Example 5-3.
EXAMPLE 5-1:
ERASING PROGRAM MEMORY PAGE
Initialize NVMCON
NVMCON block erase operation #0x4042, NVMCON Init pointer ERASED #tblpage(PROG_ADDR), TBLPAG #tbloffset(PROG_ADDR), TBLWTL [W0] DISI BSET #0x55, NVMKEY #0xAA, NVMKEY NVMCON,
Initialize Page Boundary Initialize in-page EA[15:0] pointer base address erase block Block interrupts with priority next instructions Write Write Start erase sequence Insert NOPs after erase command asserted
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EXAMPLE 5-2: LOADING WRITE BUFFERS
NVMCON programming operations #0x4001, NVMCON Initialize NVMCON pointer first program memory location written program memory selected, writes enabled #0x0000, TBLPAG Initialize Page Boundary #0x6000, example program memory address Perform TBLWT instructions write latches 0th_program_word #LOW_WORD_0, #HIGH_BYTE_0, TBLWTL [W0] Write word into program latch TBLWTH [W0++] Write high byte into program latch 1st_program_word #LOW_WORD_1, #HIGH_BYTE_1, TBLWTL [W0] Write word into program latch TBLWTH [W0++] Write high byte into program latch 2nd_program_word #LOW_WORD_2, #HIGH_BYTE_2, TBLWTL [W0] Write word into program latch TBLWTH [W0++] Write high byte into program latch 63rd_program_word #LOW_WORD_31, #HIGH_BYTE_31, TBLWTL [W0] Write word into program latch TBLWTH [W0++] Write high byte into program latch
EXAMPLE 5-3:
DISI BSET
INITIATING PROGRAMMING SEQUENCE
Block interrupts with priority next instructions Write Write Start erase sequence Insert NOPs after erase command asserted
#0x55, NVMKEY #0xAA, NVMKEY NVMCON,
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PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
Note:
RESETS
This data sheet summarizes features PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 families devices. intended comprehensive reference source. complement information this data sheet, refer "PIC24H Family Reference Manual", Section "Reset" (DS70229), which available from Microchip website (www.microchip.com).
simplified block diagram Reset module shown Figure 6-1. active source reset will make SYSRST signal active. system Reset, some registers associated with peripherals forced known Reset state some unaffected. Note: Refer specific peripheral section Section "CPU" this manual register Reset states.
Reset module combines reset sources controls device Master Reset Signal, SYSRST. following list device Reset sources: POR: Power-on Reset BOR: Brown-out Reset MCLR: Master Clear Reset SWR: RESET Instruction WDTO: Watchdog Timer Reset Configuration Mismatch Reset TRAPR: Trap Conflict Reset IOPUWR: Illegal Condition Device Reset Illegal Opcode Reset Uninitialized Register Reset Security Reset
types device Reset sets corresponding status RCON register indicate type Reset (see Register 6-1). clears bits, except (RCON<0>), that set. user application clear time during code execution. RCON bits only serve status bits. Setting particular Reset status software does cause device Reset occur. RCON register also other bits associated with Watchdog Timer device power-saving states. function these bits discussed other sections this manual. Note: status bits RCON register should cleared after they read that next RCON register value after device Reset meaningful.
FIGURE 6-1:
RESET SYSTEM BLOCK DIAGRAM
RESET Instruction Glitch Filter MCLR Module Sleep Idle SYSRST
Internal Regulator Rise Detect
Trap Conflict Illegal Opcode Uninitialized Register Configuration Mismatch
2009 Microchip Technology Inc.
DS70293C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
REGISTER 6-1:
R/W-0 TRAPR R/W-0 EXTR Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0 R/W-0 SWDTEN(2) R/W-0 WDTO R/W-0 SLEEP R/W-0 IDLE R/W-1
RCON: RESET CONTROL REGISTER(1)
R/W-0 IOPUWR R/W-0 R/W-0 VREGS R/W-1
TRAPR: Trap Reset Flag Trap Conflict Reset occurred Trap Conflict Reset occurred IOPUWR: Illegal Opcode Uninitialized Access Reset Flag illegal opcode detection, illegal address mode uninitialized register used Address Pointer caused Reset illegal opcode uninitialized Reset occurred Unimplemented: Read Configuration Mismatch Flag configuration mismatch Reset occurred. configuration mismatch Reset occurred. VREGS: Voltage Regulator Standby During Sleep Voltage regulator active during Sleep Voltage regulator goes into Standby mode during Sleep EXTR: External Reset (MCLR) Master Clear (pin) Reset occurred Master Clear (pin) Reset occurred SWR: Software Reset (Instruction) Flag RESET instruction been executed RESET instruction been executed SWDTEN: Software Enable/Disable bit(2) enabled disabled WDTO: Watchdog Timer Time-out Flag time-out occurred time-out occurred SLEEP: Wake-up from Sleep Flag Device been Sleep mode Device been Sleep mode IDLE: Wake-up from Idle Flag Device Idle mode Device Idle mode
13-10
Note Reset status bits cleared software. Setting these bits software does cause device Reset. FWDTEN Configuration (unprogrammed), always enabled, regardless SWDTEN setting.
DS70293C-page
2009 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
REGISTER 6-1:
RCON: RESET CONTROL REGISTER(1) (CONTINUED)
BOR: Brown-out Reset Flag Brown-out Reset occurred Brown-out Reset occurred POR: Power-on Reset Flag Power-up Reset occurred Power-up Reset occurred
Note Reset status bits cleared software. Setting these bits software does cause device Reset. FWDTEN Configuration (unprogrammed), always enabled, regardless SWDTEN setting.
2009 Microchip Technology Inc.
DS70293C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
System Reset
Reset: on-chip voltage regulator circuit that keeps device Reset until crosses VBOR threshold delay TBOR elapsed. delay TBOR ensures that voltage regulator output becomes stable. PWRT Timer: programmable power-up timer continues hold processor Reset specific period time (TPWRT) after BOR. delay TPWRT ensures that system power supplies have stabilized appropriate level full-speed operation. After delay TPWRT elapsed, SYSRST becomes inactive, which turn enables selected oscillator start generating clock cycles. Oscillator Delay: total delay clock ready various clock source selections given Table 6-1. Refer Section "Oscillator Configuration" more information. When oscillator clock ready, processor begins execution from location 0x000000. user application programs GOTO instruction reset address, which redirects program execution appropriate start-up routine. Fail-safe clock monitor (FSCM), enabled, begins monitor system clock when system clock ready delay TFSCM elapsed.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04 family devices have types Reset: Cold Reset Warm Reset cold Reset result Power-on Reset (POR) Brown-out Reset (BOR). cold Reset, FNOSC configuration bits FOSC device configuration register selects device clock source. warm Reset result other reset sources, including RESET instruction. warm Reset, device will continue operate from current clock source indicated Current Oscillator Selection (COSC<2:0>) bits Oscillator Control (OSCCON<14:12>) register. device kept Reset state until system power supplies have stabilized appropriate levels oscillator clock ready. sequence which this occurs detailed below shown Figure 6-2. Reset: circuit holds device Reset when power supply turned circuit active until crosses VPOR threshold delay TPOR elapsed.
TABLE 6-1:
OSCILLATOR DELAY
Oscillator Startup Delay TOSCD TOSCD TOSCD TOSCD TOSCD TOSCD TOSCD TOSCD Oscillator Startup Timer TOST TOST TOST TOST TOST Lock Time TLOCK TLOCK TLOCK TLOCK Total Delay TOSCD TOSCD TLOCK TOSCD TOST TOSCD TOST TOSCD TOST TLOCK TOSCD TOST TLOCK TLOCK TOSCD TOST TOSCD
Oscillator Mode FRC, FRCDIV16, FRCDIVN FRCPLL XTPLL HSPLL ECPLL SOSC LPRC Note
TOSCD Oscillator Start-up Delay (1.1 FRC, LPRC). Crystal Oscillator start-up times vary with crystal characteristics, load capacitance, etc. TOST Oscillator Start-up Timer Delay (1024 oscillator clock period). example, TOST 102.4 crystal TOST crystal. TLOCK lock time (1.5 nominal), enabled.
DS70293C-page
2009 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
FIGURE 6-2: SYSTEM RESET TIMING
VBOR Vbor VPOR
TPOR Reset TBOR
Reset
TPWRT
SYSRST
Oscillator Clock TOSCD TOST TLOCK FSCM Device Status Reset TFSCM
Time
Note
Reset: circuit holds device Reset when power supply turned circuit active until crosses VPOR threshold delay TPOR elapsed. Reset: on-chip voltage regulator circuit that keeps device Reset until crosses VBOR threshold delay TBOR elapsed. delay TBOR ensures voltage regulator output becomes stable. PWRT Timer: programmable power-up timer continues hold processor Reset specific period time (TPWRT) after BOR. delay TPWRT ensures that system power supplies have stabilized appropriate level full-speed operation. After delay TPWRT elapsed, SYSRST becomes inactive, which turn enables selected oscillator start generating clock cycles. Oscillator Delay: total delay clock ready various clock source selections given Table 6-1. Refer Section "Oscillator Configuration" more information. When oscillator clock ready, processor begins execution from location 0x000000. user application programs GOTO instruction reset address, which redirects program execution appropriate start-up routine. Fail-safe clock monitor (FSCM), enabled, begins monitor system clock when system clock ready delay TFSCM elapsed.
2009 Microchip Technology Inc.
DS70293C-page
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, PIC24HJ128GPX02/X04
TABLE 6-2:
VPOR TPOR VBOR TBOR TPWRT TFSCM Note:
OSCILLATOR DELAY
Symbol Parameter threshold extension time threshold extension time Programmable power-up time delay Fail-safe Clock Monitor Delay 1.8V nominal maximum 2.5V nominal maximum 0-128 nominal maximum Value
When device exits Reset condition (begins normal operatio
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