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PIC24HJ12GP201/202 Data Sheet
High-Performance, 16-bit Microcontrollers
2009 Microchip Technology Inc.
DS70282D
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Trademarks Microchip name logo, Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC UNI/O registered trademarks Microchip Technology Incorporated U.S.A. other countries. FilterLab, Hampshire, HI-TECH Linear Active Thermistor, MXDEV, MXLAB, SEEVAL Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, Omniscient Code Generation, PICC, PICC-18, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2009, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
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2009 Microchip Technology Inc.
PIC24HJ12GP201/202
High-Performance, 16-Bit Digital Signal Controllers
Operating Range:
MIPS operation 3.0-3.6V): Industrial temperature range (-40°C +85°C) Extended temperature range (-40°C +125°C)
Digital I/O:
Peripheral Select Functionality programmable digital pins Wake-up/Interrupt-on-Change pins Output pins drive from 3.0V 3.6V output with open drain configuration digital input pins tolerant sink pins
High-Performance CPU:
Modified Harvard architecture compiler optimized instruction 16-bit-wide data path 24-bit-wide instructions Linear program memory addressing instruction words Linear data memory addressing Kbytes base instructions, mostly word/one cycle Sixteen 16-bit general purpose registers Flexible powerful addressing modes Software stack multiply operations 32/16 16/16 divide operations ±16-bit shifts 40-bit data
System Management:
Flexible clock options: External, crystal, resonator, internal Fully integrated Phase-Locked Loop (PLL) Extremely low-jitter Power-up Timer Oscillator Start-up Timer/Stabilizer Watchdog Timer with oscillator Fail-Safe Clock Monitor Reset multiple sources
Power Management:
On-chip 2.5V voltage regulator Switch between clock sources real time Idle, Sleep, Doze modes with fast wake-up
Interrupt Controller:
5-cycle latency available interrupt sources three external interrupts Seven programmable priority levels Four processor exceptions
Timers/Capture/Compare:
Timer/Counters, three 16-bit timers: pair make 32-bit timer timer runs Real-Time Clock with external 32.768 oscillator Programmable prescaler Input Capture four channels): Capture down, both edges 16-bit capture input functions 4-deep FIFO each capture Output Compare channels): Single Dual 16-bit Compare mode 16-bit Glitchless Mode
On-Chip Flash SRAM:
Flash program memory Kbytes) Data SRAM (1024 bytes) Boot General Security Program Flash
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Communication Modules:
4-wire SPI: Framing supports interface simple codecs Supports 8-bit 16-bit data Supports serial clock formats sampling modes I2CTM: Full Multi-Master Slave mode support 7-bit 10-bit addressing collision detection arbitration Integrated signal conditioning Slave address masking UART: Interrupt address detect Interrupt UART error Wake-up Start from Sleep mode 4-character FIFO buffers support IrDA® encoding decoding hardware High-Speed Baud mode Hardware Flow Control with
Analog-to-Digital Converters (ADCs):
10-bit, Msps 12-bit, Ksps conversion: four simultaneous samples (10-bit ADC) input channels with auto-scanning Conversion start manual synchronized with four trigger sources Conversion possible Sleep mode integral nonlinearity differential nonlinearity
CMOS Flash Technology:
Low-power, high-speed Flash technology Fully static design 3.3V (±10%) operating voltage Industrial extended temperature power consumption
Packaging:
18-pin SDIP/SOIC 28-pin SDIP/SOIC/QFN/SSOP Note: Table exact peripheral features device.
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PIC24HJ12GP201/202 Product Families
device names, counts, memory sizes peripheral availability each family listed below, followed their pinout diagrams.
TABLE
PIC24HJ12GP201/202 CONTROLLER FAMILIES
Program Flash Memory (Kbyte) Remappable Peripherals External Interrupts(2) 10-Bit/12-Bit Remappable Pins Output Compare Std. Pins (Max) (Kbyte) Input Capture Packages SDIP SOIC SDIP SOIC SSOP
16-bit Timer
UART
PIC24HJ12GP201 PIC24HJ12GP202
3(1) 3(1)
Device
ADC, ADC,
Note
Only three timers remappable. Only three interrupts remappable.
2009 Microchip Technology Inc.
I2C1
Pins
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Diagrams
18-Pin SDIP, SOIC
MCLR PGED2/AN0/VREF+/CN2/RA0 PGEC2/AN1/VREF-/CN3/RA1 PGED1/AN2/RP0(1)/CN4/RB0 PGEC1/AN3/RP1 /CN5/RB1 OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 PGED3/SOSCI/RP4(1)/CN1/RB4 PGEC3/SOSCO/T1CK/CN0/RA4
Pins tolerant
AN6/RP15(1)/CN11/RB15 AN7/RP14(1)/CN12/RB14 VCAP/VDDCORE SDA1/RP9(1)/CN21/RB9 SCL1/RP8(1)/CN22/RB8 INT0/RP7(1)/CN23/RB7
PIC24HJ12GP201
28-Pin SDIP, SOIC, SSOP
Pins tolerant
MCLR PGED2/AN0/VREF+/CN2/RA0 PGEC2/AN1/VREF-/CN3/RA1 PGED1/AN2/RP0(1)/CN4/RB0 PGEC1/AN3/RP1(1)/CN5/RB1 AN4/RP2(1)/CN6/RB2 AN5/RP3 /CN7/RB3 OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 PGED3/SOSC/RP4(1)/CN1/RB4 PGEC3/SOSCO/T1CK/CN0/RA4 ASDA1/RP5(1)/CN27/RB5
AVDD AVSS AN6/RP15(1)/CN11/RB15 AN7/RP14(1)/CN12/RB14 AN8/RP13(1)/CN13/RB13 AN9/RP12(1)/CN14/RB12 TMS/RP11(1)/CN15/RB11 TDI/RP10(1)/CN16/RB10 VCAP/VDDCORE TDO/SDA1/RP9(1)/CN21/RB9 TCK/SCL1/RP8(1)/CN22/RB8 INT0/RP7(1)/CN23/RB7 ASCL1/RP6(1)/CN24/RB6
PIC24HJ12GP202
Note pins used remappable peripheral. Table list available peripherals.
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Diagrams (Continued)
28-Pin QFN(2)
Pins tolerant
PGEC2//AN1/VREF-/CN3/RA1
PGED2/AN0/VREF+/CN2/RA0
PGED1/AN2/RP0(1)/CN4/RB0 PGEC1/AN3/RP1(1)/CN5/RB1 AN4/RP2(1)/CN6/RB2 AN5/RP3(1)/CN7/RB3 OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 PGED3/SOSCI/RP4(1)/CN1/RB4
AN6/RP15(1)/CN11/RB15
MCLR
AN7/RP14(1)/CN12/RB14 AN8/RP13(1)/CN13/RB13 AN9/RP12(1)/CN14/RB12 TMS/RP11(1)/CN15/RB11 TDI/RP10(1)/CN16/RB10 VCAP/VDDCORE TDO/SDA1/RP9(1)/CN21/RB9 TCK/SCL1/RP8(1)/CN22/RB8
PIC24HJ12GP202
AVDD ASDA1/RP5 /CN27/RB5
AVSS ASCL1/RP6 /CN24/RB6
INT0/RP7(1)/CN23/RB7
PGEC3/SOSCO/T1CK/CN0/RA4
Note pins used remappable peripheral. Table list available peripherals. metal plane bottom device connected pins recommended connected externally.
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Table Contents
Device Overview Guidelines Getting Started with 16-bit Microcontrollers CPU. Memory Organization Flash Program Memory Resets Interrupt Controller Oscillator Configuration Power-Saving Features. 10.0 Ports 11.0 Timer1 12.0 Timer2/3 Feature. 13.0 Input Capture. 14.0 Output Compare. 15.0 Serial Peripheral Interface (SPI). 16.0 Inter-Integrated Circuit(I2C) 17.0 Universal Asynchronous Receiver Transmitter (UART) 18.0 10-bit/12-bit Analog-to-Digital Converter (ADC) 19.0 Special Features 20.0 Instruction Summary 21.0 Development Support. 22.0 Electrical Characteristics 23.0 Packaging Information. Appendix Revision History. Index Microchip Site Customer Change Notification Service Customer Support Reader Response Product Identification System.
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Most Current Data Sheet
obtain most up-to-date version this data sheet, please register Worldwide site http://www.microchip.com determine version data sheet examining literature number found bottom outside corner page. last character literature number version number, (e.g., DS30000A version document DS30000).
Errata
errata sheet, describing minor operational differences from data sheet recommended workarounds, exist current devices. device/documentation issues become known will publish errata sheet. errata will specify revision silicon revision document which applies. determine errata sheet exists particular device, please check with following: Microchip's Worldwide site; http://www.microchip.com Your local Microchip sales office (see last page) When contacting sales office, please specify which device, revision silicon data sheet (include literature number) using.
Customer Notification System
Register site www.microchip.com receive most current information products.
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DEVICE OVERVIEW
This data sheet summarizes features PIC24HJ12GP201/202 devices. intended comprehensive reference source. complement information this data sheet, refer "PIC24H Family Reference Manual". Please Microchip site (www.microchip.com) latest family reference manual sections. This document contains device specific information PIC24HJ12GP201/202 devices. PIC24H devices contain extensive functionality with highperformance, 16-bit microcontroller (MCU) architecture. Figure shows general block diagram core peripheral modules PIC24HJ12GP201/202 family devices. Table lists functions various pins shown pinout diagrams.
2009 Microchip Technology Inc.
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FIGURE 1-1:
Table Data Access Control Block Interrupt Controller Program Counter Loop Stack Control Control Logic Logic Address Latch
PORTB
PIC24HJ12GP201/202 BLOCK DIAGRAM
Data Data Latch
PORTA
Address Generator Units
Remappable Pins
Address Latch
Program Memory Data Latch Latch
Literal Data
Instruction Decode Control Control Signals Various Blocks
OSC2/CLKO OSC1/CLKI Timing Generation FRC/LPRC Oscillators Precision Band Reference Voltage Regulator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset
Instruction
Multiplier Register Array
Divide Support
16-bit
VCAP/VDDCORE
VDD,
MCLR
Timers
ADC1
UART1
IC1,2,7,8
PWM1,2
SPI1
I2C1
Note:
pins features implemented device pinout configurations. "Pin Diagrams" specific pins features present each device.
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TABLE 1-1:
Name AN0-AN9 CLKI CLKO
PINOUT DESCRIPTIONS
Type Buffer Type Analog ST/CMOS Analog input channels. External clock source input. Always associated with OSC1 function. Oscillator crystal output. Connects crystal resonator Crystal Oscillator mode. Optionally functions CLKO modes. Always associated with OSC2 function. Oscillator crystal input. buffer when configured mode; CMOS otherwise. Oscillator crystal output. Connects crystal resonator Crystal Oscillator mode. Optionally functions CLKO modes. 32.768 low-power oscillator crystal input; CMOS otherwise. 32.768 low-power oscillator crystal output. Change notification inputs. software programmed internal weak pull-ups inputs. Description
OSC1 OSC2 SOSCI SOSCO CN0-CN7 CN11-CN15 CN21-CN24 CN27 CN29-CN30 IC1-IC2 IC7-IC8 OCFA OC1-OC2 INT0 INT1 INT2 RA0-RA4 RB0-RB15 T1CK T2CK T3CK U1CTS U1RTS U1RX U1TX SCK1 SDI1 SDO1 SCL1 SDA1 ASCL1 ASDA1 PGED1 PGEC1 PGED2 PGEC2 PGED3 PGEC3
ST/CMOS ST/CMOS
Capture inputs Capture inputs Compare Fault input (for Compare Channels Compare outputs through External interrupt External interrupt External interrupt PORTA bidirectional port. PORTB bidirectional port. Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. UART1 clear send. UART1 ready send. UART1 receive. UART1 transmit. Synchronous serial clock input/output SPI1. SPI1 data SPI1 data out. SPI1 slave synchronization frame pulse I/O. Synchronous serial clock input/output I2C1. Synchronous serial data input/output I2C1. Alternate synchronous serial clock input/output I2C1. Alternate synchronous serial data input/output I2C1. JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin. Data programming/debugging communication channel Clock input programming/debugging communication channel Data programming/debugging communication channel Clock input programming/debugging communication channel Data programming/debugging communication channel Clock input programming/debugging communication channel Analog Analog input Output Power Input
Legend: CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Peripheral Select
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TABLE 1-1:
Name VCAP/ VDDCORE VREF+ VREFAVDD MCLR AVSS
PINOUT DESCRIPTIONS (CONTINUED)
Type Buffer Type Analog Analog Description logic filter capacitor connection. Ground reference logic pins. Analog voltage reference (high) input. Analog voltage reference (low) input. Positive supply analog modules. This must connected times. Master Clear (Reset) input. This active-low Reset device. Ground reference analog modules. Positive supply peripheral logic pins. Analog Analog input Output Power Input
Legend: CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Peripheral Select
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GUIDELINES GETTING STARTED WITH 16-BIT MICROCONTROLLERS
This data sheet summarizes features PIC24HJ12GP201/202 family devices. intended comprehensive reference source. complement information this data sheet, refer "PIC24H Family Reference Manual", which available from Microchip site (www.microchip.com).
Decoupling Capacitors
Note:
decoupling capacitors every pair power supply pins, such VDD, VSS, AVDD, AVSS required. Consider following criteria when using decoupling capacitors: Value type capacitor: Recommendation (100 nF), 10-20V. This capacitor should low-ESR have resonance frequency range higher. recommended that ceramic capacitors used. Placement printed circuit board: decoupling capacitors should placed close pins possible. recommended place capacitors same side board microcontroller. space constricted, capacitor placed another layer using via; however, ensure that trace length from capacitor within one-quarter inch length. Handling high frequency noise: board experiencing high frequency noise, upward tens MHz, second ceramic-type capacitor parallel above described decoupling capacitor. value second capacitor range 0.01 0.001 Place this second capacitor next primary decoupling capacitor. high-speed circuit designs, consider implementing decade pair capacitances close power ground pins possible. example, parallel with 0.001 Maximizing performance: board layout from power supply circuit, power return traces decoupling capacitors first, then microcontroller pins. This ensures that decoupling capacitors first power chain. Equally important keep trace length between capacitor power pins minimum thereby reducing track inductance.
Basic Connection Requirements
Getting started with PIC24HJ12GP201/202 family 16-bit microcontrollers requires attention minimal device connections before proceeding with development. following list names, which must always connected: pins (see Section "Decoupling Capacitors") AVDD AVSS pins (even module used) (see Section "Decoupling Capacitors") VCAP/VDDCORE (see Section "Capacitor Internal Voltage Regulator (Vcap/Vddcore)") MCLR (see Section "Master Clear (MCLR) Pin") PGECx/PGEDx pins used In-Circuit Serial Programming(ICSPTM) debugging purposes (see Section "ICSP Pins") OSC1 OSC2 pins when external oscillator source used (see Section "External Oscillator Pins") Additionally, following pins required: VREF+/VREF- pins used when external voltage reference module implemented Note: AVDD AVSS pins must connected independent voltage reference source.
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FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION
Ceramic
Master Clear (MCLR)
MCLR provides specific device functions: Device Reset Device programming debugging During device programming debugging, resistance capacitance that added must considered. Device programmers debuggers drive MCLR pin. Consequently, specific voltage levels (VIH VIL) fast signal transitions must adversely affected. Therefore, specific values will need adjusted based application requirements.
MCLR
VCAP/VDDCORE
PIC24H
AVDD AVSS
Ceramic
Ceramic
Ceramic
Ceramic
example, shown Figure 2-2, recommended that capacitor isolated from MCLR during programming debugging operations. Place components shown Figure within one-quarter inch from MCLR pin.
2.2.1
TANK CAPACITORS
FIGURE 2-2:
boards with power traces running longer than inches length, suggested tank capacitor integrated circuits including microcontrollers supply local power source. value tank capacitor should determined based trace resistance that connects power supply source microcontroller, maximum current drawn microcontroller application. other words, select tank capacitor that meets acceptable voltage device. Typical values range from
EXAMPLE MCLR CONNECTIONS
MCLR PIC24H
Capacitor Internal Voltage Regulator (VCAP/VDDCORE)
Note
recommended. suggested starting value Ensure that MCLR specifications met. will limit current flowing into MCLR from external capacitor event MCLR breakdown, Electrostatic Discharge (ESD) Electrical Overstress (EOS). Ensure that MCLR specifications met.
low-ESR Ohms) capacitor required VCAP/VDDCORE pin, which used stabilize voltage regulator output voltage. VCAP/VDDCORE must connected VDD, must have capacitor between connected ground. type ceramic tantalum. Refer Section 22.0 "Electrical Characteristics" additional information. placement this capacitor should close VCAP/VDDCORE. recommended that trace length exceed one-quarter inch mm). Refer Section 19.2 "On-Chip Voltage Regulator" details.
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ICSP Pins External Oscillator Pins
PGECx PGEDx pins used In-Circuit Serial Programming (ICSP) debugging purposes. recommended keep trace length between ICSP connector ICSP pins microcontroller short possible. ICSP connector expected experience event, series resistor recommended, with value range tens Ohms, exceed Ohms. Pull-up resistors, series diodes capacitors PGECx PGEDx pins recommended they will interfere with programmer/debugger communications device. such discrete components application requirement, they should removed from circuit during programming debugging. Alternately, refer AC/DC characteristics timing requirements information respective device Flash programming specification information capacitive loading limits input voltage high (VIH) input (VIL) requirements. Ensure that "Communication Channel Select" (i.e., PGECx/PGEDx pins) programmed into device matches physical connections ICSP MPLAB® MPLAB MPLAB REAL ICEin-circuit emulator more information MPLAB MPLAB MPLAB REAL in-circuit emulator connection requirements, refer following documents that available Microchip site. "MPLAB® In-Circuit Debugger User's Guide" DS51331 "Using MPLAB® (poster) DS51265 "MPLAB® Design Advisory" DS51566 "Using MPLAB® (poster) DS51765 "MPLAB® Design Advisory" DS51764 "MPLAB® REAL ICEIn-Circuit Emulator User's Guide" DS51616 "Using MPLAB® REAL ICEIn-Circuit Emulator" (poster) DS51749
Many microcontrollers have options least oscillators: high-frequency primary oscillator low-frequency secondary oscillator (refer Section "Oscillator Configuration" details). oscillator circuit should placed same side board microcontroller. Also, place oscillator circuit close respective oscillator pins, exceeding one-half inch distance between them. load capacitors should placed next oscillator itself, same side board. grounded copper pour around oscillator circuit isolate them from surrounding circuits. grounded copper pour should routed directly ground. signal traces power traces inside ground pour. Also, using two-sided board, avoid traces other side board where crystal placed. suggested layout shown Figure 2-3.
FIGURE 2-3:
SUGGESTED PLACEMENT OSCILLATOR CIRCUIT
Main Oscillator Guard Ring Guard Trace Secondary Oscillator
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Oscillator Value Conditions Device Start-up Unused I/Os
target device enabled configured device start-up oscillator, maximum oscillator source frequency must limited MHz. This means that external oscillator frequency outside this range, application must start-up mode first. default settings after with oscillator frequency outside this range will violate device operating speed. When device powers application firmware initialize SFRs, CLKDIV PLLDBF suitable value, then perform clock switch Oscillator clock source. Note that clock switching must enabled device Configuration word.
Unused pins should configured outputs driven logic state. Alternately, connect resistor unused pins drive output logic low.
Configuration Analog Digital Pins During ICSP Operations
MPLAB MPLAB MPLAB REAL in-circuit emulator selected debugger, automatically initializes input pins (ANx) "digital" pins, setting bits AD1PCFGL register. bits register that correspond pins that initialized MPLAB MPLAB MPLAB REAL in-circuit emulator, must cleared user application firmware; otherwise, communication errors will result between debugger device. your application needs certain pins analog input pins during debug session, user application must clear corresponding bits AD1PCFGL register during initialization module. When MPLAB MPLAB MPLAB REAL in-circuit emulator used programmer, user application firmware must correctly configure AD1PCFGL register. Automatic initialization this register only done during debugger operation. Failure correctly configure register(s) will result pins being recognized analog input pins, resulting port value being read logic `0', which affect user application functionality.
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Note:
This data sheet summarizes features PIC24HJ12GP201/202 family devices. However, intended comprehensive reference source. complement information this data sheet, refer "PIC24H Family Reference Manual", Section "CPU" (DS70245), which available from Microchip site (www.microchip.com).
Data Addressing Overview
data space linearly addressed words Kbytes using Address Generation Unit (AGU). upper Kbytes data space memory optionally mapped into program space program word boundary defined 8-bit Program Space Visibility Page (PSVPAG) register. program data space mapping feature lets instruction access program space were data space. data space also includes Kbytes RAM, which primarily used data transfers, used general purpose RAM.
PIC24HJ12GP201/202 module 16-bit (data) modified Harvard architecture with enhanced instruction addressing modes. 24-bit instruction word with variable length opcode field. Program Counter (PC) bits wide addresses bits user program memory space. actual amount program memory implemented varies device. single-cycle instruction prefetch mechanism used help maintain throughput provides predictable execution. instructions execute single cycle, with exception instructions that change program flow, double-word move (MOV.D) instruction table instructions. Overhead-free, single-cycle program loop constructs supported using REPEAT instruction, which interruptible point. PIC24HJ12GP201/202 devices have sixteen, 16-bit working registers programmer's model. Each working registers serve data, address address offset register. 16th working register (W15) operates software Stack Pointer (SP) interrupts calls. PIC24HJ12GP201/202 instruction includes many addressing modes designed optimum compiler efficiency. most instructions, PIC24HJ12GP201/202 devices capable executing data program data) memory read, working register (data) read, data memory write, program (instruction) memory read instruction cycle. result, three parameter instructions supported, allowing operations executed single cycle. block diagram shown Figure 3-1, programmer's model PIC24HJ12GP201/202 shown Figure 3-2.
Special Features
PIC24HJ12GP201/202 features 17-bit 17-bit, single-cycle multiplier. multiplier perform signed, unsigned mixed-sign multiplication. Using 17-bit 17-bit multiplier 16-bit 16-bit multiplication makes mixed-sign multiplication possible. PIC24HJ12GP201/202 supports 16/16 32/16 integer divide operations. divide instructions iterative operations. They must executed within REPEAT loop, resulting total execution time instruction cycles. divide operation interrupted during those cycles without loss data. multi-bit data shifter used perform 16-bit, left right shift single cycle.
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FIGURE 3-1:
Table Data Access Control Block Interrupt Controller Program Counter Loop Stack Control Control Logic Logic Data
PIC24HJ12GP201/202 CORE BLOCK DIAGRAM
Data Latch Address Latch
Address Latch Address Generator Units
Program Memory Data Latch Latch Literal Data
Instruction Decode Control
Instruction Multiplier
Control Signals Various Blocks
Divide Support
Register Array
16-bit
Peripheral Modules
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FIGURE 3-2: PIC24HJ12GP201/202 PROGRAMMER'S MODEL
W0/WREG W14/Frame Pointer W15/Stack Pointer SPLIM Stack Pointer Limit Register Working Registers PUSH.S Shadow Shadow Legend
PC22 TBLPAG PSVPAG Data Table Page Address
Program Counter
Program Space Visibility Page Address RCOUNT REPEAT Loop Counter
CORCON
Core Configuration Register
IPL2 IPL1 IPL0
STATUS Register
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Control Registers
STATUS REGISTER
R/W-0 R/W-0(2) IPL<2:0>(2) Legend: Clear only only 15-9 Readable Writable cleared Unimplemented: Read Half Carry/Borrow carry-out from low-order (for byte-sized data) low-order (for word-sized data) result occurred carry-out from low-order (for byte-sized data) low-order (for word-sized data) result occurred IPL<2:0>: Interrupt Priority Level Status bits(2) Interrupt Priority Level (15), user interrupts disabled Interrupt Priority Level (14) Interrupt Priority Level (13) Interrupt Priority Level (12) Interrupt Priority Level (11) Interrupt Priority Level (10) Interrupt Priority Level Interrupt Priority Level REPEAT Loop Active REPEAT loop progress REPEAT loop progress Negative Result negative Result non-negative (zero positive) Overflow This used signed arithmetic (2's complement). indicates overflow magnitude which causes sign change state. Overflow occurred signed arithmetic this arithmetic operation) overflow occurred Zero operation which affects some time past most recent operation which affects cleared (i.e., non-zero result) Carry/Borrow carry-out from Most Significant (MSb) result occurred carry-out from Most Significant result occurred Unimplemented bit, read Value unknown R/W-0(2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0(1)
REGISTER 3-1:
Note IPL<2:0> bits concatenated with IPL<3> (CORCON<3>) form Interrupt Priority Level. value parentheses indicates IPL<3> User interrupts disabled when IPL<3> IPL<2:0> Status bits read-only when NSTDIS (INTCON1<15>).
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REGISTER 3-2:
Legend: Readable cleared 15-4 Clear only Writable unknown
CORCON: CORE CONTROL REGISTER
R/C-0 IPL3(1) R/W-0
Value Unimplemented bit, read
Unimplemented: Read IPL3: Interrupt Priority Level Status 3(1) interrupt priority level greater than interrupt priority level less PSV: Program Space Visibility Data Space Enable Program space visible data space Program space visible data space Unimplemented: Read
Note IPL3 concatenated with IPL<2:0> bits (SR<7:5>) form interrupt priority level.
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Arithmetic Logic Unit (ALU)
3.4.2 DIVIDER
PIC24HJ12GP201/202 bits wide capable addition, subtraction, shifts, logic operations. Unless otherwise mentioned, arithmetic operations complement nature. Depending operation, affect values Carry (C), Zero (Z), Negative (N), Overflow (OV), Digit Carry (DC) Status bits register. Status bits operate Borrow Digit Borrow bits, respectively, subtraction operations. perform 8-bit 16-bit operations, depending mode instruction that used. Data operation come from register array, data memory, depending addressing mode instruction. Likewise, output data from written register array data memory location. Refer dsPIC30F/33F Programmer's Reference Manual (DS70157) information bits affected each instruction. PIC24HJ12GP201/202 incorporates hardware support both multiplication division. This includes dedicated hardware multiplier support hardware 16-bit divisor division. divide block supports 32-bit/16-bit 16-bit/16-bit signed unsigned integer divide operations with following data sizes: 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide
quotient divide instructions ends remainder Sixteen-bit signed unsigned instructions specify register both 16-bit divisor (Wn) register (aligned) pair (W(m 1):Wm) 32-bit dividend. divide algorithm takes cycle divisor, both 32-bit/16-bit 16-bit/16-bit instructions take same number cycles execute.
3.4.3
MULTI-BIT DATA SHIFTER
multi-bit data shifter capable performing 16-bit arithmetic logic right shifts, 16-bit left shifts single cycle. source either working register memory location. shifter requires signed binary value determine both magnitude (number bits) direction shift operation. positive value shifts operand right. negative value shifts operand left. value does modify operand.
3.4.1
MULTIPLIER
Using high-speed 17-bit 17-bit multiplier, supports unsigned, signed mixed-sign operation several multiplication modes: 16-bit 16-bit signed 16-bit 16-bit unsigned 16-bit signed 5-bit (literal) unsigned 16-bit unsigned 16-bit unsigned 16-bit unsigned 5-bit (literal) unsigned 16-bit unsigned 16-bit signed 8-bit unsigned 8-bit unsigned
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PIC24HJ12GP201/202
Note:
MEMORY ORGANIZATION
This data sheet summarizes features PIC24HJ12GP201/202 family devices. However, intended comprehensive reference source. complement information this data sheet, refer "PIC24H Family Reference Manual", Section "Data Memory" (DS70237), which available from Microchip site (www.microchip.com).
Program Address Space
program address memory space PIC24HJ12GP201/202 devices instructions. space addressable 24-bit value derived either from 23-bit Program Counter (PC) during program execution, from table operation data space remapping described Section "Interfacing Program Data Memory Spaces". User application access program memory space restricted lower half address range (0x000000 0x7FFFFF). exception TBLRD/TBLWT operations, which TBLPAG<7> permit access Configuration bits Device sections configuration memory space. memory PIC24HJ12GP201/202 family devices shown Figure 4-1.
PIC24HJ12GP201/202 architecture features separate program data memory spaces buses. This architecture also allows direct access program memory from data space during code execution.
FIGURE 4-1:
PROGRAM MEMORY PIC24HJ12GP201/202 DEVICES
PIC24HJ12GP201/202 GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table
User Memory Space
0x000000 0x000002 0x000004 0x0000FE 0x000100 0x000104 0x0001FE 0x000200
User Program Flash Memory instructions)
0x001FFE 0x002000
Unimplemented (Read `0's)
0x7FFFFE 0x800000
Reserved
Configuration Memory Space
Device Configuration Registers
0xF7FFFE 0xF80000 0xF80017 0xF80018
Reserved
DEVID
0xFEFFFE 0xFF0000 0xFFFFFE
2009 Microchip Technology Inc.
DS70282D-page
PIC24HJ12GP201/202
4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.2 INTERRUPT TRAP VECTORS
program memory space organized wordaddressable blocks. Although treated bits wide, more appropriate think each address program memory lower upper word, with upper byte upper word being unimplemented. lower word always even address, while upper word address (Figure 4-2). Program memory addresses always word-aligned lower word, addresses incremented decremented during code execution. This arrangement provides compatibility with data memory space addressing makes data program memory space accessible. PIC24HJ12GP201/202 devices reserve addresses between 0x00000 0x000200 hardcoded program execution vectors. hardware Reset vector provided redirect code execution from default value device Reset actual start code. GOTO instruction programmed user application 0x000000, with actual address start code 0x000002. PIC24HJ12GP201/202 devices also have interrupt vector tables, located from 0x000004 0x0000FF 0x000100 0x0001FF. These vector tables allow each many device interrupt sources handled separate Interrupt Service Routines (ISRs). more detailed discussion interrupt vector tables provided Section "Interrupt Vector Table".
FIGURE 4-2:
Address 0x000001 0x000003 0x000005 0x000007
PROGRAM MEMORY ORGANIZATION
most significant word (msw) 00000000 00000000 00000000 00000000 Program Memory `Phantom' Byte (read `0') Instruction Width least significant word (lsw) 0x000000 0x000002 0x000004 0x000006 Address (lsw Address)
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PIC24HJ12GP201/202
Data Address Space
PIC24HJ12GP201/202 separate 16bit-wide data memory space. data space accessed using separate Address Generation Units (AGUs) read write operations. data memory maps shown Figure 4-3. Effective Addresses (EAs) data memory space bits wide point bytes within data space. This arrangement gives data space address range Kbytes words. lower half data memory space (that when EA<15> used implemented memory addresses, while upper half (EA<15> reserved Program Space Visibility area (see Section 4.4.3 "Reading Data From Program Memory Using Program Space Visibility"). PIC24HJ12GP201/202 devices implement Kbytes data memory. Should point location outside this area, all-zero word byte will returned. word accesses must aligned even address. Misaligned word data fetches supported, care must taken when mixing byte word operations, translating from 8-bit code. misaligned read write attempted, address error trap generated. error occurred read, instruction progress completed. instruction occurred write, instruction executed write does occur. either case, trap then executed, allowing system and/or user application examine machine state prior execution address Fault. byte loads into register loaded into LSB. modified. sign-extend instruction (SE) provided allow users translate 8-bit signed data 16-bit signed values. Alternately, 16-bit unsigned data, user applications clear register executing zero-extend (ZE) instruction appropriate address.
4.2.1
DATA SPACE WIDTH
4.2.3
SPACE
data memory space organized byte addressable, 16-bit-wide blocks. Data aligned data memory registers 16-bit words, data space resolve bytes. Least Significant Bytes (LSBs) each word have even addresses, while Most Significant Bytes (MSBs) have addresses.
first Kbytes near data space, from 0x0000 0x07FF, primarily occupied Special Function Registers (SFRs). These used PIC24HJ12GP201/202 core peripheral modules controlling operation device. SFRs distributed among modules that they control, generally grouped together module. Much space contains unused addresses; these read `0'. complete listing implemented SFRs, including their addresses, shown Table through Table 4-21. Note: actual peripheral features interrupts varies device. Refer corresponding device tables pinout diagrams device-specific information.
4.2.2
DATA MEMORY ORGANIZATION ALIGNMENT
maintain backward compatibility with PIC® devices improve data space memory usage efficiency, PIC24HJ12GP201/202 instruction supports both word byte operations. consequence byte accessibility, effective address calculations internally scaled step through word-aligned memory. example, core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result value byte operations word operations. Data byte reads will read complete word that contains byte, using determine which byte select. selected byte placed onto data path. That data memory registers organized parallel byte-wide entities with shared (word) address decoding separate write lines. Data byte writes only write corresponding side array register that matches byte address.
4.2.4
NEAR DATA SPACE
Kbyte area between 0x0000 0x1FFF referred near data space. Locations this space directly addressable 13-bit absolute address field within memory direct instructions. Additionally, whole data space addressable using class instructions, which support Memory Direct Addressing mode with 16-bit address field, using Indirect Addressing mode with working register address pointer.
2009 Microchip Technology Inc.
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PIC24HJ12GP201/202
FIGURE 4-3: DATA MEMORY PIC24HJ12GP201/202 DEVICES WITH
Address Kbyte Space 0x0001 Space 0x07FF 0x0801 Data 0x0BFF 0x0C01 0x1FFF 0x2001 0x0BFE 0x0C00 0x1FFFF 0x2000 0x07FE 0x0800 Kbyte Near Data Space Address 0x0000
bits
Kbyte SRAM Space
0x8001
0x8000
Optionally Mapped into Program Memory
Data Unimplemented
0xFFFF
0xFFFE
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2009 Microchip Technology Inc.
TABLE 4-1:
Name WREG0 WREG1 WREG2 WREG3 WREG4 WREG5 WREG6 WREG7 WREG8 WREG9 WREG10 WREG11 WREG12 WREG13 WREG14 WREG15 SPLIM TBLPAG PSVPAG RCOUNT CORCON DISICNT Legend:
CORE REGISTERS
Addr 0000 0002 0004 0006 0008 000A 000C 000E 0010 0012 0014 0016 0018 001A 001C 001E 0020 002E 0030 0032 0034 0036 0042 0044 0052 Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 xxxx 0000
Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Stack Pointer Limit Register Program Counter Word Register IPL2 Program Counter High Byte Register Table Page Address Pointer Register Program Memory Visibility Page Address Pointer Register IPL1 IPL0 IPL3
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0000 0000 0000 xxxx 0000 0000 xxxx
Repeat Loop Counter Register
Disable Interrupts Counter Register
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
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TABLE 4-2:
Name CNEN1 CNEN2 CNPU1 CNPU2 Legend: Addr 0060 0062 0068 006A
CHANGE NOTIFICATION REGISTER PIC24HJ12GP202
CN15IE CN14IE CN30IE CN13IE CN29IE CN12IE CN11IE CN27IE CN24IE CN7IE CN23IE CN7PUE CN6IE CN22IE CN6PUE CN5IE CN21IE CN5PUE CN4IE CN4PUE CN3IE CN3PUE CN2IE CN2PUE CN1IE CN1PUE CN0IE CN16IE CN0PUE CN16PUE Resets 0000 0000 0000 0000
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN30PUE CN29PUE CN27PUE
CN24PUE CN23PUE CN22PUE CN21PUE
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-3:
Name CNEN1 CNEN2 CNPU1 Addr 0060 0062 0068 006A
CHANGE NOTIFICATION REGISTER PIC24HJ12GP201
CN30IE CN29IE CN12IE CN11IE CN23IE CN22IE CN5IE CN21IE CN5PUE CN4IE CN3IE CN2IE CN1IE CN0IE Resets 0000 0000 0000 0000
CN12PUE CN11PUE
CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE
2009 Microchip Technology Inc.
CNPU2 Legend:
CN30PUE CN29PUE
CN23PUE CN22PUE CN21PUE
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
2009 Microchip Technology Inc.
TABLE 4-4:
Name INTCON1 INTCON2 IFS0 IFS1 IFS4 IEC0 IEC1 IEC4 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC7 IPC16 INTTREG Legend: Addr 0080 0082 0084 0086 008C 0094 0096 009C 00A4 00A6 00A8 00AA 00AC 00AE 00B2 00C4 00E0
INTERRUPT CONTROLLER REGISTER
NSTDIS ALTIVT DISI AD1IF INT2IF AD1IE INT2IE T1IP<2:0> T2IP<2:0> U1RXIP<2:0> CNIP<2:0> IC8IP<2:0> U1TXIF U1TXIE U1RXIF U1RXIE OC1IP<2:0> OC2IP<2:0> SPI1IP<2:0> IC7IP<2:0> T3IF T3IE T2IF IC8IF T2IE IC8IE DIV0ERR OC2IF IC7IF OC2IE IC7IE IC2IF IC2IE IC1IP<2:0> IC2IP<2:0> SPI1EIP<2:0> AD1IP<2:0> MI2C1IP<2:0> INT2IP<2:0> U1EIP<2:0> OSCFAIL INT1EP IC1IF MI2C1IF U1EIF IC1IE U1EIE INT0IP<2:0> T3IP<2:0> U1TXIP<2:0> SI2C1IP<2:0> INT1IP<2:0> INT0EP INT0IF SI2C1IF INT0IE Resets 0000 0000 0000 0000 0000 0000 0000 0000 4444 4440 4444 0044 4044 4404 0040 0040 0000
MATHERR ADDRERR STKERR INT1IF INT1IE T1IF CNIF T1IE CNIE VECNUM<6:0> INT2EP OC1IF OC1IE
SPI1IF SPI1EIF
SPI1IE SPI1EIE
MI2C1IE SI2C1IE
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ILR<3:0>>
PIC24HJ12GP201/202
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
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TABLE 4-5:
Name TMR1 T1CON TMR2 TMR3HLD TMR3 T2CON T3CON Legend: Addr 0100 0102 0104 0106 0108 010A 010C 010E 0110 0112
TIMER REGISTER
Resets xxxx FFFF TGATE TCKPS<1:0> TSYNC 0000 xxxx xxxx xxxx FFFF FFFF TGATE TGATE TCKPS<1:0> TCKPS<1:0> 0000 0000
Timer1 Register Period Register TSIDL Timer2 Register Timer3 Holding Register (for 32-bit timer operations only) Timer3 Register Period Register Period Register TSIDL TSIDL
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-6:
INPUT CAPTURE REGISTER
Resets xxxx ICI<1:0> ICI<1:0> ICI<1:0> ICI<1:0> ICOV ICOV ICOV ICOV ICBNE ICBNE ICBNE ICBNE ICM<2:0> ICM<2:0> ICM<2:0> ICM<2:0> 0000 xxxx 0000 xxxx 0000 xxxx 0000
2009 Microchip Technology Inc.
Name IC1BUF IC1CON IC2BUF IC2CON IC7BUF IC7CON IC8BUF IC8CON Legend:
Addr 0140 0142 0144 0146 0158 015A 015C 015E
Input Capture Register ICSIDL ICSIDL ICSIDL ICSIDL ICTMR ICTMR ICTMR ICTMR Input Capture Register Input Capture Register Input 8Capture Register
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-7:
Name OC1RS OC1R OC1CON OC2RS OC2R OC2CON Legend: Addr 0180 0182 0184 0186 0188 018A
OUTPUT COMPARE REGISTER
Resets xxxx xxxx OCFLT OCTSEL OCM<2:0> 0000 xxxx xxxx OCFLT OCTSEL OCM<2:0> 0000
Output Compare Secondary Register Output Compare Register OCSIDL Output Compare Secondary Register Output Compare Register OCSIDL
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
2009 Microchip Technology Inc.
TABLE 4-8:
Name I2C1RCV I2C1TRN I2C1BRG I2C1CON I2C1STAT I2C1ADD I2C1MSK Legend: Addr 0200 0202 0204 0206 0208 020A 020C
I2C1 REGISTER
I2CEN ACKSTAT TRSTAT I2CSIDL SCLREL IPMIEN A10M DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV ACKDT Resets 0000 00FF 0000 RSEN 1000 0000 0000 0000
Receive Register Transmit Register Baud Rate Generator Register ACKEN RCEN
Address Register Address Mask Register
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-9:
Name U1MODE Addr 0220 0222 0224 0226 0228
UART1 REGISTER
UARTEN UTXISEL1 UTXINV USIDL UTXISEL0 IREN RTSMD UTXBRK UTXEN UEN1 UTXBF Baud Rate Generator Prescaler UEN0 TRMT WAKE LPBACK ABAUD ADDEN URXINV RIDLE BRGH PERR STSEL URXDA Resets 0000 0110 xxxx 0000 0000
PDSEL<1:0> FERR OERR
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U1STA U1TXREG U1RXREG U1BRG Legend:
URXISEL<1:0>
UART Transmit Register UART Receive Register
PIC24HJ12GP201/202
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-10:
Name SPI1STAT SPI1CON1 SPI1CON2 SPI1BUF Legend: Addr 0240 0242 0244 0248
SPI1 REGISTER
SPIEN FRMEN SPIFSD SPISIDL FRMPOL DISSCK DISSDO MODE16 SSEN SPIROV MSTEN SPRE<2:0> SPITBF FRMDLY SPIRBF Resets 0000 0000 0000 0000
PPRE<1:0>
SPI1 Transmit Receive Buffer Register
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
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PIC24HJ12GP201/202
TABLE 4-11:
File Name RPINR0 RPINR1 RPINR3 RPINR7 RPINR10 RPINR11 RPINR18 RPINR20 RPINR21 Legend: Addr 0680 0682 0686 068E 0694 0696 06A4 06A8 06AA
PERIPHERAL SELECT INPUT REGISTER
INT1R<4:0> T3CKR<4:0> IC2R<4:0> IC8R<4:0> U1CTSR<4:0> SCK1R<4:0> INT2R<4:0> T2CKR<4:0> IC1R<4:0> IC7R<4:0> OCFAR<4:0> U1RX<R4:0> SDI1R<4:0> SS1R<4:0> Resets 1F00 001F 1F1F 1F1F 1F1F 001F 1F1F 1F1F 001F
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-12:
File Name RPOR0 RPOR1 RPOR2 RPOR3 RPOR4 RPOR5 RPOR6 RPOR7 Legend:
PERIPHERAL SELECT OUTPUT REGISTER PIC24HJ12GP202
RP1R<4:0> RP3R<4:0> RP5R<4:0> RP7R<4:0> RP9R<4:0> RP11R<4:0> RP13R<4:0> RP15R<4:0> RP0R<4:0> RP2R<4:0> RP4R<4:0> RP6R<4:0> RP8R<4:0> RP10R<4:0> RP12R<4:0> RP14R<4:0> Resets 0000 0000 0000 0000 0000 0000 0000 0000
2009 Microchip Technology Inc.
Addr 06C0 06C2 06C4 06C6 06C8 06CA 06CC 06CE
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-13:
File Name RPOR0 RPOR2 RPOR3 RPOR4 RPOR7 Legend: Addr 06C0 06C4 06C6 06C8
PERIPHERAL SELECT OUTPUT REGISTER PIC24HJ12GP201
RP1R<4:0> RP7R<4:0> RP9R<4:0> RP0R<4:0> RP4R<4:0> RP8R<4:0> RP14R<4:0> Resets 0000 0000 0000 0000 0000
06CE RP15R<4:0> unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-14:
File Name ADC1BUF0 ADC1BUF1 ADC1BUF2 ADC1BUF3 ADC1BUF4 ADC1BUF5 ADC1BUF6 ADC1BUF7 ADC1BUF8 ADC1BUF9 ADC1BUFA ADC1BUFB ADC1BUFC ADC1BUFD ADC1BUFE ADC1BUFE AD1CON1 AD1CON2 AD1CON3 AD1CHS123 AD1CHS0 AD1PCFGL AD1CSSL Legend: Addr 0300 0302 0304 0306 0308 030A 030C 030E 0310 0312 0314 0316 0318 031A 031C 031E 0320 0322 0324 0326 0328 032C 0330
ADC1 REGISTER PIC24HJ12GP201
Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx SSRC<2:0> BUFS CH0NA PCGG7 CSS7 PCGF6 CSS6 PCFG3 CSS3 SIMSAM ASAM SAMP BUFM CH123NA<1:0> CH0SA<4:0> PCFG2 CSS2 PCFG1 CSS1 PCFG0 CSS0 DONE ALTS CH123SA 0000 0000 0000 0000 0000 0000 0000 SMPI<3:0> ADCS<7:0> CH123SB
2009 Microchip Technology Inc.
Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer ADON ADRC CH0NB VCFG<2:0> ADSIDL AD12B CSCNA SAMC<4:0> CH123NB<1:0> CH0SB<4:0> FORM<1:0> CHPS<1:0>
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PIC24HJ12GP201/202
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-15:
File Name ADC1BUF0 ADC1BUF1 ADC1BUF2 ADC1BUF3 ADC1BUF4 ADC1BUF5 ADC1BUF6 ADC1BUF7 ADC1BUF8 ADC1BUF9 ADC1BUFA ADC1BUFB ADC1BUFC ADC1BUFD ADC1BUFE ADC1BUFF AD1CON1 AD1CON2 AD1CON3 AD1CHS123 AD1CHS0 AD1PCFGL AD1CSSL Legend: Addr 0300 0302 0304 0306 0308 030A 030C 030E 0310 0312 0314 0316 0318 031A 031C 031E 0320 0322 0324 0326 0328 032C 0330
ADC1 REGISTER PIC24HJ12GP202
Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx SSRC<2:0> BUFS CH0NA PCFG8 CSS8 PCFG7 CSS7 CSS9 PCFG6 CSS6 PCFG5 CSS5 PCFG4 CSS4 PCFG3 CSS3 SIMSAM ASAM SAMP BUFM CH123NA<1:0> CH0SA<4:0> PCFG2 CSS2 PCFG1 CSS1 PCFG0 CSS0 DONE ALTS CH123SA 0000 0000 0000 0000 0000 0000 0000 SMPI<3:0> ADCS<7:0> CH123SB
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PIC24HJ12GP201/202
Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer ADON ADRC CH0NB VCFG<2:0> ADSIDL AD12B CSCNA SAMC<4:0> CH123NB<1:0> CH0SB<4:0> PCFG9 FORM<1:0> CHPS<1:0>
2009 Microchip Technology Inc.
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
2009 Microchip Technology Inc.
TABLE 4-16:
File Name TRISA PORTA LATA ODCA Legend: Addr 02C0 02C2 02C4 02C6
PORTA REGISTER
TRISA4 LATA4 ODCA4 TRISA3 LATA3 ODCA3 TRISA2 LATA2 ODCA2 TRISA1 LATA1 ODCA1 TRISA0 LATA0 ODCA0 Resets 001F xxxx xxxx 0000
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-17:
File Name TRISB PORTB LATB ODCB Addr 02C8 02CA 02CC 02CE
PORTB REGISTER PIC24HJ12GP202
TRISB15 RB15 LATB15 ODCB15 TRISB14 RB14 LATB14 ODCB14 TRISB13 RB13 LATB13 ODCB13 TRISB12 RB12 LATB12 ODCB12 TRISB11 RB11 LATB11 ODCB11 TRISB10 RB10 LATB10 ODCB10 TRISB9 LATB9 ODCB9 TRISB8 LATB8 ODCB8 TRISB7 LATB7 ODCB7 TRISB6 LATB6 ODCB6 TRISB5 LATB5 ODCB5 TRISB4 LATB4 ODCB4 TRISB3 LATB3 ODCB3 TRISB2 LATB2 ODCB2 TRISB1 LATB1 ODCB1 TRISB0 LATB0 ODCB0 Resets FFFF xxxx xxxx 0000
DS70282D-page
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-18:
File Name TRISB PORTB LATB ODCB Legend: Addr 02C8 02CA 02CC 02CE
PORTB REGISTER PIC24HJ12GP201
TRISB9 LATB9 ODCB9 TRISB8 LATB8 ODCB8 TRISB7 LATB7 ODCB7 TRISB4 LATB4 ODCB4 TRISB1 LATB1 ODCB1 TRISB0 LATB0 ODCB0 Resets C393 xxxx xxxx 0000
PIC24HJ12GP201/202
TRISB15 TRISB14 RB15 LATB15 ODCB15 RB14 LATB14 ODCB14
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
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PIC24HJ12GP201/202
TABLE 4-19:
File Name RCON OSCCON CLKDIV PLLFBD OSCTUN Legend: Note Addr 0740 0742 0744 0746 0748
SYSTEM CONTROL REGISTER
TRAPR IOPUWR COSC<2:0> DOZE<2:0> DOZEN NOSC<2:0> FRCDIV<2:0> VREGS EXTR SWDTEN LOCK PLLDIV<8:0> TUN<5:0> WDTO SLEEP IDLE PLLPRE<4:0> LPOSCEN OSWEN Resets xxxx(1) 0300(2) 3040 0030 0000
CLKLOCK IOLOCK PLLPOST<1:0>
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. RCON register Reset values dependent type Reset. OSCCON register Reset values dependent FOSC Configuration bits type Reset.
TABLE 4-20:
File Name NVMCON NVMKEY Legend: Note Addr 0760 0766
REGISTER
WREN WRERR ERASE NVMKEY<7:0> Resets 0000(1) 0000
NVMOP<3:0>
2009 Microchip Technology Inc.
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. Reset value shown only. Value other Reset states dependent state memory write erase operations time Reset.
TABLE 4-21:
File Name PMD1 PMD2 Legend: Addr 0770 0772
REGISTER
IC8MD IC7MD T3MD T2MD T1MD IC2MD IC1MD I2C1MD U1MD SPI1MD OC2MD AD1MD OC1MD Resets 0000 0000
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
PIC24HJ12GP201/202
4.2.5 SOFTWARE STACK 4.2.6 DATA PROTECTION FEATURE
addition working register, register PIC24HJ12GP201/202 devices also used software Stack Pointer. Stack Pointer always points first available free word grows from lower higher addresses. pre-decrements stack pops post-increments stack pushes, shown Figure 4-4. push during CALL instruction, zero-extended before push, ensuring that always clear. Note: push during exception processing concatenates register prior push. PIC24H product family supports Data protection features that enable segments protected when used conjunction with Boot Secure Code Segment Security. BSRAM (Secure segment accessible only from Boot Segment Flash code, when enabled. SSRAM (Secure segment RAM) accessible only from Secure Segment Flash code, when enabled. Table overview BSRAM SSRAM SFRs.
Instruction Addressing Modes
Stack Pointer Limit register (SPLIM) associated with Stack Pointer sets upper address boundary stack. SPLIM uninitialized Reset. case Stack Pointer, SPLIM<0> forced because stack operations must word-aligned. When generated using source destination pointer, resulting address compared with value SPLIM. contents Stack Pointer (W15) SPLIM register equal push operation performed, stack error trap will occur. However, stack error trap will occur subsequent push operation. example, cause stack error trap when stack grows beyond address 0x0C00 RAM, initialize SPLIM with value 0x0BFE. Similarly, Stack Pointer underflow (stack error) trap generated when Stack Pointer address found less than 0x0800. This prevents stack from interfering with space. write SPLIM register should immediately followed indirect read operation using W15.
addressing modes shown Table 4-22 form basis addressing modes that optimized support specific features individual instructions. addressing modes provided class instructions differ from those provided other instruction types.
4.3.1
FILE REGISTER INSTRUCTIONS
Most file register instructions 13-bit address field directly address data present first 8192 bytes data memory (Near Data Space). Most file register instructions employ working register, which denoted WREG these instructions. destination typically either same file register WREG (with exception instruction), which writes result register register pair. instruction allows additional flexibility access entire data space.
4.3.2
INSTRUCTIONS
three-operand instructions form: Operand Operand <function> Operand where Operand always working register (that addressing mode only register direct), which referred Operand register, fetched from data memory, 5-bit literal. result location either register data memory location. following addressing modes supported instructions: Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified 5-bit 10-bit Literal Note: instructions support addressing modes given above. Individual instructions support different subsets these addressing modes.
FIGURE 4-4:
0x0000
CALL STACK FRAME
Stack Grows Toward Higher Address
PC<15:0> 000000000 PC<22:16> <Free Word>
(before CALL) (after CALL) [-W15] PUSH [W15++]
2009 Microchip Technology Inc.
DS70282D-page
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TABLE 4-22: FUNDAMENTAL ADDRESSING MODES SUPPORTED
Description address file register specified explicitly. contents register accessed directly. contents forms Effective Address (EA.) contents forms post-modified (incremented decremented) constant value. pre-modified (incremented decremented) signed constant value form Addressing Mode File Register Direct Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified
Register Indirect with Register Offset forms (Register Indexed) Register Indirect with Literal Offset literal forms
4.3.3
MOVE (MOV) INSTRUCTIONS
4.3.4
OTHER INSTRUCTIONS
Move instructions provide greater degree addressing flexibility than other instructions. addition addressing modes supported most instructions, instructions also support Register Indirect with Register Offset Addressing mode, also referred Register Indexed mode. Note: instructions, addressing mode specified instruction differ source destination However, 4-bit (Register Offset) field shared both source destination (but typically only used one).
addition addressing modes outlined previously, some instructions literal constants various sizes. example, (branch) instructions 16-bit signed literals specify branch destination directly, whereas DISI instruction uses 14-bit unsigned literal field. some instructions, such Acc, source operand result implied opcode itself. Certain operations, such NOP, have operands.
summary, following addressing modes supported move instructions: Register Direct Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset (Indexed) Register Indirect with Literal Offset 8-bit Literal 16-bit Literal Note: instructions support addressing modes given above. Individual instructions support different subsets these addressing modes.
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Interfacing Program Data Memory Spaces
4.4.1 ADDRESSING PROGRAM SPACE
Since address ranges data program spaces bits, respectively, method needed create 23-bit 24-bit program address from 16-bit data registers. solution depends interface method used. table operations, 8-bit Table Page register (TBLPAG) used define word region within program space. This concatenated with 16-bit arrive full 24-bit program space address. this format, TBLPAG used determine operation occurs user memory (TBLPAG<7> configuration memory (TBLPAG<7> remapping operations, 8-bit Program Space Visibility register (PSVPAG) used define word page program space. When `1', PSVPAG concatenated with lower bits form 23-bit program space address. Unlike table operations, this limits remapping operations strictly user memory area. Table 4-23 Figure show program created table operations remapping accesses from data
PIC24HJ12GP201/202 architecture uses 24-bitwide program space 16-bit-wide data space. architecture also modified Harvard scheme, meaning that data also present program space. this data successfully, must accessed that preserves alignment information both spaces. Aside from normal execution, PIC24HJ12GP201/ architecture provides methods which program space accessed during operation: Using table instructions access individual bytes words anywhere program space Remapping portion program space into data space (Program Space Visibility) Table instructions allow application read write small areas program memory. This capability makes method ideal accessing data tables that need updated periodically. also allows access bytes program word. remapping method allows application access large block data read-only basis, which ideal look from large table static data. application only access program word.
TABLE 4-23:
PROGRAM SPACE ADDRESS CONSTRUCTION
Access Space User User Configuration Program Space Address <23> xxxx TBLPAG<7:0> 0xxx xxxx TBLPAG<7:0> 1xxx xxxx PSVPAG<7:0> xxxx xxxx <22:16> <15> PC<22:1> xxxx xxxx xxxx xxx0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<14:0>(1) xxxx xxxx xxxx <14:1>
Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write)
Program Space Visibility (Block Remap/Read) Note
User
Data EA<15> always this case, used calculating program space address. address PSVPAG<0>.
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FIGURE 4-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter bits
Table Operations(2)
TBLPAG bits bits bits
Select Program Space Visibility(1) (Remapping) PSVPAG bits
bits bits
User/Configuration Space Select
Byte Select
Note program space addresses always fixed maintain word alignment data program data spaces. Table operations required word-aligned. Table read operations permitted configuration memory space.
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4.4.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS
Byte mode, either upper lower byte lower program word mapped lower byte data address. upper byte selected when Byte Select `1'; lower byte selected when `0'. TBLRDH (Table Read High): Word mode, this instruction maps entire upper word program address (P<23:16>) data address. Note that D<15:8>, `phantom byte', will always `0'. Byte mode, this instruction maps upper lower byte program word D<7:0> data address, TBLRDL instruction. Note that data will always when upper `phantom' byte selected (Byte Select similar fashion, table instructions, TBLWTH TBLWTL, used write individual bytes words program space address. details their operation explained Section "Flash Program Memory". table operations, area program memory space accessed determined Table Page register (TBLPAG). TBLPAG covers entire program memory space device, including user configuration spaces. When TBLPAG<7> table page located user memory space. When TBLPAG<7> page located configuration space.
TBLRDL TBLWTL instructions offer direct method reading writing lower word address within program space without going through data space. TBLRDH TBLWTH instructions only method read write upper bits program space word data. incremented each successive 24-bit program word. This allows program memory addresses directly data space addresses. Program memory thus regarded 16-bitwide word address spaces, residing side side, each with same address range. TBLRDL TBLWTL access space that contains least significant data word. TBLRDH TBLWTH access space that contains upper data byte. table instructions provided move byte- word-sized (16-bit) data from program space. Both function either byte word operations. TBLRDL (Table Read Low): Word mode, this instruction maps lower word program space location (P<15:0>) data address (D<15:0>).
FIGURE 4-6:
TBLPAG
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
0x000000
00000000 00000000 00000000 00000000
0x020000 0x030000
`Phantom' Byte
TBLRDH.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.W address table operation determined data within page defined TBLPAG register. Only read operations shown; write operations also valid user memory area.
0x800000
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4.4.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY
24-bit program word used contain data. upper bits program space location used data should programmed with `1111 1111' `0000 0000' force NOP. This prevents possible issues should area code ever accidentally executed. Note: access temporarily disabled during table reads/writes.
upper Kbytes data space optionally mapped into word page program space. This option provides transparent access stored constant data from data space without need special instructions (such TBLRDL TBLRDH). Program space access through data space occurs data space program space visibility enabled setting Core Control register (CORCON<2>). location program memory space mapped into data space determined Program Space Visibility Page register (PSVPAG). This 8-bit register defines possible pages words program space. effect, PSVPAG functions upper bits program memory address, with bits functioning lower bits. incrementing each program memory word, lower bits data space addresses directly lower bits corresponding program space addresses. Data reads this area cycle instruction being executed, since program memory fetches required. Although each data space address 8000h higher maps directly into corresponding program memory address (see Figure 4-7), only lower bits
operations that executed outside REPEAT loop, MOV.D instructions require instruction cycle addition specified execution time. other instructions require instruction cycles addition specified execution time. operations that PSV, executed inside REPEAT loop, these instances require instruction cycles addition specified execution time instruction: Execution first iteration Execution last iteration Execution prior exiting loop interrupt Execution upon re-entering loop after interrupt serviced other iteration REPEAT loop will allow instruction using access data execute single cycle.
FIGURE 4-7:
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> EA<15>
Program Space
PSVPAG 0x000000 0x010000 0x018000 data page designated PSVPAG mapped into upper half data memory space.
Data Space
0x0000 Data EA<14:0>
0x8000
Area .while lower bits specify exact address within 0xFFFF area. This corresponds exactly same lower bits actual program space address.
0x800000
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Note:
FLASH PROGRAM MEMORY
This data sheet summarizes features PIC24HJ12GP201/202 family devices. However, intended comprehensive reference source. complement information this data sheet, refer "PIC24H Family Reference Manual", Section "Program Memory" (DS70228), which available from Microchip site (www.microchip.com).
RTSP accomplished using TBLRD (table read) TBLWT (table write) instructions. With RTSP, user application write program memory data either blocks `rows' instructions (192 bytes) single program memory word, erase program memory blocks `pages' instructions (1536 bytes).
Table Instructions Flash Programming
PIC24HJ12GP201/202 devices contain internal Flash program memory storing executing application code. memory readable, writable erasable during normal operation over entire range. Flash memory programmed ways: In-Circuit Serial Programming(ICSPTM) programming capability Run-Time Self-Programming (RTSP) ICSP allows PIC24HJ12GP201/202 device serially programmed while application circuit. This done with lines programming clock programming data (one alternate programming pairs: PGECx/PGEDx), three other lines power (VDD), ground (VSS) Master Clear (MCLR). This allows users manufacture boards with unprogrammed devices then program digital signal controller just before shipping product. This also allows most recent firmware custom firmware programmed.
Regardless method used, programming Flash memory done with table-read tablewrite instructions. These allow direct read write access program memory space from data memory while device normal operating mode. 24-bit target address program memory formed using bits <7:0> TBLPAG register Effective Address (EA) from register specified table instruction, shown Figure 5-1. TBLRDL TBLWTL instructions used read write bits<15:0> program memory. TBLRDL TBLWTL access program memory both Word Byte modes. TBLRDH TBLWTH instructions used read write bits<23:16> program memory. TBLRDH TBLWTH also access program memory Word Byte mode.
FIGURE 5-1:
ADDRESSING TABLE REGISTERS
bits Using Program Counter Program Counter
Working Using Table Instruction TBLPAG bits bits
User/Configuration Space Select
24-bit
Byte Select
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RTSP Operation Programming Operations
PIC24HJ12GP201/202 Flash program memory array organized into rows instructions bytes. RTSP allows user application erase page memory, which consists eight rows (512 instructions), program word. 8-row erase pages single write rows edgealigned from beginning program memory, boundaries 1536 bytes bytes, respectively. program memory implements holding buffers that contain instructions programming data. Prior actual programming operation, write data must loaded into buffers sequentially. instruction words loaded must always from group boundary. basic sequence RTSP programming Table Pointer, then series TBLWT instructions load buffers. Programming performed setting control bits NVMCON register. total TBLWTL TBLWTH instructions required load instructions. table write operations single-word writes (two instruction cycles) because only buffers written. programming cycle required programming each row. complete programming sequence necessary programming erasing internal Flash RTSP mode. processor stalls (waits) until programming operation finished. programming time depends accuracy (see Table 22-18) value Oscillator Tuning register (see Register 8-4). following formula calculate minimum maximum values Write Time, Page Erase Time, Word Write Cycle Time parameters (see Table 22-12).
EQUATION 5-1:
PROGRAMMING TIME
-7.37 Accuracy Tuning example, device operating +125°C, accuracy will ±5%. TUN<5:0> bits (see Register 8-4) `b111111, Minimum Write Time 11064 Cycles 1.435ms 7.37 0.05 0.00375 and, Maximum Write Time 11064 Cycles 1.586ms 7.37 0.05 0.00375 Setting (NVMCON<15>) starts operation, automatically cleared when operation finished.
Control Registers
SFRs used read write program Flash memory: NVMCON: Flash Memory Control Register NVMKEY: Nonvolatile Memory Register NVMCON register (Register 5-1) controls which blocks erased, which memory type programmed start programming cycle. NVMKEY (Register 5-2) write-only register that used write protection. start programming erase sequence, user application must consecutively write 0x55 0xAA NVMKEY register. Refer Section "Programming Operations" further details.
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REGISTER 5-1:
R/SO-0(1) Legend: Readable Value Satiable only Writable Unimplemented bit, read cleared unknown R/W-0(1) ERASE R/W-0(1) R/W-0(1) R/W-0(1)
NVMCON: FLASH MEMORY CONTROL REGISTER
R/W-0(1) WRERR R/W-0(1) WREN
R/W-0(1)
NVMOP<3:0>
Write Control Initiates Flash memory program erase operation. operation self-timed cleared hardware when operation complete. Program erase operation complete inactive WREN: Write Enable Enable Flash program/erase operations Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag improper program erase sequence attempt termination occurred (bit automatically attempt bit) program erase operation completed normally Unimplemented: Read ERASE: Erase/Program Enable Perform erase operation specified NVMOP<3:0> next command Perform program operation specified NVMOP<3:0> next command Unimplemented: Read NVMOP<3:0>: Operation Select bits(2) ERASE 1111 Memory bulk erase operation 1101 Erase General Segment 1100 Erase Secure Segment 0011 operation 0010 Memory page erase operation 0001 operation 0000 Erase single Configuration register byte ERASE 1111 operation 1101 operation 1100 operation 0011 Memory word program operation 0010 operation 0001 Memory program operation 0000 Program single Configuration register byte
12-7
Note These bits only Reset POR. other combinations NVMOP<3:0> unimplemented.
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REGISTER 5-2:
Legend: Readable Value 15-8 Satiable only Writable Unimplemented bit, read cleared unknown
NVMKEY: NONVOLATILE MEMORY REGISTER
NVMKEY<7:0>
Unimplemented: Read NVMKEY<7:0>: Register (write-only) bits
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5.4.1 PROGRAMMING ALGORITHM FLASH PROGRAM MEMORY
Programmers program program Flash memory time. this, necessary erase 8-row erase page that contains desired row. general process Read eight rows program memory (512 instructions) store data RAM. Update program data with desired data. Erase block (see Example 5-1): NVMOP bits (NVMCON<3:0>) `0010' configure block erase. ERASE (NVMCON<6>) WREN (NVMCON<14>) bits. Write starting address page erased into TBLPAG registers. Write 0x55 NVMKEY. Write 0xAA NVMKEY. (NVMCON<15>). erase cycle begins stalls duration erase cycle. When erase done, cleared automatically. Write first instructions from data into program memory buffers (see Example 5-2). Write program block Flash memory: NVMOP bits `0001' configure programming. Clear ERASE WREN bit. Write 0x55 NVMKEY. Write 0xAA NVMKEY. bit. programming cycle begins stalls duration write cycle. When write Flash memory done, cleared automatically. Repeat steps using next available instructions from block data incrementing value TBLPAG, until instructions written back Flash memory.
protection against accidental operations, write initiate sequence NVMKEY must used allow erase program operation proceed. After programming command been executed, user application must wait programming time until programming complete. instructions following start programming sequence should NOPs, shown Example 5-3.
EXAMPLE 5-1:
ERASING PROGRAM MEMORY PAGE
Initialize NVMCON
NVMCON block erase operation #0x4042, NVMCON Init pointer ERASED #tblpage(PROG_ADDR), TBLPAG #tbloffset(PROG_ADDR), TBLWTL [W0] DISI BSET #0x55, NVMKEY #0xAA, NVMKEY NVMCON,
Initialize Page Boundary Initialize in-page EA[15:0] pointer base address erase block Block interrupts with priority next instructions Write Write Start erase sequence Insert NOPs after erase command asserted
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EXAMPLE 5-2: LOADING WRITE BUFFERS
NVMCON programming operations #0x4001, NVMCON Initialize NVMCON pointer first program memory location written program memory selected, writes enabled #0x0000, TBLPAG Initialize Page Boundary #0x6000, example program memory address Perform TBLWT instructions write latches 0th_program_word #LOW_WORD_0, #HIGH_BYTE_0, TBLWTL [W0] Write word into program latch TBLWTH [W0++] Write high byte into program latch 1st_program_word #LOW_WORD_1, #HIGH_BYTE_1, TBLWTL [W0] Write word into program latch TBLWTH [W0++] Write high byte into program latch 2nd_program_word #LOW_WORD_2, #HIGH_BYTE_2, TBLWTL [W0] Write word into program latch TBLWTH [W0++] Write high byte into program latch 63rd_program_word #LOW_WORD_31, #HIGH_BYTE_31, TBLWTL [W0] Write word into program latch TBLWTH [W0++] Write high byte into program latch
EXAMPLE 5-3:
DISI BSET
INITIATING PROGRAMMING SEQUENCE
Block interrupts with priority next instructions Write Write Start erase sequence Insert NOPs after erase command asserted
#0x55, NVMKEY #0xAA, NVMKEY NVMCON,
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Note:
RESETS
This data sheet summarizes features PIC24HJ12GP201/202 families devices. intended comprehensive reference source. complement information this data sheet, refer PIC24H Family Reference Manual, "Section Reset" (DS70229), which available from Microchip site (www.microchip.com).
active source Reset will make SYSRST signal active. system Reset, some registers associated with peripherals forced known Reset state, some unaffected. Note: Refer specific peripheral section Section "CPU" this manual register Reset states.
types device Reset corresponding status RCON register indicate type Reset (see Register 6-1). bits that set, with exception (RCON<0>), cleared during event. user application clear time during code execution. RCON bits only serve status bits. Setting particular Reset status software does cause device Reset occur. RCON register also other bits associated with Watchdog Timer device power-saving states. function these bits discussed other sections this data sheet. Note: status bits RCON register should cleared after they read that next RCON register value after device Reset meaningful.
Reset module combines Reset sources controls device Master Reset Signal, SYSRST. following list device Reset sources: POR: Power-on Reset BOR: Brown-out Reset MCLR: Master Clear Reset SWR: RESET Instruction WDTO: Watchdog Timer Reset Configuration Mismatch Reset TRAPR: Trap Conflict Reset IOPUWR: Illegal Condition Device Reset Illegal Opcode Reset Uninitialized Register Reset Security Reset
simplified block diagram Reset module shown Figure 6-1.
FIGURE 6-1:
RESET SYSTEM BLOCK DIAGRAM
RESET Instruction
Glitch Filter MCLR Module Sleep Idle SYSRST
Internal Regulator Rise Detect
Trap Conflict Illegal Opcode Uninitialized Register Configuration Mismatch
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REGISTER 6-1:
R/W-0 TRAPR R/W-0 EXTR Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0 R/W-0 SWDTEN(2) R/W-0 WDTO R/W-0 SLEEP R/W-0 IDLE R/W-1
RCON: RESET CONTROL REGISTER(1)
R/W-0 IOPUWR R/W-0 R/W-0 VREGS R/W-1
TRAPR: Trap Reset Flag Trap Conflict Reset occurred Trap Conflict Reset occurred IOPUWR: Illegal Opcode Uninitialized Access Reset Flag illegal opcode detection, illegal address mode uninitialized register used Address Pointer caused Reset illegal opcode uninitialized Reset occurred Unimplemented: Read Configuration Mismatch Flag configuration mismatch Reset occurred. configuration mismatch Reset occurred. VREGS: Voltage Regulator Standby During Sleep Voltage regulator active during Sleep Voltage regulator goes into Standby mode during Sleep EXTR: External Reset (MCLR) Master Clear (pin) Reset occurred Master Clear (pin) Reset occurred SWR: Software Reset (Instruction) Flag RESET instruction been executed RESET instruction been executed SWDTEN: Software Enable/Disable bit(2) enabled disabled WDTO: Watchdog Timer Time-out Flag time-out occurred time-out occurred SLEEP: Wake-up from Sleep Flag Device been Sleep mode Device been Sleep mode IDLE: Wake-up from Idle Flag Device Idle mode Device Idle mode
13-10
Note Reset status bits cleared software. Setting these bits software does cause device Reset. FWDTEN Configuration (unprogrammed), always enabled, regardless SWDTEN setting.
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REGISTER 6-1:
RCON: RESET CONTROL REGISTER(1) (CONTINUED)
BOR: Brown-out Reset Flag Brown-out Reset occurred Brown-out Reset occurred POR: Power-on Reset Flag Power-up Reset occurred Power-up Reset occurred
Note Reset status bits cleared software. Setting these bits software does cause device Reset. FWDTEN Configuration (unprogrammed), always enabled, regardless SWDTEN setting.
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System Reset
PIC24HJ12GP201/202 family devices have types Reset: Cold Reset Warm Reset cold Reset result Power-on Reset (POR) BOR. cold Reset, FNOSC configuration bits FOSC device configuration register selects device clock source. warm Reset result other Reset sources, including RESET instruction. warm Reset, device will continue operate from current clock source indicated Current Oscillator Selection (COSC<2:0>) bits Oscillator Control (OSCCON<14:12>) register. device kept Reset state until system power supplies have stabilized appropriate levels oscillator clock ready. sequence which this occurs detailed below shown Figure 6-2. Reset: circuit holds device Reset when power supply turned circuit active until crosses VPOR threshold delay TPOR elapsed. Reset: on-chip voltage regulator circuit that keeps device Reset until crosses VBOR threshold delay TBOR elapsed. delay TBOR ensures that voltage regulator output becomes stable. PWRT Timer: programmable power-up timer continues hold processor Reset specific period time (TPWRT) after BOR. delay TPWRT ensures that system power supplies have stabilized appropriate level full-speed operation. After delay TPWRT elapsed, SYSRST becomes inactive, which enables selected oscillator start generating clock cycles. Oscillator Delay: total delay clock ready various clock source selections given Table 6-1. Refer Section "Oscillator Configuration" more information. When oscillator clock ready, processor begins execution from location 0x000000. user application programs GOTO instruction Reset address, which redirects program execution appropriate start-up routine. Fail-safe clock monitor (FSCM), enabled, begins monitor system clock when system clock ready delay TFSCM elapsed.
TABLE 6-1:
OSCILLATOR DELAY
Oscillator Startup Delay TOSCD TOSCD TOSCD TOSCD TOSCD TOSCD TOSCD TOSCD Oscillator Startup Timer TOST TOST TOST TOST TOST Lock Time TLOCK TLOCK TLOCK TLOCK Total Delay TOSCD TOSCD TLOCK TOSCD TOST TOSCD TOST TOSCD TOST TLOCK TOSCD TOST TLOCK TLOCK TOSCD TOST TOSCD
Oscillator Mode FRC, FRCDIV16, FRCDIVN FRCPLL XTPLL HSPLL ECPLL SOSC LPRC Note
TOSCD Oscillator Start-up Delay (1.1 FRC, LPRC). Crystal Oscillator start-up times vary with crystal characteristics, load capacitance, etc. TOST Oscillator Start-up Timer Delay (1024 oscillator clock period). example, TOST 102.4 crystal TOST crystal. TLOCK lock time (1.5 nominal), enabled.
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FIGURE 6-2: SYSTEM RESET TIMING
VBOR Vbor VPOR
TPOR Reset TBOR
Reset
TPWRT
SYSRST
Oscillator Clock TOSCD TOST TLOCK FSCM Device Status Reset TFSCM
Time
Reset: circuit holds device Reset when power supply turned circuit active until crosses VPOR threshold delay TPOR elapsed. Reset: on-chip voltage regulator circuit that keeps device Reset until crosses VBOR threshold delay TBOR elapsed. delay TBOR ensures voltage regulator output becomes stable. PWRT Timer: programmable power-up timer continues hold processor Reset specific period time (TPWRT) after BOR. delay TPWRT ensures that system power supplies have stabilized appropriate level full-speed operation. After delay TPWRT elapsed, SYSRST becomes inactive, which turn enables selected oscillator start generating clock cycles. Oscillator Delay: total delay clock ready various clock source selections given Table 6-1. Refer Section "Oscillator Configuration" more information. When oscillator clock ready, processor begins execution from location 0x000000. user application programs GOTO instruction Reset address, which redirects program execution appropriate start-up routine. Fail-safe clock monitor (FSCM), enabled, begins monitor system clock when system clock ready delay TFSCM elapsed.
TABLE 6-2:
Symbol VPOR TPOR VBOR TBOR TPWRT
OSCILLATOR DELAY
Parameter Value 1.8V nominal 2.5V nominal 0-128 nominal
Note:
threshold threshold Programmable power-up time delay Fail-safe Clock Monitor Delay
extension time maximum extension time maximum
TFSCM
maximum
When device exits Reset condition (begins normal operation), device operating parameters (voltage, frequency, temperature, etc.) must within their operating ranges, otherwise device function correctly. user application must ensure that delay between time power first applied, time SYSRST becomes inactive, long enough operating parameters within specification.
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PWRT
circuit ensures device reset from poweron. circuit active until crosses VPOR threshold delay TPOR elapsed. delay TPOR ensures internal device bias circuits become stable. device supply voltage characteristics must meet specified starting voltage rise rate requirements generate POR. Refer Section 22.0 "Electrical Characteristics" details. status (POR) Reset Control (RCON<0>) register indicate Power-on Reset. on-chip regulator circuit that resets device when (VDD VBOR) proper device operation. circuit keeps device Reset until crosses VBOR threshold delay TBOR elapsed. delay TBOR ensures voltage regulator output becomes stable. status (BOR) Reset Control (RCON<1>) register indicate Brown-out Reset. device will full speed after should rise acceptable levels full-speed operation. PWRT provides power-up time delay (TPWRT) ensure that system power supplies have stabilized appropriate levels full-speed operation before SYSRST released. power-up timer delay (TPWRT) programmed Power-on Reset Timer Value Select (FPWRT<2:0>) bits Configuration (FPOR<2:0>) register, which provides eight settings (from ms). Refer Section 19.0 "Special Features" further details. Figure shows typical brown-out scenarios. Reset delay (TBOR TPWRT) initiated each time rises above VBOR trip point.
FIGURE 6-3:
BROWN-OUT SITUATIONS
VBOR TBOR TPWRT SYSRST
VBOR TBOR TPWRT SYSRST dips before PWRT expires VBOR TBOR TPWRT SYSRST
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External Reset (EXTR) Trap Conflict Reset
external Reset generated driving MCLR low. MCLR Schmitt trigger input with additional glitch filter. Reset pulses that longer than minimum pulse width will generate Reset. Refer Section 22.0 "Electrical Characteristics" minimum pulse width specifications. External Reset (MCLR) (EXTR) Reset Control (RCON) register indicate MCLR Reset. lower-priority hard trap occurs while higher-priority trap being processed, hard trap conflict Reset occurs. hard traps include exceptions priority level through level inclusive. address error (level oscillator error (level traps fall into this category. Trap Reset Flag (TRAPR) Reset Control (RCON<15>) register indicate Trap Conflict Reset. Refer Section "Interrupt Controller" more information trap conflict Resets.
6.4.0.1
EXTERNAL SUPERVISORY CIRCUIT
Many systems have external supervisory circuits that generate Reset signals Reset multiple devices system. This external Reset signal directly connected MCLR Reset device when rest system Reset.
Configuration Mismatch Reset
6.4.0.2
INTERNAL SUPERVISORY CIRCUIT
When using internal power supervisory circuit Reset device, external Reset (MCLR) should tied directly resistively VDD. this case, MCLR will used generate Reset. external Reset (MCLR) does have internal pull-up must left unconnected.
maintain integrity peripheral select control registers, they constantly monitored with shadow registers hardware. unexpected change registers occur (such cell disturbances caused other external events), configuration mismatch Reset occurs. Configuration Mismatch Flag (CM) Reset Control (RCON<9>) register indicate configuration mismatch Reset. Refer Section 10.0 "I/O Ports" more information configuration mismatch Reset. Note: configuration mismatch feature associated Reset flag available devices.
Software RESET Instruction (SWR)
Whenever RESET instruction executed, device will assert SYSRST, placing device special Reset state. This Reset state will reinitialize clock. clock source effect prior RESET instruction will remain. SYSRST released next instruction cycle, Reset vector fetch will commence. Software Reset (Instruction) Flag (SWR) Reset Control (RCON<6>) register indicate software Reset.
Illegal Condition Device Reset
illegal condition device Reset occurs following sources: Illegal Opcode Reset Uninitialized Register Reset Security Reset Illegal Opcode Uninitialized Access Reset Flag (IOPUWR) Reset Control (RCON<14>) register indicate illegal condition device Reset.
Watchdog Time-out Reset (WDTO)
Whenever Watchdog Time-out occurs, device will asynchronously assert SYSRST. clock source will remain unchanged. time-out during Sleep Idle mode will wake-up processor, will reset processor. Watchdog Timer Time-out Flag (WDTO) Reset Control (RCON<4>) register indicate Watchdog Reset. Refer Section 19.4 "Watchdog Timer (WDT)" more information Watchdog Reset.
6.9.0.1
ILLEGAL OPCODE RESET
device Reset generated device attempts execute illegal opcode value that fetched from program memory. illegal opcode Reset function prevent device from executing program memory sections that used store constant data. take advantage illegal opcode Reset, only lower bits each program memory section store data values. upper bits should programmed with 3Fh, which illegal opcode value.
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6.9.0.2 UNINITIALIZED REGISTER RESET
6.10
Using RCON Status Bits
attempts uninitialized register address pointer will Reset device. register array (with exception W15) cleared during Resets considered uninitialized until written
user application read Reset Control (RCON) register after device Reset determine cause Reset. Note: status bits RCON register should cleared after they read that next RCON register value after device Reset will meaningful.
6.9.0.3
SECURITY RESET
Program Flow Change (PFC) Vector Flow Change (VFC) targets restricted location protected segment (Boot Secure Segment), that operation will cause security Reset. occurs when Program Counter reloaded result Call, Jump, Computed Jump, Return, Return from Subroutine, other form branch instruction. occurs when Program Counter reloaded with Interrupt Trap vector. Refer Section 19.6 "Code Protection CodeGuardSecurity" more information Security Reset.
Table provides summary Reset Flag operation.
TABLE 6-3:
RESET FLAG OPERATION
Flag Trap conflict event Illegal opcode uninitialized register access Security Reset Configuration Mismatch MCLR Reset RESET instruction Time-out PWRSAV #SLEEP instruction PWRSAV #IDLE instruction POR, Cleared POR, POR, POR, POR, PWRSAV instruction, CLRWDT instruction, POR, POR, POR,
TRAPR (RCON<15>) IOPWR (RCON<14>) (RCON<9>) EXTR (RCON<7>) (RCON<6>) WDTO (RCON<4>) SLEEP (RCON<3>) IDLE (RCON<2>) (RCON<1>) (RCON<0>) Note:
Reset flag bits cleared user software.
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Note:
INTERRUPT CONTROLLER
This data sheet summarizes features PIC24HJ12GP201/202 family devices. However, intended comprehensive reference source. complement information this data sheet, refer "PIC24H Family Reference Manual", Section "Interrupts (Part II)" (DS70233), which available from Microchip site (www.microchip.com).
7.1.1
ALTERNATE INTERRUPT VECTOR TABLE
Alternate Interrupt Vector Table (AIVT) located after IVT, shown Figure 7-1. Access AIVT provided ALTIVT control (INTCON2<15>). ALTIVT set, interrupt exception processes alternate vectors instead default vectors. alternate vectors organized same manner default vectors. AIVT supports debugging providing switch between application support environment without requiring interrupt vectors reprogrammed. This feature also enables switching between applications facilitate evaluation different software algorithms time. AIVT needed, AIVT should programmed with same addresses used IVT.
PIC24HJ12GP201/202 interrupt controller reduces numerous peripheral interrupt request signals single interrupt request signal PIC24HJ12GP201/202 CPU. following features: eight processor exceptions software traps Seven user-selectable priority levels Interrupt Vector Table (IVT) with vectors unique vector each interrupt exception source Fixed priority within specified user priority level Alternate Interrupt Vector Table (AIVT) debug support Fixed interrupt entry return latencies
Reset Sequence
Interrupt Vector Table
device Reset true exception because interrupt controller involved Reset process. PIC24HJ12GP201/202 device clears registers response Reset, which forces zero. digital signal controller then begins program execution location 0x000000. user application GOTO instruction Reset address that redirects program execution appropriate start-up routine. Note: unimplemented unused vector locations AIVT should programmed with address default interrupt handler routine that contains RESET instruction.
Interrupt Vector Table shown Figure 7-1. resides program memory, starting location 000004h. contains vectors consisting nonmaskable trap vectors, plus sources interrupt. general, each interrupt source vector. Each interrupt vector contains 24-bit-wide address. value programmed into each interrupt vector location starting address associated Interrupt Service Routine (ISR). Interrupt vectors prioritized terms their natural priority; this priority linked their position vector table. Lower addresses generally have higher natural priority. example, interrupt associated with vector will take priority over interrupts other vector address. PIC24HJ12GP201/202 devices implement unique interrupts nonmaskable traps. These summarized Table Table 7-2.
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FIGURE 7-1: PIC24HJ12GP201/202 INTERRUPT VECTOR TABLE
Reset GOTO Instruction Reset GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Start Code 0x000000 0x000002 0x000004
0x000014
Decreasing Natural Order Priority
0x00007C 0x00007E 0x000080
Interrupt Vector Table (IVT)(1)
0x0000FC 0x0000FE 0x000100 0x000102
0x000114
Alternate Interrupt Vector Table (AIVT)(1) 0x00017C 0x00017E 0x000180
0x0001FE 0x000200
Note
Table list implemented interrupt vectors.
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TABLE 7-1:
Vector Number
INTERRUPT VECTORS
Interrupt Request (IRQ) Number Address 0x000014 0x000016 0x000018 0x00001A 0x00001C 0x00001E 0x000020 0x000022 0x000024 0x000026 0x000028 0x00002A 0x00002C 0x00002E 0x000030 0x000032 0x000034 0x000036 0x000038 0x00003A 0x00003C 0x00003E 0x000040 0x000042 0x000044 0x000046 0x000048 0x00004A 0x00004C 0x00004E 0x000050 0x000052 0x000054 0x000056 0x000058 0x00005A 0x00005C 0x00005E 0x000060 0x000062 0x000064 0x000066 0x000068 0x00006A 0x00006C 0x00006E AIVT Address 0x000114 0x000116 0x000118 0x00011A 0x00011C 0x00011E 0x000120 0x000122 0x000124 0x000126 0x000128 0x00012A 0x00012C 0x00012E 0x000130 0x000132 0x000134 0x000136 0x000138 0x00013A 0x00013C 0x00013E 0x000140 0x000142 0x000144 0x000146 0x000148 0x00014A 0x00014C 0x00014E 0x000150 0x000152 0x000154 0x000156 0x000158 0x00015A 0x00015C 0x00015E 0x000160 0x000162 0x000164 0x000166 0x000168 0x00016A 0x00016C 0x00016E Interrupt Source INT0 External Interrupt Input Compare Output Compare Timer1 Reserved Input Capture Output Compare Timer2 Timer3 SPI1E SPI1 Error SPI1 SPI1 Transfer Done U1RX UART1 Receiver U1TX UART1 Transmitter ADC1 ADC1 Reserved Reserved SI2C1 I2C1 Slave Events MI2C1 I2C1 Master Events Reserved Change Notification Interrupt INT1 External Interrupt Reserved Input Capture Input Capture Reserved Reserved Reserved Reserved Reserved INT2 External Interrupt Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
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TABLE 7-1:
Vector Number 80-125
INTERRUPT VECTORS (CONTINUED)
Interrupt Request (IRQ) Number 72-117 Address 0x000070 0x000072 0x000074 0x000076 0x000078 0x00007A 0x00007C 0x00007E 0x000080 0x000082 0x000084 0x000086 0x000088 0x00008A 0x00008C 0x00008E 0x000090 0x000092 0x000094 0x000096 0x000098 0x00009A 0x00009C 0x00009E 0x0000A0 0x0000A2 0x0000A40x0000FE AIVT Address 0x000170 0x000172 0x000174 0x000176 0x000178 0x00017A 0x00017C 0x00017E 0x000180 0x000182 0x000184 0x000186 0x000188 0x00018A 0x00018C 0x00018E 0x000190 0x000192 0x000194 0x000196 0x000198 0x00019A 0x00019C 0x00019E 0x0001A0 0x0001A2 0x0001A40x0001FE Interrupt Source Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved UART1 Error Reserved Reserved Reserved Reserved Reserved Reserved Reserved
TABLE 7-2:
TRAP VECTORS
Address 0x000004 0x000006 0x000008 0x00000A 0x00000C 0x00000E 0x000010 0x000012 AIVT Address 0x000104 0x000106 0x000108 0x00010A 0x00010C 0x00010E 0x000110 0x000112 Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved
Vector Number
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Interrupt Control Status Registers
7.3.4 IPCx
registers used interrupt priority level each source interrupt. Each user interrupt source assigned eight priority levels.
PIC24HJ12GP201/202 devices implement total registers interrupt controller: Interrupt Control Register (INTCON1) Interrupt Control Register (INTCON2) Interrupt Flag Status Registers (IFSx) Interrupt Enable Control Registers (IECx) Interrupt Priority Control Registers (IPCx) Interrupt Control Status Register (INTTREG)
7.3.5
INTTREG
INTTREG register contains associated interrupt vector number interrupt priority level, which latched into vector number (VECNUM<6:0>) interrupt level (ILR<3:0>) fields INTTREG register. interrupt priority level priority pending interrupt. interrupt sources assigned IFSx, IECx, IPCx registers same sequence that they listed Table 7-1. example, INT0 (External Interrupt shown having vector number natural order priority Thus, INT0IF found IFS0<0>, INT0IE IEC0<0>, INT0IP bits first positions IPC0 (IPC0<2:0>).
7.3.1
INTCON1 INTCON2
Global interrupt control functions controlled from INTCON1 INTCON2. INTCON1 contains Interrupt Nesting Disable (NSTDIS) well control status flags processor trap sources. INTCON2 register controls external interrupt request signal behavior Alternate Interrupt Vector Table.
7.3.6
STATUS REGISTERS
7.3.2
IFSx
registers maintain interrupt request flags. Each source interrupt status bit, which respective peripherals external signal cleared software.
Although they specifically part interrupt control hardware, Control registers contain bits that control interrupt functionality: STATUS register, contains IPL<2:0> bits (SR<7:5>). These bits indicate current interrupt priority level. user change current priority level writing bits. CORCON register contains IPL3 which, together with IPL<2:0>, also indicates current priority level. IPL3 read-only bit, that trap events cannot masked user software. Interrupt registers described Register through Register 7-19 following pages.
7.3.3
IECx
registers maintain interrupt enable bits. These control bits used individually enable interrupts from peripherals external signals.
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REGISTER 7-1:
R/W-0(3) IPL2(2) Legend: Clear only only Readable Writable cleared Unimplemented bit, read Value unknown R/W-0(3) IPL1
STATUS REGISTER(1)
R/W-0 R/W-0(3) IPL0(2) R/W-0 R/W-0 R/W-0 R/W-0
IPL<2:0>: Interrupt Priority Level Status bits(1) Interrupt Priority Level (15), user interrupts disabled Interrupt Priority Level (14) Interrupt Priority Level (13) Interrupt Priority Level (12) Interrupt Priority Level (11) Interrupt Priority Level (10) Interrupt Priority Level Interrupt Priority Level
Note complete register details, Register 3-1: "SR: Status Register". IPL<2:0> bits concatenated with IPL<3> (CORCON<3>) form Interrupt Priority Level. value parentheses indicates IPL<3> User interrupts disabled when IPL<3> IPL<2:0> Status bits read-only when NSTDIS (INTCON1<15>)
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REGISTER 7-2:
Legend: Readable cleared Clear only Writable unknown
CORCON: CORE CONTROL REGISTER(1)
R/C-0 IPL3(2) R/W-0
Value Unimplemented bit, read
IPL3: Interrupt Priority Level Status 3(2) interrupt priority level greater than interrupt priority level less
Note complete register details, Register 3-2: "CORCON: Core Control Register". IPL3 concatenated with IPL<2:0> bits (SR<7:5>) form Interrupt Priority Level.
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REGISTER 7-3:
R/W-0 NSTDIS Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0 DIV0ERR R/W-0 MATHERR R/W-0 ADDRERR R/W-0 STKERR R/W-0 OSCFAIL
INTCON1: INTERRUPT CONTROL REGISTER
NSTDIS: Interrupt Nesting Disable Interrupt nesting disabled Interrupt nesting enabled Unimplemented: Read `0'. DIV0ERR: Arithmetic Error Status Math error trap caused divide zero Math error trap caused divide zero Unimplemented: Read MATHERR: Arithmetic Error Status Math error trap occurred Math error trap occurred ADDRERR: Address Error Trap Status Address error trap occurred Address error trap occurred STKERR: Stack Error Trap Status Stack error trap occurred Stack error trap occurred OSCFAIL: Oscillator Failure Trap Status Oscillator failure trap occurred Oscillator failure trap occurred Unimplemented: Read
14-7
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REGISTER 7-4:
R/W-0 ALTIVT Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0 INT2EP R/W-0 INT1EP
INTCON2: INTERRUPT CONTROL REGISTER
DISI R/W-0 INT0EP
ALTIVT: Enable Alternate Interrupt Vector Table alternate vector table standard (default) vector table DISI: DISI Instruction Status DISI instruction active DISI instruction active Unimplemented: Read INT2EP: External Interrupt Edge Detect Polarity Select Interrupt negative edge Interrupt positive edge INT1EP: External Interrupt Edge Detect Polarity Select Interrupt negative edge Interrupt positive edge INT0EP: External Interrupt Edge Detect Polarity Select Interrupt negative edge Interrupt positive edge
13-3
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REGISTER 7-5:
R/W-0 T2IF Legend: Readable Value 15-14 Writable Unimplemented bit, read cleared unknown R/W-0 OC2IF R/W-0 IC2IF R/W-0 T1IF R/W-0 OC1IF R/W-0 IC1IF
IFS0: INTERRUPT FLAG STATUS REGISTER
R/W-0 AD1IF R/W-0 U1TXIF R/W-0 U1RXIF R/W-0 SPI1IF R/W-0 SPI1EIF R/W-0 T3IF R/W-0 INT0IF
Unimplemented: Read AD1IF: ADC1 Conversion Complete Interrupt Flag Status Interrupt request occurred Interrupt request occurred U1TXIF: UART1 Transmitter Interrupt Flag Status Interrupt request occurred Interrupt request occurred U1RXIF: UART1 Receiver Interrupt Flag Status Interrupt request occurred Interrupt request occurred SPI1IF: SPI1 Event Interrupt Flag Status Interrupt request occurred Interrupt request occurred SPI1EIF: SPI1 Fault Interrupt Flag Status Interrupt request occurred Interrupt request occurred T3IF: Timer3 Interrupt Flag Status Interrupt request occurred Interrupt request occurred T2IF: Timer2 Interrupt Flag Status Interrupt request occurred Interrupt request occurred OC2IF: Output Compare Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred IC2IF: Input Capture Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read T1IF: Timer1 Interrupt Flag Status Interrupt request occurred Interrupt request occurred OC1IF: Output Compare Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred
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REGISTER 7-5:
IFS0: INTERRUPT FLAG STATUS REGISTER (CONTINUED)
IC1IF: Input Capture Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred INT0IF: External Interrupt Flag Status Interrupt request occurred Interrupt request occurred
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REGISTER 7-6:
R/W-0 IC8IF Legend: Readable Value 15-14 Writable Unimplemented bit, read cleared unknown R/W-0 IC7IF R/W-0 INT1IF R/W-0 CNIF R/W-0 MI2C1IF
IFS1: INTERRUPT FLAG STATUS REGISTER
R/W-0 INT2IF R/W-0 SI2C1IF
Unimplemented: Read INT2IF: External Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read IC8IF: Input Capture Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred IC7IF: Input Capture Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read INT1IF: External Interrupt Flag Status Interrupt request occurred Interrupt request occurred CNIF: Input Change Notification Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read MI2C1IF: I2C1 Master Events Interrupt Flag Status Interrupt request occurred Interrupt request occurred SI2C1IF: I2C1 Slave Events Interrupt Flag Status Interrupt request occurred Interrupt request occurred
12-8
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REGISTER 7-7:
Legend: Readable Value 15-2 Writable Unimplemented bit, read cleared unknown U1EIF
IFS4: INTERRUPT FLAG STATUS REGISTER
Unimplemented: Read U1EIF: UART1 Error Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read
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REGISTER 7-8:
R/W-0 T2IE Legend: Readable Value 15-14 Writable Unimplemented bit, read cleared unknown R/W-0 OC2IE R/W-0 IC2IE R/W-0 T1IE R/W-0 OC1IE R/W-0 IC1IE
IEC0: INTERRUPT ENABLE CONTROL REGISTER
R/W-0 AD1IE R/W-0 U1TXIE R/W-0 U1RXIE R/W-0 SPI1IE R/W-0 SPI1EIE R/W-0 T3IE R/W-0 INT0IE
Unimplemented: Read AD1IE: ADC1 Conversion Complete Interrupt Enable Interrupt request enabled Interrupt request enabled U1TXIE: UART1 Transmitter Interrupt Enable Interrupt request enabled Interrupt request enabled U1RXIE: UART1 Receiver Interrupt Enable Interrupt request enabled Interrupt request enabled SPI1IE: SPI1 Event Interrupt Enable Interrupt request enabled Interrupt request enabled SPI1EIE: SPI1 Error Interrupt Enable Interrupt request enabled Interrupt request enabled T3IE: Timer3 Interrupt Enable Interrupt request enabled Interrupt request enabled T2IE: Timer2 Interrupt Enable Interrupt request enabled Interrupt request enabled OC2IE: Output Compare Channel Interrupt Enable Interrupt request enabled Interrupt request enabled IC2IE: Input Capture Channel Interrupt Enable Interrupt request enabled Interrupt request enabled Unimplemented: Read T1IE: Timer1 Interrupt Enable Interrupt request enabled Interrupt request enabled OC1IE: Output Compare Channel Interrupt Enable Interrupt request enabled Interrupt request enabled
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REGISTER 7-8:
IEC0: INTERRUPT ENABLE CONTROL REGISTER (CONTINUED)
IC1IE: Input Capture Channel Interrupt Enable Interrupt request enabled Interrupt request enabled INT0IE: External Interrupt Enable Interrupt request enabled Interrupt request enabled
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REGISTER 7-9:
R/W-0 IC8IE Legend: Readable Value 15-14 Writable Unimplemented bit, read cleared unknown R/W-0 IC7IE R/W-0 INT1IE R/W-0 CNIE R/W-0 MI2C1IE
IEC1: INTERRUPT ENABLE CONTROL REGISTER
R/W-0 INT2IE R/W-0 SI2C1IE
Unimplemented: Read INT2IE: External Int
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