64/100-Pin General Purpose 32-Bit Flash Microcontrollers 2009 Mic
|
|
|
Top Searches for this datasheet
PIC32MX3XX/4XX Family Data Sheet
64/100-Pin General Purpose 32-Bit Flash Microcontrollers
2009 Microchip Technology Inc.
DS61143F
Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
Code protection constantly evolving. Microchip committed continuously improving code protection features products. Attempts break Microchip's code protection feature violation Digital Millennium Copyright Act. such acts allow unauthorized access your software other copyrighted work, have right relief under that Act.
Information contained this publication regarding device applications like provided only your convenience superseded updates. your responsibility ensure that your application meets with your specifications. MICROCHIP MAKES REPRESENTATIONS WARRANTIES KIND WHETHER EXPRESS IMPLIED, WRITTEN ORAL, STATUTORY OTHERWISE, RELATED INFORMATION, INCLUDING LIMITED CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY FITNESS PURPOSE. Microchip disclaims liability arising from this information use. Microchip devices life support and/or safety applications entirely buyer's risk, buyer agrees defend, indemnify hold harmless Microchip from damages, claims, suits, expenses resulting from such use. licenses conveyed, implicitly otherwise, under Microchip intellectual property rights.
Trademarks Microchip name logo, Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC UNI/O registered trademarks Microchip Technology Incorporated U.S.A. other countries. FilterLab, Hampshire, HI-TECH Linear Active Thermistor, MXDEV, MXLAB, SEEVAL Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, Omniscient Code Generation, PICC, PICC-18, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2009, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
DS61143F-page
2009 Microchip Technology Inc.
PIC32MX3XX/4XX
High-Performance MIPS-Based 32-bit Flash Microcontroller
64/100-Pin General Purpose
High-Performance 32-bit RISC CPU:
MIPS32® M4K32-bit Core with 5-Stage Pipeline Maximum Frequency 1.56 DMIPS/MHz (Dhrystone 2.1) Performance Wait State Flash Access Single-Cycle Multiply High-Performance Divide Unit MIPS16eMode Smaller Code Size Sets Core Register Files (32-bit) Reduce Interrupt Latency Prefetch Cache Module Speed Execution from Flash
Microcontroller Features:
Operating Voltage Range 2.3V 3.6V 512K Flash Memory (plus additional 12KB Boot Flash) SRAM Memory Pin-Compatible with Most PIC24/dsPIC® Devices Multiple Power Management Modes Multiple Interrupt Vectors with Individually Programmable Priority Fail-Safe Clock Monitor Mode Configurable Watchdog Timer with On-Chip Low-Power Oscillator Reliable Operation
Separate PLLs Clocks I2CModules UART Modules with: RS-232, RS-485 support IrDA® with On-Chip Hardware Encoder Decoder Parallel Master Slave Port (PMP/PSP) with 8-bit 16-bit Data Address Lines Hardware Real-Time Clock/Calendar (RTCC) Five 16-bit Timers/Counters (two 16-bit pairs combine create 32-bit timers) Five Capture Inputs Five Compare/PWM Outputs Five External Interrupt Pins High-Speed Pins Capable Toggling High-Current Sink/Source mA/18 Pins Configurable Open-Drain Output Digital Pins
Debug Features:
Programming Debugging Interfaces: 2-Wire Interface with Unintrusive Access Real-time Data Exchange with Application 4-wire MIPS® Standard Enhanced JTAG interface Unintrusive Hardware-Based Instruction Trace IEEE 1149.2 Compatible (JTAG) Boundary Scan
Peripheral Features:
Atomic SET, CLEAR INVERT Operation Select Peripheral Registers 4-Channel Hardware with Automatic Data Size Detection Compliant Full Speed Device On-The-Go (OTG) Controller Dedicated Channel Crystal Oscillator Internal Oscillators
Analog Features:
16-Channel 10-bit Analog-to-Digital Converter: 1000 ksps Conversion Rate Conversion Available During Sleep, Idle Analog Comparators Tolerant Input Pins (digital pins only)
2009 Microchip Technology Inc.
DS61143F-page
PIC32MX3XX/4XX
TABLE PIC32MX GENERAL PURPOSE FEATURES
GENERAL PURPOSE
Timers/Capture/Compare Program Memory (KB) Programmable Channels
Data Memory (KB)
EUART/SPI/I2C
10-bit (ch)
Comparators
Device
PIC32MX320F032H PIC32MX320F064H PIC32MX320F128H PIC32MX340F128H PIC32MX340F256H PIC32MX340F512H PIC32MX320F128L PIC32MX340F128L PIC32MX360F256L PIC32MX360F512L Legend: Note TQFP
12(1) 12(1) 12(1) 12(1) 12(1) 12(1) 12(1) 12(1) 12(1) 12(1)
5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5
2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 2/2/2
This device features Boot Flash memory. Legend explanation acronyms. Section 29.0 "Packaging Information" details.
TABLE
PIC32MX FEATURES
Timers/Capture/Compare Program Memory (KB) Dedicated Channels Programmable Channels
Data Memory (KB)
EUART/SPI/I2C
10-bit (ch)
Comparators
Device
PIC32MX420F032H PIC32MX440F128H PIC32MX440F256H PIC32MX440F512H PIC32MX440F128L PIC32MX460F256L PIC32MX460F512L Legend: Note TQFP
12(1)
5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5
2/1/2 2/1/2 2/1/2 2/1/2 2/2/2
12(1)
12(1) 12(1) 12(1)
2/2/2 2/2/2
This device features Boot Flash memory. Legend explanation acronyms. Section 29.0 "Packaging Information" details.
DS61143F-page
2009 Microchip Technology Inc.
Packages(2)
PMP/PSP
VREG
Trace
JTAG
Pins
Packages(2)
PMP/PSP
VREG
Trace
JTAG
Pins
PIC32MX3XX/4XX
DIAGRAM: 64-PIN GENERAL PURPOSE
64-Pin (General Purpose)
Pins tolerant
PMD5/RE5 PMD6/RE6 PMD7/RE7 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1
PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/PMA14/INT4/RD11 IC3/PMCS2/PMA15/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/RTCC/INT1/RD8 OSC2/CLKO/RC15 OSC1/CLKI/RC12 SCL1/RG2 SDA1/RG3 U1RTS/BCLK1/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3
PIC32MX3XXH
PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS U2CTS/C1OUT/AN8/RB8 PMA7/C2OUT/AN9/RB9 TMS/CVREFOUT/PMA13/AN10/RB10 TDO/PMA12/AN11/RB11 TCK/PMA11/AN12/RB12 TDI/PMA10/AN13/RB13 PMALL/PMA0/AN15/OCFB/CN12/RB15 PMA9/U2RX/SDA2/CN17/RF4 PMA8/U2TX/SCL2/CN18/RF5
Note:
metal plane bottom device connected pins recommended connected externally.
2009 Microchip Technology Inc.
DS61143F-page
PIC32MX3XX/4XX
DIAGRAM: 64-PIN TQFP GENERAL PURPOSE
64-Pin TQFP (General Purpose)
Pins tolerant
PMD5/RE5 PMD6/RE6 PMD7/RE7 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1
PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1
PIC32MX3XXH
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/PMA14/INT4/RD11 IC3/PMCS2/PMA15/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/RTCC/INT1/RD8 OSC2/CLKO/RC15 OSC1/CLKI/RC12 SCL1/RG2 SDA1/RG3 U1RTS/BCLK1/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3
PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS U2CTS/C1OUT/AN8/RB8 PMA7/C2OUT/AN9/RB9 TMS/CVREFOUT/PMA13/AN10/RB10 TDO/PMA12/AN11/RB11 TCK/PMA11/AN12/RB12 TDI/PMA10/AN13/RB13 PMALL/PMA0/AN15/OCFB/CN12/RB15 PMA9/U2RX/SDA2/CN17/RF4 PMA8/U2TX/SCL2/CN18/RF5
DS61143F-page
2009 Microchip Technology Inc.
PIC32MX3XX/4XX
DIAGRAM: 100-PIN TQFP GENERAL PURPOSE
100-Pin TQFP (General Purpose)
Pins tolerant
PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 PMD9/RG1 PMD10/RF1 PMD11/RF0 ENVREG VCAP/VDDCORE PMD15/CN16/RD7 PMD14/CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/CN13/RD4 PMD13/CN19/RD13 PMD12/IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1
RG15 PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/RC4 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 TMS/RA0 INT1/RE8 INT2/RE9 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0
PIC32MX3XXL
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/PMA14/RD11 IC3/PMCS2/PMA15/RD10 IC2/RD9 IC1/RTCC/RD8 INT4/RA15 INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKI/RC12 TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3
2009 Microchip Technology Inc.
PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 PMA7/VREF-/CVREF-/RA9 PMA6/VREF+/CVREF+/RA10 AVDD AVSS C1OUT/AN8/RB8 C2OUT/AN9/RB9 CVREFOUT/PMA13/AN10/RB10 PMA12/AN11/RB11 TCK/RA1 U2RTS/BCLK2/RF13 U2CTS/RF12 PMA11/AN12/RB12 PMA10/AN13/RB13 PMALH/PMA1/AN14/RB14 PMALL/PMA0/AN15/OCFB/CN12/RB15 CN20/U1CTS/RD14 U1RTS/BCLK1/CN21/RD15 PMA9/U2RX/CN17/RF4 PMA8/U2TX/CN18/RF5
DS61143F-page
PIC32MX3XX/4XX
DIAGRAM: 64-PIN
64-Pin (USB)
Pins tolerant
PMD5/RE5 PMD6/RE6 PMD7/RE7 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 VBUSON/C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1
ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/IC5/CN13/RD4 OC4/U1TX/RD3 OC3/U1RX/RD2 OC2/U1RTS/BCLK1/RD1
PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0
PIC32MX4XXH
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 IC4/PMCS1/PMA14/INT4/RD11 IC3/PMCS2/PMA15/INT3/SCL1/RD10 IC2/U1CTS//INT2/SDA1/RD9 IC1/RTCC/INT1/RD8 OSC2/CLKO/RC15 OSC1/CLKI/RC12 D+/RG2 D-/RG3 VUSB VBUS USBID/RF3
PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS U2CTS/C1OUT/AN8/RB8 PMA7/C2OUT/AN9/RB9 TMS/CVREFOUT/PMA13/AN10/RB10 TDO/PMA12/AN11/RB11 TCK/PMA11/AN12/RB12 TDI/PMA10/AN13/RB13 PMALL/PMA0/AN15/OCFB/CN12/RB15 PMA9/U2RX/SDA2/CN17/RF4 PMA8/U2TX/SCL2/CN18/RF5
Note:
metal plane bottom device connected pins recommended connected externally.
DS61143F-page
2009 Microchip Technology Inc.
PIC32MX3XX/4XX
DIAGRAM: 64-PIN TQFP
64-Pin TQFP (USB)
Pins tolerant
PMD5/RE5 PMD6/RE6 PMD7/RE7 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 VBUSON/C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1
PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/IC5/CN13/RD4 OC4/U1TX/RD3 OC3/U1RX/RD2 OC2/U1RTS/BCLK1/RD1
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 IC4/PMCS1/PMA14/INT4/RD11 IC3/PMCS2/PMA15/INT3/SCL1/RD10 IC2/U1CTS//INT2/SDA1/RD9 IC1/RTCC/INT1/RD8 OSC2/CLKO/RC15 OSC1/CLKI/RC12 D+/RG2 D-/RG3 VUSB VBUS USBID/RF3
PIC32MX4XXH
2009 Microchip Technology Inc.
PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS U2CTS/C1OUT/AN8/RB8 PMA7/C2OUT/AN9/RB9 TMS/CVREFOUT/PMA13/AN10/RB10 TDO/PMA12/AN11/RB11 TCK/PMA11/AN12/RB12 TDI/PMA10/AN13/RB13 PMALL/PMA0/AN15/OCFB/CN12/RB15 PMA9/U2RX/SDA2/CN17/RF4 PMA8/U2TX/SCL2/CN18/RF5
DS61143F-page
PIC32MX3XX/4XX
DIAGRAM: 100-PIN TQFP
100-Pin TQFP (USB)
Pins tolerant
RG15 PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 SDI1/T5CK/RC4 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 TMS/RA0 INT1/RE8 INT2/RE9 VBUSON/C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0
PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 PMD9/RG1 PMD10/RF1 PMD11/RF0 ENVREG VCAP/VDDCORE PMD15/CN16/RD7 PMD14/CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/CN13/RD4 PMD13/CN19/RD13 PMD12/IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1
PIC32MX4XXL
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 IC4/PMCS1/PMA14/RD11 IC3/SCK1/PMCS2/PMA15/RD10 IC2/SS1/RD9 IC1/RTCC/RD8 SDA1/INT4/RA15 SCL1/INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKI/RC12 TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 D+/RG2 D-/RG3 VUSB VBUS U1TX/RF8 U1RX/RF2 USBID/RF3
PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 PMA7/VREF-/CVREF-/RA9 PMA6/VREF+/CVREF+/RA10 AVDD AVSS C1OUT/AN8/RB8 C2OUT/AN9/RB9 CVREFOUT/PMA13/AN10/RB10 PMA12/AN11/RB11 TCK/RA1 U2RTS/BCLK2/RF13 U2CTS/RF12 PMA11/AN12/RB12 PMA10/AN13/RB13 PMALH/PMA1/AN14/RB14 PMALL/PMA0/AN15/OCFB/CN12/RB15 CN20/U1CTS/RD14 U1RTS/BCLK1/CN21/RD15 PMA9/U2RX/CN17/RF4 PMA8/U2TX/CN18/RF5
DS61143F-page
2009 Microchip Technology Inc.
PIC32MX3XX/4XX
Table Contents
High-Performance MIPS-Based 32-bit Flash Microcontroller 64/100-Pin General Purpose Device Overview Guidelines Getting Started with 32-bit Microcontrollers PIC32MX MCU. Memory Organization Flash Program Memory. Resets Interrupt Controller Oscillator Configuration Prefetch Cache. 10.0 Direct Memory Access (DMA) Controller 11.0 On-The-Go (OTG). 12.0 Ports 13.0 Timer1 14.0 Timers 15.0 Input Capture. 16.0 Output Compare. 17.0 Serial Peripheral Interface (SPI). 18.0 Inter-Integrated Circuit (I2CTM) 19.0 Universal Asynchronous Receiver Transmitter (UART) 20.0 Parallel Master Port (PMP). 21.0 Real-Time Clock Calendar (RTCC). 22.0 10-bit Analog-to-Digital Converter (ADC) 23.0 Comparator 24.0 Comparator Voltage Reference (CVref) 25.0 Power-Saving Features. 26.0 Special Features 27.0 Instruction 28.0 Development Support. 28.0 Electrical Characteristics 29.0 Packaging Information. INDEX Worldwide Sales Service
2009 Microchip Technology Inc.
DS61143F-page
PIC32MX3XX/4XX
VALUED CUSTOMERS
intention provide valued customers with best documentation possible ensure successful your Microchip products. this end, will continue improve publications better suit your needs. publications will refined enhanced volumes updates introduced. have questions comments regarding this publication, please contact Marketing Communications Department E-mail docerrors@microchip.com Reader Response Form back this data sheet (480) 792-4150. welcome your feedback.
Most Current Data Sheet
obtain most up-to-date version this data sheet, please register Worldwide site http://www.microchip.com determine version data sheet examining literature number found bottom outside corner page. last character literature number version number, (e.g., DS30000A version document DS30000).
Errata
errata sheet, describing minor operational differences from data sheet recommended workarounds, exist current devices. device/documentation issues become known will publish errata sheet. errata will specify revision silicon revision document which applies. determine errata sheet exists particular device, please check with following: Microchip's Worldwide site; http://www.microchip.com Your local Microchip sales office (see last page) When contacting sales office, please specify which device, revision silicon data sheet (include literature number) using.
Customer Notification System
Register site www.microchip.com receive most current information products.
DS61143F-page
2009 Microchip Technology Inc.
PIC32MX3XX/4XX
Note:
DEVICE OVERVIEW
This data sheet summarizes features PIC32MX3XX/4XX family devices. intended comprehensive reference source. complement information this data sheet, refer appropriate section "PIC32MX Family Reference Manual", which available from Microchip site (www.microchip.com/PIC32)
This document contains device-specific information PIC32MX3XX/4XX devices. Figure shows general block diagram core peripheral modules PIC32MX3XX/4XX families devices. Table lists functions various pins shown pinout diagrams.
FIGURE 1-1:
BLOCK DIAGRAM(1,2)
OSC2/CLKO OSC1/CLKI VDDCORE/VCAP OSC/SOSC Oscillators FRC/LPRC Oscillators DIVIDERS PLL-USB Timing Generation Precision Band Reference USBCLK SYSCLK PBCLK ENVREG Voltage Regulator
Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset
VDD, MCLR
Peripheral Clocked SYSCLK PORTA Priority Interrupt Controller EJTAG DMAC
CN1-22 Timer1-5 Peripheral Clocked PBCLK
JTAG BSCAN
PORTB
PORTC
MIPS M4K® Core Matrix
PORTD
PORTE Prefetch Module
Data
Peripheral Bridge 10-bit
PORTF
UART 128-bit wide Program Flash Memory Flash Controller RTCC Comparators
PORTG
Note
Some features available device variants. functionality provided when on-board voltage regulator enabled.
2009 Microchip Technology Inc.
DS61143F-page
PIC32MX3XX/4XX
TABLE 1-1:
Name AN0-AN15 CLKI CLKO OSC1 OSC2 SOSCI SOSCO CN0-CN21 IC1-IC5 OCFA OC1-OC5 OCFB INT0 INT1 INT2 INT3 INT4 RA0-RA15 RB0-RB15 RC0-RC15 RD0-RD15 RE0-RE15 RF0-RF15 RG0, RG1, RG4-RG15 RG2, T1CK T2CK T3CK T4CK T5CK U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX
PINOUT DESCRIPTIONS
Type Buffer Type Analog Analog input channels. Description
ST/CMOS External clock source input. Always associated with OSC1 function. Oscillator crystal output. Connects crystal resonator Crystal Oscillator mode. Optionally functions CLKO modes. Always associated with OSC2 function. ST/CMOS Oscillator crystal input. buffer when configured mode; CMOS otherwise. Oscillator crystal output. Connects crystal resonator Crystal Oscillator mode. Optionally functions CLKO modes. ST/CMOS 32.768 low-power oscillator crystal input; CMOS otherwise. 32.768 low-power oscillator crystal output. Change notification inputs. software programmed internal weak pull-ups inputs. Capture inputs 1-5. Compare Fault input. Compare outputs through Output Compare Fault Input. External interrupt External interrupt External interrupt External interrupt External interrupt PORTA bidirectional port. PORTB bidirectional port. PORTC bidirectional port. PORTD bidirectional port. PORTE bidirectional port. PORTF bidirectional port. PORTG bidirectional port. PORTG input pins. Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. Timer4 external clock input. Timer5 external clock input. UART1 clear send. UART1 ready send. UART1 receive. UART1 transmit. UART2 clear send. UART2 ready send. UART2 receive. UART2 transmit. Analog Analog input Output Power Input
Legend: CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels input buffer
DS61143F-page
2009 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 1-1:
Name SCK1 SDI1 SDO1 SCK2 SDI2 SDO2 SCL1 SDA1 RTCC CVREF- CVREF+ CVREFOUT C1INC1IN+ C1OUT C2INC2IN+ C2OUT PMA0 PMA1 PMA2-PMPA15 PMENB PMCS1 PMCS2 PMD0-PMD15 PMRD PMWR PMALL PMALH PMRD/PMWR PMALL PMALH PMRD/PMWR
PINOUT DESCRIPTIONS (CONTINUED)
Type Buffer Type TTL/ST TTL/ST TTL/ST Description Synchronous serial clock input/output SPI1. SPI1 data SPI1 data out. SPI1 slave synchronization frame pulse I/O. Synchronous serial clock input/output SPI2. SPI2 data SPI2 data out. SPI2 slave synchronization frame pulse I/O. Synchronous serial clock input/output I2C1. Synchronous serial data input/output I2C1. JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin. Real-Time Clock Alarm Output. Comparator Voltage Reference (low). Comparator Voltage Reference (high). Comparator Voltage Reference Output. Comparator Negative Input. Comparator Positive Input. Comparator Output. Comparator Negative Input. Comparator Positive Input. Comparator Output. Parallel Master Port Address Input (Buffered Slave modes) Output (Master modes). Parallel Master Port Address Input (Buffered Slave modes) Output (Master modes). Parallel Master Port Address (Demultiplexed Master Modes). Parallel Master Port Enable Strobe (Master mode Parallel Master Port Chip Select Strobe. Parallel Master Port Chip Select Strobe. Parallel Master Port Data (Demultiplexed Master mode) Address/Data (Multiplexed Master modes). Parallel Master Port Read Strobe. Parallel Master Port Write Strobe. Parallel Master Port Address Latch Enable low-byte (Multiplexed Master modes). Parallel Master Port Address Latch Enable high-byte (Multiplexed Master modes). Parallel Master Port Read/Write Strobe (Master mode Parallel Master Port Address Latch Enable low-byte (Multiplexed Master modes). Parallel Master Port Address Latch Enable high-byte (Multiplexed Master modes). Parallel Master Port Read/Write Strobe (Master mode Analog Analog input Output Power Input
Legend: CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels input buffer
2009 Microchip Technology Inc.
DS61143F-page
PIC32MX3XX/4XX
TABLE 1-1:
Name VBUS VUSB VBUSON USBID ENVREG TRCLK TRD0-TRD3 PGED1 PGEC1 PGED2 PGEC2 MCLR AVdd AVss Vcap/Vddcore VREF+ VREF-
PINOUT DESCRIPTIONS (CONTINUED)
Type Buffer Type Analog Analog Description Power Monitor. Internal Transceiver Supply. Host Power Control Output. Detect. Enable On-Chip Voltage Regulator. Trace Clock. Trace Data Bits Data programming/debugging communication channel Clock input programming/debugging communication channel Data programming/debugging communication channel Clock input programming/debugging communication channel Master Clear (Reset) input. This active-low Reset device. Positive supply analog modules. This must connected times. Ground reference analog modules. Positive supply peripheral logic pins. logic filter capacitor connection. Ground reference logic pins. Analog voltage reference (high) input. Analog voltage reference (low) input. Analog Analog input Output Power Input
Legend: CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels input buffer
DS61143F-page
2009 Microchip Technology Inc.
PIC32MX3XX/4XX
GUIDELINES GETTING STARTED WITH 32-BIT MICROCONTROLLERS
This data sheet summarizes features PIC32MX3XX/4XX family devices. intended comprehensive reference source. Refer "PIC32MX Family Reference Manual" detailed description PIC32MX MCU. manual available from Microchip site (www.Microchip.com/PIC32).
Decoupling Capacitors
Note:
decoupling capacitors every pair power supply pins, such VDD, VSS, AVDD, AVSS required. Figure 2-1. Consider following criteria when using decoupling capacitors: Value type capacitor: Recommendation (100 nF), 10-20V. This capacitor should low-ESR have resonance frequency range higher. recommended that ceramic capacitors used. Placement printed circuit board: decoupling capacitors should placed close pins possible. recommended place capacitors same side board device. space constricted, capacitor placed another layer using via; however, ensure that trace length from capacitor within onequarter inch length. Handling high frequency noise: board experiencing high frequency noise, upward tens MHz, second ceramic-type capacitor parallel above described decoupling capacitor. value second capacitor range 0.01 0.001 Place this second capacitor next primary decoupling capacitor. high-speed circuit designs, consider implementing decade pair capacitances close power ground pins possible. example, parallel with 0.001 Maximizing performance: board layout from power supply circuit, power return traces decoupling capacitors first, then device pins. This ensures that decoupling capacitors first power chain. Equally important keep trace length between capacitor power pins minimum thereby reducing track inductance.
Basic Connection Requirements
Getting started with PIC32MX3XX/4XX family 32-bit Microcontrollers (MCU) requires attention minimal device connections before proceeding with development. following list names, which must always connected: pins (see Section 2.2) AVDD AVSS pins (regardless module used) (see Section 2.2) VCAP/VDDCORE (see Section 2.3) MCLR (see Section 2.4) PGECx/PGEDx pins used In-Circuit Serial Programming(ICSPTM) debugging purposes (see Section 2.5) OSC1 OSC2 pins when external oscillator source used (see Section 2.8) Additionally, following pins required: VREF+/VREF- pins used when external voltage reference module implemented Note: AVDD AVSS pins must connected independent voltage reference source.
2009 Microchip Technology Inc.
DS61143F-page
PIC32MX3XX/4XX
FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION
Ceramic VCAP/VDDCORE
Master Clear (MCLR)
MCLR provides specific device functions: Device Reset Device Programming Debugging Pulling MCLR generates device reset. Figure shows typical MCLR circuit. During device programming debugging, resistance capacitance that added must considered. Device programmers debuggers drive MCLR pin. Consequently, specific voltage levels (VIH VIL) fast signal transitions must adversely affected. Therefore, specific values will need adjusted based application requirements. example, shown Figure 2-2, recommended that capacitor isolated from MCLR during programming debugging operations. Place components shown Figure within one-quarter inch from MCLR pin.
MCLR
PIC32MX
Ceramic Ceramic AVDD AVSS Ceramic
Ceramic
2.2.1
BULK CAPACITORS
bulk capacitor recommended improve power supply stability. Typical values range from This capacitor should located close device possible.
FIGURE 2-2:
EXAMPLE MCLR CONNECTIONS
MCLR PIC32MX
2.3.1
Capacitor Internal Voltage Regulator (VCAP/VDDCORE)
INTERNAL REGULATOR MODE
low-ESR Ohms) capacitor required VCAP/VDDCORE pin, which used stabilize internal voltage regulator output. VCAP/VDDCORE must connected VDD, must have capacitor, with least rating, connected ground. type ceramic tantalum. Refer Section 28.0 "Electrical Characteristics" additional information. This mode enabled connecting ENVREG VDD.
Note
recommended. suggested starting value Ensure that MCLR specifications met. will limit current flowing into MCLR from external capacitor event MCLR breakdown, Electrostatic Discharge (ESD) Electrical Overstress (EOS). Ensure that MCLR specifications met. capacitor sized prevent unintentional resets from brief glitches extend device reset period during POR.
2.3.2
EXTERNAL REGULATOR MODE
this mode core voltage supplied externally through VDDCORE pin. low-ESR capacitor recommended VDDCORE pin. This mode enabled grounding ENVREG pin. placement this capacitor should close VCAP/VDDCORE. recommended that trace length exceed one-quarter inch mm). Refer Section 26.3 "On-Chip Voltage Regulator" details.
DS61143F-page
2009 Microchip Technology Inc.
PIC32MX3XX/4XX
ICSP Pins
PGECx PGEDx pins used In-Circuit Serial Programming(ICSPTM) debugging purposes. recommended keep trace length between ICSP connector ICSP pins device short possible. ICSP connector expected experience event, series resistor recommended, with value range tens Ohms, exceed Ohms. Pull-up resistors, series diodes, capacitors PGECx PGEDx pins recommended they will interfere with programmer/debugger communications device. such discrete components application requirement, they should removed from circuit during programming debugging. Alternately, refer AC/DC characteristics timing requirements information respective device Flash programming specification information capacitive loading limits input voltage high (VIH) input (VIL) requirements. Ensure that "Communication Channel Select" (i.e., PGECx/PGEDx pins) programmed into device matches physical connections ICSP MPLAB® MPLAB® MPLAB® REAL ICETM. more information REAL connection requirements, refer following documents that available Microchip website. "MPLAB® In-Circuit Debugger User's Guide" DS51331 "Using MPLAB® (poster) DS51265 "MPLAB® Design Advisory" DS51566 "Using MPLAB® (poster) DS51765 "MPLAB® Design Advisory" DS51764 "MPLAB® REAL ICEIn-Circuit Debugger User's Guide" DS51616 "Using MPLAB® REAL ICETM" (poster) DS51749 Pull-up resistors, series diodes, capacitors TMS, TDO, TDI, pins recommended they will interfere with programmer/debugger communications device. such discrete components application requirement, they should removed from circuit during programming debugging. Alternately, refer AC/DC characteristics timing requirements information respective device Flash programming specification information capacitive loading limits input voltage high (VIH) input (VIL) requirements.
Trace
trace pins connected hardware-traceenabled programmer provide compress real time instruction trace. When used trace TRD3, TRD2, TRD1, TRD0, TRCLK pins should dedicated this use. trace hardware requires series resistor between trace pins trace connector.
External Oscillator Pins
Many MCUs have options least oscillators: high-frequency primary oscillator low-frequency secondary oscillator (refer Section "Oscillator Configuration" details). oscillator circuit should placed same side board device. Also, place oscillator circuit close respective oscillator pins, exceeding one-half inch distance between them. load capacitors should placed next oscillator itself, same side board. grounded copper pour around oscillator circuit isolate them from surrounding circuits. grounded copper pour should routed directly ground. signal traces power traces inside ground pour. Also, using two-sided board, avoid traces other side board where crystal placed. suggested layout shown Figure 2-3.
JTAG
TMS, TDO, TDI, pins used testing debugging according Joint Test Action Group (JTAG) standard. recommended keep trace length between JTAG connector JTAG pins device short possible. JTAG connector expected experience event, series resistor recommended, with value range tens Ohms, exceed Ohms.
FIGURE 2-3:
SUGGESTED PLACEMENT OSCILLATOR CIRCUIT
Oscillator Secondary Guard Trace Guard Ring Main Oscillator
2009 Microchip Technology Inc.
DS61143F-page
PIC32MX3XX/4XX
Configuration Analog Digital Pins During ICSP Operations 2.10 Unused I/Os
Unused pins should allowed float inputs. They configured outputs driven logic-low state. Alternately, inputs reserved connecting through resistor configuring input.
MPLAB REAL selected debugger, automatically initializes input pins (ANx) "digital" pins setting bits ADPCFG register. bits this register that correspond pins that initialized MPLAB REAL ICE, must cleared user application firmware; otherwise, communication errors will result between debugger device. your application needs certain pins analog input pins during debug session, user application must clear corresponding bits ADPCFG register during initialization module. When MPLAB REAL used programmer, user application firmware must correctly configure ADPCFG register. Automatic initialization this register only done during debugger operation. Failure correctly configure register(s) will result pins being recognized analog input pins, resulting port value being read logic '0', which affect user application functionality.
DS61143F-page
2009 Microchip Technology Inc.
PIC32MX3XX/4XX
Note:
PIC32MX
This data sheet summarizes features PIC32MX3XX/4XX Family devices. intended comprehensive reference source. Refer "PIC32MX Family Reference Manual" Section "MCU" (DS61113) detailed description PIC32MX MCU. manual available from Microchip site (www.Microchip.com/PIC32). Resources MIPS32® M4K® Processor Core available mips32-m4k/#.
module heart PIC32MX3XX/4XX Family processor. fetches instructions, decodes each instruction, fetches source operands, executes each instruction, writes results instruction execution proper destinations.
Features
5-stage pipeline 32-bit Address Data Paths MIPS32 Enhanced Architecture (Release Multiply-Accumulate Multiply-Subtract Instructions Targeted Multiply Instruction Zero/One Detect Instructions WAIT Instruction Conditional Move Instructions (MOVN, MOVZ) Vectored interrupts Programmable exception vector base Atomic interrupt enable/disable shadow registers minimize latency interrupt handlers field manipulation instructions
MIPS16eCode Compression 16-bit encoding 32-bit instructions improve code density Special PC-relative instructions efficient loading addresses constants SAVE RESTORE macro instructions setting tearing down stack frames within subroutines Improved support handling 16-bit data types Simple Fixed Mapping Translation (FMT) mechanism Simple Dual Interface Independent 32-bit address data busses Transactions aborted improve interrupt latency Autonomous Multiply/Divide Unit Maximum issue rate 32x16 multiply clock Maximum issue rate 32x32 multiply every other clock Early-in iterative divide. Minimum maximum clock latency (dividend (rs) sign extension-dependent) Power Control Minimum frequency: Low-Power mode (triggered WAIT instruction) Extensive local gated clocks EJTAG Debug Instruction Trace Support single stepping Virtual instruction data address/value breakpoints tracing with trace compression
FIGURE 3-1:
BLOCK DIAGRAM
EJTAG Trace Trace Off-Chip Debug
Interface
Dual
System Coprocessor
Power Mgmt
2009 Microchip Technology Inc.
Matrix
DS61143F-page
Execution Core (RF/ALU/Shift)
PIC32MX3XX/4XX
Architecture Overview
3.2.2 MULTIPLY/DIVIDE UNIT (MDU)
PIC32MX3XX/4XX Family core contains several logic blocks working together parallel, providing efficient high performance computing engine. following blocks included with core: Execution Unit Multiply/Divide Unit (MDU) System Control Coprocessor (CP0) Fixed Mapping Translation (FMT) Dual Internal interfaces Power Management MIPS16e Support Enhanced JTAG (EJTAG) Controller PIC32MX3XX/4XX Family core includes multiply/divide unit (MDU) that contains separate pipeline multiply divide operations. This pipeline operates parallel with integer unit (IU) pipeline does stall when pipeline stalls. This allows operations partially masked system stalls and/or other integer unit instructions. high-performance consists 32x16 booth recoded multiplier, result/accumulation registers LO), divide state machine, necessary multiplexers control logic. first number shown (`32' 32x16) represents operand. second number (`16' 32x16) represents operand. PIC32MX core only checks value latter (rt) operand determine many times operation must pass through multiplier. 16x16 32x16 operations pass through multiplier once. 32x32 operation passes through multiplier twice. supports execution 16x16 32x16 multiply operation every clock cycle; 32x32 multiply operations issued every other clock cycle. Appropriate interlocks implemented stall issuance back-to-back 32x32 multiply operations. multiply operand size automatically determined logic built into MDU. Divide operations implemented with simple clock iterative algorithm. early-in detection checks sign extension dividend (rs) operand. bits wide, iterations skipped. 16bit-wide iterations skipped, 24-bitwide iterations skipped. attempt issue subsequent instruction while divide still active causes pipeline stall until divide operation completed. Table lists repeat rate (peak issue rate cycles until operation reissued) latency (number cycles until result available) PIC32MX core multiply divide instructions. approximate latency repeat rates listed terms pipeline clocks.
3.2.1
EXECUTION UNIT
PIC32MX3XX/4XX Family core execution unit implements load/store architecture with single-cycle operations (logical, shift, add, subtract) autonomous multiply/divide unit. core contains thirty-two 32-bit general purpose registers used integer operations address calculation. additional register file shadow (containing thirty-two registers) added minimize context switching overhead during interrupt/exception processing. register file consists read ports write port fully bypassed minimize operation latency pipeline. execution unit includes: 32-bit adder used calculating data address Address unit calculating next instruction address Logic branch determination branch target address calculation Load aligner Bypass multiplexers used avoid stalls when executing instructions streams where data producing instructions followed closely consumers their results Leading Zero/One detect unit implementing instructions Arithmetic Logic Unit (ALU) performing bitwise logical operations Shifter Store Aligner
DS61143F-page
2009 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 3-1: PIC32MX3XX/4XX FAMILY CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT LATENCIES REPEAT RATES
Opcode MULT/MULTU, MADD/MADDU, MSUB/MSUBU DIV/DIVU Operand Size (mul (div bits bits bits bits bits bits bits bits MIPS architecture defines that result multiply divide operation placed registers. Using Move-From-HI (MFHI) MoveFrom-LO (MFLO) instructions, these values transferred general purpose register file. addition HI/LO targeted operations, MIPS32 architecture also defines multiply instruction, MUL, which places least significant results primary register file instead HI/LO register pair. avoiding explicit MFLO instruction, required when using register, supporting multiple destination registers, throughput multiply-intensive operations increased. other instructions, multiply-add (MADD) multiply-subtract (MSUB), used perform multiplyaccumulate multiply-subtract operations. MADD instruction multiplies numbers then adds Latency Repeat Rate
product current contents registers. Similarly, MSUB instruction multiplies operands then subtracts product from registers. MADD MSUB operations commonly used algorithms.
3.2.3
SYSTEM CONTROL COPROCESSOR (CP0)
MIPS architecture, responsible virtual-to-physical address translation, exception control system, processor's diagnostics capability, operating modes (kernel, user, debug), whether interrupts enabled disabled. Configuration information, such presence options like MIPS16e, also available accessing registers, listed Table 3-2.
TABLE 3-2:
COPROCESSOR REGISTERS
Function Reserved PIC32MX3XX/4XX Family core Enables access RDHWR instruction selected hardware registers Reports address most recent address-related exception Processor cycle count Reserved PIC32MX3XX/4XX Family core Timer interrupt control Processor status control Interrupt system status control Shadow register status control Provides mapping from vectored interrupt shadow Cause last general exception Program counter last exception Processor identification revision Exception vector base register Configuration register Configuration register Configuration register Configuration register
Register Register Number Name Reserved HWREna BadVAddr(1) Count(1) Reserved Compare(1) Status(1) IntCtl(1) SRSCtl(1) SRSMap(1) Cause(1) EPC(1) PRId EBASE Config Config1 Config2 Config3
2009 Microchip Technology Inc.
DS61143F-page
PIC32MX3XX/4XX
TABLE 3-2: COPROCESSOR REGISTERS (CONTINUED)
Function Reserved PIC32MX3XX/4XX Family core Debug control exception status Program counter last debug exception Reserved PIC32MX3XX/4XX Family core Program counter last error Debug handler scratchpad register Register Register Number Name 17-22 25-29 Note Reserved Debug(2) DEPC(2) Reserved ErrorEPC(1) DESAVE(2)
Registers used exception processing. Registers used during debug.
Coprocessor also contains logic identifying managing exceptions. Exceptions caused variety sources, including alignment errors data, external events, program errors. Table shows exception types order priority.
TABLE 3-3:
Exception Reset DINT Interrupt AdEL DDBL DDBS AdEL AdES DDBL
PIC32MX3XX/4XX FAMILY CORE EXCEPTION TYPES
Description Assertion MCLR Power-On Reset (POR) EJTAG Debug Single Step EJTAG Debug Interrupt. Caused assertion external EJ_DINT input, setting EjtagBrk register Assertion signal Assertion unmasked hardware software interrupt signal EJTAG debug hardware instruction break matched Fetch address alignment error Fetch reference protected address Instruction fetch error EJTAG Breakpoint (execution SDBBP instruction) Execution SYSCALL instruction Execution BREAK instruction Execution Reserved Instruction Execution coprocessor instruction coprocessor that enabled Execution CorExtend instruction when CorExtend enabled Execution arithmetic instruction that overflowed Execution trap (when trap condition true) EJTAG Data Address Break (address only) EJTAG Data Value Break Store (address value) Load address alignment error Load reference protected address Store address alignment error Store protected address Load store error EJTAG data hardware breakpoint matched load data compare
DS61143F-page
2009 Microchip Technology Inc.
PIC32MX3XX/4XX
Power Management EJTAG Debug Support
PIC32MX3XX/4XX Family core offers number power management features, including low-power design, active power management, power-down modes operation. core static design that supports slowing halting clocks, which reduces system power consumption during idle periods. PIC32MX3XX/4XX Family core provides Enhanced JTAG (EJTAG) interface software debug application kernel code. addition standard user mode kernel modes operation, PIC32MX3XX/4XX Family core provides Debug mode that entered after debug exception (derived from hardware breakpoint, single-step exception, etc.) taken continues until debug exception return (DERET) instruction executed. During this time, processor executes debug exception handler routine. EJTAG interface operates through Test Access Port (TAP), serial communication port used transferring test data PIC32MX3XX/4XX Family core. addition standard JTAG instructions, special instructions defined EJTAG specification define what registers selected they used.
3.3.1
INSTRUCTION-CONTROLLED POWER MANAGEMENT
mechanism invoking power-down mode through execution WAIT instruction. more information power management, Section 25.0 "Power-Saving Features".
3.3.2
LOCAL CLOCK GATING
majority power consumed PIC32MX3XX/4XX Family core clock tree clocking registers. PIC32MX family uses extensive local gated-clocks reduce this dynamic power consumption.
2009 Microchip Technology Inc.
DS61143F-page
PIC32MX3XX/4XX
NOTES:
DS61143F-page
2009 Microchip Technology Inc.
PIC32MX3XX/4XX
Note:
MEMORY ORGANIZATION
This data sheet summarizes features PIC32MX3XX/4XX family devices. intended comprehensive reference source. Refer "PIC32MX Family Reference Manual" Section "Memory Organization" (DS61115) detailed description this peripheral. manual available from Microchip site (www.Microchip.com/PIC32).
PIC32MX3XX/4XX Memory Layout
PIC32MX3XX/4XX microcontrollers implement address spaces: Virtual Physical. hardware resources such program memory, data memory, peripherals located their respective physical addresses. Virtual addresses exclusively used fetch execute instructions well access peripherals. Physical addresses used peripherals such Flash controller that access memory independently CPU.
PIC32MX3XX/4XX microcontrollers provide unified virtual memory address space. memory regions including program, data memory, SFRs, Configuration registers reside this address space their respective unique addresses. program data memories optionally partitioned into user kernel memories. addition, data memory made executable, allowing PIC32MX3XX/4XX execute from data memory. Features: 32-bit native data width Separate User Kernel mode address space Flexible program Flash memory partitioning Flexible data partitioning data program space Separate boot Flash memory protected code Robust exception handling intercept runaway code. Simple memory mapping with Fixed Mapping Translation (FMT) unit Cacheable non-cacheable address regions
2009 Microchip Technology Inc.
DS61143F-page
PIC32MX3XX/4XX
FIGURE 4-1: MEMORY RESET PIC32MX320F032H, PIC32MX420F032H DEVICES(1)
Virtual Memory 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD008000 0xBD007FFF Program Flash(2) 0xBD000000 0xA0002000 0xA0001FFF RAM(2) 0xA0000000 0x9FC02FF0 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D008000 0x9D007FFF Program Flash(2) 0x9D000000 0x80002000 0x80001FFF RAM(2) 0x80000000 0x00000000 Note Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00002000 0x00001FFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D008000 0x1D007FFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory 0xFFFFFFFF
Memory areas shown scale. size this memory region programmable (see Section "Memory Organization" (DS61115)) changed initialization code provided end-user development tools (refer specific development tool documentation information).
DS61143F-page
2009 Microchip Technology Inc.
PIC32MX3XX/4XX
FIGURE 4-2: MEMORY RESET PIC32MX320F064H DEVICES(1)
Virtual Memory 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD010000 0xBD00FFFF Program Flash(2) 0xBD000000 0xA0004000 0xA0003FFF RAM(2) 0xA0000000 0x9FC02FF0 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D010000 0x9D00FFFF Program Flash(2) 0x9D000000 0x80004000 0x80003FFF RAM(2) 0x80000000 0x00000000 Note Reserved Reserved
Physical Memory 0xFFFFFFFF
Reserved Device Configuration Registers
Reserved
Reserved
Reserved
KSEG1
SFRs
Reserved
0x1FC03000 Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 Reserved 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D010000 Reserved 0x1D00FFFF Program Flash(2) 0x1D000000 0x00004000 0x00003FFF 0x00000000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF
Memory areas shown scale. size this memory region programmable (see Section "Memory Organization" (DS61115)) changed initialization code provided end-user development tools (refer specific development tool documentation information).
2009 Microchip Technology Inc.
DS61143F-page
PIC32MX3XX/4XX
FIGURE 4-3: MEMORY RESET PIC32MX320F128H, PIC32MX320F128L DEVICES(1)
Virtual Memory 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD020000 0xBD01FFFF Program Flash(2) 0xBD000000 0xA0004000 0xA0003FFF RAM(2) 0xA0000000 0x9FC02FF0 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D020000 0x9D01FFFF Program Flash(2) 0x9D000000 0x80004000 0x80003FFF RAM(2) 0x80000000 0x00000000 Note Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00004000 0x00003FFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D020000 0x1D01FFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory 0xFFFFFFFF
Memory areas shown scale. size this memory region programmable (see Section "Memory Organization" (DS61115)) changed initialization code provided end-user development tools (refer specific development tool documentation information).
DS61143F-page
2009 Microchip Technology Inc.
PIC32MX3XX/4XX
FIGURE 4-4: MEMORY RESET PIC32MX340F128H, PIC32MX340F128L, PIC32MX440F128H, PIC32MX440F128L DEVICES(1)
Virtual Memory 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD020000 0xBD01FFFF Program Flash(2) 0xBD000000 0xA0008000 0xA0007FFF RAM(2) 0xA0000000 0x9FC02FF0 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D020000 0x9D01FFFF Program Flash(2) 0x9D000000 0x80008000 0x80007FFF RAM(2) 0x80000000 0x00000000 Note Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00008000 0x00007FFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D020000 0x1D01FFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory 0xFFFFFFFF
Memory areas shown scale. size this memory region programmable (see Section "Memory Organization" (DS61115)) changed initialization code provided end-user development tools (refer specific development tool documentation information).
2009 Microchip Technology Inc.
DS61143F-page
PIC32MX3XX/4XX
FIGURE 4-5: MEMORY RESET PIC32MX340F256H, PIC32MX360F256L, PIC32MX440F256H, PIC32MX460F256L DEVICES(1)
Virtual Memory 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD040000 0xBD03FFFF Program Flash(2) 0xBD000000 0xA0008000 0xA0007FFF RAM(2) 0xA0000000 0x9FC02FF0 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D040000 0x9D03FFFF Program Flash(2) 0x9D000000 0x80008000 0x80007FFF RAM(2) 0x80000000 0x00000000 Note Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00008000 0x00007FFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D040000 0x1D03FFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory 0xFFFFFFFF
Memory areas shown scale. size this memory region programmable (see Section "Memory Organization" (DS61115)) changed initialization code provided end-user development tools (refer specific development tool documentation information).
DS61143F-page
2009 Microchip Technology Inc.
PIC32MX3XX/4XX
FIGURE 4-6: MEMORY RESET PIC32MX340F512H, PIC32MX360F512L, PIC32MX440F512H, PIC32MX460F512L DEVICES(1)
Virtual Memory 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD080000 0xBD07FFFF Program Flash(2) 0xBD000000 0xA0008000 0xA0007FFF RAM(2) 0xA0000000 0x9FC02FF0 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D080000 0x9D07FFFF Program Flash(2) 0x9D000000 0x80008000 0x80007FFF RAM(2) 0x80000000 0x00000000 Note Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00008000 0x00007FFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D080000 0x1D07FFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory 0xFFFFFFFF
Memory areas shown scale. size this memory region programmable (see Section "Memory Organization" (DS61115)) changed initialization code provided end-user development tools (refer specific development tool documentation information).
2009 Microchip Technology Inc.
DS61143F-page
PIC32MX3XX/4XX
4.1.1 PERIPHERAL REGISTERS LOCATIONS
Table through Table 4-25 contain peripheral address maps PIC32MX3XX/4XX device. Peripherals located mapped byte boundaries. Peripherals mapped Kbyte boundaries.
DS61143F-page
2009 Microchip Technology Inc.
TABLE 4-1:
Virtual Addr Name
MATRIX REGISTERS
Bits 31/15
31:16
2009 Microchip Technology Inc.
Bits 30/14
Bits 29/13
Bits 28/12
Bits 27/11
Bits 26/10
CHEDMA
Bits 25/9
Bits 24/8
Bits 23/7
Bits 22/6
WSDRM
Bits 21/5
Bits 20/4
ERRIXI
Bits 19/3
ERRICD
Bits 18/2
ERRDMA
Bits 17/1
ERRDS
Bits 16/0
ERRIS
BF88_2000 BMXCON(1) 15:0 BF88_2010 BF88_2020 BF88_2030 DKPBA(1) DUDBA(1) DUPBA(1) 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
BMXARB<2:0>
BMXDKPBA<15:0> BMXDUDBA<15:0> BMXDUPBA<15:0> BMXDRMSZ<31:0> BMXPUPBA<19:16>
BF88_2040 BMXDRMSZ BF88_2050 PUPBA(1)
BMXPUPBA<15:0> BMXPFMSZ<31:0>
BF88_2060 BMXPFMSZ
DS61143F-page
BF88_2070 Legend: Note
BOOTSZ
BMXBOOTSZ<31:0> 15:0 unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. This register corresponding CLR, SET, Registers virtual address, plus offset 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-2:
Virtual Addr
BF88_1000 BF88_1010 BF88_1020 BF88_1030 BF88_1040 Legend: Note
INTERRUPT REGISTERS MAP(1)
Bits 31/15
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 I2C1MIF INT3IF I2C1SIF OC3IF I2C1BIF IC3IF U1TXIF T3IF U1RXIF INT2IF U1EIF OC2IF SPI1RXIF IC2IF USBIF(4)
Name
INTCON INTSTAT IPTMR IFS0 IFS1
Bits 30/14
Bits 29/13
Bits 28/12
MVEC
Bits 27/11
Bits 26/10
Bits 25/9
TRC<2:0> RIPL<2:0>
Bits 24/8
Bits 23/7
Bits 22/6
Bits 21/5
Bits 20/4
INT4EP
Bits 19/3
INT3EP
Bits 18/2
INT2EP
Bits 17/1
INT1EP
Bits 16/0
INT0EP
PIC32MX3XX/4XX
VEC<5:0>
IPTMR<31:0> SPI1TXIF T2IF FCEIF SPI1EIF INT1IF OC5IF OC1IF IC5IF IC1IF T5IF T1IF INT4IF INT0IF OC4IF CS1IF IC4IF CS0IF T4IF CTIF
DMA3IF(2) DMA2IF(2) DMA1IF(2) DMA0IF(2)
15:0 RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2RXIF(3) SPI2TXIF(3) SPI2EIF(3) CMP2IF CMP1IF PMPIF AD1IF CNIF unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information. These bits present PIC32MX320FXXXX/420FXXXX devices. These bits present PIC32MX420FXXXX/440FXXXX devices. These bits present devices.
TABLE 4-2:
Virtual Addr
BF88_1060 BF88_1070 BF88_1090 BF88_10A0 BF88_10B0 BF88_10C0 BF88_10D0 BF88_10E0 BF88_10F0 BF88_1100 BF88_1110 BF88_1120 BF88_1140 Legend: Note
INTERRUPT REGISTERS MAP(1) (CONTINUED)
Bits 31/15
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 I2C1MIE INT3IE RTCCIE
DS61143F-page
PIC32MX3XX/4XX
Name
IEC0 IEC1 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC9 IPC11
Bits 30/14
I2C1SIE OC3IE FSCMIE
Bits 29/13
I2C1BIE IC3IE I2C2MIE
Bits 28/12
U1TXIE T3IE I2C2SIE
Bits 27/11
U1RXIE INT2IE I2C2BIE INT0IP<2:0> CS0IP<2:0> INT1IP<2:0> IC1IP<2:0> INT2IP<2:0> IC2IP<2:0> INT3IP<2:0> IC3IP<2:0> INT4IP<2:0> IC4IP<2:0> SPI1IP<2:0> IC5IP<2:0> AD1IP<2:0> I2C1IP<2:0> SPI2IP<2:0>(3) CMP1IP<2:0> RTCCIP<2:0> I2C2IP<2:0> DMA3IP<2:0>(2) DMA1IP<2:0>(2)
Bits 26/10
U1EIE OC2IE U2TXIE
Bits 25/9
Bits 24/8
Bits 23/7
SPI1EIE INT1IE
Bits 22/6
OC5IE OC1IE
Bits 21/5
IC5IE IC1IE SPI2EIE(3)
Bits 20/4
T5IE T1IE CMP2IE
Bits 19/3
INT4IE INT0IE CMP1IE CS1IP<2:0> CTIP<2:0> OC1IP<2:0> T1IP<2:0> OC2IP<2:0> T2IP<2:0> OC3IP<2:0> T3IP<2:0> OC4IP<2:0> T4IP<2:0> OC5IP<2:0> T5IP<2:0> CNIP<2:0> U1IP<2:0> CMP2IP<2:0> PMPIP<2:0> FSCMIP<2:0> U2IP<2:0> DMA2IP<2:0>(2) DMA0IP<2:0>(2)
Bits 18/2
OC4IE CS1IE PMPIE
Bits 17/1
IC4IE CS0IE AD1IE
Bits 16/0
T4IE CTIE CNIE
SPI1RXIE SPI1TXIE IC2IE USBIE U2RXIE T2IE FCEIE U2EIE
DMA3IE(2) DMA2IE(2) DMA1IE(2) DMA0IE(2) CS1IS<1:0> CTIS<1:0> OC1IS<1:0> T1IS<1:0> OC2IS<1:0> T2IS<1:0> OC3IS<1:0> T3IS<1:0> OC4IS<1:0> T4IS<1:0> OC5IS<1:0> T5IS<1:0> CNIS<1:0> U1IS<1:0> CMP2IS<1:0> PMPIS<1:0> FSCMIS<1:0> U2IS<1:0> DMA2IS<1:0>(2) DMA0IS<1:0>(2)
SPI2RXIE(3) SPI2TXIE(3)
INT0IS<1:0> CS0IS<1:0> INT1IS<1:0> IC1IS<1:0> INT2IS<1:0> IC2IS<1:0> INT3IS<1:0> IC3IS<1:0> INT4IS<1:0> IC4IS<1:0> SPI1IS<1:0> IC5IS<1:0> AD1IS<1:0> I2C1IS<1:0> SPI2IS<1:0>(3) CMP1IS<1:0> RTCCIS<1:0> I2C2IS<1:0> DMA3IS<1:0>(2) DMA1IS<1:0>(2)
2009 Microchip Technology Inc.
15:0 USBIP<2:0>(4) USBIS<1:0>(4) FCEIP<2:0> FCEIS<1:0> unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information. These bits present PIC32MX320FXXXX/420FXXXX devices. These bits present PIC32MX420FXXXX/440FXXXX devices. These bits present devices.
TABLE 4-3:
Virtual Addr
BF80_0600 BF80_0610 BF80_0620 BF80_0800 BF80_0810 BF80_0820 BF80_0A00 BF80_0A10 BF80_0A20 BF80_0C00 BF80_0C10 BF80_0C20 BF80_0E00 BF80_0E10 BF80_0E20 Legend: Note
TIMER1-5 REGISTERS MAP(1)
Bits 31/15
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 SIDL SIDL SIDL SIDL
2009 Microchip Technology Inc.
Name
T1CON TMR1 T2CON TMR2 T3CON TMR3 T4CON TMR4 T5CON TMR5
Bits 30/14
Bits 29/13
SIDL
Bits 28/12
TWDIS
Bits 27/11
TWIP
Bits 26/10
Bits 25/9
Bits 24/8
Bits 23/7
TGATE TGATE TGATE TGATE TGATE
Bits 22/6
Bits 21/5
TCKPS<2:0> TCKPS<2:0> TCKPS<2:0> TCKPS<2:0>
Bits 20/4
Bits 19/3
Bits 18/2
TSYNC
Bits 17/1
Bits 16/0
TCKPS<1:0>
TMR1<15:0> PR1<15:0>
TMR2<15:0> PR2<15:0>
DS61143F-page
TMR3<15:0> PR3<15:0>
TMR4<15:0>
PIC32MX3XX/4XX
PR4<15:0>
TMR5<15:0>
15:0 PR5<15:0> unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-4:
Virtual Addr Name
INPUT CAPTURE1-5 REGISTERS
Bits 31/15
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 SIDL ICFEDGE SIDL ICFEDGE SIDL ICFEDGE SIDL ICFEDGE
DS61143F-page
PIC32MX3XX/4XX
Bits 30/14
Bits 29/13
SIDL
Bits 28/12
Bits 27/11
Bits 26/10
Bits 25/9
ICFEDGE
Bits 24/8
ICC32
Bits 23/7
ICTMR
Bits 22/6
Bits 21/5
Bits 20/4
ICOV
Bits 19/3
ICBNE
Bits 18/2
Bits 17/1
ICM<2:0>
Bits 16/0
BF80_2000 IC1CON(1) BF80_2010 IC1BUF
ICI<1:0>
IC1BUF<31:0> ICC32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>
BF80_2200 IC2CON(1) BF80_2210 IC2BUF
IC2BUF<31:0> ICC32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>
BF80_2400 IC3CON(1) BF80_2410 IC3BUF
IC3BUF<31:0> ICC32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>
BF80_2600 IC4CON(1) BF80_2610 IC4BUF
IC4BUF<31:0> ICC32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>
2009 Microchip Technology Inc.
BF80_2800 IC5CON(1) BF80_2810 Legend: Note IC5BUF
IC5BUF<31:0> 15:0 unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. This register corresponding CLR, SET, Registers virtual address, plus offset 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-5:
Virtual Addr
BF80_3000 BF80_3010 BF80_3020 BF80_3200 BF80_3210 Legend: Note
OUTPUT COMPARE REGISTERS MAP(1)
Bits 31/15
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 SIDL
Name
OC1CON OC1R OC1RS OC2CON OC2R
Bits 30/14
Bits 29/13
SIDL
Bits 28/12
Bits 27/11
Bits 26/10
Bits 25/9
Bits 24/8
Bits 23/7
Bits 22/6
Bits 21/5
OC32
Bits 20/4
OCFLT
Bits 19/3
OCTSEL
Bits 18/2
Bits 17/1
OCM<2:0>
Bits 16/0
OC1R<31:0> OC1RS<31:0> OC32 OCFLT OCTSEL OCM<2:0>
OC2R<31:0> 15:0 unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-5:
Virtual Addr
BF80_3220 BF80_3400 BF80_3410 BF80_3420 BF80_3600 BF80_3610 BF80_3620 BF80_3800
OUTPUT COMPARE REGISTERS MAP(1) (CONTINUED)
Bits 31/15
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 SIDL SIDL SIDL
2009 Microchip Technology Inc.
Name
OC2RS OC3CON OC3R OC3RS OC4CON OC4R OC4RS OC5CON OC5R OC5RS
Bits 30/14
Bits 29/13
Bits 28/12
Bits 27/11
Bits 26/10
Bits 25/9
Bits 24/8
Bits 23/7
Bits 22/6
Bits 21/5
Bits 20/4
Bits 19/3
Bits 18/2
Bits 17/1
Bits 16/0
OC2RS<31:0> OC32 OCFLT OCTSEL OCM<2:0>
OC3R<31:0> OC3RS<31:0> OC32 OCFLT OCTSEL OCM<2:0>
OC4R<31:0> OC4RS<31:0> OC32 OCFLT OCTSEL OCM<2:0>
DS61143F-page
BF80_3810 BF80_3820 Legend: Note
OC5R<31:0>
OC5RS<31:0> 15:0 unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-6:
Virtual Addr
BF80_5000 BF80_5010 BF80_5020 BF80_5030 BF80_5040 Legend: Note
I2C1-2 REGISTERS MAP(1)
Bits 31/15
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 ACKSTAT
PIC32MX3XX/4XX
Name
I2C1CON I2C1STAT I2C1ADD I2C1MSK I2C1BRG
Bits 30/14
TRSTAT
Bits 29/13
SIDL
Bits 28/12
SCLREL
Bits 27/11
STRICT
Bits 26/10
A10M
Bits 25/9
DISSLW GCSTAT
Bits 24/8
SMEN ADD10
Bits 23/7
GCEN IWCOL
Bits 22/6
STREN I2COV
Bits 21/5
ACKDT
Bits 20/4
ACKEN
Bits 19/3
RCEN
Bits 18/2
Bits 17/1
RSEN
Bits 16/0
ADD<9:0> MSK<9:0>
I2C1BRG<11:0> 15:0 unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. registers this table except I2CxRCV have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-6:
Virtual Addr
BF80_5050 BF80_5260 BF80_5200 BF80_5210 BF80_5220 BF80_5230 BF80_5240
I2C1-2 REGISTERS MAP(1) (CONTINUED)
Bits 31/15
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 ACKSTAT
DS61143F-page
PIC32MX3XX/4XX
Name
I2C1TRN I2C1RCV I2C2CON I2C2STAT I2C2ADD I2C2MSK I2C2BRG I2C2TRN I2C2RCV
Bits 30/14
TRSTAT
Bits 29/13
SIDL
Bits 28/12
SCLREL
Bits 27/11
STRICT
Bits 26/10
A10M
Bits 25/9
DISSLW GCSTAT
Bits 24/8
SMEN ADD10
Bits 23/7
GCEN IWCOL
Bits 22/6
STREN I2COV
Bits 21/5
ACKDT
Bits 20/4
ACKEN
Bits 19/3
RCEN
Bits 18/2
Bits 17/1
RSEN
Bits 16/0
I2CT1DATA<7:0> I2CR1DATA<7:0>
ADD<9:0> MSK<9:0> I2C2BRG<11:0> I2CT1DATA<7:0>
BF80_5250 BF80_5260 Legend: Note
2009 Microchip Technology Inc.
15:0 I2CR1DATA<7:0> unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. registers this table except I2CxRCV have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-7:
Virtual Addr Name
UART1-2 REGISTERS
Bits 31/15
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
Bits 30/14
Bits 29/13
SIDL UTXINV
Bits 28/12
IREN URXEN
Bits 27/11
RTSMD UTXBRK
Bits 26/10
UTXEN
Bits 25/9
UTXBF
Bits 24/8
ADM_EN TRMT
Bits 23/7
WAKE
Bits 22/6
LPBACK
Bits 21/5
ABAUD ADDEN
Bits 20/4
RXINV RIDLE
Bits 19/3
BRGH PERR
Bits 18/2
Bits 17/1
Bits 16/0
STSEL URXDA
BF80_6000 U1MODE(1) BF80_6010 U1STA(1)
UEN<1:0>
PDSEL<1:0> FERR OERR
ADDR<7:0> URXISEL<1:0>
UTXISEL<1:0>
BF80_6020 U1TXREG BF80_6030 U1RXREG BF80_6040 U1BRG(1)
Transmit Register Receive Register
BRG<15:0>
BF80_6200 U2MODE(1) Legend: Note
15:0 SIDL IREN RTSMD UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. This register corresponding CLR, SET, Registers virtual address, plus offset 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-7:
Virtual Addr
BF80_6210
UART1-2 REGISTERS (CONTINUED)
Bits 31/15
31:16 15:0 31:16 15:0 31:16 15:0 31:16
2009 Microchip Technology Inc.
Name
U2STA(1)
Bits 30/14
Bits 29/13
UTXINV
Bits 28/12
URXEN
Bits 27/11
UTXBRK
Bits 26/10
UTXEN
Bits 25/9
UTXBF
Bits 24/8
ADM_EN TRMT
Bits 23/7
Bits 22/6
Bits 21/5
Bits 20/4
Bits 19/3
Bits 18/2
Bits 17/1
Bits 16/0
ADDR<7:0> URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA
UTXISEL<1:0>
BF80_6220 U2TXREG BF80_6230 U2RXREG BF80_6240 Legend: Note U2BRG(1)
Transmit Register Receive Register
15:0 BRG<15:0> unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. This register corresponding CLR, SET, Registers virtual address, plus offset 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-8:
Virtual Addr Name
SPI1CON
SPI1-2 REGISTERS MAP(1,2)
Bits 31/15
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 FRMEN SIDL DISSDO MODE32 SPIBUSY MODE16 SSEN SPIROV MSTEN FRMEN
Bits 30/14
Bits 29/13
Bits 28/12
DISSDO
Bits 27/11
MODE32 SPIBUSY
Bits 26/10
MODE16
Bits 25/9
Bits 24/8
Bits 23/7
SSEN
Bits 22/6
SPIROV
Bits 21/5
MSTEN
Bits 20/4
Bits 19/3
SPITBE
Bits 18/2
Bits 17/1
SPIFE
Bits 16/0
SPIRBF
BF80_5800
FRMSYNC FRMPOL SIDL
DS61143F-page
BF80_5810 SPI1STAT BF80_5820 BF80_5830 SPI1BUF SPI1BRG
DATA<31:0> BRG<8:0> SPITBE SPIFE
PIC32MX3XX/4XX
BF80_5A00 SPI2CON BF80_5A10 SPI2STAT BF80_5A20 SPI2BUF
FRMSYNC FRMPOL
SPIRBF
DATA<31:0>
BF80_5A30 SPI2BRG Legend: Note
15:0 BRG<8:0> unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. registers this table except SPIxBUF have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information. SPI2 Module present PIC32MX420FXXXX/440FXXXX devices.
TABLE 4-9:
Virtual Addr Name
REGISTERS
Bits 31/15
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 VCFG2 ADRC CH0NB PCFG15 CSSL15
DS61143F-page
PIC32MX3XX/4XX
Bits 30/14
VCFG1 PCFG14 CSSL14
Bits 29/13
SIDL VCFG0 PCFG13 CSSL13
Bits 28/12
OFFCAL PCFG12 CSSL12
Bits 27/11
Bits 26/10
CSCNA SAMC<4:0>
Bits 25/9
FORM<2:0>
Bits 24/8
Bits 23/7
BUFS CH0NA
Bits 22/6
SSRC<2:0> PCFG6 CSSL6
Bits 21/5
PCFG5 CSSL5
Bits 20/4
CLRASAM PCFG4 CSSL4
Bits 19/3
Bits 18/2
ASAM
Bits 17/1
SAMP BUFM
Bits 16/0
DONE ALTS
BF80_9000 AD1CON1(1) BF80_9010 AD1CON2(1) BF80_9020 AD1CON3(1) BF80_9040 AD1CHS(1) BF80_9060 AD1PCFG
SMPI<3:0> ADCS<7:0>
CH0SB<3:0> PCFG11 CSSL11 PCFG10 CSSL10 PCFG9 CSSL9 PCFG8 CSSL8
CH0SA<3:0> PCFG3 CSSL3 PCFG2 CSSL2 PCFG1 CSSL1 PCFG0 CSSL0
PCFG7 CSSL7
BF80_9050 AD1CSSL(1) BF80_9070 ADC1BUF0 BF80_9080 ADC1BUF1 BF80_9090 ADC1BUF2 BF80_90A0 ADC1BUF3 BF80_90B0 ADC1BUF4 BF80_90C0 ADC1BUF5 BF80_90D0 ADC1BUF6 BF80_90E0 ADC1BUF7
Result Word (ADC1BUF0<31:0>) Result Word (ADC1BUF1<31:0>) Result Word (ADC1BUF2<31:0>) Result Word (ADC1BUF3<31:0>) Result Word (ADC1BUF4<31:0>) Result Word (ADC1BUF5<31:0>) Result Word (ADC1BUF6<31:0>) Result Word (ADC1BUF7<31:0>) Result Word (ADC1BUF8<31:0>) Result Word (ADC1BUF9<31:0>) Result Word (ADC1BUFA<31:0>)
2009 Microchip Technology Inc.
BF80_90F0 ADC1BUF8 BF80_9100 ADC1BUF9 BF80_9110 ADC1BUFA BF80_9120 ADC1BUFB Legend: Note
Result Word (ADC1BUFB<31:0>) 15:0 unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. This register corresponding CLR, SET, Registers virtual address, plus offset 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-9:
Virtual Addr Name
REGISTERS (CONTINUED)
Bits 31/15
31:16 15:0 31:16 15:0 31:16 15:0 31:16
2009 Microchip Technology Inc.
Bits 30/14
Bits 29/13
Bits 28/12
Bits 27/11
Bits 26/10
Bits 25/9
Bits 24/8
Bits 23/7
Bits 22/6
Bits 21/5
Bits 20/4
Bits 19/3
Bits 18/2
Bits 17/1
Bits 16/0
BF80_9130 ADC1BUFC BF80_9140 ADC1BUFD BF80_9150 ADC1BUFE BF80_9160 ADC1BUFF Legend: Note
Result Word (ADC1BUFC<31:0>) Result Word (ADC1BUFD<31:0>) Result Word (ADC1BUFE<31:0>)
Result Word (ADC1BUFF<31:0>) 15:0 unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. This register corresponding CLR, SET, Registers virtual address, plus offset 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-10:
Virtual Addr Name
GLOBAL REGISTERS DEVICES ONLY
Bits 31/15
31:16 15:0 31:16 15:0 31:16
Bits 30/14
Bits 29/13
SIDL
Bits 28/12
SUSPEND
Bits 27/11
Bits 26/10
Bits 25/9
Bits 24/8
Bits 23/7
Bits 22/6
Bits 21/5
Bits 20/4
Bits 19/3
RDWR
Bits 18/2
Bits 17/1
Bits 16/0
DS61143F-page
BF88_3000 DMACON(1) BF88_3010 DMASTAT BF88_3020 DMAADDR Legend: Note
DMACH<1:0>
DMAADDR<31:0> 15:0 unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. This register corresponding CLR, SET, Registers virtual address, plus offset 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
PIC32MX3XX/4XX
TABLE 4-11:
Virtual Addr Name
REGISTERS DEVICES ONLY(1)
Bits 31/15
31:16 15:0 31:16 15:0 31:16
Bits 30/14
Bits 29/13
Bits 28/12
Bits 27/11
Bits 26/10
Bits 25/9
Bits 24/8
Bits 23/7
CRCEN
Bits 22/6
CRCAPP
Bits 21/5
Bits 20/4
Bits 19/3
Bits 18/2
Bits 17/1
Bits 16/0
BF88_3030 DCRCCON BF88_3040 DCRCDATA BF88_3050 DCRCXOR Legend: Note
PLEN<3:0>
CRCCH<1:0>
DCRCDATA<15:0>
15:0 DCRCXOR<15:0> unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-12:
Virtual Addr Name
CHANNELS REGISTERS DEVICES ONLY(1)
Bits 31/15
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
DS61143F-page
PIC32MX3XX/4XX
Bits 30/14
Bits 29/13
Bits 28/12
Bits 27/11
Bits 26/10
Bits 25/9
Bits 24/8
CHCHNS
Bits 23/7
CHEN CFORCE
Bits 22/6
CHAED CABORT CHSHIE CHSHIF
Bits 21/5
CHCHN PATEN CHDDIE CHDDIF
Bits 20/4
CHAEN SIRQEN CHDHIE CHDHIF
Bits 19/3
AIRQEN CHBCIE CHBCIF
Bits 18/2
CHEDET CHCCIE CHCCIF
Bits 17/1
Bits 16/0
BF88_3060 DCH0CON BF88_3070 DCH0ECON BF88_3080 DCH0INT
CHPRI<1:0> CHTAIE CHTAIF CHERIE CHERIF
CHAIRQ<7:0> CHSDIE CHSDIF
CHSIRQ<7:0>
BF88_3090 DCH0SSA BF88_30A0 DCH0DSA BF88_30B0 DCH0SSIZ BF88_30C0 DCH0DSIZ
CHSSA<31:0> CHDSA<31:0> CHCHNS CFORCE CHSDIE CHSDIF CABORT CHSHIE CHSHIF PATEN CHDDIE CHDDIF CHEN CHAED CHCHN CHAEN SIRQEN CHDHIE CHDHIF AIRQEN CHBCIE CHBCIF CHEDET CHCCIE CHCCIF
CHSSIZ<7:0> CHDSIZ<7:0> CHSTR<7:0> CHDPTR<7:0> CHCSIZ<7:0> CHCPTR<7:0> CHPDAT<7:0> CHPRI<1:0> CHTAIE CHTAIF CHERIE CHERIF
2009 Microchip Technology Inc.
BF88_30D0 DCH0SPTR BF88_30E0 DCH0DPTR BF88_30F0 DCH0CSIZ BF88_3100 DCH0CPTR BF88_3110 DCH0DAT BF88_3120 DCH1CON BF88_3130 DCH1ECON BF88_3140 DCH1INT
CHAIRQ<7:0>
CHSIRQ<7:0>
BF88_3150 DCH1SSA BF88_3160 DCH1DSA Legend: Note
CHSSA<31:0>
CHDSA<31:0> 15:0 unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. registers except DCHxSPTR, DCHxDPTR, DCHxCPTR have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-12:
Virtual Addr Name
CHANNELS REGISTERS (CONTINUED)FOR DEVICES ONLY(1) (CONTINUED)
Bits 31/15
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
2009 Microchip Technology Inc.
Bits 30/14
Bits 29/13
Bits 28/12
Bits 27/11
Bits 26/10
Bits 25/9
Bits 24/8
CHCHNS
Bits 23/7
CHEN CFORCE
Bits 22/6
CHAED CABORT CHSHIE CHSHIF
Bits 21/5
CHCHN PATEN CHDDIE CHDDIF
Bits 20/4
CHAEN SIRQEN CHDHIE CHDHIF
Bits 19/3
AIRQEN CHBCIE CHBCIF
Bits 18/2
CHEDET CHCCIE CHCCIF
Bits 17/1
Bits 16/0
BF88_3170 DCH1SSIZ BF88_3180 DCH1DSIZ BF88_3190 DCH1SPTR BF88_31A0 DCH1DPTR BF88_31B0 DCH1CSIZ BF88_31C0 DCH1CPTR BF88_31D0 DCH1DAT
CHSSIZ<7:0> CHDSIZ<7:0> CHSPTR<7:0> CHDPTR<7:0> CHCSIZ<7:0> CHCPTR<7:0> CHPDAT<7:0> CHPRI<1:0> CHTAIE CHTAIF CHERIE CHERIF
DS61143F-page
BF88_31E0 DCH2CON BF88_31F0 DCH2ECON BF88_3200 DCH2INT
CHAIRQ<7:0> CHSDIE CHSDIF
CHSIRQ<7:0>
BF88_3210 DCH2SSA BF88_3220 DCH2DSA BF88_3230 DCH2SSIZ BF88_3240 DCH2DSIZ BF88_3250 DCH2SPTR BF88_3260 DCH2DPTR BF88_3270 DCH2CSIZ Legend: Note
CHSSA<31:0>
PIC32MX3XX/4XX
CHDSA<31:0>
CHSSIZ<7:0> CHDSIZ<7:0> CHSPTR<7:0> CHDPTR<7:0>
15:0 CHCSIZ<7:0> unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. registers except DCHxSPTR, DCHxDPTR, DCHxCPTR have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-12:
Virtual Addr Name
CHANNELS REGISTERS (CONTINUED)FOR DEVICES ONLY(1) (CONTINUED)
Bits 31/15
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
DS61143F-page
PIC32MX3XX/4XX
Bits 30/14
Bits 29/13
Bits 28/12
Bits 27/11
Bits 26/10
Bits 25/9
Bits 24/8
CHCHNS
Bits 23/7
CHEN CFORCE
Bits 22/6
CHAED CABORT CHSHIE CHSHIF
Bits 21/5
CHCHN PATEN CHDDIE CHDDIF
Bits 20/4
CHAEN SIRQEN CHDHIE CHDHIF
Bits 19/3
AIRQEN CHBCIE CHBCIF
Bits 18/2
CHEDET CHCCIE CHCCIF
Bits 17/1
Bits 16/0
BF88_3280 DCH2CPTR BF88_3290 DCH2DAT BF88_32A0 DCH3CON BF88_32B0 DCH3ECON BF88_32C0 DCH3INT BF88_32D0 DCH3SSA BF88_32E0 DCH3DSA
CHCPTR<7:0> CHPDAT<7:0> CHPRI<1:0> CHTAIE CHTAIF CHERIE CHERIF
CHAIRQ<7:0> CHSDIE CHSDIF
CHSIRQ<7:0>
CHSSA<31:0> CHDSA<31:0>
2009 Microchip Technology Inc.
BF88_32F0 DCH3SSIZ BF88_3300 DCH3DSIZ BF88_3310 DCH3SPTR BF88_3320 DCH3DPTR BF88_3330 DCH3CSIZ BF88_3340 DCH3CPTR BF88_3350 DCH3DAT Legend: Note
CHSSIZ<7:0> CHDSIZ<7:0> CHSTR<7:0> CHDPTR<7:0> CHCSIZ<7:0> CHCPTR<7:0>
15:0 CHPDAT<7:0> unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. registers except DCHxSPTR, DCHxDPTR, DCHxCPTR have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-13:
Virtual Addr Name
COMPARATOR REGISTERS MAP(1)
Bits 31/15
31:16 15:0 31:16 15:0 31:16
2009 Microchip Technology Inc.
Bits 30/14
Bits 29/13
CPOL CPOL
Bits 28/12
Bits 27/11
Bits 26/10
Bits 25/9
Bits 24/8
COUT COUT
Bits 23/7
Bits 22/6
Bits 21/5
Bits 20/4
CREF CREF
Bits 19/3
Bits 18/2
Bits 17/1
Bits 16/0
BF80_A000 CM1CON BF80_A010 CM2CON BF80_A060 Legend: Note CMSTAT
EVPOL<1:0> EVPOL<1:0>
CCH<1:0> CCH<1:0>
15:0 SIDL C2OUT C1OUT unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-14:
Virtual Addr
BF80_9800 Legend: Note
COMPARATOR VOLTAGE REFERENCE REGISTERS MAP(1)
Bits 31/15
31:16
Name
CVRCON
Bits 30/14
Bits 29/13
Bits 28/12
Bits 27/11
Bits 26/10
Bits 25/9
Bits 24/8
Bits 23/7
Bits 22/6
Bits 21/5
Bits 20/4
Bits 19/3
Bits 18/2
Bits 17/1
Bits 16/0
15:0 CVROE CVRR CVRSS CVR<3:0> unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
DS61143F-page
TABLE 4-15:
Virtual Addr Name
FLASH CONTROLLER REGISTERS
Bits 31/15
31:16 NVMWR
Bits 30/14
WREN
Bits 29/13
NVMERR
Bits 28/12
LVDERR
Bits 27/11
LVDSTAT
Bits 26/10
Bits 25/9
Bits 24/8
Bits 23/7
Bits 22/6
Bits 21/5
Bits 20/4
Bits 19/3
Bits 18/2
Bits 17/1
Bits 16/0
BF80_F400 NVMCON(1)
PIC32MX3XX/4XX
15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
NVMOP<3:0>
BF80_F410
NVMKEY
NVMKEY<31:0> NVMADDR<31:0> NVMDATA<31:0>
BF80_F420 NVMADDR(1) BF80_F430 NVMDATA BF80_F440 Legend: Note NVMSRC ADDR
NVMSRCADDR<31:0> 15:0 unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. This register corresponding CLR, SET, Registers virtual address, plus offset 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-16:
Virtual Addr Name
SYSTEM CONTROL REGISTERS MAP(1)
Bits 31/15
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
DS61143F-page
PIC32MX3XX/4XX
Bits 30/14
Bits 29/13
Bits 28/12
PLLODIV<2:0>
Bits 27/11
Bits 26/10
Bits 25/9
RCDIV<2:0>
Bits 24/8
Bits 23/7
CLKLOCK
Bits 22/6
SOSCRDY ULOCK
Bits 21/5
LOCK
Bits 20/4
Bits 19/3
Bits 18/2
Bits 17/1
PLLMULT<2:0>
Bits 16/0
BF80_F000 OSCCON BF80_F010 OSCTUN
PBDIV<1:0> SLPEN SWDTPS<4:0> WDTO SLEEP IDLE
COSC<2:0>
NOSC<2:0> VREGS
UFRCEN
SOSCEN
OSWEN WDTCLR
EXTR
TUN<5:0>
BF80_0000 WDTCON BF80_F600 BF80_F610 Legend: Note RCON RSWRST
15:0 SWRST unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-17:
Virtual Addr Name
PORT REGISTERS MAP(11)
Bits 31/15
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 TRISA15 RA15 LATA15 ODCA15
Bits 30/14
TRISA14 RA14 LATA14 ODCA14
Bits 29/13
Bits 28/12
Bits 27/11
Bits 26/10
TRISA10 RA10 LATA10 ODCA10
Bits 25/9
TRISA9 LATA9 ODCA9
Bits 24/8
Bits 23/7
Bits 22/6
Bits 21/5
Bits 20/4
Bits 19/3
Bits 18/2
Bits 17/1
Bits 16/0
2009 Microchip Technology Inc.
BF88_6000 TRISA(1,2,3) BF88_6010 PORTA(1,2,3) BF88_6020 LATA(1,2,3) BF88_6030 ODCA(1,2,3) BF88_6040 TRISB(4,5) BF88_6050 PORTB(4,5) Legend: Note
TRISA<7:0> RA<7:0> LATA<7:0> ODCA<7:0>
TRISB<15:0>
15:0 RB<15:0> unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. TRISA, PORTA, LATA ODCA registers implemented 64-pin devices, read `0'. JTAG program/debug port multiplexed with port pins RA0, RA1, 100-pin devices. power-on-reset, these pins controlled JTAG port. these pins general purpose I/O, user's application code must clear JTAGEN (DDPCON<3>) these pins JTAG program/debug, user's application code must maintain JTAGEN specific 100-pin devices, instruction TRACE port multiplexed with PORTA pins RA6, RA7; PORTG pins RG12, RG13 RG14. Power-on Reset, these pins general purpose pins. maintain these pins general purpose pins, user's application code must maintain TROEN (DDPCON<2>) these pins instruction TRACE pins, TROEN must JTAG program/debug port multiplexed with port pins RB10, RB11, RB12 RB13 64-pin devices. power-on-reset, these pins controlled JTAG port. these pins general purpose I/O, user's application code must clear JTAGEN (DDPCON<3>) these pins JTAG program/debug, user's application code must maintain JTAGEN Port available general purpose when module enabled. implemented 64-pin devices. Read `0'. implemented 64-pin devices. Read `0'. implemented 100-pin devices. Read `0'. available general purpose when module enabled. available general purpose when module enabled. Input only when module disabled. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-17:
Virtual Addr
BF88_6060
PORT REGISTERS MAP(11) (CONTINUED)
Bits 31/15
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 TRISC15 RC15 LATC15 ODCC15 RD15(6) LAT15(6) TRISC14 RC14 LATC14 ODCC14 RD14(6) LAT14(6) TRISC13 RC13 LATC13 ODCC13 RD13(6) LAT13(6) TRISC12 RC12 LATC12 ODCC12 RD12(6) LAT12(6) RE9(6)
2009 Microchip Technology Inc.
Name
LATB(4,5)
Bits 30/14
Bits 29/13
Bits 28/12
Bits 27/11
Bits 26/10
Bits 25/9
Bits 24/8
RE8(6)
Bits 23/7
Bits 22/6
Bits 21/5
Bits 20/4
RC4(6) LATC4(6)
Bits 19/3
RC3(6) LATC3(6)
Bits 18/2
RC2(6) LATC2(6)
Bits 17/1
RC1(6) LATC1(6)
Bits 16/0
LATB<15:0> ODCB<15:0> TRISC4(6) TRISC3(6) TRISC2(6) TRISC1(6)
BF88_6070 ODCB(4,5) BF88_6080 BF88_6090 BF88_60A0 BF88_60B0 BF88_60C0 BF88_60D0 BF88_60E0 BF88_60F0 BF88_6100 BF88_6110 BF88_6120 Legend: Note TRISC PORTC LATC ODCC TRISD PORTD LATD ODCD TRISE PORTE LATE
ODCC4(6) ODCC3(6) ODCC2(6) ODCC1(6) TRISD<7:0> RD<7:0> RE<7:0> LATD<7:0> ODCD<7:0> TRISE<7:0>
15:0 TRISD15(6) TRISD14(6) TRISD13(6) TRISD12(6)
TRISD<11:8> RD<11:8> LATD<11:8> ODCD<11:8> TRISE9(6) TRISE8(6)
DS61143F-page
15:0 ODCD15(6) ODCD14(6) ODCD13(6) ODCD12(6)
PIC32MX3XX/4XX
15:0 LATE9(6) LATE8(6) LATE<7:0> unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. TRISA, PORTA, LATA ODCA registers implemented 64-pin devices, read `0'. JTAG program/debug port multiplexed with port pins RA0, RA1, 100-pin devices. power-on-reset, these pins controlled JTAG port. these pins general purpose I/O, user's application code must clear JTAGEN (DDPCON<3>) these pins JTAG program/debug, user's application code must maintain JTAGEN specific 100-pin devices, instruction TRACE port multiplexed with PORTA pins RA6, RA7; PORTG pins RG12, RG13 RG14. Power-on Reset, these pins general purpose pins. maintain these pins general purpose pins, user's application code must maintain TROEN (DDPCON<2>) these pins instruction TRACE pins, TROEN must JTAG program/debug port multiplexed with port pins RB10, RB11, RB12 RB13 64-pin devices. power-on-reset, these pins controlled JTAG port. these pins general purpose I/O, user's application code must clear JTAGEN (DDPCON<3>) these pins JTAG program/debug, user's application code must maintain JTAGEN Port available general purpose when module enabled. implemented 64-pin devices. Read `0'. implemented 64-pin devices. Read `0'. implemented 100-pin devices. Read `0'. available general purpose when module enabled. available general purpose when module enabled. Input only when module disabled. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-17:
Virtual Addr
BF88_6130 BF88_6140 BF88_6150 BF88_6160 BF88_6170 BF88_6180 BF88_6190 BF88_61A0 BF88_61B0 Legend: Note
PORT REGISTERS MAP(11) (CONTINUED)
Bits 31/15
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 31:16 15:0 31:16 31:16 RG15(6)
DS61143F-page
PIC32MX3XX/4XX
Name
ODCE TRISF PORTF LATF ODCF TRISG PORTG LATG ODCG
Bits 30/14
RG14(6)
Bits 29/13
RF13(6) RG13(6)
Bits 28/12
RF12(6) RG12(6)
Bits 27/11
Bits 26/10
Bits 25/9
TRISG9 LATG9
Bits 24/8
RF8(6) LATF8(6) TRISG8 LATG8
Bits 23/7
RF7(6,8) TRISG7 LATG7
Bits 22/6
RF6(7,8) TRISG6 LATG6
Bits 21/5
TRISF5 LATF5 ODCF5
Bits 20/4
TRISF4 LATF4 ODCF4
Bits 19/3
TRISF3 RF3(9) LATF3 ODCF3 TRISG3 RG3(10) LATG3
Bits 18/2
TRISF2(7) RF2(7) LATF2(7) ODCF2(7) TRISG2 RG2(10) LATG2
Bits 17/1
TRISF1 LATF1 ODCF1 RG1(6) LATG1(6)
Bits 16/0
TRISF0 LATF0 ODCF0 RG0(6) LATG0(6)
ODCE9(6) ODCE8(6) TRISF8(6) TRISF7(6,8) TRISF6(7,8)
ODCE<7:0>
TRISF13(6) TRISF12(6)
LATF13(6) LATF12(6) ODCF13(6) ODCF12(6)
LATF7(6,8) LATF6(7,8)
ODCF8(6) ODCF7(6,8) ODCF6(7,8)
15:0 TRISG15(6) TRISG14(6) TRISG13(6) TRISG12(6)
TRISG1(6) TRISG0(6)
2009 Microchip Technology Inc.
15:0 LATG15(6) LATG14(6) LATG13(6) LATG12(6)
15:0 ODCG15(6) ODCG14(6) ODCG13(6) ODCG12(6) ODCG9 ODCG8 ODCG7 ODCG6 ODCG3 ODCG2 ODCG1(6) ODCG0(6) unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. TRISA, PORTA, LATA ODCA registers implemented 64-pin devices, read `0'. JTAG program/debug port multiplexed with port pins RA0, RA1, 100-pin devices. power-on-reset, these pins controlled JTAG port. these pins general purpose I/O, user's application code must clear JTAGEN (DDPCON<3>) these pins JTAG program/debug, user's application code must maintain JTAGEN specific 100-pin devices, instruction TRACE port multiplexed with PORTA pins RA6, RA7; PORTG pins RG12, RG13 RG14. Power-on Reset, these pins general purpose pins. maintain these pins general purpose pins, user's application code must maintain TROEN (DDPCON<2>) these pins instruction TRACE pins, TROEN must JTAG program/debug port multiplexed with port pins RB10, RB11, RB12 RB13 64-pin devices. power-on-reset, these pins controlled JTAG port. these pins general purpose I/O, user's application code must clear JTAGEN (DDPCON<3>) these pins JTAG program/debug, user's application code must maintain JTAGEN Port available general purpose when module enabled. implemented 64-pin devices. Read `0'. implemented 64-pin devices. Read `0'. implemented 100-pin devices. Read `0'. available general purpose when module enabled. available general purpose when module enabled. Input only when module disabled. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-18:
Virtual Addr
BF88_61C0 Legend: Note
CHANGE NOTICE PULL-UP REGISTERS MAP(2)
Bits 31/15
31:16
Name
CNCON
Bits 30/14
Bits 29/13
Bits 28/12
Bits 27/11
Bits 26/10
Bits 25/9
Bits 24/8
Bits 23/7
Bits 22/6
Bits 21/5
Bits 20/4
Bits 19/3
Bits 18/2
Bits 17/1
Bits 16/0
15:0 SIDL unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. CNEN CNPUE bit(s) implemented 64-pin devices, read `0'. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-18:
Virtual Addr
BF88_61D0 BF88_61E0 Legend: Note
CHANGE NOTICE PULL-UP REGISTERS MAP(2) (CONTINUED)
Bits 31/15
31:16 15:0 31:16
2009 Microchip Technology Inc.
Name
CNEN CNPUE
Bits 30/14
Bits 29/13
Bits 28/12
Bits 27/11
Bits 26/10
Bits 25/9
Bits 24/8
Bits 23/7
Bits 22/6
Bits 21/5
Bits 20/4
Bits 19/3
Bits 18/2
Bits 17/1
CNEN17
Bits 16/0
CNEN16
CNEN21(1) CNEN20(1) CNEN19(1) CNEN18
CNEN<15:0> CNPUE21(1) CNPUE20(1) CNPUE19(1) CNPUE18 CNPUE17 CNPUE16
15:0 CNPUE<15:0> unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. CNEN CNPUE bit(s) implemented 64-pin devices, read `0'. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-19:
Virtual Addr
BF80_7000
PARALLEL MASTER PORT REGISTERS MAP(1)
Bits 31/15
31:16 15:0 31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 15:0 31:16 BUSY
Name
PMCON
Bits 30/14
Bits 29/13
SIDL
Bits 28/12
Bits 27/11
Bits 26/10
PMPTTL MODE16
Bits 25/9
PTWREN
Bits 24/8
PTRDEN
Bits 23/7
Bits 22/6
Bits 21/5
Bits 20/4
CS2P
Bits 19/3
CS1P
Bits 18/2
Bits 17/1
WRSP
Bits 16/0
RDSP
ADRMUX<1:0> INCM<1:0>
CSF<1:0> WAITB<1:0> ADDR<13:0>
BF80_7010 PMMODE
IRQM<1:0>
MODE<1:0>
WAITM<3:0>
WAITE<1:0>
DS61143F-page
BF80_7020 BF80_7030 BF80_7040 BF80_7050 BF80_7060 Legend: Note
PMADDR PMDOUT PMDIN PMAEN PMSTAT
15:0 CS2EN/A15 CS1EN/A14
DATAOUT<31:0> DATAIN<31:0>
PIC32MX3XX/4XX
PTEN<15:0>
15:0 IBOV IB3F IB2F IB1F IB0F OBUF OB3E OB2E OB1E OB0E unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-20:
Virtual Addr
BF80_F200 Legend:
PROGRAMMING DIAGNOSTICS REGISTERS
Bits 31/15
31:16
Name
DDPCON
Bits 30/14
Bits 29/13
Bits 28/12
Bits 27/11
Bits 26/10
Bits 25/9
Bits 24/8
Bits 23/7
DDPUSB
Bits 22/6
DDPU1
Bits 21/5
DDPU2
Bits 20/4
DDPSPI1
Bits 19/3
JTAGEN
Bits 18/2
TROEN
Bits 17/1
Bits 16/0
15:0 unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-21:
Virtual Addr Name
PREFETCH REGISTERS
Bits 31/15
31:16 15:0 15:0 31:16 15:0
DS61143F-page
PIC32MX3XX/4XX
Bits 30/14
Bits 29/13
Bits 28/12
Bits 27/11
Bits 26/10
Bits 25/9
Bits 24/8
Bits 23/7
Bits 22/6
Bits 21/5
Bits 20/4
Bits 19/3
Bits 18/2
Bits 17/1
Bits 16/0
BF88_4000 CHECON(1) BF88_4010 CHEACC(1)
DCSZ<1:0>
PREFEN<1:0>
CHECOH PFMWS<2:0>
31:16 CHEWEN LTAG BOOT
CHEIDX<3:0>
LTAG<23:16> LVALID LLOCK LTYPE
BF88_4020 CHETAG(1)
LTAG<15:4> LMASK<15:5>
BF88_4030 CHEMSK(1) BF88_4040 BF88_4050 BF88_4060 CHEW0 CHEW1 CHEW2 CHEW3 CHELRU CHEHIT CHEMIS
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0
CHEW0<31:0> CHEW1<31:0> CHEW2<31:0> CHEW3<31:0> CHELRU<15:0> CHEHIT<31:0> CHEMIS<31:0> CHELRU<24:16>
2009 Microchip Technology Inc.
BF88_4070 BF88_4080 BF88_4090 BF88_40A0
BF88_40C0 CHEPFABT Legend: Note
31:16 CHEPFABT<31:0> 15:0 unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. This register corresponding CLR, SET, Registers virtual address, plus offset 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-22:
Virtual Addr
BF80_0200
RTCC REGISTERS MAP(1)
Bits 31/15
31:16
Name
Bits 30/14
Bits 29/13
SIDL
Bits 28/12
Bits 27/11
Bits 26/10
Bits 25/9
Bits 24/8
Bits 23/7
Bits 22/6
Bits 21/5
Bits 20/4
Bits 19/3
Bits 18/2
Bits 17/1
Bits 16/0
CAL<11:0> RTSEC CLKON RTCWREN RTCSYNC HALFSEC RTCOE
RTCCON
15:0 31:16
BF80_0210 RTCALRM Legend: Note
ALRM CHIME AMASK<3:0> ARPT<7:0> 15:0 ALRMEN SYNC unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-22:
Virtual Addr
BF80_0220
RTCC REGISTERS MAP(1) (CONTINUED)
Bits 31/15
31:16 15:0 31:16 15:0 31:16 15:0 31:16
2009 Microchip Technology Inc.
Name
RTCTIME
Bits 30/14
Bits 29/13
Bits 28/12
Bits 27/11
Bits 26/10
Bits 25/9
Bits 24/8
Bits 23/7
Bits 22/6
Bits 21/5
Bits 20/4
Bits 19/3
Bits 18/2
Bits 17/1
Bits 16/0
HR10<3:0> SEC10<3:0> YEAR10<3:0> DAY10<3:0> MIN10<3:0> SEC10<3:0>
HR01<3:0> SEC01<3:0> YEAR01<3:0> DAY01<3:0> MIN01<3:0> SEC01<3:0>
MIN10<3:0> MONTH10<3:0> MIN10<3:0> MONTH10<3:0>
MIN01<3:0> MONTH01<3:0> WDAY01<3:0> MIN01<3:0> MONTH01<3:0>
BF80_0230 RTCDATE BF80_0240 ALRMTIME BF80_0250 ALRMDATE Legend: Note
15:0 DAY10<3:0> DAY01<3:0> WDAY01<3:0> unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. registers this table have corresponding CLR, SET, Registers their virtual addresses, plus offsets 0x4, 0x8, 0xC, respectively. Section 12.1.1 "CLR, Registers" more information.
TABLE 4-23:
Virtual Addr Name
DEVCFG: DEVICE CONFIGURATION WORD SUMMARY
Bits 31/15
31:16 31:16 31:16
Bits 30/14
Bits 29/13
Bits 28/12
Bits 27/11
Bits 26/10
IOFNC
Bits 25/9
Bits 24/8
Bits 23/7
FWDTEN IESO
Bits 22/6
Bits 21/5
FPLLMULT<2:0> FSOSCEN
Bits 20/4
Bits 19/3
Bits 18/2
Bits 17/1
FPLLODIV<2:0> FPLLIDIV<2:0>
Bits 16/0
DS61143F-page
BFC0_2FF0 DEVCFG3 BFC0_2FF4 DEVCFG2
15:0 USERID15 USERID14 USERID13 USERID12 USERID11 USERID10 USERID9 USERID8 USERID7 USERID6 USERID5 USERID4 USERID3 USERID2 USERID1 USERID0 15:0 FUPLLEN(1) FUPLLIDIV<2:0>(1)
WDTPS<4:0> PWP19 ICESEL PWP18 FNOSC<2:0> PWP17 PWP16
BFC0_2FF8 DEVCFG1
15:0 31:16
FCKSM<1:0>
FPBDIV<1:0>
POSCMD<1:0>
BFC0_2FFC DEVCFG0 Legend: Note
PIC32MX3XX/4XX
15:0 PWP15 PWP14 PWP13 PWP12 unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. These bits only available PIC32MX4XX devices.
DEBUG<1:0>
TABLE 4-24:
Virtual Addr
BF80_F220 Legend:
DEVICE REVISION SUMMARY
Bits 31/15
31:16
Name
DEVID
Bits 30/14
Bits 29/13
Bits 28/12
Bits 27/11
Bits 26/10
Bits 25/9
Bits 24/8
Bits 23/7
Bits 22/6
Bits 21/5
Bits 20/4
Bits 19/3
Bits 18/2
Bits 17/1
Bits 16/0
VER<3:0> DEVID<15:0>
DEVID<27:16>
15:0 unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-25:
Virtual Addr Name
REGISTERS
Bits 31/15
31:16 15:0 31:16 15:0 31:16 15:0 31:16
DS61143F-page
PIC32MX3XX/4XX
Bits 30/14
Bits 29/13
Bits 28/12
Bits 27/11
Bits 26/10
Bits 25/9
Bits 24/8
Bits 23/7
IDIF IDIE
Bits 22/6
Bits 21/5
LSTATE DPPUL
Bits 20/4
ACTVIF ACTVIE DMPUL USLPGRD IDLEIF IDLEIE BTOEF BTOEE USBRST BDTPTRL<7:1>
Bits 19/3
SESVD VBUSON TRNIF TRNIE DFN8EF DFN8EE HOSTEN DEVADDR<6:0>
Bits 18/2
SESEND OTGEN SOFIF SOFIE CRC16EF CRC16EE PPBI RESUME
Bits 17/1
Bits 16/0
VBUSVDIF VBUSVDIE VBUSVD
BF88_5040 U1OTGIR BF88_5050 BF88_5060 U1OTGIE U1OTG STAT
T1MSECIF LSTATEIF T1MSECIE LSTATEIE
SESVDIF SESENDIF SESVDIE SESENDIE
BF88_5070 U1OTGCON
15:0 31:16
DPPULUP DMPULUP UACTPND STALLIF STALLIE BTSEF BTSEE JSTATE LSPDEN
VBUSCHG VBUSDIS USUS PEND UERRIF UERRIE CRC5EF EOFEF CRC5EE EOFEE PPBRST FRMH<10:8> USBPWR URSTIF DETACHIF URSTIE DETACHIE PIDEF PIDEE USBEN SOFEN
BF88_5080
U1PWRC
15:0 31:16
BF88_5200
U1IR
15:0 31:16
RESUME ATTACHIF
2009 Microchip Technology Inc.
BF88_5210
U1IE
15:0 31:16
RESUME ATTACHIE BMXEF BMXEE DMAEF DMAEE PKTDIS TOKBUSY
BF88_5220
U1EIR
15:0 31:16
BF88_5230
U1EIE
15:0 31:16 15:0 31:16
BF88_5240
U1STAT
ENDPT<3:0>
BF88_5250
U1CON
15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
BF80_5260
U1ADDR
BF88_5270 U1BDTP1 BF88_5280 BF88_5290 Legend: U1FRML U1FRMH
FRML<7:0>
15:0 unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-25:
Virtual Addr
BF88_52A0 BF88_52B0
REGISTERS (CONTINUED)
Bits 31/15
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
2009 Microchip Technology Inc.
Name
U1TOK U1SOF
Bits 30/14
Bits 29/13
Bits 28/12
Bits 27/11
Bits 26/10
Bits 25/9
Bits 24/8
Bits 23/7
UTEYE LSPD
Bits 22/6
Bits 21/5
Bits 20/4
USBSIDL EPCON EPCON EPCON EPCON EPCON EPCON EPCON EPCON EPCON EPCON
Bits 19/3
EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN
Bits 18/2
Bits 17/1
Bits 16/0
EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK
PID<3:0> UOEMON RETRYDIS USBFRZ CNT<7:0>
EP<3:0> EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL
BF88_52C0 U1BDTP2 BF88_52D0 U1BDTP3 BF88_52E0 U1CNFG1
BDTPTRH<7:0> BDTPTRU<7:0>
BF88_5300
U1EP0
15:0 31:16
EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN
BF88_5310
U1EP1
15:0 31:16
DS61143F-page
BF88_5320
U1EP2
15:0 31:16
BF88_5330
U1EP3
15:0 31:16
BF88_5340
U1EP4
15:0 31:16
PIC32MX3XX/4XX
BF88_5350
U1EP5
15:0 31:16
BF88_5360
U1EP6
15:0 31:16
BF88_5370
U1EP7
15:0 31:16
BF88_5380
U1EP8
15:0 31:16
BF88_5390 Legend:
U1EP9
15:0
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-25:
Virtual Addr
BF88_53A0
REGISTERS (CONTINUED)
Bits 31/15
31:16
DS61143F-page
PIC32MX3XX/4XX
Name
Bits 30/14
Bits 29/13
Bits 28/12
Bits 27/11
Bits 26/10
Bits 25/9
Bits 24/8
Bits 23/7
Bits 22/6
Bits 21/5
Bits 20/4
EPCON EPCON EPCON EPCON EPCON EPCON
Bits 19/3
EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN
Bits 18/2
EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN
Bits 17/1
EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL
Bits 16/0
EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK
U1EP10
15:0 31:16
BF88_53B0
U1EP11
15:0 31:16
BF88_53C0
U1EP12
15:0 31:16
BF88_53D0
U1EP13
15:0 31:16
BF88_53E0
U1EP14
15:0 31:16
BF88_53F0 Legend:
U1EP15
2009 Microchip Technology Inc.
15:0
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
PIC32MX3XX/4XX
Note:
FLASH PROGRAM MEMORY
This data sheet summarizes features PIC32MX3XX/4XX family devices. intended comprehensive reference source. Refer "PIC32MX Family Reference Manual" Section "Flash Program Memory" (DS61121) detailed description this peripheral. manual available from Microchip site (www.Microchip.com/PIC32).
PIC32MX3XX/4XX devices contain internal program Flash memory executing user code. There three methods which user program this memory: Run-Time Self Programming (RTSP) In-Circuit Serial Programming(ICSPTM) EJTAG Programming
RTSP performed software executing from either Flash memory. EJTAG performed using EJTAG port device EJTAG capable programmer. ICSP performed using serial data connection device allows much faster programming times than RTSP. RTSP techniques described this chapter. ICSP EJTAG methods described "PIC32MX3XX/4XX Programming Specification" (DS61145) document, which downloaded from Microchip site.
2009 Microchip Technology Inc.
DS61143F-page
PIC32MX3XX/4XX
NOTES:
DS61143F-page
2009 Microchip Technology Inc.
PIC32MX3XX/4XX
Note:
RESETS
This data sheet summarizes features PIC32MX3XX/4XX family devices. intended comprehensive reference source. Refer "PIC32MX Family Reference Manual" Section "Resets" (DS61118) detailed description this peripheral. manual available from Microchip site (www.Microchip.com/PIC32).
Reset module combines Reset sources controls device Master Reset signal, SYSRST. following list device Reset sources: POR: Power-on Reset MCLR: Master Clear Reset SWR: Software Reset WDTR: Watchdog Timer Reset BOR: Brown-out Reset CMR: Configuration Mismatch Reset
simplified block diagram Reset module shown Figure 6-1.
FIGURE 6-1:
SYSTEM RESET BLOCK DIAGRAM
MCLR Glitch Filter Sleep Idle Voltage Regulator Enabled Time-out Power-up Timer Rise Detect Brown-out Reset SYSRST MCLR
WDTR
Configuration Mismatch Reset Software Reset
2009 Microchip Technology Inc.
DS61143F-page
PIC32MX3XX/4XX
NOTES:
DS61143F-page
2009 Microchip Technology Inc.
PIC32MX3XX/4XX
Note:
INTERRUPT CONTROLLER
This data sheet summarizes features PIC32MX3XX/4XX family devices. intended comprehensive reference source. Refer "PIC32MX Family Reference Manual" Section "Interrupt Controller" (DS61108) detailed description this peripheral. manual available from Microchip site (www.Microchip.com/PIC32).
PIC32MX3XX/4XX interrupts module includes following features: interrupt sources interrupt vectors Single Multi-Vector mode operations external interrupts with edge polarity control Interrupt proximity timer Module Freeze Debug mode user-selectable priority levels each vector user-selectable subpriority levels within each priority Dedicated shadow highest priority level Software generate interrupt User-configurable interrupt vector table location User-configurable interrupt vector spacing
PIC32MX3XX/4XX devices generate interrupt requests response interrupt events from peripheral modules. Interrupt Control module exists externally logic prioritizes interrupt events before presenting them CPU.
FIGURE 7-1:
INTERRUPT CONTROLLER MODULE
Interrupt Requests
Vector Number
Interrupt Controller
Priority Level
Core
Shadow Number
Note:
Several registers cited this section interrupt controller module. These registers (and bits) associated with CPU. Details about them available Section "PIC32MX MCU". avoid confusion, typographic distinction made registers CPU. register names this section, other sections this manual, signified uppercase letters only.CPU register names signified upper lowercase letters. example, INTSTAT Interrupts register; whereas, IntCtl register.
2009 Microchip Technology Inc.
DS61143F-page
PIC32MX3XX/4XX
TABLE 7-1: INTERRUPT VECTOR LOCATION
Vector Number Flag IFS0<0> IFS0<1> IFS0<2> IFS0<3> IFS0<4> IFS0<5> IFS0<6> IFS0<7> IFS0<8> IFS0<9> IFS0<10> IFS0<11> IFS0<12> IFS0<13> IFS0<14> IFS0<15> IFS0<16> IFS0<17> IFS0<18> IFS0<19> IFS0<20> IFS0<21> IFS0<22> IFS0<23> IFS0<24> IFS0<25> IFS0<26> IFS0<27> IFS0<28> IFS0<29> IFS0<30> IFS0<31> IFS1<0> IFS1<1> IFS1<2> IFS1<3> IFS1<4> Interrupt Location Enable IEC0<0> IEC0<1> IEC0<2> IEC0<3> IEC0<4> IEC0<5> IEC0<6> IEC0<7> IEC0<8> IEC0<9> IEC0<10> IEC0<11> IEC0<12> IEC0<13> IEC0<14> IEC0<15> IEC0<16> IEC0<17> IEC0<18> IEC0<19> IEC0<20> IEC0<21> IEC0<22> IEC0<23> IEC0<24> IEC0<25> IEC0<26> IEC0<27> IEC0<28> IEC0<29> IEC0<30> IEC0<31> IEC1<0> IEC1<1> IEC1<2> IEC1<3> IEC1<4> Priority IPC0<4:2> IPC0<12:10> IPC0<20:18> IPC0<28:26> IPC1<4:2> IPC1<12:10> IPC1<20:18> IPC1<28:26> IPC2<4:2> IPC2<12:10> IPC2<20:18> IPC2<28:26> IPC3<4:2> IPC3<12:10> IPC3<20:18> IPC3<28:26> IPC4<4:2> IPC4<12:10> IPC4<20:18> IPC4<28:26> IPC5<4:2> IPC5<12:10> IPC5<20:18> IPC5<28:26> IPC5<28:26> IPC5<28:26> IPC6<4:2> IPC6<4:2> IPC6<4:2> IPC6<12:10> IPC6<12:10> IPC6<12:10> IPC6<20:18> IPC6<28:26> IPC7<4:2> IPC7<12:10> IPC7<20:18> Subpriority IPC0<1:0> IPC0<9:8> IPC0<17:16> IPC0<25:24> IPC1<1:0> IPC1<9:8> IPC1<17:16> IPC1<25:24> IPC2<1:0> IPC2<9:8> IPC2<17:16> IPC2<25:24> IPC3<1:0> IPC3<9:8> IPC3<17:16> IPC3<25:24> IPC4<1:0> IPC4<9:8> IPC4<17:16> IPC4<25:24> IPC5<1:0> IPC5<9:8> IPC5<17:16> IPC5<25:24> IPC5<25:24> IPC5<25:24> IPC6<1:0> IPC6<1:0> IPC6<1:0> IPC6<9:8> IPC6<9:8> IPC6<9:8> IPC6<17:16> IPC6<25:24> IPC7<1:0> IPC7<9:8> IPC7<17:16> Interrupt Source(1)
Highest Natural Order Priority Core Timer Interrupt Core Software Interrupt Core Software Interrupt INT0 External Interrupt Timer1 Input Capture Output Compare INT1 External Interrupt Timer2 Input Capture Output Compare INT2 External Interrupt Timer3 Input Capture Output Compare INT3 External Interrupt Timer4 Input Capture Output Compare INT4 External Interrupt Timer5 Input Capture Output Compare SPI1E SPI1 Fault SPI1TX SPI1 Transfer Done SPI1RX SPI1 Receive Done UART1 Error U1RX UART1 Receiver U1TX UART1 Transmitter I2C1B I2C1 Collision Event I2C1S I2C1 Slave Event I2C1M I2C1 Master Event Input Change Interrupt ADC1 Convert Done Parallel Master Port CMP1 Comparator Interrupt CMP2 Comparator Interrupt Note
interrupt sources available devices. Table "PIC32MX General Purpose Features" Table "PIC32MX Features" available peripherals.
DS61143F-page
2009 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 7-1: INTERRUPT VECTOR LOCATION (CONTINUED)
Vector Number Flag IFS1<5> IFS1<6> IFS1<7> IFS1<8> IFS1<9> IFS1<10> IFS1<11> IFS1<12> IFS1<13> IFS1<14> IFS1<15> IFS1<16> IFS1<17> IFS1<18> IFS1<19> IFS1<24> IFS1<25> Interrupt Location Enable IEC1<5> IEC1<6> IEC1<7> IEC1<8> IEC1<9> IEC1<10> IEC1<11> IEC1<12> IEC1<13> IEC1<14> IEC1<15> IEC1<16> IEC1<17> IEC1<18> IEC1<19> IEC1<24> IEC1<25> Priority IPC7<28:26> IPC7<28:26> IPC7<28:26> IPC8<4:2> IPC8<4:2> IPC8<4:2> IPC8<12:10> IPC8<12:10> IPC8<12:10> IPC8<20:18> IPC8<28:26> IPC9<4:2> IPC9<12:10> IPC9<20:18> IPC9<28:26> IPC11<4:2> IPC11<12:10> Subpriority IPC7<25:24> IPC7<25:24> IPC7<25:24> IPC8<1:0> IPC8<1:0> IPC8<1:0> IPC8<9:8> IPC8<9:8> IPC8<9:8> IPC8<17:16> IPC8<25:24> IPC9<1:0> IPC9<9:8> IPC9<17:16> IPC9<25:24> IPC11<1:0> IPC11<9:8> Interrupt Source(1)
Highest Natural Order Priority SPI2E SPI2 Fault SPI2TX SPI2 Transfer Done SPI2RX SPI2 Receive Done UART2 Error U2RX UART2 Receiver U2TX UART2 Transmitter I2C2B I2C2 Collision Event I2C2S I2C2 Slave Event I2C2M I2C2 Master Event FSCM Fail-Safe Clock Monitor RTCC Real-Time Clock DMA0 Cha
Other recent searches
NC7SV04 - NC7SV04 NC7SV04 Datasheet
MSC1412-01 - MSC1412-01 MSC1412-01 Datasheet
MSC1412-02 - MSC1412-02 MSC1412-02 Datasheet
I27191 - I27191 I27191 Datasheet
HER201 - HER201 HER201 Datasheet
HER208 - HER208 HER208 Datasheet
HEF4521B - HEF4521B HEF4521B Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
