28/40/44-Pin, Enhanced Flash-Based 8-Bit CMOS Microcontrollers with na
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PIC16F882/883/884/886/887 Data Sheet
28/40/44-Pin, Enhanced Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology
2009 Microchip Technology Inc.
DS41291F
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Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt UNI/O registered trademarks Microchip Technology Incorporated U.S.A. other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2009, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
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2009 Microchip Technology Inc.
PIC16F882/883/884/886/887
28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology
High-Performance RISC CPU:
Only Instructions Learn: single-cycle instructions except branches Operating Speed: oscillator/clock input instruction cycle Interrupt Capability 8-Level Deep Hardware Stack Direct, Indirect Relative Addressing modes
Peripheral Features:
24/35 Pins with Individual Direction Control: High current source/sink direct drive Interrupt-on-Change Individually programmable weak pull-ups Ultra Low-Power Wake-up (ULPWU) Analog Comparator Module with: analog comparators Programmable on-chip voltage reference (CVREF) module VDD) Fixed voltage reference (0.6V) Comparator inputs outputs externally accessible Latch mode External Timer1 Gate (count enable) Converter: 10-bit resolution 11/14 channels Timer0: 8-bit Timer/Counter with 8-bit Programmable Prescaler Enhanced Timer1: 16-bit timer/counter with prescaler External Gate Input mode Dedicated low-power oscillator Timer2: 8-bit Timer/Counter with 8-bit Period Register, Prescaler Postscaler Enhanced Capture, Compare, PWM+ Module: 16-bit Capture, max. resolution 12.5 Compare, max. resolution 10-bit with output channels, programmable "dead time", max. frequency output steering control Capture, Compare, Module: 16-bit Capture, max. resolution 12.5 16-bit Compare, max. resolution 10-bit PWM, max. frequency Enhanced USART Module: Supports RS-485, RS-232, Auto-Baud Detect Auto-Wake-Up Start In-Circuit Serial Programming(ICSPTM) Pins Master Synchronous Serial Port (MSSP) Module supporting 3-wire (all modes) I2CMaster Slave Modes with Address Mask
Special Microcontroller Features:
Precision Internal Oscillator: Factory calibrated Software selectable frequency range Software tunable Two-Speed Start-up mode Crystal fail detect critical applications Clock mode switching during operation power savings Power-Saving Sleep mode Wide Operating Voltage Range (2.0V-5.5V) Industrial Extended Temperature Range Power-on Reset (POR) Power-up Timer (PWRT) Oscillator Start-up Timer (OST) Brown-out Reset (BOR) with Software Control Option Enhanced Low-Current Watchdog Timer (WDT) with On-Chip Oscillator (software selectable nominal seconds with full prescaler) with software enable Multiplexed Master Clear with Pull-up/Input Programmable Code Protection High Endurance Flash/EEPROM Cell: 100,000 write Flash endurance 1,000,000 write EEPROM endurance Flash/Data EEPROM retention: years Program Memory Read/Write during time In-Circuit Debugger board)
Low-Power Features:
Standby Current: 2.0V, typical Operating Current: kHz, 2.0V, typical MHz, 2.0V, typical Watchdog Timer Current: 2.0V, typical
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Program Memory Flash (words) 2048 4096 4096 8192 8192 Data Memory SRAM (bytes) EEPROM (bytes) 10-bit (ch) ECCP/ Timers 8/16-bit
Device
EUSART
MSSP
Comparators
PIC16F882 PIC16F883 PIC16F884 PIC16F886 PIC16F887
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Diagrams PIC16F882/883/886, 28-Pin PDIP, SOIC, SSOP
28-pin PDIP, SOIC, SSOP
RE3/MCLR/VPP RA3/AN3/VREF+/C1IN+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT RA7/OSC1/CLKIN RA6/OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/P1A/CCP1 RC3/SCK/SCL RB7/ICSPDAT RB6/ICSPCLK RB5/AN13/T1G RB4/AN11/P1D RB3/AN9/PGM/C12IN2RB2/AN8/P1B RB1/AN10/P1C/C12IN3RB0/AN12/INT RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA
TABLE
Note
PIC16F882/883/886 28-PIN SUMMARY (PDIP, SOIC, SSOP)
Analog AN0/ULPWU AN12 AN10 AN11 AN13 Comparators C12IN0C12IN1C2IN+ C1IN+ C1OUT C2OUT C12IN3- C12IN2- Timers T0CKI T1OSO/T1CKI T1OSI ECCP CCP2 CCP1/P1A EUSART TX/CK RX/DT MSSP SCK/SCL SDI/SDA Interrupt Pull-up IOC/INT Y(1) Basic VREF-/CVREF VREF+ OSC2/CLKOUT OSC1/CLKIN ICSPCLK ICSPDAT MCLR/VPP
Pull-up activated only with external MCLR configuration.
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Diagrams PIC16F882/883/886, 28-Pin
28-pin RB7/ICSPDAT RB6/ICSPCLK RB5/AN13/T1G RB4/AN11/P1D PIC16F882/883/886
RA2/AN2/VREF-/CVREF/C2IN+ RA3/AN3/VREF+/C1IN+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT RA7/OSC1/CLKIN RA6/OSC2/CLKOUT
RB3/AN9/PGM/C12IN2RB2/AN8/P1B RB1/AN10/P1C/C12IN3RB0/AN12/INT RC7/RX/DT
RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/P1A/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK
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TABLE
Note
PIC16F882/883/886 28-PIN SUMMARY (QFN)
Analog AN0/ULPWU AN12 AN10 AN11 AN13 Comparators C12IN0C12IN1C2IN+ C1IN+ C1OUT C2OUT C12IN3- C12IN2- Timers T0CKI T1OSO/T1CKI T1OSI ECCP CCP2 CCP1/P1A EUSART TX/CK RX/DT MSSP SCK/SCL SDI/SDA Interrupt Pull-up IOC/INT Y(1) Basic VREF-/CVREF VREF+ OSC2/CLKOUT OSC1/CLKIN ICSPCLK ICSPDAT MCLR/VPP
Pull-up activated only with external MCLR configuration.
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Diagrams PIC16F884/887, 40-Pin PDIP
40-pin PDIP
RE3/MCLR/VPP RA3/AN3/VREF+/C1IN+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT RE0/AN5 RE1/AN6 RE2/AN7 RA7/OSC1/CLKIN RA6/OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/P1A/CCP1 RC3/SCK/SCL
RB7/ICSPDAT RB6/ICSPCLK RB5/AN13/T1G RB4/AN11 RB3/AN9/PGM/C12IN2RB2/AN8 RB1/AN10/C12IN3RB0/AN12/INT RD7/P1D RD6/P1C RD5/P1B RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA
PIC16F884/887
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TABLE
PIC16F884/887 40-PIN SUMMARY (PDIP)
Analog AN0/ULPWU AN12 AN10 AN11 AN13 Comparators C12IN0C12IN1C2IN+ C1IN+ C1OUT C2OUT C12IN3- C12IN2- Timers T0CKI T1OSO/T1CKI T1OSI ECCP CCP2 CCP1/P1A EUSART TX/CK RX/DT MSSP SCK/SCL SDI/SDA Interrupt Pull-up IOC/INT Y(1) Basic VREF-/CVREF VREF+ OSC2/CLKOUT OSC1/CLKIN ICSPCLK ICSPDAT MCLR/VPP
Note
Pull-up activated only with external MCLR configuration.
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Diagrams PIC16F884/887, 44-Pin
44-pin
RC6/TX/CK RC5/SDO RC4/SDI/SDA RC3/SCK/SCL RC2/P1A/CCP1 RC1/T1OSCI/CCP2 RC0/T1OSO/T1CKI
RB3/AN9/PGM/C12IN2NC RB4/AN11 RB5/AN13/T1G RB6/ICSPCLK RB7/ICSPDAT RE3/MCLR/VPP RA3/AN3//VREF+/C1IN+
RC7/RX/DT RD5/P1B RD6/P1C RD7/P1D RB0/AN12/INT RB1/AN10/C12IN3RB2/AN8
PIC16F884/887
RA6/OSC2/CLKOUT RA7/OSC1/CLKIN RE2/AN7 RE1/AN6 RE0/AN5 RA5/AN4/SS/C2OUT RA4/T0CKI/C1OUT
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TABLE
PIC16F884/887 44-PIN SUMMARY (QFN)
Analog AN0/ULPWU AN12 AN10 AN11 AN13 Comparators C12IN0C12IN1C2IN+ C1IN+ C1OUT C2OUT C12IN3- C12IN2- Timers T0CKI T1OSO/T1CKI T1OSI ECCP CCP2 CCP1/P1A EUSART TX/CK RX/DT MSSP SCK/SCL SDI/SDA Interrupt Pull-up IOC/INT Y(1) Basic VREF-/CVREF VREF+ OSC2/CLKOUT OSC1/CLKIN ICSPCLK ICSPDAT MCLR/VPP connect) connect)
Note
Pull-up activated only with external MCLR configuration.
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Diagrams PIC16F884/887, 44-Pin TQFP
44-pin TQFP
RC6/TX/CK RC5/SDO RC4/SDI/SDA RC3/SCK/SCL RC2/P1A/CCP1 RC1/T1OSCI/CCP2
RB4/AN11 RB5/AN13/T1G RB6/ICSPCLK RB7/ICSPDAT RE3/MCLR/VPP RA3/AN3//VREF+/C1IN+
RC7/RX/DT RD5/P1B RD6/P1C RD7/P1D RB0/AN12/INT RB1/AN10/C12IN3RB2/AN8 RB3/AN9/PGM/C12IN2-
PIC16F884/887
RC0/T1OSO/T1CKI RA6/OSC2/CLKOUT RA7/OSC1/CLKIN RE2/AN7 RE1/AN6 RE0/AN5 RA5/AN4/SS/C2OUT RA4/T0CKI/C1OUT
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TABLE
PIC16F884/887 44-PIN SUMMARY (TQFP)
Analog AN0/ULPWU AN12 AN10 AN11 AN13 Comparators C12IN0C12IN1C2IN+ C1IN+ C1OUT C2OUT C12IN3- C12IN2- Timers T0CKI T1OSO/T1CKI T1OSI ECCP CCP2 CCP1/P1A EUSART TX/CK RX/DT MSSP SCK/SCL SDI/SDA Interrupt Pull-up IOC/INT Y(1) Basic VREF-/CVREF VREF+ OSC2/CLKOUT OSC1/CLKIN ICSPCLK ICSPDAT MCLR/VPP connect) connect) connect) connect)
Note
Pull-up activated only with external MCLR configuration.
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Table Contents
Device Overview Memory Organization Ports Oscillator Module (With Fail-Safe Clock Monitor). Timer0 Module Timer1 Module with Gate Control. Timer2 Module Comparator Module. Analog-to-Digital Converter (ADC) Module 10.0 Data EEPROM Flash Program Memory Control 11.0 Enhanced Capture/Compare/PWM Module 12.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) 13.0 Master Synchronous Serial Port (MSSP) Module 14.0 Special Features 15.0 Instruction Summary 16.0 Development Support. 17.0 Electrical Specifications. 18.0 Characteristics Graphs Tables 19.0 Packaging Information. Appendix Data Sheet Revision History. Appendix Migrating from other PIC® Devices Index Microchip Site Customer Change Notification Service Customer Support Reader Response Product Identification System.
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Most Current Data Sheet
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Errata
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DEVICE OVERVIEW
PIC16F882/883/884/886/887 covered this data sheet. PIC16F882/883/886 available 28pin PDIP, SOIC, SSOP packages. PIC16F884/887 available 40-pin PDIP 44pin TQFP packages. Figure shows block diagram PIC16F882/883/886 Figure shows block diagram PIC16F884/887 device. Table Table show corresponding pinout descriptions.
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FIGURE 1-1: PIC16F882/883/886 BLOCK DIAGRAM
Configuration Program Counter Flash 2K(2)/4K(1)/ Program Memory Data PORTA PORTB PORTC PORTE CCP2
8-Level Stack (13-Bit)
128(2)/256(1)/ Bytes File Registers Addr Addr
Program
Instruction Direct Addr
Indirect Addr
STATUS Power-up Timer Instruction Decode Control OSC1/CLKIN Timing Generation OSC2/CLKOUT Internal Oscillator Block MCLR In-Circuit Debugger (ICD) T1OSI T1OSO T0CKI CCP1/P1A Timer1 Oscillator TX/CK RX/DT T1CKI Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset
CCP2
SCK/SCL
SDI/SDA
Master Synchronous Timer0 Timer1 Timer2 EUSART ECCP Serial Port (MSSP)
VREF+ VREF-
Analog-To-Digital Converter (ADC)
Analog Comparators Reference
VREF+ VREFCVREF
EEDATA 128(2)/ Bytes Data EEPROM EEADDR
AN10 AN11 AN12 AN13
Note
PIC16F883 only. PIC16F882 only.
C1IN+ C12IN0C12IN1C12IN2C12IN3C1OUT C2IN+ C2OUT
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FIGURE 1-2: PIC16F884/PIC16F887 BLOCK DIAGRAM
Configuration Program Counter Flash 4K(1)/8K Program Memory 8-Level Stack (13-Bit) Data PORTA PORTB Addr Addr Direct Addr Indirect Addr PORTC PORTD CCP2 PORTE In-Circuit Debugger (ICD) T1OSI T1OSO T0CKI Timer1 Oscillator RX/DT TX/CK T1CKI
256(1)/368 Bytes File Registers
Program
Instruction
STATUS Power-up Timer Instruction Decode Control OSC1/CLKIN Timing Generation OSC2/CLKOUT Internal Oscillator Block MCLR Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset
CCP2
CCP1/P1A
SCK/SCL
SDI/SDA
Master Synchronous Timer0 Timer1 Timer2 EUSART ECCP Serial Port (MSSP)
VREF+ VREF-
Analog-To-Digital Converter (ADC)
Analog Comparators Reference
VREF+ VREFCVREF
EEDATA Bytes Data EEPROM EEADDR
AN10 AN11 AN12 AN13
Note
PIC16F884 only.
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C1IN+ C12IN0C12IN1C12IN2C12IN3C1OUT C2IN+ C2OUT
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TABLE 1-1: PIC16F882/883/886 PINOUT DESCRIPTION
Function ULPWU C12IN0RA1/AN1/C12IN1RA1 C12IN1RA2/AN2/VREF-/CVREF/C2IN+ VREFCVREF C2IN+ RA3/AN3/VREF+/C1IN+ VREF+ C1IN+ RA4/T0CKI/C1OUT T0CKI C1OUT RA5/AN4/SS/C2OUT C2OUT RA6/OSC2/CLKOUT OSC2 CLKOUT RA7/OSC1/CLKIN OSC1 CLKIN RB0/AN12/INT AN12 RB1/AN10/P1C/C12IN3RB1 AN10 C12IN3RB2/AN8/P1B Legend: Analog input output compatible input High Voltage Input Type XTAL Output Type CMOS General purpose I/O. Channel input. Ultra Low-Power Wake-up input. Comparator negative input. Channel input. Comparator negative input. Channel Negative Voltage Reference input. Comparator Voltage Reference output. Comparator positive input. General purpose I/O. Channel Programming voltage. Comparator positive input. Timer0 clock input. Description
Name RA0/AN0/ULPWU/C12IN0-
CMOS General purpose I/O.
CMOS General purpose I/O.
CMOS General purpose I/O. CMOS Comparator output. CMOS General purpose I/O. Channel Slave Select input.
CMOS Comparator output. CMOS General purpose I/O. XTAL Master Clear with internal pull-up. CMOS FOSC/4 output. CMOS General purpose I/O. Crystal/Resonator. External clock input/RC oscillator connection.
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Channel External interrupt.
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Channel Comparator negative input. CMOS output. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Channel CMOS output.
CMOS CMOS compatible input output Open Drain Schmitt Trigger input with CMOS levels XTAL Crystal
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TABLE 1-1: PIC16F882/883/886 PINOUT DESCRIPTION (CONTINUED)
Function C12IN2RB4/AN11/P1D AN11 RB5/AN13/T1G AN13 RB6/ICSPCLK ICSPCLK RB7/ICSPDAT ICSPDAT RC0/T1OSO/T1CKI T1OSO T1CKI RC1/T1OSI/CCP2 T1OSI CCP2 RC2/P1A/CCP1 CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT RE3/MCLR/VPP MCLR Legend: Analog input output compatible input High Voltage Input Type Power Power Output Type Description Name RB3/AN9/PGM/C12IN2-
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Channel Low-voltage ICSPProgramming enable pin. Comparator negative input.
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Channel CMOS output. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Channel Timer1 Gate input.
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Serial Programming Clock. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. CMOS ICSPData I/O. CMOS General purpose I/O. CMOS Timer1 oscillator output. Timer1 clock input. Timer1 oscillator input. CMOS General purpose I/O. CMOS Capture/Compare/PWM2. CMOS General purpose I/O. CMOS output. CMOS Capture/Compare/PWM1. CMOS General purpose I/O. CMOS clock. I2Cclock. data input. data input/output. CMOS General purpose I/O.
CMOS General purpose I/O. CMOS data output. CMOS General purpose I/O. CMOS EUSART asynchronous transmit. CMOS EUSART synchronous clock. CMOS General purpose I/O. EUSART asynchronous input. General purpose input. Master Clear with internal pull-up. Programming voltage. Ground reference. Positive supply. CMOS EUSART synchronous data.
CMOS CMOS compatible input output Open Drain Schmitt Trigger input with CMOS levels XTAL Crystal
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TABLE 1-2: PIC16F884/887 PINOUT DESCRIPTION
Function ULPWU C12IN0RA1/AN1/C12IN1RA1 C12IN1RA2/AN2/VREF-/CVREF/C2IN+ VREFCVREF C2IN+ RA3/AN3/VREF+/C1IN+ VREF+ C1IN+ RA4/T0CKI/C1OUT T0CKI C1OUT RA5/AN4/SS/C2OUT C2OUT RA6/OSC2/CLKOUT OSC2 CLKOUT RA7/OSC1/CLKIN OSC1 CLKIN RB0/AN12/INT AN12 RB1/AN10/C12IN3RB1 AN10 C12IN3RB2/AN8 RB3/AN9/PGM/C12IN2RB3 C12IN2Legend: Analog input output compatible input High Voltage Input Type XTAL Output Type CMOS General purpose I/O. Channel input. Ultra Low-Power Wake-up input. Comparator negative input. Channel input. Comparator negative input. Channel Negative Voltage Reference input. Comparator Voltage Reference output. Comparator positive input. Channel Positive Voltage Reference input. Comparator positive input. Timer0 clock input. Description Name RA0/AN0/ULPWU/C12IN0-
CMOS General purpose I/O.
CMOS General purpose I/O.
CMOS General purpose I/O.
CMOS General purpose I/O. CMOS Comparator output. CMOS General purpose I/O. Channel Slave Select input.
CMOS Comparator output. CMOS General purpose I/O. XTAL Crystal/Resonator. CMOS FOSC/4 output. CMOS General purpose I/O. Crystal/Resonator.
External clock input/RC oscillator connection.
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Channel External interrupt.
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Channel Comparator negative input.
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Channel CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Channel Low-voltage ICSPProgramming enable pin. Comparator negative input.
CMOS CMOS compatible input output Open Drain Schmitt Trigger input with CMOS levels XTAL Crystal
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TABLE 1-2: PIC16F884/887 PINOUT DESCRIPTION (CONTINUED)
Function AN11 RB5/AN13/T1G AN13 RB6/ICSPCLK ICSPCLK RB7/ICSPDAT ICSPDAT RC0/T1OSO/T1CKI T1OSO T1CKI RC1/T1OSI/CCP2 T1OSI CCP2 RC2/P1A/CCP1 CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT RD5/P1B RD6/P1C Legend: Analog input output compatible input High Voltage Input Type XTAL Output Type Description Name RB4/AN11
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Channel CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Channel Timer1 Gate input.
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Serial Programming Clock. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. XTAL ICSPData I/O. Timer1 oscillator output. Timer1 clock input. Timer1 oscillator input. CMOS General purpose I/O.
CMOS General purpose I/O. CMOS Capture/Compare/PWM2. CMOS General purpose I/O. CMOS output. CMOS Capture/Compare/PWM1. CMOS General purpose I/O. CMOS clock. I2Cclock. data input. data input/output. CMOS General purpose I/O.
CMOS General purpose I/O. CMOS data output. CMOS General purpose I/O. CMOS EUSART asynchronous transmit. CMOS EUSART synchronous clock. CMOS General purpose I/O. EUSART asynchronous input. CMOS EUSART synchronous data. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS output. CMOS General purpose I/O. CMOS output.
CMOS CMOS compatible input output Open Drain Schmitt Trigger input with CMOS levels XTAL Crystal
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TABLE 1-2: PIC16F884/887 PINOUT DESCRIPTION (CONTINUED)
Function RE0/AN5 RE1/AN6 RE2/AN7 RE3/MCLR/VPP MCLR Legend: Analog input output compatible input High Voltage Input Type Power Power Output Type CMOS General purpose I/O. output. Channel Channel Channel General purpose input. Master Clear with internal pull-up. Programming voltage. Ground reference. Positive supply. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. Description Name RD7/P1D
CMOS CMOS compatible input output Open Drain Schmitt Trigger input with CMOS levels XTAL Crystal
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MEMORY ORGANIZATION
Program Memory Organization
FIGURE 2-2:
PROGRAM MEMORY STACK PIC16F883/PIC16F884
PC<12:0>
PIC16F882/883/884/886/887 13-bit program counter capable addressing (0000h-07FFh) PIC16F882, (0000h-0FFFh) PIC16F883/PIC16F884, (0000h-1FFFh) PIC16F886/PIC16F887 program memory space. Accessing location above these boundaries will cause wrap-around within first space. Reset vector 0000h interrupt vector 0004h (see Figures 2-3).
CALL, RETURN RETFIE, RETLW
Stack Level Stack Level
Stack Level Reset Vector
FIGURE 2-1:
PROGRAM MEMORY STACK PIC16F882
PC<12:0>
0000h
Interrupt Vector On-Chip Program Memory Page
CALL, RETURN RETFIE, RETLW
0004h 0005h 07FFh 0800h
Stack Level Stack Level
Page 0FFFh
Stack Level Reset Vector
FIGURE 2-3:
0000h
PROGRAM MEMORY STACK PIC16F886/PIC16F887
PC<12:0>
Interrupt Vector On-Chip Program Memory Page
0004h 0005h 07FFh
CALL, RETURN RETFIE, RETLW
Stack Level Stack Level
Stack Level Reset Vector
0000h
Interrupt Vector Page
0004h 0005h 07FFh 0800h
On-Chip Program Memory
Page 0FFFh 1000h Page 17FFh 1800h Page 1FFFh
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Data Memory Organization
data memory (see Figures 2-3) partitioned into four banks which contain General Purpose Registers (GPR) Special Function Registers (SFR). Special Function Registers located first locations each bank. General Purpose Registers, implemented static RAM, located last locations each Bank. Register locations F0h-FFh Bank 170h-17Fh Bank 1F0h-1FFh Bank point addresses 70h-7Fh Bank actual number General Purpose Resisters (GPR) implemented each Bank depends device. Details shown Figures 2-6. other unimplemented returns when read. RP<1:0> STATUS register bank select bits: Bank selected Bank selected Bank selected Bank selected
2.2.1
GENERAL PURPOSE REGISTER FILE
register file organized PIC16F882, PIC16F883/PIC16F884, PIC16F886/PIC16F887. Each register accessed, either directly indirectly, through File Select Register (FSR) (see Section "Indirect Addressing, INDF Registers").
2.2.2
SPECIAL FUNCTION REGISTERS
Special Function Registers registers used peripheral functions controlling desired operation device (see Table 2-1). These registers static RAM. special registers classified into sets: core peripheral. Special Function Registers associated with "core" described this section. Those related operation peripheral features described section that peripheral feature.
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FIGURE 2-4: PIC16F882 SPECIAL FUNCTION REGISTERS
File Address Indirect addr. TMR0 STATUS PORTA PORTB PORTC PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 TRISE PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE SSPCON2 SSPADD SSPSTAT WPUB IOCB VRCON TXSTA SPBRG SPBRGH PWM1CON ECCPAS PSTRCON ADRESL ADCON1 General Purpose Registers Bytes Indirect addr. OPTION_REG STATUS TRISA TRISB TRISC File Address Indirect addr. TMR0 STATUS WDTCON PORTB CM1CON0 CM2CON0 CM2CON1 PCLATH INTCON EEDAT EEADR EEDATH EEADRH File Address 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h Indirect addr. OPTION_REG STATUS SRCON TRISB BAUDCTL ANSEL ANSELH PCLATH INTCON EECON1 EECON2(1) Reserved Reserved File Address 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h
General Purpose Registers Bytes
Bank accesses 70h-7Fh Bank accesses 70h-7Fh Bank
16Fh 170h 17Fh accesses 70h-7Fh Bank
1EFh 1F0h 1FFh
Unimplemented data memory locations, read `0'. Note physical register.
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FIGURE 2-5: PIC16F883/PIC16F884 SPECIAL FUNCTION REGISTERS
File Address Indirect addr. TMR0 STATUS PORTA PORTB PORTC PORTD(2) PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 General Purpose Registers Bytes Bank accesses 70h-7Fh Bank Indirect addr. OPTION_REG STATUS TRISA TRISB TRISC TRISD(2) TRISE PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE SSPCON2 SSPADD SSPSTAT WPUB IOCB VRCON TXSTA SPBRG SPBRGH PWM1CON ECCPAS PSTRCON ADRESL ADCON1 General Purpose Registers Bytes accesses 70h-7Fh Bank File Address General Purpose Registers Bytes 16Fh 170h 17Fh accesses 70h-7Fh Bank 1EFh 1F0h 1FFh Indirect addr. TMR0 STATUS WDTCON PORTB CM1CON0 CM2CON0 CM2CON1 PCLATH INTCON EEDAT EEADR EEDATH EEADRH File Address 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h Indirect addr. OPTION_REG STATUS SRCON TRISB BAUDCTL ANSEL ANSELH PCLATH INTCON EECON1 EECON2(1) Reserved Reserved File Address 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h
Unimplemented data memory locations, read `0'. Note physical register. PIC16F884 only.
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FIGURE 2-6: PIC16F886/PIC16F887 SPECIAL FUNCTION REGISTERS
File Address Indirect addr. TMR0 STATUS PORTA PORTB PORTC PORTD(2) PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 General Purpose Registers Bytes Indirect addr. OPTION_REG STATUS TRISA TRISB TRISC TRISD(2) TRISE PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE SSPCON2 SSPADD SSPSTAT WPUB IOCB VRCON TXSTA SPBRG SPBRGH PWM1CON ECCPAS PSTRCON ADRESL ADCON1 General Purpose Registers Bytes Bank accesses 70h-7Fh Bank accesses 70h-7Fh Bank File Address General Purpose Registers Bytes 16Fh 170h 17Fh accesses 70h-7Fh Bank General Purpose Registers Bytes Indirect addr. TMR0 STATUS WDTCON PORTB CM1CON0 CM2CON0 CM2CON1 PCLATH INTCON EEDAT EEADR EEDATH EEADRH File Address 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h General Purpose Registers Bytes 1EFh 1F0h 1FFh General Purpose Registers Bytes Indirect addr. OPTION_REG STATUS SRCON TRISB BAUDCTL ANSEL ANSELH PCLATH INTCON EECON1 EECON2(1) Reserved Reserved File Address 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h
Unimplemented data memory locations, read `0'. Note physical register. PIC16F887 only.
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TABLE 2-1:
Addr Bank INDF TMR0 STATUS PORTA(3) PORTB(3) PORTC(3) PORTD(3,4) PORTE(3) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON(2) CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 Addressing this location uses contents address data memory (not physical register) Timer0 Module Register Program Counter's (PC) Least Significant Byte xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx RE2(4) RE1(4) RE0(4) RBIF(1) TMR1IF CCP2IF xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 000x -000 0000 0000 00-0 xxxx xxxx xxxx xxxx TMR1CS TMR1ON 0000 0000 0000 0000 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 xxxx xxxx SSPM2 SSPM1 SSPM0 0000 0000 xxxx xxxx xxxx xxxx CCP1M2 FERR CCP1M1 OERR CCP1M0 RX9D 0000 0000 0000 000x 0000 0000 0000 0000 xxxx xxxx xxxx xxxx CCP2M2 CCP2M1 CCP2M0 0000 xxxx xxxx CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 37,217 73,217 37,217 29,217 37,217 39,217 48,217 53,217 57,217 59,217 37,217 31,217 34,217 35,217 76,217 76,217 79,217 81,217 82,217 183,217 181,217 126,217 126,217 124,217 161,217 153,217 158,217 126,217 126,218 125,218 99,218 104,218 Name
PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK
Value POR, Page
Indirect Data Memory Address Pointer OSFIF PEIE ADIF C2IF T0IE RCIF C1IF
Write Buffer upper bits Program Counter INTE TXIF EEIF RBIE SSPIF BCLIF T0IF CCP1IF ULPWUIF INTF TMR2IF
Holding Register Least Significant Byte 16-bit TMR1 Register Holding Register Most Significant Byte 16-bit TMR1 Register T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
Timer2 Module Register TOUTPS3 TOUTPS2
Synchronous Serial Port Receive Buffer/Transmit Register WCOL SSPOV SSPEN SSPM3
Capture/Compare/PWM Register Byte (LSB) Capture/Compare/PWM Register High Byte (MSB) P1M1 SPEN P1M0 DC1B1 SREN DC1B0 CREN CCP1M3 ADDEN
EUSART Transmit Data Register EUSART Receive Data Register Capture/Compare/PWM Register Byte (LSB) Capture/Compare/PWM Register High Byte (MSB) DC2B1 DC2B0 CCP2M3
Result Register High Byte ADCS1 ADCS0 CHS3
Legend: Note
Unimplemented locations read `0', unchanged, unknown, value depends condition, shaded unimplemented MCLR Reset affect previous value data latch. RBIF will cleared upon Reset will again mismatch exists. When SSPCON register bits SSPM<3:0> 1001, reads writes SSPADD address accessed through SSPMSK register. Registers 13-4 more detail. Port pins with analog functions controlled ANSEL ANSELH registers will read immediately after Reset even though data latches either undefined (POR) unchanged (other Resets). PIC16F884/PIC16F887 only.
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TABLE 2-2:
Addr Bank INDF OPTION_REG STATUS TRISA TRISB TRISC TRISD(3) TRISE PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE SSPCON2 SSPADD(2) SSPMSK(2) SSPSTAT WPUB IOCB VRCON TXSTA SPBRG SPBRGH PWM1CON ECCPAS PSTRCON ADRESL ADCON1 Addressing this location uses contents address data memory (not physical register) RBPU INTEDG T0CS T0SE xxxx xxxx 1111 1111 0000 0000 0001 1xxx xxxx xxxx TRISA4 TRISB4 TRISC4 TRISD4 TRISA3 TRISB3 TRISC3 TRISD3 TRISE3 TRISA2 TRISB2 TRISC2 TRISD2 TRISA1 TRISB1 TRISC1 TRISD1 TRISA0 TRISB0 TRISC0 TRISD0 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 000x -000 0000 0000 00-0 -110 q000 0000 0000 0000 1111 1111 0000 0000 MSK2 WPUB2 IOCB2 BRGH BRG2 BRG10 PDC2 PSSAC0 STRC MSK1 WPUB1 IOCB1 TRMT BRG1 BRG9 PDC1 PSSBD1 STRB MSK0 WPUB0 IOCB0 TX9D BRG0 BRG8 PDC0 PSSBD0 STRA 1111 1111 0000 0000 1111 1111 0000 0000 0000 0000 0000 0010 0000 0000 0000 0000 0000 0000 0000 0000 0001 xxxx xxxx VCFG0 0-00 -37,217 30,218 37,217 29,217 37,217 39,218 48,218 53,218 57,218 59,218 37,217 31,217 32,218 33,218 36,218 62,218 66,218 181,218 81,218 189,218 189,218 189,218 49,218 49,218 97,218 160,218 163,218 163,218 145,218 142,218 146,218 99,218 105,218 Name
PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK
Value POR, Page
Program Counter's (PC) Least Significant Byte
Indirect Data Memory Address Pointer TRISA7 TRISB7 TRISC7 TRISD7 OSFIE GCEN TRISA6 TRISB6 TRISC6 TRISD6 PEIE ADIE C2IE IRCF2 ACKSTAT TRISA5 TRISB5 TRISC5 TRISD5 T0IE RCIE C1IE ULPWUE IRCF1 ACKDT
TRISE2(3) TRISE1(3) TRISE0(3) RBIF(1) TMR1IE CCP2IE TUN0
Write Buffer upper bits Program Counter INTE TXIE EEIE SBOREN IRCF0 TUN4 ACKEN RBIE SSPIE BCLIE OSTS TUN3 RCEN T0IF CCP1IE ULPWUIE TUN2 INTF TMR2IE TUN1 RSEN
Timer2 Period Register Synchronous Serial Port (I2C mode) Address Register MSK7 WPUB7 IOCB7 VREN CSRC BRG7 BRG15 PRSEN MSK6 WPUB6 IOCB6 VROE BRG6 BRG14 PDC6 MSK5 WPUB5 IOCB5 TXEN BRG5 BRG13 PDC5 MSK4 WPUB4 IOCB4 VRSS SYNC BRG4 BRG12 PDC4 MSK3 WPUB3 IOCB3 SENDB BRG3 BRG11 PDC3 PSSAC1 STRD
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 STRSYNC
Result Register Byte ADFM VCFG1
Legend: Note
Unimplemented locations read `0', unchanged, unknown, value depends condition, shaded unimplemented MCLR Reset affect previous value data latch. RBIF will cleared upon Reset will again mismatch exists. Accessible only when SSPCON register bits SSPM<3:0> 1001. PIC16F884/PIC16F887 only.
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TABLE 2-3:
Addr Bank 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h INDF TMR0 STATUS WDTCON PORTB CM1CON0 CM2CON0 CM2CON1 Addressing this location uses contents address data memory (not physical register) Timer0 Module Register Program Counter's (PC) Least Significant Byte xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx WDTPS3 C1POL C2POL C2RSEL WDTPS2 WDTPS1 WDTPS0 C1CH1 C2CH1 T1GSS SWDTEN C1CH0 C2CH0 C2SYNC RBIF(1) EEDAT0 EEADR0 EEDATH0 1000 xxxx xxxx 0000 -000 0000 -000 0000 0000 0000 000x 0000 0000 0000 0000 0000 37,217 73,217 37,217 29,217 37,217 225,218 48,217 88,218 89,218 91,219 37,217 31,217 112,219 112,219 112,219 112,219 Name
PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK
Value POR, Page
Indirect Data Memory Address Pointer C1ON C2ON MC1OUT EEDAT7 EEADR7 C1OUT C2OUT MC2OUT PEIE EEDAT6 EEADR6 C1OE C2OE C1RSEL T0IE EEDAT5 EEADR5 EEDATH5
10Ah PCLATH 10Bh INTCON 10Ch EEDAT 10Dh EEADR 10Eh EEDATH 10Fh EEADRH Legend: Note
Write Buffer upper bits Program Counter INTE EEDAT4 EEADR4 EEDATH4 RBIE EEDAT3 EEADR3 EEDATH3 T0IF EEDAT2 EEADR2 EEDATH2 INTF EEDAT1 EEADR1 EEDATH1
EEADRH4(2) EEADRH3 EEADRH2 EEADRH1 EEADRH0 0000
Unimplemented locations read `0', unchanged, unknown, value depends condition, shaded unimplemented MCLR Reset does affect previous value data latch. RBIF will cleared upon Reset will again mismatch exists. PIC16F886/PIC16F887 only.
TABLE 2-4:
Addr Bank 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh INDF Name
PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK
Value POR, Page
Addressing this location uses contents address data memory (not physical register) RBPU INTEDG T0CS T0SE
xxxx xxxx 1111 1111 0000 0000
37,217 30,218 37,217 29,217 37,217 93,219 48,218 162,219 40,219 99,219 37,217 31,217 113,219 111,219
OPTION_REG STATUS SRCON TRISB BAUDCTL ANSEL ANSELH PCLATH INTCON EECON1 EECON2
Program Counter's (PC) Least Significant Byte
0001 1xxx xxxx xxxx
Indirect Data Memory Address Pointer TRISB7 ABDOVF ANS7(2) EEPGD TRISB6 RCIDL ANS6(2) PEIE C1SEN TRISB5 ANS5(2) ANS13 T0IE C2REN TRISB4 SCKP ANS4 ANS12 PULSS TRISB3 BRG16 ANS3 ANS11 PULSR TRISB2 ANS2 ANS10 TRISB1 ANS1 ANS9 FVREN TRISB0 ABDEN ANS0 ANS8 RBIF(1)
0000 00-0 1111 1111 01-0 0-00 1111 1111 1111 0000 0000 000x x000
Write Buffer upper bits Program Counter INTE RBIE WRERR T0IF WREN INTF
EEPROM Control Register (not physical register)
Legend: Note
Unimplemented locations read `0', unchanged, unknown, value depends condition, shaded unimplemented MCLR Reset does affect previous value data latch. RBIF will cleared upon Reset will again mismatch exists. PIC16F884/PIC16F887 only.
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2.2.2.1 STATUS Register
STATUS register, shown Register 2-1, contains: arithmetic status Reset status bank select bits data memory (GPR SFR) STATUS register destination instruction, like other register. STATUS register destination instruction that affects bits, then write these three bits disabled. These bits cleared according device logic. Furthermore, bits writable. Therefore, result instruction with STATUS register destination different than intended. example, CLRF STATUS, will clear upper three bits bit. This leaves STATUS register `000u u1uu' (where unchanged). recommended, therefore, that only BCF, BSF, SWAPF MOVWF instructions used alter STATUS register, because these instructions affect Status bits. other instructions affecting Status bits, Section 15.0 "Instruction Summary" Note bits operate Borrow Digit Borrow bit, respectively, subtraction.
REGISTER 2-1:
R/W-0 Legend: Readable Value
STATUS: STATUS REGISTER
R/W-0 R/W-0 R/W-x R/W-x DC(1) R/W-x C(1)
Writable
Unimplemented bit, read cleared unknown
IRP: Register Bank Select (used indirect addressing) Bank (100h-1FFh) Bank (00h-FFh) RP<1:0>: Register Bank Select bits (used direct addressing) Bank (00h-7Fh) Bank (80h-FFh) Bank (100h-17Fh) Bank (180h-1FFh) Time-out After power-up, CLRWDT instruction SLEEP instruction time-out occurred Power-down After power-up CLRWDT instruction execution SLEEP instruction Zero result arithmetic logic operation zero result arithmetic logic operation zero Digit Carry/Borrow (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) carry-out from low-order result occurred carry-out from low-order result Carry/Borrow (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) carry-out from Most Significant result occurred carry-out from Most Significant result occurred Borrow, polarity reversed. subtraction executed adding two's complement second operand. rotate (RRF, RLF) instructions, this loaded with either high-order low-order source register.
Note
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2.2.2.2 OPTION Register
Note: achieve prescaler assignment Timer0, assign prescaler setting OPTION register `1'. Section "Timer1 Prescaler". OPTION register, shown Register 2-2, readable writable register, which contains various control bits configure: Timer0/WDT prescaler External interrupt Timer0 Weak pull-ups PORTB
REGISTER 2-2:
R/W-1 RBPU Legend: Readable Value
OPTION_REG: OPTION REGISTER
R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 R/W-1 R/W-1 R/W-1
Writable
Unimplemented bit, read cleared unknown
RBPU: PORTB Pull-up Enable PORTB pull-ups disabled PORTB pull-ups enabled individual PORT latch values INTEDG: Interrupt Edge Select Interrupt rising edge Interrupt falling edge T0CS: Timer0 Clock Source Select Transition T0CKI Internal instruction cycle clock (FOSC/4) T0SE: Timer0 Source Edge Select Increment high-to-low transition T0CKI Increment low-to-high transition T0CKI PSA: Prescaler Assignment Prescaler assigned Prescaler assigned Timer0 module PS<2:0>: Prescaler Rate Select bits
Value Timer0 Rate Rate
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2.2.2.3 INTCON Register
Note: Interrupt flag bits when interrupt condition occurs, regardless state corresponding enable Global Enable bit, INTCON register. User software should ensure appropriate interrupt flag bits clear prior enabling interrupt. INTCON register, shown Register 2-3, readable writable register, which contains various enable flag bits TMR0 register overflow, PORTB change external interrupts.
REGISTER 2-3:
R/W-0 Legend: Readable Value
INTCON: INTERRUPT CONTROL REGISTER
R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 RBIE(1) R/W-0 T0IF(2) R/W-0 INTF R/W-x RBIF
Writable
Unimplemented bit, read cleared unknown
GIE: Global Interrupt Enable Enables unmasked interrupts Disables interrupts PEIE: Peripheral Interrupt Enable Enables unmasked peripheral interrupts Disables peripheral interrupts T0IE: Timer0 Overflow Interrupt Enable Enables Timer0 interrupt Disables Timer0 interrupt INTE: External Interrupt Enable Enables external interrupt Disables external interrupt RBIE: PORTB Change Interrupt Enable bit(1) Enables PORTB change interrupt Disables PORTB change interrupt T0IF: Timer0 Overflow Interrupt Flag bit(2) TMR0 register overflowed (must cleared software) TMR0 register overflow INTF: External Interrupt Flag external interrupt occurred (must cleared software) external interrupt occur RBIF: PORTB Change Interrupt Flag When least PORTB general purpose pins changed state (must cleared software) None PORTB general purpose pins have changed state IOCB register must also enabled. T0IF when Timer0 rolls over. Timer0 unchanged Reset should initialized before clearing T0IF bit.
Note
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2.2.2.4 PIE1 Register
Note: PEIE INTCON register must enable peripheral interrupt. PIE1 register contains interrupt enable bits, shown Register 2-4.
REGISTER 2-4:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER
R/W-0 ADIE R/W-0 RCIE R/W-0 TXIE R/W-0 SSPIE R/W-0 CCP1IE R/W-0 TMR2IE R/W-0 TMR1IE
Legend: Readable Value Writable Unimplemented bit, read cleared unknown
Unimplemented: Read ADIE: Converter (ADC) Interrupt Enable Enables interrupt Disables interrupt RCIE: EUSART Receive Interrupt Enable Enables EUSART receive interrupt Disables EUSART receive interrupt TXIE: EUSART Transmit Interrupt Enable Enables EUSART transmit interrupt Disables EUSART transmit interrupt SSPIE: Master Synchronous Serial Port (MSSP) Interrupt Enable Enables MSSP interrupt Disables MSSP interrupt CCP1IE: CCP1 Interrupt Enable Enables CCP1 interrupt Disables CCP1 interrupt TMR2IE: Timer2 Match Interrupt Enable Enables Timer2 match interrupt Disables Timer2 match interrupt TMR1IE: Timer1 Overflow Interrupt Enable Enables Timer1 overflow interrupt Disables Timer1 overflow interrupt
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2.2.2.5 PIE2 Register
Note: PEIE INTCON register must enable peripheral interrupt. PIE2 register contains interrupt enable bits, shown Register 2-5.
REGISTER 2-5:
R/W-0 OSFIE Legend: Readable Value
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER
R/W-0 C2IE R/W-0 C1IE R/W-0 EEIE R/W-0 BCLIE R/W-0 ULPWUIE R/W-0 CCP2IE
Writable
Unimplemented bit, read cleared unknown
OSFIE: Oscillator Fail Interrupt Enable Enables oscillator fail interrupt Disables oscillator fail interrupt C2IE: Comparator Interrupt Enable Enables Comparator interrupt Disables Comparator interrupt C1IE: Comparator Interrupt Enable Enables Comparator interrupt Disables Comparator interrupt EEIE: EEPROM Write Operation Interrupt Enable Enables EEPROM write operation interrupt Disables EEPROM write operation interrupt BCLIE: Collision Interrupt Enable Enables Collision interrupt Disables Collision interrupt ULPWUIE: Ultra Low-Power Wake-up Interrupt Enable Enables Ultra Low-Power Wake-up interrupt Disables Ultra Low-Power Wake-up interrupt Unimplemented: Read CCP2IE: CCP2 Interrupt Enable Enables CCP2 interrupt Disables CCP2 interrupt
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2.2.2.6 PIR1 Register
Note: Interrupt flag bits when interrupt condition occurs, regardless state corresponding enable Global Enable bit, INTCON register. User software should ensure appropriate interrupt flag bits clear prior enabling interrupt. PIR1 register contains interrupt flag bits, shown Register 2-6.
REGISTER 2-6:
Legend: Readable Value
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER
R/W-0 ADIF RCIF TXIF R/W-0 SSPIF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read ADIF: Converter Interrupt Flag conversion complete (must cleared software) conversion completed been started RCIF: EUSART Receive Interrupt Flag EUSART receive buffer full (cleared reading RCREG) EUSART receive buffer full TXIF: EUSART Transmit Interrupt Flag EUSART transmit buffer empty (cleared writing TXREG) EUSART transmit buffer full SSPIF: Master Synchronous Serial Port (MSSP) Interrupt Flag MSSP interrupt condition occurred, must cleared software before returning from Interrupt Service Routine. conditions that will this are: transmission/reception taken place Slave/Master transmission/reception taken place Master initiated Start condition completed MSSP module initiated Stop condition completed MSSP module initiated restart condition completed MSSP module initiated Acknowledge condition completed MSSP module Start condition occurred while MSSP module idle (Multi-master system) Stop condition occurred while MSSP module idle (Multi-master system) MSSP interrupt condition occurred CCP1IF: CCP1 Interrupt Flag Capture mode: TMR1 register capture occurred (must cleared software) TMR1 register capture occurred Compare mode: TMR1 register compare match occurred (must cleared software) TMR1 register compare match occurred mode: Unused this mode TMR2IF: Timer2 Interrupt Flag Timer2 match occurred (must cleared software) Timer2 match occurred TMR1IF: Timer1 Overflow Interrupt Flag TMR1 register overflowed (must cleared software) TMR1 register overflow
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2.2.2.7 PIR2 Register
Note: Interrupt flag bits when interrupt condition occurs, regardless state corresponding enable Global Enable bit, INTCON register. User software should ensure appropriate interrupt flag bits clear prior enabling interrupt. PIR2 register contains interrupt flag bits, shown Register 2-7.
REGISTER 2-7:
R/W-0 OSFIF Legend: Readable Value
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER
R/W-0 C2IF R/W-0 C1IF R/W-0 EEIF R/W-0 BCLIF R/W-0 ULPWUIF R/W-0 CCP2IF
Writable
Unimplemented bit, read cleared unknown
OSFIF: Oscillator Fail Interrupt Flag System oscillator failed, clock input changed INTOSC (must cleared software) System clock operating C2IF: Comparator Interrupt Flag Comparator output (C2OUT bit) changed (must cleared software) Comparator output (C2OUT bit) changed C1IF: Comparator Interrupt Flag Comparator output (C1OUT bit) changed (must cleared software) Comparator output (C1OUT bit) changed EEIF: Write Operation Interrupt Flag Write operation completed (must cleared software) Write operation completed started BCLIF: Collision Interrupt Flag collision occurred MSSP when configured Master mode collision occurred ULPWUIF: Ultra Low-Power Wake-up Interrupt Flag Wake-up condition occurred (must cleared software) Wake-up condition occurred Unimplemented: Read CCP2IF: CCP2 Interrupt Flag Capture mode: TMR1 register capture occurred (must cleared software) TMR1 register capture occurred Compare mode: TMR1 register compare match occurred (must cleared software) TMR1 register compare match occurred mode: Unused this mode
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2.2.2.8 PCON Register
Power Control (PCON) register (see Register 2-8) contains flag bits differentiate between Power-on Reset (POR) Brown-out Reset (BOR) Watchdog Timer Reset (WDT) External MCLR Reset
PCON register also controls Ultra Low-Power Wake-up software enable BOR.
REGISTER 2-8:
Legend: Readable Value
PCON: POWER CONTROL REGISTER
R/W-0 ULPWUE R/W-1 SBOREN(1) R/W-0 R/W-x
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read ULPWUE: Ultra Low-Power Wake-up Enable Ultra Low-Power Wake-up enabled Ultra Low-Power Wake-up disabled SBOREN: Software Enable bit(1) enabled disabled Unimplemented: Read POR: Power-on Reset Status Power-on Reset occurred Power-on Reset occurred (must software after Power-on Reset occurs) BOR: Brown-out Reset Status Brown-out Reset occurred Brown-out Reset occurred (must software after Brown-out Reset occurs) BOREN<1:0> Configuration Word Register this control BOR.
Note
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PCLATH
2.3.2 STACK
Program Counter (PC) bits wide. byte comes from register, which readable writable register. high byte (PC<12:8>) directly readable writable comes from PCLATH. Reset, cleared. Figure shows situations loading upper example Figure shows loaded write (PCLATH<4:0> PCH). lower example Figure shows loaded during CALL GOTO instruction (PCLATH<4:3> PCH). PIC16F882/883/884/886/887 devices have 8-level 13-bit wide hardware stack (see Figures 2-3). stack space part either program data space Stack Pointer readable writable. PUSHed onto stack when CALL instruction executed interrupt causes branch. stack POPed event RETURN, RETLW RETFIE instruction execution. PCLATH affected PUSH operation. stack operates circular buffer. This means that after stack been PUSHed eight times, ninth push overwrites value that stored from first push. tenth push overwrites second push (and on). Note There Status bits indicate stack overflow stack underflow conditions. There instructions/mnemonics called PUSH POP. These actions that occur from execution CALL, RETURN, RETLW RETFIE instructions vectoring interrupt address.
FIGURE 2-7:
LOADING DIFFERENT SITUATIONS
Instruction with Destination Result
PCLATH<4:0>
PCLATH PCLATH<4:3> OPCODE<10:0> PCLATH GOTO, CALL
Indirect Addressing, INDF Registers
INDF register physical register. Addressing INDF register will cause indirect addressing. Indirect addressing possible using INDF register. instruction using INDF register actually accesses data pointed File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing INDF register indirectly results operation (although Status bits affected). effective 9-bit address obtained concatenating 8-bit STATUS register, shown Figure 2-8. simple program clear location 20h-2Fh using indirect addressing shown Example 2-1.
2.3.1
MODIFYING
Executing instruction with register destination simultaneously causes Program Counter PC<12:8> bits (PCH) replaced contents PCLATH register. This allows entire contents program counter changed writing desired upper bits PCLATH register. When lower bits written register, bits program counter will change values contained PCLATH register those being written register. computed GOTO accomplished adding offset program counter (ADDWF PCL). Care should exercised when jumping into look-up table program branch table (computed GOTO) modifying register. Assuming that PCLATH table start address, table length greater than instructions lower bits memory address rolls over from 0xFF 0x00 middle table, then PCLATH must incremented each address rollover that occurs between table beginning target location within table. more information refer Application Note AN556, "Implementing Table Read" (DS00556).
EXAMPLE 2-1:
MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE
INDIRECT ADDRESSING
0x20 INDF FSR,4 NEXT ;initialize pointer ;clear INDF register ;inc pointer ;all done? clear next ;yes continue
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FIGURE 2-8: DIRECT/INDIRECT ADDRESSING PIC16F882/883/884/886/887
Indirect Addressing File Select Register Direct Addressing From Opcode
Bank Select
Location Select
Bank Select 180h
Location Select
Data Memory
Bank Bank Bank Bank
1FFh
Note:
memory detail, Figures 2-3.
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PORTS
There many thirty-five general purpose pins available. Depending which peripherals enabled, some pins available general purpose I/O. general, when peripheral enabled, associated used general purpose pin. operations. Therefore, write port implies that port pins read, this value modified then written PORT data latch. TRISA register (Register 3-2) controls PORTA output drivers, even when they being used analog inputs. user should ensure bits TRISA register maintained when using them analog inputs. pins configured analog input always read `0'. Note: ANSEL register must initialized configure analog channel digital input. Pins configured analog inputs will read `0'.
PORTA TRISA Registers
PORTA 8-bit wide, bidirectional port. corresponding data direction register TRISA (Register 3-2). Setting TRISA will make corresponding PORTA input (i.e., disable output driver). Clearing TRISA will make corresponding PORTA output (i.e., enables output driver puts contents output latch selected pin). Example shows initialize PORTA. Reading PORTA register (Register 3-1) reads status pins, whereas writing will write PORT latch. write operations read-modify-write
EXAMPLE 3-1:
BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF PORTA PORTA ANSEL ANSEL TRISA TRISA
INITIALIZING PORTA
;Init PORTA ;digital ;Set RA<3:2> inputs ;and RA<5:4,1:0> outputs
REGISTER 3-1:
R/W-x Legend: Readable Value
PORTA: PORTA REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
Writable
Unimplemented bit, read cleared unknown
RA<7:0>: PORTA Port Port
REGISTER 3-2:
R/W-1(1) TRISA7 Legend: Readable Value
TRISA: PORTA TRI-STATE REGISTER
R/W-1(1) TRISA6 R/W-1 TRISA5 R/W-1 TRISA4 R/W-1 TRISA3 R/W-1 TRISA2 R/W-1 TRISA1 R/W-1 TRISA0
Writable
Unimplemented bit, read cleared unknown
TRISA<7:0>: PORTA Tri-State Control PORTA configured input (tri-stated) PORTA configured output TRISA<7:6> always reads Oscillator modes.
Note
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Additional Functions
also Ultra Low-Power Wake-up option. next three sections describe these functions.
3.2.1
ANSEL REGISTER
ANSEL register (Register 3-3) used configure Input mode analog. Setting appropriate ANSEL high will cause digital reads read allow analog functions operate correctly. state ANSEL bits affect digital output functions. with TRIS clear ANSEL will still operate digital output, Input mode will analog. This cause unexpected behavior when executing read-modify-write instructions affected port.
REGISTER 3-3:
R/W-1 ANS7(2) Legend: Readable Value
ANSEL: ANALOG SELECT REGISTER
R/W-1 ANS6(2) R/W-1 ANS5(2) R/W-1 ANS4 R/W-1 ANS3 R/W-1 ANS2 R/W-1 ANS1 R/W-1 ANS0
Writable
Unimplemented bit, read cleared unknown
ANS<7:0>: Analog Select bits Analog select between analog digital function pins AN<7:0>, respectively. Analog input. assigned analog input(1). Digital I/O. assigned port special function. Setting analog input automatically disables digital input circuitry, weak pull-ups, interrupt-on-change available. corresponding TRIS must Input mode order allow external control voltage pin. implemented PIC16F883/886.
Note
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3.2.2 ULTRA LOW-POWER WAKE-UP
Ultra Low-Power Wake-up (ULPWU) allows slow falling voltage generate interrupt-on-change without excess current consumption. mode selected setting ULPWUE PCON register. This enables small current sink, which used discharge capacitor RA0. Follow these steps this feature: Charge capacitor configuring output Configure input. ULPWUIE PIE2 register enable interrupt. ULPWUE PCON register begin capacitor discharge. Execute SLEEP instruction. series resistor between external capacitor provides overcurrent protection RA0/AN0/ULPWU/C12IN0- allow software calibration time-out (see Figure 3-1). timer used measure charge time discharge time capacitor. charge time then adjusted provide desired interrupt delay. This technique will compensate affects temperature, voltage component accuracy. Ultra Low-Power Wake-up peripheral also configured simple Programmable Voltage Detect temperature sensor. Note: more information, refer AN879, "Using Microchip Ultra Low-Power Wake-up Module" Application Note (DS00879).
When voltage drops below VIL, interrupt will generated which will cause device wake-up execute next instruction. INTCON register set, device will then call interrupt vector (0004h). This feature provides low-power technique periodically waking device from Sleep. time-out dependent discharge time circuit RA0. Example initializing Ultra Low-Power Wake-up module.
EXAMPLE 3-2:
BANKSEL BANKSEL BANKSEL CALL BANKSEL BANKSEL MOVLW MOVWF SLEEP
ULTRA LOW-POWER WAKE-UP INITIALIZATION
;Set data latch ;RA0 digital ;Output high ;charge capacitor ;Clear flag ;Enable Wake-up ;RA0 input ;Enable interrupt ;Enable peripheral ;interrupt ;Wait
PORTA PORTA,0 ANSEL ANSEL,0 TRISA TRISA,0 CapDelay PIR2 PIR2,ULPWUIF PCON PCON,ULPWUE TRISA,0 PIE2, ULPWUIE B'11000000' INTCON
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3.2.3 DESCRIPTIONS DIAGRAMS 3.2.3.1 RA0/AN0/ULPWU/C12IN0Each PORTA multiplexed with other functions. pins their combined functions briefly described here. specific information about individual functions such comparator Converter (ADC), refer appropriate section this data sheet. Figure shows diagram this pin. This configurable function following: general purpose analog input negative analog input Comparator analog input Ultra Low-Power Wake-up
FIGURE 3-1:
BLOCK DIAGRAM
Data
PORTA
TRISA TRISA PORTA IULP Analog(1) Input Mode ULPWUE
VTRG
Comparator Converter
Note
ANSEL determines Analog Input mode.
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3.2.3.2 RA1/AN1/C12IN13.2.3.3 RA2/AN2/VREF-/CVREF/C2IN+
Figure shows diagram this pin. This configurable function following: general purpose analog input negative analog input Comparator Figure shows diagram this pin. This configurable function following: general purpose analog input negative voltage reference input CVREF comparator voltage reference output positive analog input Comparator
FIGURE 3-2:
Data
BLOCK DIAGRAM
PORTA
FIGURE 3-3:
Data
BLOCK DIAGRAM
VROE CVREF
TRISA TRISA PORTA Analog(1) Input Mode TRISA TRISA Comparator Converter Note ANSEL determines Analog Input mode. PORTA PORTA
Analog(1) Input Mode
Comparator (positive input) Comparator (VREF-) Converter (VREF-) Converter (analog channel) Note ANSEL determines Analog Input mode.
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3.2.3.4 RA3/AN3/VREF+/C1IN+ 3.2.3.5 RA4/T0CKI/C1OUT
Figure shows diagram this pin. This configurable function following: general purpose input analog input positive voltage reference input CVREF positive analog input Comparator Figure shows diagram this pin. This configurable function following: general purpose clock input Timer0 digital output from Comparator
FIGURE 3-5:
Data
BLOCK DIAGRAM
C1OUT Enable
FIGURE 3-4:
Data PORTA
BLOCK DIAGRAM
PORTA
C1OUT
TRISA TRISA
TRISA TRISA PORTA
Analog(1) Input Mode
PORTA Timer0 Comparator (positive input) Comparator (VREF+) Converter (VREF+) Converter (analog channel)
Note
ANSEL determines Analog Input mode.
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3.2.3.6 RA5/AN4/SS/C2OUT 3.2.3.7 RA6/OSC2/CLKOUT
Figure shows diagram this pin. This configurable function following: general purpose analog input slave select input digital output from Comparator Figure shows diagram this pin. This configurable function following: general purpose crystal/resonator connection clock output
FIGURE 3-7: FIGURE 3-6:
Data PORTA C2OUT TRISA TRISA Analog(1) Input Mode TRISA TRISA PORTA Input Converter Note ANSEL determines Analog Input mode. Note With option. PORTA PORTA
BLOCK DIAGRAM
Oscillator Circuit OSC2 CLKOUT Enable
BLOCK DIAGRAM
Data C2OUT Enable CLKOUT Enable INTOSCIO/ EXTRCIO/EC(1) CLKOUT Enable
FOSC/4
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3.2.3.8 RA7/OSC1/CLKIN
Figure shows diagram this pin. This configurable function following: general purpose crystal/resonator connection clock input
FIGURE 3-8:
Data
BLOCK DIAGRAM
Oscillator Circuit OSC1
PORTA
INTOSC Mode
TRISA TRISA PORTA
CLKIN
TABLE 3-1:
Name ADCON0 ANSEL CM1CON0 CM2CON0 CM2CON1 PCON OPTION_REG PORTA SSPCON TRISA Legend:
SUMMARY REGISTERS ASSOCIATED WITH PORTA
ADCS1 ANS7 C1ON C2ON MC1OUT RBPU WCOL TRISA7 ADCS0 ANS6 C1OUT C2OUT MC2OUT INTEDG SSPOV TRISA6 CHS3 ANS5 C1OE C2OE C1RSEL ULPWUE T0CS SSPEN TRISA5 CHS2 ANS4 C1POL C2POL C2RSEL SBOREN T0SE TRISA4 CHS1 ANS3 SSPM3 TRISA3 CHS0 ANS2 SSPM2 TRISA2 GO/DONE ANS1 C1CH1 C2CH1 T1GSS SSPM1 TRISA1 ADON ANS0 C1CH0 C2CH0 C2SYNC SSPM0 TRISA0 Value POR, 0000 0000 1111 1111 0000 -000 0000 -000 0000 1111 1111 xxxx xxxx 0000 0000 1111 1111 Value other Resets 0000 0000 1111 1111 0000 -000 0000 -000 0000 1111 1111 uuuu uuuu 0000 0000 1111 1111
unknown, unchanged, unimplemented locations read `0'. Shaded cells used PORTA.
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PORTB TRISB Registers
3.4.1 ANSELH REGISTER
PORTB 8-bit wide, bidirectional port. corresponding data direction register TRISB (Register 3-6). Setting TRISB will make corresponding PORTB input (i.e., corresponding output driver High-Impedance mode). Clearing TRISB will make corresponding PORTB output (i.e., enable output driver contents output latch selected pin). Example shows initialize PORTB. Reading PORTB register (Register 3-5) reads status pins, whereas writing will write PORT latch. write operations read-modify-write operations. Therefore, write port implies that port pins read, this value modified then written PORT data latch. TRISB register (Register 3-6) controls PORTB output drivers, even when they being used analog inputs. user should ensure bits TRISB register maintained when using them analog inputs. pins configured analog input always read `0'. Example shows initialize PORTB. ANSELH register (Register 3-4) used configure Input mode analog. Setting appropriate ANSELH high will cause digital reads read allow analog functions operate correctly. state ANSELH bits affect digital output functions. with TRIS clear ANSELH will still operate digital output, Input mode will analog. This cause unexpected behavior when executing read-modify-write instructions affected port.
3.4.2
WEAK PULL-UPS
Each PORTB pins individually configurable internal weak pull-up. Control bits WPUB<7:0> enable disable each pull-up (see Register 3-7). Each weak pull-up automatically turned when port configured output. pull-ups disabled Power-on Reset RBPU OPTION register.
3.4.3
INTERRUPT-ON-CHANGE
EXAMPLE 3-3:
BANKSEL CLRF BANKSEL MOVLW MOVWF
INITIALIZING PORTB
PORTB PORTB ;Init PORTB TRISB B`11110000' ;Set RB<7:4> inputs ;and RB<3:0> outputs TRISB
PORTB pins individually configurable interrupt-on-change pin. Control bits IOCB<7:0> enable disable interrupt function each pin. Refer Register 3-8. interrupt-on-change feature disabled Power-on Reset. enabled interrupt-on-change pins, present value compared with value latched last read PORTB determine which bits have changed mismatched value. `mismatch' outputs last read OR'd together PORTB Change Interrupt flag (RBIF) INTCON register. This interrupt wake device from Sleep. user, Interrupt Service Routine, clears interrupt read write PORTB. This will mismatch condition. Clear flag RBIF.
Note:
ANSELH register must initialized configure analog channel digital input. Pins configured analog inputs will read `0'.
Additional PORTB Functions
PORTB pins RB<7:0> device family device have interrupt-on-change option weak pull-up option. following three sections describe these PORTB functions. Every PORTB this device family interrupt-on-change option weak pull-up option.
mismatch condition will continue flag RBIF. Reading writing PORTB will mismatch condition allow flag RBIF cleared. latch holding last read value affected MCLR Brown-out Reset. After these Resets, RBIF flag will continue mismatch present. Note: change should occur when read operation being executed (start cycle), then RBIF interrupt flag set. Furthermore, since read write port affects bits that port, care must taken when using multiple pins Interrupt-on-Change mode. Changes seen while servicing changes another pin.
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REGISTER 3-4:
Legend: Readable Value Writable Unimplemented bit, read cleared unknown
ANSELH: ANALOG SELECT HIGH REGISTER
R/W-1 ANS13 R/W-1 ANS12 R/W-1 ANS11 R/W-1 ANS10 R/W-1 ANS9 R/W-1 ANS8
Unimplemented: Read ANS<13:8>: Analog Select bits Analog select between analog digital function pins AN<13:8>, respectively. Analog input. assigned analog input(1). Digital I/O. assigned port special function. Setting analog input automatically disables digital input circuitry, weak pull-ups, interrupt-on-change available. corresponding TRIS must Input mode order allow external control voltage pin.
Note
REGISTER 3-5:
R/W-x Legend: Readable Value
PORTB: PORTB REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
Writable
Unimplemented bit, read cleared unknown
RB<7:0>: PORTB Port Port
REGISTER 3-6:
R/W-1 TRISB7 Legend: Readable Value
TRISB: PORTB TRI-STATE REGISTER
R/W-1 TRISB6 R/W-1 TRISB5 R/W-1 TRISB4 R/W-1 TRISB3 R/W-1 TRISB2 R/W-1 TRISB1 R/W-1 TRISB0
Writable
Unimplemented bit, read cleared unknown
TRISB<7:0>: PORTB Tri-State Control PORTB configured input (tri-stated) PORTB configured output
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REGISTER 3-7:
R/W-1 WPUB7 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1 WPUB6 R/W-1 WPUB5 R/W-1 WPUB4 R/W-1 WPUB3 R/W-1 WPUB2 R/W-1 WPUB1 R/W-1 WPUB0
WPUB<7:0>: Weak Pull-up Register Pull-up enabled Pull-up disabled weak pull-up device automatically disabled configured output.
Note Global RBPU OPTION register must cleared individual pull-ups enabled.
REGISTER 3-8:
R/W-0 IOCB7 Legend: Readable Value
IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER
R/W-0 IOCB6 R/W-0 IOCB5 R/W-0 IOCB4 R/W-0 IOCB3 R/W-0 IOCB2 R/W-0 IOCB1 R/W-0 IOCB0
Writable
Unimplemented bit, read cleared unknown
IOCB<7:0>: Interrupt-on-Change PORTB Control Interrupt-on-change enabled Interrupt-on-change disabled
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3.4.4 DESCRIPTIONS DIAGRAMS FIGURE 3-9: BLOCK DIAGRAM RB<3:0>
Analog(1) Input Mode Weak RBPU
Each PORTB multiplexed with other functions. pins their combined functions briefly described here. specific information about individual functions such SSP, interrupts, refer appropriate section this data sheet.
Data WPUB WPUB
3.4.4.1
RB0/AN12/INT
Figure shows diagram this pin. This configurable function following: general purpose analog input external edge triggered interrupt
PORTB
CCP1OUT Enable CCP1OUT
TRISB TRISB PORTB IOCB IOCB Interrupt-onChange PORTB Analog(1) Input Mode
3.4.4.2
RB1/AN10/P1C /C12IN3-
Figure shows diagram this pin. This configurable function following: general purpose analog input output(1) analog input Comparator Note available PIC16F882/883/886 only.
3.4.4.3
RB2/AN8/P1B(1)
Figure shows diagram this pin. This configurable function following: general purpose analog input output(1) Note available PIC16F882/883/886 only.
RB0/INT RB3/PGM Converter Comparator (RB1, RB3) Note ANSELH determines Analog Input mode.
3.4.4.4
RB3/AN9/PGM/C12IN2-
Figure shows diagram this pin. This configurable function following: general purpose analog input Low-voltage In-Circuit Serial Programming enable analog input Comparator
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3.4.4.5 RB4/AN11/P1D(1) 3.4.4.7 RB6/ICSPCLK
Figure 3-10 shows diagram this pin. This configurable function following: general purpose analog input output(1) Note available PIC16F882/883/886 only. Figure 3-10 shows diagram this pin. This configurable function following: general purpose In-Circuit Serial Programming clock
3.4.4.8
RB7/ICSPDAT
Figure 3-10 shows diagram this pin. This configurable function following: general purpose In-Circuit Serial Programming data
3.4.4.6
RB5/AN13/T1G
Figure 3-10 shows diagram this pin. This configurable function following: general purpose analog input Timer1 gate input
FIGURE 3-10:
Data
BLOCK DIAGRAM RB<7:4>
Analog(1) Input Mode WPUB WPUB PORTB TRISB TRISB PORTB IOCB IOCB PORTB Timer1 T1G(3) Converter ICSPCLK (RB6) ICSPDAT (RB7) ICSPTM(2) Weak
RBPU CCP1OUT Enable CCP1OUT
Analog(1) Input Mode
Interrupt-onChange
Available PIC16F882/PIC16F883/PIC16F886 only. Note ANSELH determines Analog Input mode. Applies RB<7:6> pins only). Applies only.
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TABLE 3-2:
Name ANSELH CCP1CON CM2CON1 IOCB INTCON OPTION_REG PORTB TRISB WPUB Legend:
SUMMARY REGISTERS ASSOCIATED WITH PORTB
P1M1 IOCB7 RBPU TRISB7 WPUB7 P1M0 IOCB6 PEIE INTEDG TRISB6 WPUB6 ANS13 DC1B1 IOCB5 T0IE T0CS TRISB5 WPUB5 ANS12 DC1B0 IOCB4 INTE T0SE TRISB4 WPUB4 ANS11 IOCB3 RBIE TRISB3 WPUB3 ANS10 IOCB2 T0IF TRISB2 WPUB2 ANS9 T1GSS IOCB1 INTF TRISB1 WPUB1 ANS8 Value POR, Value other Resets
1111 1111
CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 C2SYNC 0000 0000 IOCB0 RBIF TRISB0 WPUB0 0000 0000 0000 0000 0000 000x 0000 000x 1111 1111 1111 1111 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 1111 1111 1111 1111
MC1OUT MC2OUT C1RSEL C2RSEL
unknown, unchanged, unimplemented read `0'. Shaded cells used PORTB.
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PORTC TRISC Registers
PORTC 8-bit wide, bidirectional port. corresponding data direction register TRISC (Register 3-10). Setting TRISC will make corresponding PORTC input (i.e., corresponding output driver High-Impedance mode). Clearing TRISC will make corresponding PORTC output (i.e., enable output driver contents output latch selected pin). Example shows initialize PORTC. Reading PORTC register (Register 3-9) reads status pins, whereas writing will write PORT latch. write operations read-modify-write operations. Therefore, write port implies that port pins read, this value modified then written PORT data latch. TRISC register (Register 3-10) controls PORTC output drivers, even when they being used analog inputs. user should ensure bits TRISC register maintained when using them analog inputs. pins configured analog input always read `0'.
EXAMPLE 3-4:
BANKSEL CLRF BANKSEL MOVLW MOVWF
INITIALIZING PORTC
;Init PORTC ;Set RC<3:2> inputs ;and RC<7:4,1:0> outputs
PORTC PORTC TRISC B`00001100' TRISC
REGISTER 3-9:
R/W-x Legend: Readable Value
PORTC: PORTC REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
Writable
Unimplemented bit, read cleared unknown
RC<7:0>: PORTC General Purpose Port Port
REGISTER 3-10:
R/W-1 TRISC7 Legend: Readable Value
TRISC: PORTC TRI-STATE REGISTER
R/W-1 R/W-1 TRISC5 R/W-1 TRISC4 R/W-1 TRISC3 R/W-1 TRISC2 R/W-1(1) TRISC1 R/W-1(1) TRISC0
TRISC6
Writable
Unimplemented bit, read cleared unknown
TRISC<7:0>: PORTC Tri-State Control PORTC configured input (tri-stated) PORTC configured output TRISC<1:0> always reads Oscillator mode.
Note
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3.5.1 RC0/T1OSO/T1CKI 3.5.3 RC2/P1A/CCP1
Figure 3-11 shows diagram this pin. This configurable function following: general purpose Timer1 oscillator output Timer1 clock input Figure 3-13 shows diagram this pin. This configurable function following: general purpose output Capture input Compare output Comparator
FIGURE 3-11:
Data
BLOCK DIAGRAM
Timer1 Oscillator Circuit CCP1/P1A
FIGURE 3-13:
Data
BLOCK DIAGRAM
CCP1CON
T1OSCEN PORTC
PORTC
TRISC TRISC PORTC
TRISC TRISC PORTC Enhanced CCP1
Timer1 clock input
3.5.2
RC1/T1OSI/CCP2
Figure 3-12 shows diagram this pin. This configurable function following: general purpose Timer1 oscillator input Capture input Compare/PWM output Comparator
FIGURE 3-12:
Data
BLOCK DIAGRAM
Timer1 Oscillator Circuit
T1OSCEN T1OSI
CCP2CON PORTC CCP2
TRISC TRISC PORTC
T1OSCEN
CCP2
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3.5.4 RC3/SCK/SCL 3.5.6 RC5/SDO
Figure 3-14 shows diagram this pin. This configurable function following: general purpose clock I2Cclock Figure 3-16 shows diagram this pin. This configurable function following: general purpose serial data output
FIGURE 3-16: FIGURE 3-14:
Data SSPEN PORTC
BLOCK DIAGRAM
Port/SDO Select
BLOCK DIAGRAM
Data PORTC
TRISC TRISC PORTC
TRISC TRISC PORTC SSPSR
3.5.5
RC4/SDI/SDA
Figure 3-15 shows diagram this pin. This configurable function following: general purpose data data
FIGURE 3-15:
Data
BLOCK DIAGRAM
SSPEN PORTC SDI/SDA
TRISC TRISC PORTC
SSPSR
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3.5.7 RC6/TX/CK 3.5.8 RC7/RX/DT
Figure 3-17 shows diagram this pin. This configurable function following: general purpose asynchronous serial output synchronous clock Figure 3-18 shows diagram this pin. This configurable function following: general purpose asynchronous serial input synchronous serial data
FIGURE 3-17:
BLOCK DIAGRAM
SPEN TXEN SYNC
FIGURE 3-18:
Data
BLOCK DIAGRAM
SPEN SYNC
Data
EUSART EUSART PORTC
EUSART
PORTC
TRISC TRISC PORTC EUSART RX/DT
TRISC TRISC PORTC
TABLE 3-3:
Name CCP1CON CCP2CON PORTC PSTRCON RCSTA SSPCON T1CON TRISC Legend:
SUMMARY REGISTERS ASSOCIATED WITH PORTC
P1M1 SPEN WCOL T1GINV TRISC7 P1M0 SSPOV TMR1GE TRISC6 DC1B1 DC2B1 SREN SSPEN T1CKPS1 TRISC5 DC1B0 DC2B0 STRSYNC CREN T1CKPS0 TRISC4 CCP1M3 CCP2M3 STRD ADDEN SSPM3 T1OSCEN TRISC3 CCP1M2 CCP2M2 STRC FERR SSPM2 T1SYNC TRISC2 CCP1M1 CCP2M1 STRB OERR SSPM1 TMR1CS TRISC1 CCP1M0 CCP2M0 STRA RX9D SSPM0 TMR1ON TRISC0 Value POR, 0000 0000 0000 xxxx xxxx 0001 0000 000x 0000 0000 0000 0000 1111 1111 Value other Resets 0000 0000 0000 uuuu uuuu 0001 0000 000x 0000 0000 0000 0000 1111 1111
unknown, unchanged, unimplemented locations read `0'. Shaded cells used PORTC.
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PORTD TRISD Registers
PORTD(1) 8-bit wide, bidirectional port. corresponding data direction register TRISD (Register 3-12). Setting TRISD will make corresponding PORTD input (i.e., corresponding output driver High-Impedance mode). Clearing TRISD will make corresponding PORTD output (i.e., enable output driver contents output latch selected pin). Example shows initialize PORTD. Reading PORTD register (Register 3-11) reads status pins, whereas writing will write PORT latch. write operations read-modify-write operations. Therefore, write port implies that port pins read, this value modified then written PORT data latch. Note PORTD available PIC16F884/887 only. TRISD register (Register 3-12) controls PORTD output drivers, even when they being used analog inputs. user should ensure bits TRISD register maintained when using them analog inputs. pins configured analog input always read `0'.
EXAMPLE 3-5:
BANKSEL CLRF BANKSEL MOVLW MOVWF
INITIALIZING PORTD
;Init PORTD ;Set RD<3:2> inputs ;and RD<7:4,1:0> outputs
PORTD PORTD TRISD B`00001100' TRISD
REGISTER 3-11:
R/W-x Legend: Readable Value
PORTD: PORTD REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
Writable
Unimplemented bit, read cleared unknown
RD<7:0>: PORTD General Purpose Port Port
REGISTER 3-12:
R/W-1 TRISD7 Legend: Readable Value
TRISD: PORTD TRI-STATE REGISTER
R/W-1 R/W-1 TRISD5 R/W-1 TRISD4 R/W-1 TRISD3 R/W-1 TRISD2 R/W-1 TRISD1 R/W-1 TRISD0
TRISD6
Writable
Unimplemented bit, read cleared unknown
TRISD<7:0>: PORTD Tri-State Control PORTD configured input (tri-stated) PORTD configured output
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3.6.1 RD<4:0> 3.6.3 RD6/P1C(1)
Figure 3-19 shows diagram these pins. These pins configured function general purpose I/O's. Note: RD<4:0> available PIC16F884/887 only. Figure 3-20 shows diagram this pin. This configurable function following: general purpose output Note RD6/P1C available PIC16F884/887 only. RB1/AN10/P1C/C12IN3- this function PIC16F882/883/886.
FIGURE 3-19:
BLOCK DIAGRAM RD<4:0>
3.6.4
Data
RD7/P1D(1)
Figure 3-20 shows diagram this pin. This configurable function following: general purpose output
PORTD
TRISD TRISD PORTD
Note RD7/P1D available PIC16F884/887 only. RB4/AN11/P1D this function PIC16F882/883/886.
FIGURE 3-20:
BLOCK DIAGRAM RD<7:5>
PSTRCON
Data PORTD
3.6.2
RD5/P1B(1)
CCP1
Figure 3-20 shows diagram this pin. This configurable function following: general purpose output Note RD5/P1B available PIC16F884/887 only. RB2/AN8/P1B this function PIC16F882/883/886.
TRISD TRISD PORTD
TABLE 3-4:
Name PORTD PSTRCON TRISD Legend:
SUMMARY REGISTERS ASSOCIATED WITH PORTD
TRISD7 TRISD6 TRISD5 STRSYNC TRISD4 STRD TRISD3 STRC TRISD2 STRB TRISD1 STRA TRISD0 Value POR, xxxx xxxx 0001 1111 1111 Value other Resets uuuu uuuu 0001 1111 1111
unknown, unchanged, unimplemented locations read `0'. Shaded cells used PORTD.
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PORTE TRISE Registers
PORTE(1) 4-bit wide, bidirectional port. corresponding data direction register TRISE. Setting TRISE will make corresponding PORTE input (i.e., corresponding output driver High-Impedance mode). Clearing TRISE will make corresponding PORTE output (i.e., enable output driver contents output latch selected pin). exception RE3, which input only TRIS will always read `1'. Example shows initialize PORTE. Reading PORTE register (Register 3-13) reads status pins, whereas writing will write PORT latch. write operations read-modify-write operations. Therefore, write port implies that port pins read, this value modified then written PORT data latch. reads when MCLRE Note RE<2:0> pins PIC16F884/887 only. available TRISE register (Register 3-14) controls PORTE output drivers, even when they being used analog inputs. user should ensure bits TRISE register maintained when using them analog inputs. pins configured analog input always read `0'. Note: ANSEL register must initialized configure analog channel digital input. Pins configured analog inputs will read `0'.
EXAMPLE 3-6:
BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF
INITIALIZING PORTE
;Init PORTE ;digital ;Bank ;Set RE<3:2> inputs ;and RE<1:0> outputs
PORTE PORTE ANSEL ANSEL STATUS,RP1 TRISE B`00001100' TRISE
REGISTER 3-13:
Legend: Readable Value
PORTE: PORTE REGISTER
R/W-x R/W-x R/W-x
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read RD<3:0>: PORTE General Purpose Port Port
REGISTER 3-14:
Legend: Readable Value
TRISE: PORTE TRI-STATE REGISTER
R-1(1) TRISE3 R/W-1 TRISE2 R/W-1 TRISE1 R/W-1 TRISE0
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read TRISE<3:0>: PORTE Tri-State Control PORTE configured input (tri-stated) PORTE configured output TRISE<3> always reads `1'.
Note
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3.7.1 RE0/AN5(1) 3.7.4 RE3/MCLR/VPP
This configurable function following: general purpose analog input Note RE0/AN5 available PIC16F884/887 only. Figure 3-22 shows diagram this pin. This configurable function following: general purpose input Master Clear Reset with weak pull-up
FIGURE 3-22:
BLOCK DIAGRAM
MCLRE
3.7.2
RE1/AN6(1)
Data
Weak
This configurable function following: general purpose analog input Note RE1/AN6 available PIC16F884/887 only.
Reset
MCLRE
Input
TRISE PORTE
MCLRE
3.7.3
RE2/AN7(1)
This configurable function following: general purpose analog input Note RE2/AN7 available PIC16F884/887 only.
FIGURE 3-21:
Data
BLOCK DIAGRAM RE<2:0>
PORTE
TRISE TRISE PORTE Converter Note ANSEL determines Analog Input mode. Analog(1) Input Mode
TABLE 3-5:
Name ANSEL PORTE TRISE Legend:
SUMMARY REGISTERS ASSOCIATED WITH PORTE
ANS7 ANS6 ANS5 ANS4 ANS3 TRISE3 ANS2 TRISE2 ANS1 TRISE1 ANS0 TRISE0 Value POR, 1111 1111 xxxx 1111 Value other Resets 1111 1111 uuuu 1111
unknown, unchanged, unimplemented locations read `0'. Shaded cells used PORTE
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OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR)
Overview
oscillator module configured eight clock modes. External clock with OSC2/CLKOUT. Low-Power Crystal mode. Medium Gain Crystal Ceramic Resonator Oscillator mode. High Gain Crystal Ceramic Resonator mode. External Resistor-Capacitor (RC) with FOSC/4 output OSC2/CLKOUT. RCIO External Resistor-Capacitor (RC) with OSC2/CLKOUT. INTOSC Internal oscillator with FOSC/4 output OSC2 OSC1/CLKIN. INTOSCIO Internal oscillator with OSC1/CLKIN OSC2/CLKOUT.
oscillator module wide variety clock sources selection features that allow used wide range applications while maximizing performance minimizing power consumption. Figure illustrates block diagram oscillator module. Clock sources configured from external oscillators, quartz crystal resonators, ceramic resonators Resistor-Capacitor (RC) circuits. addition, system clock source configured from internal oscillators, with choice speeds selectable software. Additional clock features include: Selectable system clock source between external internal software. Two-Speed Start-up mode, which minimizes latency between external oscillator start-up code execution. Fail-Safe Clock Monitor (FSCM) designed detect failure external clock source (LP, modes) switch automatically internal oscillator.
Clock Source modes configured FOSC<2:0> bits Configuration Word Register (CONFIG1). internal clock generated from internal oscillators. HFINTOSC calibrated highfrequency oscillator. LFINTOSC uncalibrated low-frequency oscillator.
FIGURE 4-1:
SIMPLIFIED PIC® CLOCK SOURCE BLOCK DIAGRAM
FOSC<2:0> (Configuration Word Register SCS<0> (OSCCON Register)
External Oscillator OSC2 Sleep OSC1
RCIO, INTOSC
IRCF<2:0> (OSCCON Register) Internal Oscillator Postscaler LFINTOSC HFINTOSC
System Clock (CPU Peripherals)
Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM)
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Oscillator Control
Oscillator Control (OSCCON) register (Figure 4-1) controls system clock frequency selection options. OSCCON register contains following bits: Frequency selection bits (IRCF) Frequency Status bits (HTS, LTS) System clock control bits (OSTS, SCS)
REGISTER 4-1:
Legend: Readable Value
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-1 IRCF2 R/W-1 IRCF1 R/W-0 IRCF0 OSTS(1) R/W-0
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read IRCF<2:0>: Internal Oscillator Frequency Select bits (default) (LFINTOSC) OSTS: Oscillator Start-up Time-out Status bit(1) Device running from clock defined FOSC<2:0> CONFIG1 register Device running from internal oscillator (HFINTOSC LFINTOSC) HTS: HFINTOSC Status (High Frequency kHz) HFINTOSC stable HFINTOSC stable LTS: LFINTOSC Stable (Low Frequency kHz) LFINTOSC stable LFINTOSC stable SCS: System Clock Select Internal oscillator used system clock Clock source defined FOSC<2:0> CONFIG1 register resets with Two-Speed Start-up selected Oscillator mode Fail-Safe mode enabled.
Note
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Clock Source Modes
4.4.1
External Clock Modes
OSCILLATOR START-UP TIMER (OST)
Clock Source modes classified external internal. External Clock modes rely external circuitry clock source. Examples are: oscillator modules mode), quartz crystal resonators ceramic resonators (LP, modes) Resistor-Capacitor (RC) mode circuits. Internal clock sources contained internally within oscillator module. oscillator module internal oscillators: HighFrequency Internal Oscillator (HFINTOSC) Low-Frequency Internal Oscillator (LFINTOSC). system clock selected between external internal clock sources System Clock Select (SCS) OSCCON register. Section "Clock Switching" additional information.
oscillator module configured modes, Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following Power-on Reset (POR) when Power-up Timer (PWRT) expired configured), wake-up from Sleep. During this time, program counter does increment program execution suspended. ensures that oscillator circuit, using quartz crystal resonator ceramic resonator, started providing stable system clock oscillator module. When switching between clock sources, delay required allow clock stabilize. These oscillator delays shown Table 4-1. order minimize latency between external oscillator start-up code execution, Two-Speed Clock Start-up mode selected (see Section "TwoSpeed Clock Start-up Mode").
TABLE 4-1:
Switch From Sleep/POR Sleep/POR
OSCILLATOR DELAY EXAMPLES
Switch LFINTOSC HFINTOSC HFINTOSC Frequency Oscillator Delay Oscillator Warm-up Delay (TWARM) cycles cycle each 1024 Clock Cycles (OST) (approx.)
LFINTOSC kHz) Sleep/POR LFINTOSC kHz)
4.4.2
MODE
FIGURE 4-2:
External Clock (EC) mode allows externally generated logic level system clock source. When operating this mode, external clock source connected OSC1 input OSC2 available general purpose I/O. Figure shows connections mode. Oscillator Start-up Timer (OST) disabled when mode selected. Therefore, there delay operation after Power-on Reset (POR) wake-up from Sleep. Because PIC® design fully static, stopping external clock input will have effect halting device while leaving data intact. Upon restarting external clock, device will resume operation time elapsed.
EXTERNAL CLOCK (EC) MODE OPERATION
OSC1/CLKIN PIC® OSC2/CLKOUT(1)
Clock from Ext. System
Note
Alternate functions listed Section "Device Overview".
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4.4.3 MODES
modes support quartz crystal resonators ceramic resonators connected OSC1 OSC2 (Figure 4-3). mode selects low, medium high gain setting internal inverteramplifier support various resonator types speed. Oscillator mode selects lowest gain setting internal inverter-amplifier. mode current consumption least three modes. This mode designed drive only 32.768 tuning-fork type crystals (watch crystals). Oscillator mode selects intermediate gain setting internal inverter-amplifier. mode current consumption medium three modes. This mode best suited drive resonators with medium drive level specification. Oscillator mode selects highest gain setting internal inverter-amplifier. mode current consumption highest three modes. This mode best suited resonators that require high drive setting. Figure Figure show typical circuits quartz crystal ceramic resonators, respectively. Note Quartz crystal characteristics vary according type, package manufacturer. user should consult manufacturer data sheets specifications recommended application. Always verify oscillator performance over temperature range that expected application. oscillator design assistance, reference following Microchip Applications Notes: AN826, "Crystal Oscillator Basics Crystal Selection rfPIC® PIC® Devices" (DS00826) AN849, "Basic PIC® Oscillator Design" (DS00849) AN943, "Practical PIC® Oscillator Analysis Design" (DS00943) AN949, "Making Your Oscillator Work" (DS00949)
FIGURE 4-4:
FIGURE 4-3:
QUARTZ CRYSTAL OPERATION (LP, MODE)
PIC®
OSC1/CLKIN
CERAMIC RESONATOR OPERATION MODE)
PIC®
OSC1/CLKIN Internal Logic RP(3) RF(2) Sleep
Quartz Crystal
Internal Logic RF(2) Sleep
Ceramic RS(1) Resonator OSC2/CLKOUT
OSC2/CLKOUT
RS(1)
Note
series resistor (RS) required ceramic resonators with drive level.
Note
series resistor (RS) required quartz crystals with drive level. value varies with Oscillator mode selected (typically between
value varies with Oscillator mode selected (typically between additional parallel feedback resistor (RP) required proper ceramic resonator operation.
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4.4.4 EXTERNAL MODES
Internal Clock Modes
external Resistor-Capacitor (RC) modes support external circuit. This allows designer maximum flexibility frequency choice while keeping costs minimum when clock accuracy required. There modes: RCIO. mode, circuit connects OSC1. OSC2/ CLKOUT outputs oscillator frequency divided This signal used provide clock external circuitry, synchronization, calibration, test other application requirements. Figure shows external mode connections.
oscillator module independent, internal oscillators that configured selected system clock source. HFINTOSC (High-Frequency Internal Oscillator) factory calibrated operates MHz. frequency HFINTOSC user-adjusted software using OSCTUNE register (Register 4-2). LFINTOSC (Low-Frequency Internal Oscillator) uncalibrated operates kHz.
FIGURE 4-5:
REXT
EXTERNAL MODES
PIC®
system clock speed selected software using Internal Oscillator Frequency Select bits IRCF<2:0> OSCCON register. system clock selected between external internal clock sources System Clock Selection (SCS) OSCCON register. Section "Clock Switching" more information.
OSC1/CLKIN CEXT FOSC/4 I/O(2) OSC2/CLKOUT
Internal Clock
4.5.1
INTOSC INTOSCIO MODES
Recommended values: REXT REXT 3-5V CEXT 2-5V Note Alternate functions listed Section "Device Overview". Output depends upon RCIO Clock mode.
INTOSC INTOSCIO modes configure internal oscillators system clock source when device programmed using oscillator selection FOSC<2:0> bits Configuration Word Register (CONFIG1). INTOSC mode, OSC1/CLKIN available general purpose I/O. OSC2/CLKOUT outputs selected internal oscillator frequency divided CLKOUT signal used provide clock external circuitry, synchronization, calibration, test other application requirements. INTOSCIO mode, OSC1/CLKIN OSC2/CLKOUT available general purpose I/O.
RCIO mode, circuit connected OSC1. OSC2 becomes additional general purpose pin. oscillator frequency function supply voltage, resistor (REXT) capacitor (CEXT) values operating temperature. Other factors affecting oscillator frequency are: threshold voltage variation component tolerances packaging variations capacitance user also needs take into account variation tolerance external components used.
4.5.2
HFINTOSC
High-Frequency Internal Oscillator (HFINTOSC) factory calibrated internal clock source. frequency HFINTOSC altered software using OSCTUNE register (Register 4-2). output HFINTOSC connects postscaler multiplexer (see Figure 4-1). seven frequencies selected software using IRCF<2:0> bits OSCCON register. Section 4.5.4 "Frequency Select Bits (IRCF)" more information. HFINTOSC enabled selecting frequency between setting IRCF<2:0> bits OSCCON register 000. Then, System Clock Source (SCS) OSCCON register enable Two-Speed Start-up setting IESO Configuration Word Register (CONFIG1) `1'. Internal Oscillator (HTS) OSCCON register indicates whether HFINTOSC stable not.
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4.5.2.1 OSCTUNE Register
HFINTOSC factory calibrated adjusted software writing OSCTUNE register (Register 4-2). default value OSCTUNE register `0'. value 5-bit two's complement number. When OSCTUNE register modified, HFINTOSC frequency will begin shifting frequency. Code execution continues during this shift. There indication that shift occurred. OSCTUNE does affect LFINTOSC frequency. Operation features that depend LFINTOSC clock source frequency, such Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) peripherals, affected change frequency.
REGISTER 4-2:
Legend: Readable Value
OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 R/W-0 TUN0
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read TUN<4:0>: Frequency Tuning bits 01111 Maximum frequency 01110 00001 00000 Oscillator module running factory-calibrated frequency. 11111 10000 Minimum frequency
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4.5.3 LFINTOSC 4.5.5
Low-Frequency Internal Oscillator (LFINTOSC) uncalibrated internal clock source. output LFINTOSC connects postscaler multiplexer (see Figure 4-1). Select kHz, software, using IRCF<2:0> bits OSCCON register. Section 4.5.4 "Frequency Select Bits (IRCF)" more information. LFINTOSC also frequency Power-up Timer (PWRT), Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM). LFINTOSC enabled selecting (IRCF<2:0> bits OSCCON register 000) system clock source (SCS OSCCON register when following enabled: Two-Speed Start-up IESO Configuration Word Register IRCF<2:0> bits OSCCON register Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM) Internal Oscillator (LTS) OSCCON register indicates whether LFINTOSC stable not.
HFINTOSC LFINTOSC CLOCK SWITCH TIMING
When switching between LFINTOSC HFINTOSC, oscillator already shut down save power (see Figure 4-6). this case, there delay after IRCF<2:0> bits OSCCON register modified before frequency selection takes place. bits OSCCON register will reflect current active status LFINTOSC HFINTOSC oscillators. timing frequency selection follows: IRCF<2:0> bits OSCCON register modified. clock shut down, clock start-up delay started. Clock switch circuitry waits falling edge current clock. CLKOUT held clock switch circuitry waits rising edge clock. CLKOUT connected with clock. bits OSCCON register updated required. Clock switch complete.
Figure more details. internal oscillator speed selected between kHz, there start-up delay before frequency selected. This because frequencies derived from HFINTOSC postscaler multiplexer. Start-up delay specifications located oscillator tables Section 17.0 "Electrical Specifications".
4.5.4
FREQUENCY SELECT BITS (IRCF)
output HFINTOSC LFINTOSC connects postscaler multiplexer (see Figure 4-1). Internal Oscillator Frequency Select bits IRCF<2:0> OSCCON register select frequency output internal oscillators. eight frequencies selected software: (Default after Reset) (LFINTOSC) Note: Following Reset, IRCF<2:0> bits OSCCON register `110' frequency selection MHz. user modify IRCF bits select different frequency.
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FIGURE 4-6: INTERNAL OSCILLATOR SWITCH TIMING
HFINTOSC HFINTOSC
LFINTOSC (FSCM disabled)
Start-up Time
2-cycle Sync
Running
LFINTOSC IRCF <2:0> System Clock
HFINTOSC HFINTOSC
LFINTOSC (Either FSCM enabled)
2-cycle Sync
Running
LFINTOSC IRCF <2:0> System Clock
LFINTOSC LFINTOSC
HFINTOSC
LFINTOSC turns unless FSCM enabled
Start-up Time
2-cycle Sync
Running
HFINTOSC IRCF <2:0> System Clock
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Clock Switching
system clock source switched between external internal clock sources software using System Clock Select (SCS) OSCCON register. When oscillator module configured modes, Oscillator Start-up Timer (OST) enabled (see Section 4.4.1 "Oscillator Start-up Timer (OST)"). will suspend program execution until 1024 oscillations counted. Two-Speed Start-up mode minimizes delay code execution operating from internal oscillator counting. When count reaches 1024 OSTS OSCCON register set, program execution switches external oscillator.
4.6.1
SYSTEM CLOCK SELECT (SCS)
System Clock Select (SCS) OSCCON register selects system clock source that used peripherals. When OSCCON register system clock source determined configuration FOSC<2:0> bits Configuration Word Register (CONFIG1). When OSCCON register system clock source chosen internal oscillator frequency selected IRCF<2:0> bits OSCCON register. After Reset, OSCCON register always cleared. Note: automatic clock switch, which occur from Two-Speed Start-up Fail-Safe Clock Monitor, does update OSCCON register. user monitor OSTS OSCCON register determine current system clock source.
4.7.1
TWO-SPEED START-UP MODE CONFIGURATION
Two-Speed Start-up mode configured following settings: IESO Configuration Word Register Internal/External Switchover (Two-Speed Startup mode enabled). OSCCON register) FOSC<2:0> bits Configuration Word Register (CONFIG1) configured mode. Two-Speed Start-up mode entered after: Power-on Reset (POR) and, enabled, after Power-up Timer (PWRT) expired, Wake-up from Sleep. external clock oscillator configured anything other than mode, then Twospeed Start-up disabled. This because external clock oscillator does require stabilization time after exit from Sleep.
4.6.2
OSCILLATOR START-UP TIME-OUT STATUS (OSTS)
Oscillator Start-up Time-out Status (OSTS) OSCCON register indicates whether system clock running from external clock source, defined FOSC<2:0> bits Configuration Word Register (CONFIG1), from internal clock source. particular, OSTS indicates that Oscillator Start-up Timer (OST) timed modes.
4.7.2
TWO-SPEED START-UP SEQUENCE
Two-Speed Clock Start-up Mode
Two-Speed Start-up mode provides additional power savings minimizing latency between external oscillator start-up code execution. applications that make heavy Sleep mode, Two-Speed Start-up will remove external oscillator start-up time from time spent awake reduce overall power consumption device. This mode allows application wake-up from Sleep, perform instructions using INTOSC clock source back Sleep without waiting primary oscillator become stable. Note: Executing SLEEP instruction will abort oscillator start-up time will cause OSTS OSCCON register remain clear.
Wake-up from Power-on Reset Sleep. Instructions begin execution internal oscillator frequency IRCF<2:0> bits OSCCON register. enabled count 1024 clock cycles. timed out, wait falling edge internal oscillator. OSTS set. System clock held until next falling edge clock (LP, mode). System clock switched external clock source.
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4.7.3 CHECKING TWO-SPEED CLOCK STATUS
Checking state OSTS OSCCON register will confirm microcontroller running from external clock source, defined FOSC<2:0> bits Configuration Word Register (CONFIG1), internal oscillator.
FIGURE 4-7:
TWO-SPEED START-UP
HFINTOSC TOST OSC1 1022 1023
OSC2 Program Counter
System Clock
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Fail-Safe Clock Monitor
4.8.3 FAIL-SAFE CONDITION CLEARING
Fail-Safe Clock Monitor (FSCM) allows device continue operating should external oscillator fail. FSCM detect oscillator failure time after Oscillator Start-up Timer (OST) expired. FSCM enabled setting FCMEN Configuration Word Register (CONFIG1). FSCM applicable external Oscillator modes (LP, RCIO). Fail-Safe condition cleared after Reset, executing SLEEP instruction toggling OSCCON register. When toggled, restarted. While running, device continues operate from INTOSC selected OSCCON. When times out, Fail-Safe condition cleared device will operating from external clock source. Fail-Safe condition must cleared before OSFIF flag cleared.
FIGURE 4-8:
FSCM BLOCK DIAGRAM
Clock Monitor Latch
4.8.4
RESET WAKE-UP FROM SLEEP
External Clock
LFINTOSC Oscillator (~32
FSCM designed detect oscillator failure after Oscillator Start-up Timer (OST) expired. used after waking from Sleep after type Reset. used with Clock modes that FSCM will active soon Reset wake-up completed. When FSCM enabled, Two-Speed Start-up also enabled. Therefore, device will always executing code while operating. Note:
Clock Failure Detected
Sample Clock
4.8.1
FAIL-SAFE DETECTION
FSCM module detects failed oscillator comparing external oscillator FSCM sample clock. sample clock generated dividing LFINTOSC Figure 4-8. Inside fail detector block latch. external clock sets latch each falling edge external clock. sample clock clears latch each rising edge sample clock. failure detected when entire halfcycle sample clock elapses before primary clock goes low.
wide range oscillator start-up times, Fail-Safe circuit active during oscillator start-up (i.e., after exiting Reset Sleep). After appropriate amount time, user should check OSTS OSCCON register verify oscillator start-up that system clock switchover successfully completed.
4.8.2
FAIL-SAFE OPERATION
When external clock fails, FSCM switches device clock internal clock source sets flag OSFIF PIR2 register. Setting this flag will generate interrupt OSFIE PIE2 register also set. device firmware then take steps mitigate problems that arise from failed clock. system clock will continue sourced from internal clock source until device firmware successfully restarts external oscillator switches back external operation. internal clock source chosen FSCM determined IRCF<2:0> bits OSCCON register. This allows internal oscillator configured before failure occurs.
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FIGURE 4-9:
Sample Clock System Clock Output Clock Monitor Output Failure Detected OSCFIF Oscillator Failure
FSCM TIMING DIAGRAM
Test Note:
Test
Test
system clock normally much higher frequency than sample clock. relative frequencies this example have been chosen clarity.
TABLE 4-2:
Name CONFIG1(2) OSCCON OSCTUNE PIE2 PIR2 Legend: Note
SUMMARY REGISTERS ASSOCIATED WITH CLOCK SOURCES
OSFIE OSFIF IRCF2 C2IE C2IF MCLRE IRCF1 C1IE C1IF PWRTE IRCF0 TUN4 EEIE EEIF WDTE OSTS TUN3 BCLIE BCLIF FOSC2 TUN2 ULPWUIE ULPWUIF FOSC1 TUN1 FOSC0 TUN0 CCP2IE CCP2IF Value POR, -110 x000 0000 0000 00-0 0000 00-0 Value other Resets(1) -110 x000 uuuu 0000 00-0 0000 00-0
unknown, unchanged, unimplemented locations read `0'. Shaded cells used oscillators. Other (non Power-up) Resets include MCLR Reset Watchdog Timer Reset during normal operation. Configuration Word Register (Register 14-1) operation register bits.
DS41291F-page
2009 Microchip Technology Inc.
PIC16F882/883/884/886/887
TIMER0 MODULE
Timer0 Operation
Timer0 module 8-bit timer/counter with following features: 8-bit timer/counter register (TMR0) 8-bit prescaler (shared with Watchdog Timer) Programmable internal external clock source Programmable external clock edge selection Interrupt overflow When used timer, Timer0 module used either 8-bit timer 8-bit counter.
5.1.1
8-BIT TIMER MODE
When used timer, Timer0 module will increment every instruction cycle (without prescaler). Timer mode selected clearing T0CS OPTION register `0'. When TMR0 written, increment inhibited instruction cycles immediately following write. Note: value written TMR0 register adjusted, order account instruction cycle delay when TMR0 written.
Figure block diagram Timer0 module.
5.1.2
8-BIT COUNTER MODE
When used counter, Timer0 module will increment every rising falling edge T0CKI pin. incrementing edge determined T0SE OPTION register. Counter mode selected setting T0CS OPTION register `1'.
FIGURE 5-1:
FOSC/4
TIMER0/WDT PRESCALER BLOCK DIAGRAM
Data T0CKI T0SE T0CS 8-bit Prescaler Flag T0IF Overflow Sync TMR0
WDTE SWDTEN
PS<2:0> 16-bit Prescaler INTOSC Watchdog Timer WDTPS<3:0>
Note T0SE, T0CS, PSA, PS<2:0> bits OPTION register. SWDTEN WDTPS<3:0> bits WDTCON register. WDTE Configuration Word Register1.
Time-out
2009 Microchip Technology In
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