64/80/100-Pin, 16-Bit, General Purpose Flash Microcontrollers with Per
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PIC24FJ256GA110 Family Data Sheet
64/80/100-Pin, 16-Bit, General Purpose Flash Microcontrollers with Peripheral Select
2009 Microchip Technology Inc.
DS39905C
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Trademarks Microchip name logo, Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC UNI/O registered trademarks Microchip Technology Incorporated U.S.A. other countries. FilterLab, Hampshire, HI-TECH Linear Active Thermistor, MXDEV, MXLAB, SEEVAL Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, Omniscient Code Generation, PICC, PICC-18, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2009, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
DS39905C-page
2009 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY
64/80/100-Pin, 16-Bit, General Purpose Flash Microcontrollers with Peripheral Select
Power Management:
On-Chip 2.5V Voltage Regulator Switch between Clock Sources Real Time Idle, Sleep Doze modes with Fast Wake-up Two-Speed Start-up mode: mA/MIPS, 2.0V Typical Standby Current with Oscillator: 2.0V Typical
Peripheral Features:
Peripheral Select: Allows independent mapping many peripherals time Continuous hardware integrity checking safety interlocks prevent unintentional configuration changes available pins (100-pin devices) Three 3-Wire/4-Wire modules (supports Frame modes) with 8-Level FIFO Buffer Three I2Cmodules support Multi-Master/Slave modes 7-Bit/10-Bit Addressing Four UART modules: Supports RS-485, RS-232, LIN/J2602 protocols IrDA® On-chip hardware encoder/decoder IrDA Auto-wake-up Auto-Baud Detect (ABD) 4-level deep FIFO buffer Five 16-Bit Timers/Counters with Programmable Prescaler Nine 16-Bit Capture Inputs, each with Dedicated Time Base Nine 16-Bit Compare/PWM Outputs, each with Dedicated Time Base 8-Bit Parallel Master Port (PMP/PSP): address pins Programmable polarity control lines Hardware Real-Time Clock/Calendar (RTCC): Provides clock, calendar alarm functions Programmable Cyclic Redundancy Check (CRC) Generator External Interrupt Sources
High-Performance CPU:
Modified Harvard Architecture MIPS Operation Internal Oscillator 17-Bit 17-Bit Single-Cycle Hardware Multiplier 32-Bit 16-Bit Hardware Divider 16-Bit Working Register Array Compiler Optimized Instruction Architecture with Flexible Addressing modes Linear Program Memory Addressing, Mbytes Linear Data Memory Addressing, Kbytes Address Generation Units Separate Read Write Addressing Data Memory
Analog Features:
10-Bit, 16-Channel Analog-to-Digital (A/D) Converter ksps: Conversions available Sleep mode Three Analog Comparators with Programmable Input/ Output Configuration Charge Time Measurement Unit (CTMU)
Program Memory (Bytes)
10-Bit (ch)
Remappable Peripherals SRAM (Bytes) UART IrDA® Capture Input Timers 16-Bit Compare/ Output Remappable Pins I2C
Comparators
PMP/PSP
128GA106 192GA106 256GA106 128GA108 192GA108 256GA108 128GA110 192GA110 256GA110
128K 192K 256K 128K 192K 256K 128K 192K 256K
PIC24FJ Device
2009 Microchip Technology Inc.
DS39905C-page
CTMU
JTAG
Pins
PIC24FJ256GA110 FAMILY
Special Microcontroller Features:
Operating Voltage Range 2.0V 3.6V Self-Reprogrammable under Software Control 5.5V Tolerant Input (digital pins only) Configurable Open-Drain Outputs Digital High-Current Sink/Source mA/18 Selectable Power Management modes: Sleep, Idle Doze modes with fast wake-up Fail-Safe Clock Monitor Operation: Detects clock failure switches on-chip oscillator On-Chip Regulator Power-on Reset (POR), Power-up Timer (PWRT), Low-Voltage Detect (LVD) Oscillator Start-up Timer (OST) Flexible Watchdog Timer (WDT) with On-Chip Low-Power Oscillator Reliable Operation In-Circuit Serial Programming(ICSPTM) In-Circuit Debug (ICD) Pins JTAG Boundary Scan Support Brown-out Reset (BOR) Flash Program Memory: 10,000 erase/write cycle endurance (minimum) 20-year data retention minimum Selectable write protection boundary Write protection option Flash Configuration Words
Diagram (64-Pin TQFP QFN(1))
RP25/CN13/PMWR/RD4 C3INB/CN15/RD6 RP20/CN14/PMRD/RD5 RP22/CN52/PMBE/RD3 RP23/CN51/RD2 RP24/CN50/RD1
VCAP/VDDCORE C3INA/CN16/RD7
CN62/PMD4/RE4
CN61/PMD3/RE3
CN60/PMD2/RE2 CN59/PMD1/RE1
CN58/PMD0/RE0 CN69/RF1
CN68/RF0
ENVREG
CN63/PMD5/RE5 SCL3/CN64/PMD6/RE6 SDA3/CN65/PMD7/RE7 PMA5/RP21/C1IND/CN8/RG6 C1INC/RP26/CN9/PMA4/RG7 C2IND/RP19/CN10/PMA3/RG8 MCLR C2INC/RP27/CN11/PMA2/RG9 PGEC3/AN5/C1INA/RP18/CN7/RB5 PGED3/AN4/C1INB/RP28/CN6/RB4 AN3/C2INA/CN5/RB3 AN2/C2INB/RP13/CN4/RB2 PGEC1/AN1/VREF-/RP1/CN3/RB1
SOSCO/C3INC/RPI37/CN0/RC14 SOSCI/C3IND/CN1/RC13 RP11/CN49/RD0 RP12/CN56/PMCS1/RD11 RP3/CN55/PMCS2/RD10 RP4/CN54/RD9 RTCC/RP2/CN53/RD8 OSCO/CLKO/CN22/RC15 OSCI/CLKI/CN23/RC12 SCL1/CN83/RG2 SDA1/CN84/RG3 ASCK1/RPI45/INT0/CN72/RF6 RP30/CN70/RF2 RP16/CN71/RF3
PIC24FJ128GA106 PIC24FJ192GA106 PIC24FJ256GA106
AVSS AN8/RP8/CN26/RB8
TDO/AN11/CN29/PMA12/RB11
AVDD
AN9/RP9/CN27/PMA7/RB9
AN14/CTPLS/RP14/CN32/PMA1/RB14
TMS/AN10/CVREF/CN28/PMA13/RB10
TCK/AN12/CTED2/CN30/PMA11/RB12
TDI/PMA10/AN13/CTED1/CN31/RB13
AN15/REFO/RP29/CN12/PMA0/RB15
PGEC2/AN6/RP6/CN24/RB6
PGED2/AN7/RP7/CN25/RB7
SDA2/RP10/CN17/PMA9/RF4
Legend: Note
Shaded pins indicate pins tolerant +5.5 VDC. represents remappable pins Peripheral Select feature. devices, backplane underside device must also connected VSS.
DS39905C-page
SCL2/RP17/CN18/PMA8/RF5
2009 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY
Diagram (80-Pin TQFP)
RP20/CN14/PMRD/RD5 RP25/CN13/PMWR/RD4 CN19/RD13 RPI42/CN57/RD12
RP22/CN52/PMBE/RD3 RP23/CN51/RD2 RP24/CN50/RD1
VCAP/VDDCORE C3INA/CN16/RD7 C3INB/CN15/RD6
CN62/PMD4/RE4 CN61/PMD3/RE3
CN60/PMD2/RE2
CN59/PMD1/RE1 CN58/PMD0/RE0 CN77/RG0 CN78/RG1 CN69/RF1 CN68/RF0
ENVREG
CN63/PMD5/RE5 SCL3/CN64/PMD6/RE6 SDA3/CN65/PMD7/RE7 RPI38/CN45/RC1 RPI40/CN47/RC3 C1IND/RP21/CN8/PMA5/RG6 C1INC/RP26/CN9/PMA4/RG7 C2IND/RP19/CN10/PMA3/RG8 MCLR C2INC/RP27/CN11/PMA2/RG9 TMS/RPI33/CN66/RE8 TDO/RPI34/CN67/RE9 PGEC3/AN5/C1INA/CN7/RP18/RB5 PGED3/AN4/C1INB/RP28/CN6/RB4 AN3/C2INA/CN5/RB3 AN2/C2INB/RP13/CN4/RB2 PGEC1/AN1/RP1/CN3/RB1 PGED1/AN0/RP0/CN2/RB0
SOSCO/C3INC/ RPI37/CN0/RC14 SOSCI/C3IND/CN1/RC13 RP11/CN49/RD0 RP12/CN56/PMCS1/RD11 RP3/CN55/PMCS2/RD10 RP4/CN54/RD9 RTCC/RP2/CN53/RD8 SDA2/RPI35/CN44/RA15 SCL2/RPI36/CN43/RA14 OSCO/CLKO/CN22/RC15 OSCI/CLKI/CN23/RC12 SCL1/CN83/RG2 SDA1/CN84/RG3 ASCK1/RPI45/INT0/CN72/RF6 RPI44/CN73/RF7 RP15/CN74/RF8 RP30/CN70/RF2 RP16/CN71/RF3
PIC24FJ128GA108 PIC24FJ192GA108 PIC24FJ256GA108
PMA12/AN11/CN29/RB11
TDI/AN13/CTED1/CN31/PMA10/RB13
TCK/AN12/CTED2/CN30/PMA11/RB12
AN14/CTPLS/RP14/CN32/PMA1/RB14
AN15/REFO/RP29/CN12/PMA0/RB15 RPI43/CN20/RD14
PMA7/VREF-/CN41/RA9
PMA6/VREF+/CN42/RA10
PMA13/AN10/CVREF/CN28/RB10
PGEC2/AN6/RP6/CN24/RB6
PGED2/RP7/AN7/CN25/RB7
AVSS RP8/AN8/CN26/RB8
RP9/AN9/CN27/RB9
RP5/CN21/RD15
AVDD
RP10/CN17/PMA9/RF4
Legend:
Shaded pins indicate pins tolerant +5.5 VDC. represents remappable pins Peripheral Select feature.
2009 Microchip Technology Inc.
RP17/CN18/PMA8/RF5
DS39905C-page
PIC24FJ256GA110 FAMILY
Diagram (100-Pin TQFP)
CN62/PMD4/RE4 CN61/PMD3/RE3 CN60/PMD2/RE2 CN80/RG13 CN79/RG12 CN81/RG14 CN59/PMD1/RE1 CN58/PMD0/RE0 CN40/RA7 CN39/RA6 CN77/RG0 CN78/RG1 CN69/RF1 CN68/RF0 ENVREG VCAP/VDDCORE C3INA/CN16/RD7 C3INB/CN15/RD6 RP20/CN14/PMRD/RD5 RP25/CN13/PMWR/RD4 CN19/RD13 RPI42/CN57/RD12 RP22/CN52/PMBE/RD3 RP23/CN51/RD2 RP24/CN50/RD1
CN82/RG15 CN63/PMD5/RE5 SCL3/CN64/PMD6/RE6 SDA3/CN65/PMD7/RE7 RPI38/CN45/RC1 RPI39/CN46/RC2 RPI40/CN47/RC3 RPI41/CN48/RC4 C1IND/RP21/CN8/PMA5/RG6 C1INC/RP26/CN9/PMA4/RG7 C2IND/RP19/CN10/PMA3/RG8 MCLR C2INC/RP27/CN11/PMA2/RG9 TMS/CN33/RA0 RPI33/CN66/RE8 RPI34/CN67/RE9 PGEC3/AN5/C1INA/RP18/CN7/RB5 PGED3/AN4/C1INB/RP28/CN6/RB4 AN3/C2INA/CN5/RB3 AN2/C2INB/RP13/CN4/RB2 PGEC1/AN1/RP1/CN3/RB1 PGED1/AN0/RP0/CN2/RB0
SOSCO/C3INC/ RPI37/CN0/RC14 SOSCI/C3IND/CN1/RC13 RP11/CN49/RD0 RP12/CN56/PMCS1/RD11 RP3/CN55/PMCS2/RD10 RP4/CN54/RD9 RTCC/RP2/CN53/RD8 ASDA2/RPI35/CN44/RA15 ASCL2/RPI36/CN43/RA14 OSCO/CLKO/CN22/RC15 OSCI/CLKI/CN23/RC12 TDO/CN38/RA5 TDI/CN37/RA4 SDA2/CN36/RA3 SCL2/CN35/RA2 SCL1/CN83/RG2 SDA1/CN84/RG3 ASCK1/RPI45/INT0/CN72/RF6 RPI44/CN73/RF7 RP15/CN74/RF8 RP30/CN70/RF2 RP16/CN71/RF3
PIC24FJ128GA110 PIC24FJ192GA110 PIC24FJ256GA110
Legend:
Shaded pins indicate pins tolerant +5.5 VDC. represents remappable pins Peripheral Select feature.
PGEC2/AN6/RP6/CN24/RB6 PGED2/AN7/RP7/CN25/RB7 VREF-/CN41/PMA7/RA9 PMA6/VREF+/CN42/RA10 AVDD AVSS AN8/RP8/CN26/RB8 AN9/RP9/CN27/RB9 AN10/CVREF/CN28/PMA13/RB10 AN11/CN29/PMA12/RB11 TCK/CN34/RA1 RP31/CN76/RF13 RPI32/CN75/RF12 AN12/CTED2/CN30/PMA11/RB12 AN13/CTED1/CN31/PMA10/RB13 AN14/CTPLS/RP14/CN32/PMA1/RB14 AN15/REFO/RP29/CN12/PMA0/RB15
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RPI43/CN20/RD14 RP5/CN21/RD15 RP10/CN17/PMA9/RF4 RP17/CN18/PMA8/RF5
2009 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY
Table Contents
Device Overview Guidelines Getting Started with 16-bit Microcontrollers Memory Organization Flash Program Memory. Resets Interrupt Controller Oscillator Configuration Power-Saving Features. 10.0 Ports 11.0 Timer1 12.0 Timer2/3 Timer4/5 13.0 Input Capture with Dedicated Timer. 14.0 Output Compare with Dedicated Timer 15.0 Serial Peripheral Interface (SPI). 16.0 Inter-Integrated Circuit (I2CTM) 17.0 Universal Asynchronous Receiver Transmitter (UART) 18.0 Parallel Master Port (PMP). 19.0 Real-Time Clock Calendar (RTCC) 20.0 Programmable Cyclic Redundancy Check (CRC) Generator 21.0 10-Bit High-Speed Converter 22.0 Triple Comparator Module. 23.0 Comparator Voltage Reference. 24.0 Charge Time Measurement Unit (CTMU) 25.0 Special Features 26.0 Development Support. 27.0 Instruction Summary 28.0 Electrical Characteristics 29.0 Packaging Information. Appendix Revision History. Index Microchip Site Customer Change Notification Service Customer Support Reader Response Product Identification System
2009 Microchip Technology Inc.
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PIC24FJ256GA110 FAMILY
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Most Current Data Sheet
obtain most up-to-date version this data sheet, please register Worldwide site http://www.microchip.com determine version data sheet examining literature number found bottom outside corner page. last character literature number version number, (e.g., DS30000A version document DS30000).
Errata
errata sheet, describing minor operational differences from data sheet recommended workarounds, exist current devices. device/documentation issues become known will publish errata sheet. errata will specify revision silicon revision document which applies. determine errata sheet exists particular device, please check with following: Microchip's Worldwide site; http://www.microchip.com Your local Microchip sales office (see last page) When contacting sales office, please specify which device, revision silicon data sheet (include literature number) using.
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DS39905C-page
2009 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY
DEVICE OVERVIEW
This document contains device-specific information following devices: PIC24FJ128GA106 PIC24FJ192GA106 PIC24FJ256GA106 PIC24FJ128GA108 PIC24FJ192GA108 PIC24FJ256GA108 This family expands existing line Microchip`s 16-bit general purpose microcontrollers, combining enhanced computational performance with expanded highly configurable peripheral feature set. PIC24FJ256GA110 family provides platform high-performance applications, which have outgrown their 8-bit platforms, don't require power digital signal processor. PIC24FJ128GA110 PIC24FJ192GA110 PIC24FJ256GA110 Doze Mode Operation: When timing-sensitive applications, such serial communications, require uninterrupted operation peripherals, clock speed selectively reduced, allowing incremental power savings without missing beat. Instruction-Based Power-Saving Modes: microcontroller suspend operations, selectively shut down core while leaving peripherals active, with single instruction software.
1.1.3
OSCILLATOR OPTIONS FEATURES
devices PIC24FJ256GA110 family offer five different oscillator options, allowing users range choices developing application hardware. These include: Crystal modes using crystals ceramic resonators. External Clock modes offering option divide-by-2 clock output. Fast Internal Oscillator (FRC) with nominal output, which also divided under software control provide clock speeds kHz. Phase Lock Loop (PLL) frequency multiplier available external oscillator modes Oscillator, which allows clock speeds MHz. separate internal Oscillator (LPRC) with fixed output, which provides low-power option timing-insensitive applications. internal oscillator block also provides stable reference source Fail-Safe Clock Monitor. This option constantly monitors main clock source against reference signal provided internal oscillator enables controller switch internal oscillator, allowing continued low-speed operation safe application shutdown.
1.1.1
Core Features
16-BIT ARCHITECTURE
Central PIC24F devices 16-bit modified Harvard architecture, first introduced with Microchip's dsPIC® digital signal controllers. PIC24F core offers wide range enhancements, such 16-bit data 24-bit address paths with ability move information between data memory spaces Linear addressing Mbytes (program space) Kbytes (data) 16-element working register array with built-in software stack support hardware multiplier with support integer math Hardware support 16-bit division instruction that supports multiple addressing modes optimized high-level languages, such Operational performance MIPS
1.1.4
EASY MIGRATION
1.1.2
POWER-SAVING TECHNOLOGY
devices PIC24FJ256GA110 family incorporate range features that significantly reduce power consumption during operation. items include: On-the-Fly Clock Switching: device clock changed under software control Timer1 source internal, low-power Oscillator during operation, allowing user incorporate power-saving ideas into their software designs.
Regardless memory size, devices share same rich peripherals, allowing smooth migration path applications grow evolve. consistent pinout scheme used throughout entire family also aids migrating from device next larger, even jumping from 64-pin 100-pin devices. PIC24F family pin-compatible with devices dsPIC33 PIC32 families, shares some compatibility with pinout schema PIC18 dsPIC30 devices. This extends ability applications grow from relatively simple, powerful complex, still selecting Microchip device.
2009 Microchip Technology Inc.
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PIC24FJ256GA110 FAMILY
Other Special Features
Peripheral Select: Peripheral Select feature allows most digital peripherals mapped over fixed digital pins. Users independently input and/or output many digital peripherals pins. Communications: PIC24FJ256GA110 family incorporates range serial communication peripherals handle range application requirements. There three independent I2Cmodules that support both Master Slave modes operation. Devices also have, through Peripheral Select (PPS) feature, four independent UARTs with built-in IrDA® encoder/decoders three modules. Analog Features: members PIC24FJ256GA110 family include 10-bit Converter module triple comparator module. module incorporates programmable acquisition time, allowing channel selected conversion initiated without waiting sampling period, well faster sampling speeds. comparator module includes three analog comparators that configurable wide range operations. CTMU Interface: addition their other analog features, members PIC24FJ256GA110 family include brand CTMU interface module. This provides convenient method precision time measurement pulse generation, serve interface capacitive sensors. Parallel Master Port: general purpose ports reconfigured enhanced parallel data communications. this mode, port configured both master slave operations, supports 8-bit transfers with external address lines Master modes. Real-Time Clock/Calendar: This module implements full-featured clock calendar with alarm functions hardware, freeing timer resources program memory space core application.
Details Individual Family Members
Devices PIC24FJ256GA110 family available 64-pin, 80-pin 100-pin packages. general block diagram devices shown Figure 1-1. devices differentiated from each other four ways: Flash program memory (128 Kbytes PIC24FJ128GA1 devices, Kbytes PIC24FJ192GA1 devices Kbytes PIC24FJ256GA1 devices). Available pins ports pins ports 64-pin devices, pins ports 80-pin devices pins ports 100-pin devices). Available Interrupt-on-Change Notification (ICN) inputs (same number available pins devices). Available remappable pins pins 64-pin devices, pins 80-pin devices pins 100-pin devices)
other features devices this family identical. These summarized Table 1-1. list features available PIC24FJ256GA110 family devices, sorted function, shown Table 1-4. Note that this table shows location individual peripheral features they multiplexed same pin. This information provided pinout diagrams beginning this data sheet. Multiplexed features sorted priority given feature, with highest priority peripheral being listed first.
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TABLE 1-1: DEVICE FEATURES PIC24FJ256GA110 FAMILY: 64-PIN DEVICES
Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) Ports Total Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART (3-wire/4-wire) I2CParallel Communications (PMP/PSP) JTAG Boundary Scan/Programming 10-Bit Analog-to-Digital Module (input channels) Analog Comparators CTMU Interface Resets (and delays) 4(1) 3(1) POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, Lock) Base Instructions, Multiple Addressing Mode Variations 64-Pin TQFP Peripherals accessible through remappable pins. 5(1) 9(1) 9(1) 128K 44,032 PIC24FJ128GA106 PIC24FJ192GA106 192K 67,072 16,384 (62/4) Ports I/O, input only) 256K 87,552 PIC24FJ256GA106
Instruction Packages Note
2009 Microchip Technology Inc.
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PIC24FJ256GA110 FAMILY
TABLE 1-2: DEVICE FEATURES PIC24FJ256GA110 FAMILY: 80-PIN DEVICES
Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) Ports Total Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART (3-wire/4-wire) I2CParallel Communications (PMP/PSP) JTAG Boundary Scan/Programming 10-Bit Analog-to-Digital Module (input channels) Analog Comparators CTMU Interface Resets (and delays) 4(1) 3(1) POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, Lock) Base Instructions, Multiple Addressing Mode Variations 80-Pin TQFP Peripherals accessible through remappable pins. 5(1) 9(1) 9(1) 128K 44,032 PIC24FJ128GA108 PIC24FJ192GA108 192K 67,072 16,384 (62/4) Ports I/O, input only) 256K 87,552 PIC24FJ256GA108
Instruction Packages Note
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TABLE 1-3: DEVICE FEATURES PIC24FJ256GA110 FAMILY: 100-PIN DEVICES
Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) Ports Total Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART (3-wire/4-wire) I2CParallel Communications (PMP/PSP) JTAG Boundary Scan/Programming 10-Bit Analog-to-Digital Module (input channels) Analog Comparators CTMU Interface Resets (and delays) 4(1) 3(1) POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, Lock) Base Instructions, Multiple Addressing Mode Variations 100-Pin TQFP Peripherals accessible through remappable pins. 5(1) 9(1) 9(1) 128K 44,032 PIC24FJ128GA110 PIC24FJ192GA110 192K 67,072 16,384 (62/4) Ports I/O, input only) 256K 87,552 PIC24FJ256GA110
Instruction Packages Note
2009 Microchip Technology Inc.
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PIC24FJ256GA110 FAMILY
FIGURE 1-1: PIC24FJ256GA110 FAMILY GENERAL BLOCK DIAGRAM
Data
Table Data Access Control Block Data Latch Program Counter Repeat Stack Control Control Logic Logic Data Address Latch Read Write PORTB I/O) PORTA(1) I/O)
Interrupt Controller
Address Latch Program Memory Data Latch
PORTC(1) I/O)
Address
Inst Latch Inst Register Instruction Decode Control OSCO/CLKO OSCI/CLKI Timing Generation FRC/LPRC Oscillators Precision Band Reference ENVREG Voltage Regulator Control Signals Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer LVD(2) Literal Data
PORTD(1) I/O)
PORTE(1) Divide Support 17x17 Multiplier Array I/O)
REFO
16-Bit
PORTF(1) I/O)
PORTG(1) I/O)
VDDCORE/VCAP
VDD,
MCLR
Timer1
Timer2/3(3)
Timer4/5(3)
RTCC
10-Bit
Comparators(3)
PMP/PSP PWM/OC 1-9(3) 1/2/3(3)
1-9(3) Note
ICNs(1)
1/2/3
UART 1/2/3/4(3)
CTMU
pins features implemented device pinout configurations. Table specific implementations count. functionality provided when on-board voltage regulator enabled. These peripheral I/Os only accessible through remappable pins.
DS39905C-page
2009 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY
TABLE 1-4:
Function
PIC24FJ256GA110 FAMILY PINOUT DESCRIPTIONS
Number 80-Pin TQFP 100-Pin TQFP Input Buffer
64-Pin TQFP,
Description
AN10 AN11 AN12 AN13 AN14 AN15 ASCL2 ASDA2 AVDD AVSS C1INA C1INB C1INC C1IND C2INA C2INB C2INC C2IND C3INA C3INB C3INC C3IND CLKI CLKO Legend:
Analog Inputs.
Alternate I2C2 Synchronous Serial Clock Input/Output. Alternate I2C2 Data Input/Output. Positive Supply Analog modules. Ground Reference Analog modules. Comparator Input Comparator Input Comparator Input Comparator Input Comparator Input Comparator Input Comparator Input Comparator Input Comparator Input Comparator Input Comparator Input Comparator Input Main Clock Input Connection. System Clock Output.
input buffer Analog level input/output
Schmitt Trigger input buffer I2C= I2C/SMBus input buffer
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TABLE 1-4:
Function
PIC24FJ256GA110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number 80-Pin TQFP 100-Pin TQFP Input Buffer Schmitt Trigger input buffer I2C= I2C/SMBus input buffer Description
64-Pin TQFP,
CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 CN18 CN19 CN20 CN21 CN22 CN23 CN24 CN25 CN26 CN27 CN28 CN29 CN30 CN31 CN32 CN33 CN34 CN35 CN36 CN37 CN38 CN39 CN40 CN41 CN42 Legend:
Interrupt-on-Change Inputs.
input buffer Analog level input/output
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TABLE 1-4:
Function
PIC24FJ256GA110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number 80-Pin TQFP 100-Pin TQFP Input Buffer Schmitt Trigger input buffer I2C= I2C/SMBus input buffer Description
64-Pin TQFP,
CN43 CN44 CN45 CN46 CN47 CN48 CN49 CN50 CN51 CN52 CN53 CN54 CN55 CN56 CN57 CN58 CN59 CN60 CN61 CN62 CN63 CN64 CN65 CN66 CN67 CN68 CN69 CN70 CN71 CN72 CN73 CN74 CN75 CN76 CN77 CN78 CN79 CN80 CN81 CN82 CN83 CN84 Legend:
Interrupt-on-Change Inputs.
input buffer Analog level input/output
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TABLE 1-4:
Function
PIC24FJ256GA110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number 80-Pin TQFP 100-Pin TQFP Input Buffer ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL Parallel Master Port Read Strobe. Parallel Master Port Write Strobe. Parallel Master Port Chip Select Strobe/Address Parallel Master Port Chip Select Strobe/Address Parallel Master Port Byte Enable Strobe. Parallel Master Port Data (Demultiplexed Master mode) Address/Data (Multiplexed Master modes). Description
64-Pin TQFP,
CTED1 CTED2 CTPLS CVREF ENVREG INT0 MCLR OSCI OSCO PGEC1 PGED1 PGEC2 PGED2 PGEC3 PGED3 PMA0 PMA1 PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMCS1 PMCS2 PMBE PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMRD PMWR Legend:
CTMU External Edge Input CTMU External Edge Input CTMU Pulse Output. Comparator Voltage Reference Output. Voltage Regulator Enable. External Interrupt Input. Master Clear (device Reset) Input. This line brought cause Reset. Main Oscillator Input Connection. Main Oscillator Output Connection. In-Circuit Clock. In-Circuit Debugger/Emulator/ICSP Programming Data. In-Circuit Debugger/Emulator/ICSP Programming Clock. In-Circuit Debugger/Emulator/ICSP Programming Data. In-Circuit Debugger/Emulator/ICSP Programming Clock. In-Circuit Debugger/Emulator/ICSP Programming Data. Parallel Master Port Address Input (Buffered Slave modes) Output (Master modes). Parallel Master Port Address Input (Buffered Slave modes) Output (Master modes). Parallel Master Port Address (Demultiplexed Master modes).
input buffer Analog level input/output
Schmitt Trigger input buffer I2C= I2C/SMBus input buffer
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TABLE 1-4:
Function
PIC24FJ256GA110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number 80-Pin TQFP 100-Pin TQFP Input Buffer Schmitt Trigger input buffer I2C= I2C/SMBus input buffer PORTC Digital I/O. PORTB Digital I/O. PORTA Digital I/O. Description
64-Pin TQFP,
RA10 RA14 RA15 RB10 RB11 RB12 RB13 RB14 RB15 RC12 RC13 RC14 RC15 Legend:
input buffer Analog level input/output
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TABLE 1-4:
Function
PIC24FJ256GA110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number 80-Pin TQFP 100-Pin TQFP Input Buffer Schmitt Trigger input buffer I2C= I2C/SMBus input buffer Reference Clock Output. PORTF Digital I/O. PORTE Digital I/O. PORTD Digital I/O. Description
64-Pin TQFP,
RD10 RD11 RD12 RD13 RD14 RD15 REFO RF12 RF13 Legend:
input buffer Analog level input/output
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TABLE 1-4:
Function
PIC24FJ256GA110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number 80-Pin TQFP 100-Pin TQFP Input Buffer Schmitt Trigger input buffer I2C= I2C/SMBus input buffer Remappable Peripheral (input output). PORTG Digital I/O. Description
64-Pin TQFP,
RG12 RG13 RG14 RG15 RP10 RP11 RP12 RP13 RP14 RP15 RP16 RP17 RP18 RP19 RP20 RP21 RP22 RP23 RP24 RP25 RP26 RP27 RP28 RP29 RP30 RP31 Legend:
input buffer Analog level input/output
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TABLE 1-4:
Function
PIC24FJ256GA110 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number 80-Pin TQFP 100-Pin TQFP Input Buffer
64-Pin TQFP,
Description
RPI32 RPI33 RPI34 RPI35 RPI36 RPI37 RPI38 RPI39 RPI40 RPI41 RPI42 RPI43 RPI44 RPI45 RTCC SCL1 SCL2 SCL3 SDA1 SDA2 SDA3 SOSCI SOSCO VCAP VDDCORE VREFVREF+ Legend:
Remappable Peripheral (input only).
Real-Time Clock Alarm/Seconds Pulse Output. I2C1 Synchronous Serial Clock Input/Output. I2C2 Synchronous Serial Clock Input/Output. I2C3 Synchronous Serial Clock Input/Output. I2C1 Data Input/Output. I2C2 Data Input/Output. I2C3 Data Input/Output. Secondary Oscillator/Timer1 Clock Input. Secondary Oscillator/Timer1 Clock Output. JTAG Test Clock/Programming Clock Input. JTAG Test Data/Programming Data Input. JTAG Test Data Output. JTAG Test Mode Select Input. External Filter Capacitor Connection (regulator enabled). Positive Supply Peripheral Digital Logic Pins. Positive Supply Microcontroller Core Logic (regulator disabled). Comparator Reference Voltage (low) Input. Comparator Reference Voltage (high) Input. Ground Reference Logic Pins.
input buffer Analog level input/output
Schmitt Trigger input buffer I2C= I2C/SMBus input buffer
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GUIDELINES GETTING STARTED WITH 16-BIT MICROCONTROLLERS
Basic Connection Requirements
FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS
C2(2)
MCLR
Getting started with PIC18F45J10 family 16-bit microcontrollers requires attention minimal device connections before proceeding with development. following pins must always connected: pins (see Section "Power Supply Pins") AVDD AVSS pins, regardless whether analog device features used (see Section "Power Supply Pins") MCLR (see Section "Master Clear (MCLR) Pin") ENVREG/DISVREG VCAP/VDDCORE pins (PIC24FJ devices only) (see Section "Voltage Regulator Pins (ENVREG/DISVREG VCAP/VDDCORE)") These pins must also connected they being used application: PGECx/PGEDx pins used In-Circuit Serial Programming(ICSPTM) debugging purposes (see Section "ICSP Pins") OSCI OSCO pins when external oscillator source used (see Section "External Oscillator Pins") Additionally, following pins required: VREF+/VREF- pins used when external voltage reference analog modules implemented Note: AVDD AVSS pins must always connected, regardless whether analog modules being used.
(EN/DIS)VREG VCAP/VDDCORE
PIC24FXXXX
C6(2)
AVDD AVSS
C3(2)
C5(2)
C4(2)
(all values recommendations): through ceramic tantalum ceramic Note Section "Voltage Regulator Pins (ENVREG/DISVREG VCAP/VDDCORE)" explanation ENVREG/DISVREG connections. example shown PIC24F device with five VDD/VSS AVDD/AVSS pairs. Other devices have more less pairs; adjust number decoupling capacitors appropriately.
minimum mandatory connections shown Figure 2-1.
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2.2.1
Power Supply Pins
DECOUPLING CAPACITORS
Master Clear (MCLR)
decoupling capacitors every pair power supply pins, such VDD, VSS, AVDD AVSS, required. Consider following criteria when using decoupling capacitors: Value type capacitor: (100 nF), 10-20V capacitor recommended. capacitor should low-ESR device with resonance frequency range higher. Ceramic capacitors recommended. Placement printed circuit board: decoupling capacitors should placed close pins possible. recommended place capacitors same side board device. space constricted, capacitor placed another layer using via; however, ensure that trace length from capacitor greater than 0.25 inch mm). Handling high-frequency noise: board experiencing high-frequency noise (upward tens MHz), second ceramic type capacitor parallel above described decoupling capacitor. value second capacitor range 0.01 0.001 Place this second capacitor next each primary decoupling capacitor. high-speed circuit designs, consider implementing decade pair capacitances close power ground pins possible (e.g., parallel with 0.001 Maximizing performance: board layout from power supply circuit, power return traces decoupling capacitors first, then device pins. This ensures that decoupling capacitors first power chain. Equally important keep trace length between capacitor power pins minimum, thereby reducing trace inductance.
MCLR provides specific device functions: device Reset, device programming debugging. programming debugging required application, direct connection that required. addition other components, help increase application's resistance spurious Resets from voltage sags, beneficial. typical configuration shown Figure 2-1. Other circuit designs implemented, depending application's requirements. During programming debugging, resistance capacitance that added must considered. Device programmers debuggers drive MCLR pin. Consequently, specific voltage levels (VIH VIL) fast signal transitions must adversely affected. Therefore, specific values will need adjusted based application requirements. example, recommended that capacitor, isolated from MCLR during programming debugging operations using jumper (Figure 2-2). jumper replaced normal run-time operations. components associated with MCLR should placed within 0.25 inch pin.
FIGURE 2-2:
EXAMPLE MCLR CONNECTIONS
MCLR PIC24FXXXX
2.2.2
TANK CAPACITORS
Note
boards with power traces running longer than inches length, suggested tank capacitor integrated circuits, including microcontrollers, supply local power source. value tank capacitor should determined based trace resistance that connects power supply source device, maximum current drawn device application. other words, select tank capacitor that meets acceptable voltage device. Typical values range from
recommended. suggested starting value Ensure that MCLR specifications met. will limit current flowing into MCLR from external capacitor, event MCLR breakdown, Electrostatic Discharge (ESD) Electrical Overstress (EOS). Ensure that MCLR specifications met.
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Voltage Regulator Pins (ENVREG/DISVREG VCAP/VDDCORE)
This section applies only PIC24FJ devices with on-chip voltage regulator.
ICSP Pins
Note:
on-chip voltage regulator enable/disable (ENVREG DISVREG, depending device family) must always connected directly either supply voltage ground. particular connection determined whether regulator used: ENVREG, enable regulator ground disable regulator DISVREG, ground enable regulator disable regulator Refer Section 25.2 "On-Chip Voltage Regulator" details connecting using on-chip regulator. When regulator enabled, low-ESR (<5) capacitor required VCAP/VDDCORE stabilize voltage regulator output voltage. VCAP/VDDCORE must connected VDD, must capacitor connected ground. type ceramic tantalum. placement this capacitor should close VCAP/VDDCORE. recommended that trace length exceed 0.25 inch mm). Refer Section 28.0 "Electrical Characteristics" additional information. When regulator disabled, VCAP/VDDCORE must tied voltage supply VDDCORE level. Refer Section 28.0 "Electrical Characteristics" information VDDCORE.
PGECx PGEDx pins used In-Circuit Serial Programming (ICSP) debugging purposes. recommended keep trace length between ICSP connector ICSP pins device short possible. ICSP connector expected experience event, series resistor recommended, with value range tens ohms, exceed 100. Pull-up resistors, series diodes capacitors PGECx PGEDx pins recommended they will interfere with programmer/debugger communications device. such discrete components application requirement, they should removed from circuit during programming debugging. Alternatively, refer AC/DC characteristics timing requirements information respective device Flash programming specification information capacitive loading limits input voltage high (VIH) input (VIL) requirements. device emulation, ensure that "Communication Channel Select" (i.e., PGECx/PGEDx pins) programmed into device matches physical connections ICSP MPLAB® MPLAB® REAL ICEemulator. more information REAL emulator connection requirements, refer following documents that available Microchip site. "MPLAB® In-Circuit Debugger User's Guide" (DS51331) "Using MPLAB® (poster) (DS51265) "MPLAB® Design Advisory" (DS51566) "Using MPLAB® (poster) (DS51765) "MPLAB® Design Advisory" (DS51764) "MPLAB® REAL ICEIn-Circuit Emulator User's Guide" (DS51616) "Using MPLAB® REAL ICEIn-Circuit Emulator" (poster) (DS51749)
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External Oscillator Pins
Many microcontrollers have options least oscillators: high-frequency Primary Oscillator low-frequency Secondary Oscillator (refer Section "Oscillator Configuration" details). oscillator circuit should placed same side board device. Place oscillator circuit close respective oscillator pins, with more than inch between circuit components pins. load capacitors should placed next oscillator itself, same side board. grounded copper pour around oscillator circuit isolate from surrounding circuits. grounded copper pour should routed directly ground. signal traces power traces inside ground pour. Also, using two-sided board, avoid traces other side board where crystal placed. suggested layout shown Figure 2-3. additional information design guidance oscillator circuits, please refer these Microchip Application Notes, available corporate site (www.microchip.com): AN826, "Crystal Oscillator Basics Crystal Selection rfPICand PICmicro® Devices" AN849, "Basic PICmicro® Oscillator Design" AN943, "Practical PICmicro® Oscillator Analysis Design" AN949, "Making Your Oscillator Work"
Configuration Analog Digital Pins During ICSP Operations
MPLAB REAL emulator selected debugger, automatically initializes input pins (ANx) "digital" pins, setting bits AD1PCFGL register. bits this register that correspond pins that initialized MPLAB REAL emulator, must cleared user application firmware; otherwise, communication errors will result between debugger device. your application needs certain pins analog input pins during debug session, user application must clear corresponding bits AD1PCFGL register during initialization module. When MPLAB REAL emulator used programmer, user application firmware must correctly configure AD1PCFGL register. Automatic initialization this register only done during debugger operation. Failure correctly configure register(s) will result pins being recognized analog input pins, resulting port value being read logic `0', which affect user application functionality.
Unused I/Os
FIGURE 2-3:
SUGGESTED PLACEMENT OSCILLATOR CIRCUIT
Unused pins should configured outputs driven logic state. Alternatively, connect resistor unused pins drive output logic low.
Main Oscillator Guard Ring Guard Trace Secondary Oscillator
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Note:
This data sheet summarizes features this group PIC24F devices. intended comprehensive reference source. more information, refer "PIC24F Family Reference Manual", Section "CPU" (DS39703).
most instructions, core capable executing data program data) memory read, working register (data) read, data memory write program (instruction) memory read instruction cycle. result, three parameter instructions supported, allowing trinary operations (that executed single cycle. high-speed, 17-bit 17-bit multiplier been included significantly enhance core arithmetic capability throughput. multiplier supports Signed, Unsigned Mixed mode, 16-bit 16-bit 8-bit 8-bit integer multiplication. multiply instructions execute single cycle. 16-bit been enhanced with integer divide assist hardware that supports iterative non-restoring divide algorithm. operates conjunction with REPEAT instruction looping mechanism selection iterative divide instructions support 32-bit 16-bit), divided 16-bit, integer signed unsigned division. divide operations require cycles complete, interruptible cycle boundary. PIC24F vectored exception scheme with sources non-maskable traps interrupt sources. Each interrupt source assigned seven priority levels. block diagram shown Figure 3-1.
PIC24F 16-bit (data), modified Harvard architecture with enhanced instruction 24-bit instruction word with variable length opcode field. Program Counter (PC) bits wide addresses instructions user program memory space. single-cycle instruction prefetch mechanism used help maintain throughput provides predictable execution. instructions execute single cycle, with exception instructions that change program flow, double-word move (MOV.D) instruction table instructions. Overhead-free program loop constructs supported using REPEAT instructions, which interruptible point. PIC24F devices have sixteen, 16-bit working registers programmer's model. Each working registers data, address address offset register. 16th working register (W15) operates Software Stack Pointer interrupts calls. upper Kbytes data space memory optionally mapped into program space word boundary defined 8-bit Program Space Visibility Page Address (PSVPAG) register. program data space mapping feature lets instruction access program space were data space. Instruction Architecture (ISA) been significantly enhanced beyond that PIC18, maintains acceptable level backward compatibility. PIC18 instructions addressing modes supported either directly through simple macros. Many enhancements have been driven compiler efficiency needs. core supports Inherent operand), Relative, Literal, Memory Direct three groups addressing modes. modes support Register Direct various Register Indirect modes. Each group offers seven addressing modes. Instructions associated with predefined addressing modes depending upon their functional requirements.
Programmer's Model
programmer's model PIC24F shown Figure 3-2. registers programmer's model memory mapped manipulated directly instructions. description each register provided Table 3-1. registers associated with programmer's model memory mapped.
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FIGURE 3-1:
Table Data Access Control Block Interrupt Controller Program Counter Loop Stack Control Control Logic Logic Data Address Latch RAGU WAGU Data Data Latch
PIC24F CORE BLOCK DIAGRAM
Address Latch
Program Memory Address Data Latch Latch Literal Data
Instruction Decode Control
Instruction
Control Signals Various Blocks
Hardware Multiplier Divide Support
Register Array
16-Bit
Peripheral Modules
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TABLE 3-1:
through SPLIM TBLPAG PSVPAG RCOUNT CORCON
CORE REGISTERS
Description Working Register Array 23-Bit Program Counter STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register Control Register
Register(s) Name
FIGURE 3-2:
PROGRAMMER'S MODEL
(WREG) Frame Pointer Stack Pointer Stack Pointer Limit Value Register Program Counter Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register Working/Address Registers
Divider Working Registers
Multiplier Registers
SPLIM TBLPAG PSVPAG RCOUNT
STATUS Register (SR)
Control Register (CORCON)
IPL3
Registers bits shadowed PUSH.S POP.S instructions.
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Control Registers
STATUS REGISTER
R/W-0 R/W-0(1) IPL1
REGISTER 3-1:
R/W-0(1) IPL2 Legend: Readable Value 15-9
R/W-0(1) IPL0(2)
R/W-0
R/W-0
R/W-0
R/W-0
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read Half Carry/Borrow carry-out from low-order (for byte-sized data) low-order (for word-sized data) result occurred carry-out from low-order result occurred IPL<2:0>: Interrupt Priority Level Status bits(1,2) interrupt priority level (15); user interrupts disabled interrupt priority level (14) interrupt priority level (13) interrupt priority level (12) interrupt priority level (11) interrupt priority level (10) interrupt priority level interrupt priority level REPEAT Loop Active REPEAT loop progress REPEAT loop progress Negative Result negative Result non-negative (zero positive) Overflow Overflow occurred signed (2's complement) arithmetic this arithmetic operation overflow occurred Zero operation which effects some time past most recent operation which effects cleared (i.e., non-zero result) Carry/Borrow carry-out from Most Significant result occurred carry-out from Most Significant result occurred Status bits read-only when NSTDIS (INTCON1<15>) Status bits concatenated with IPL3 (CORCON<3>) form Interrupt Priority Level (IPL). value parentheses indicates when IPL3
Note
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REGISTER 3-2:
Legend: Readable Value 15-4 Clearable Writable Unimplemented bit, read cleared unknown R/C-0 IPL3
CORCON: CONTROL REGISTER
R/W-0
Unimplemented: Read IPL3: Interrupt Priority Level Status bit(1) interrupt priority level greater than interrupt priority level less PSV: Program Space Visibility Data Space Enable Program space visible data space Program space visible data space Unimplemented: Read User interrupts disabled when IPL3
Note
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Arithmetic Logic Unit (ALU)
3.3.2 DIVIDER
PIC24F bits wide capable addition, subtraction, shifts logic operations. Unless otherwise mentioned, arithmetic operations complement nature. Depending operation, affect values Carry (C), Zero (Z), Negative (N), Overflow (OV) Digit Carry (DC) Status bits register. Status bits operate Borrow Digit Borrow bits, respectively, subtraction operations. perform 8-bit 16-bit operations, depending mode instruction that used. Data operation come from register array, data memory, depending addressing mode instruction. Likewise, output data from written register array data memory location. PIC24F incorporates hardware support both multiplication division. This includes dedicated hardware multiplier support hardware 16-bit divisor division. divide block supports signed unsigned integer divide operations with following data sizes: 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide
quotient divide instructions ends remainder Sixteen-bit signed unsigned instructions specify register both 16-bit divisor (Wn), register (aligned) pair (W(m 1):Wm) 32-bit dividend. divide algorithm takes cycle divisor, both 32-bit/16-bit 16-bit/16-bit instructions take same number cycles execute.
3.3.3
MULTI-BIT SHIFT SUPPORT
3.3.1
MULTIPLIER
contains high-speed, 17-bit 17-bit multiplier. supports unsigned, signed mixed sign operation several multiplication modes: 16-bit 16-bit signed 16-bit 16-bit unsigned 16-bit signed 5-bit (literal) unsigned 16-bit unsigned 16-bit unsigned 16-bit unsigned 5-bit (literal) unsigned 16-bit unsigned 16-bit signed 8-bit unsigned 8-bit unsigned
PIC24F supports both single single-cycle, multi-bit arithmetic logic shifts. Multi-bit shifts implemented using shifter block, capable performing 15-bit arithmetic right shift, 15-bit left shift, single cycle. multi-bit shift instructions only support Register Direct Addressing both operand source result destination. full summary instructions that shift operation provided below Table 3-2.
TABLE 3-2:
Instruction
INSTRUCTIONS THAT SINGLE MULTI-BIT SHIFT OPERATION
Description Arithmetic shift right source register more bits. Shift left source register more bits. Logical shift right source register more bits.
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MEMORY ORGANIZATION
Harvard architecture devices, PIC24F microcontrollers feature separate program data memory spaces busses. This architecture also allows direct access program memory from data space during code execution. from either 23-bit Program Counter (PC) during program execution, from table operation data space remapping, described Section "Interfacing Program Data Memory Spaces". User access program memory space restricted lower half address range (000000h 7FFFFFh). exception TBLRD/TBLWT operations which TBLPAG<7> permit access Configuration bits Device sections configuration memory space. Memory maps PIC24FJ256GA110 family devices shown Figure 4-1.
Program Address Space
program address memory space PIC24FJ256GA110 family devices instructions. space addressable 24-bit value derived
FIGURE 4-1:
PROGRAM SPACE MEMORY PIC24FJ256GA110 FAMILY DEVICES
PIC24FJ192GA1XX
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table
PIC24FJ128GA1XX
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory (44K instructions) User Memory Space
PIC24FJ256GA1XX
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table 000000h 000002h 000004h 0000FEh 000100h 000104h 0001FEh 000200h
User Flash Program Memory (67K instructions)
Flash Config Words
User Flash Program Memory (87K instructions)
0157FEh 015800h 020BFEh 020C00h
Flash Config Words
Flash Config Words Unimplemented Read Unimplemented Read
02ABFEh 02AC00h
Unimplemented Read
7FFFFFh 800000h
Reserved Configuration Memory Space
Reserved
Reserved
Device Config Registers
Device Config Registers
Device Config Registers
F7FFFEh F80000h F8000Eh F80010h
Reserved
Reserved
Reserved
DEVID
DEVID
DEVID
FEFFFEh FF0000h FFFFFFh
Note:
Memory areas shown scale.
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4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.3 FLASH CONFIGURATION WORDS
program memory space organized word-addressable blocks. Although treated bits wide, more appropriate think each address program memory lower upper word, with upper byte upper word being unimplemented. lower word always even address, while upper word address (Figure 4-2). Program memory addresses always word-aligned lower word addresses incremented decremented during code execution. This arrangement also provides compatibility with data memory space addressing makes possible access data program memory space. PIC24FJ256GA110 family devices, three words on-chip program memory reserved configuration information. device Reset, configuration information copied into appropriate Configuration registers. addresses Flash Configuration Word devices PIC24FJ256GA110 family shown Table 4-1. Their location memory shown with other memory vectors Figure 4-1. Configuration Words program memory compact format. actual Configuration bits mapped several different registers configuration memory space. Their order Flash Configuration Words reflect corresponding arrangement configuration space. Additional details device Configuration Words provided Section 25.1 "Configuration Bits".
4.1.2
HARD MEMORY VECTORS
PIC24F devices reserve addresses between 00000h 000200h hard coded program execution vectors. hardware Reset vector provided redirect code execution from default value device Reset actual start code. GOTO instruction programmed user 000000h with actual address start code 000002h. PIC24F devices also have interrupt vector tables, located from 000004h 0000FFh 000100h 0001FFh. These vector tables allow each many device interrupt sources handled separate ISRs. more detailed discussion interrupt vector tables provided Section "Interrupt Vector Table".
TABLE 4-1:
FLASH CONFIGURATION WORDS PIC24FJ256GA110 FAMILY DEVICES
Program Memory (Words) 44,032 67,072 87,552 Configuration Word Addresses 0157FAh: 0157FEh 020BFAh: 020BFEh 02ABFAh: 02ABFEh
Device
PIC24FJ128GA PIC24FJ192GA PIC24FJ256GA
FIGURE 4-2:
Address 000001h 000003h 000005h 000007h
PROGRAM MEMORY ORGANIZATION
most significant word 00000000 00000000 00000000 00000000 Program Memory `Phantom' Byte (read `0') Instruction Width least significant word 000000h 000002h 000004h 000006h Address (lsw Address)
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Data Address Space
PIC24F core separate, 16-bit wide data memory space, addressable single linear range. data space accessed using Address Generation Units (AGUs), each read write operations. data space memory shown Figure 4-3. Effective Addresses (EAs) data memory space bits wide point bytes within data space. This gives data space address range Kbytes words. lower half data memory space (that when EA<15> used implemented memory addresses, while upper half (EA<15> reserved program space visibility area (see Section 4.3.3 "Reading Data From Program Memory Using Program Space Visibility"). PIC24FJ256GA110 family devices implement total Kbytes data memory. Should point location outside this area, zero word byte will returned.
4.2.1
DATA SPACE WIDTH
data memory space organized byte-addressable, 16-bit wide blocks. Data aligned data memory registers 16-bit words, data space resolve bytes. Least Significant Bytes (LSBs) each word have even addresses, while Most Significant Bytes (MSBs) have addresses.
FIGURE 4-3:
DATA SPACE MEMORY PIC24FJ256GA110 FAMILY DEVICES
Address 0001h 07FFh 0801h 1FFFh 2001h Data Address 0000h 07FEh 0800h 1FFEh 2000h Space
Space
Near Data Space
Implemented Data
47FFh 4801h Unimplemented Read 7FFFh 8001h
47FEh 4800h
7FFFh 8000h
Program Space Visibility Area
FFFFh Data memory areas shown scale.
FFFEh
Note:
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4.2.2 DATA MEMORY ORGANIZATION ALIGNMENT
maintain backward compatibility with PIC® devices improve data space memory usage efficiency, PIC24F instruction supports both word byte operations. consequence byte accessibility, Effective Address (EA) calculations internally scaled step through word-aligned memory. example, core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result value byte operations word operations. Data byte reads will read complete word which contains byte, using determine which byte select. selected byte placed onto data path. That data memory registers organized parallel, byte-wide entities with shared (word) address decode, separate write lines. Data byte writes only write corresponding side array register which matches byte address. word accesses must aligned even address. Misaligned word data fetches supported, care must taken when mixing byte word operations translating from 8-bit code. misaligned read write attempted, address error trap will generated. error occurred read, instruction underway completed; occurred write, instruction will executed write will occur. either case, trap then executed, allowing system and/or user examine machine state prior execution address Fault. byte loads into register loaded into Least Significant Byte. Most Significant Byte modified. Sign-Extend (SE) instruction provided allow users translate 8-bit signed data 16-bit signed values. Alternatively, 16-bit unsigned data, users clear register executing Zero-Extend (ZE) instruction appropriate address. Although most instructions capable operating word byte data sizes, should noted that some instructions operate only words.
4.2.3
NEAR DATA SPACE
8-Kbyte area between 0000h 1FFFh referred near data space. Locations this space directly addressable 13-bit absolute address field within memory direct instructions. remainder data space indirectly addressable. Additionally, whole data space addressable using instructions, which support Memory Direct Addressing with 16-bit address field.
4.2.4
SPACE
first Kbytes near data space, from 0000h 07FFh, primarily occupied with Special Function Registers (SFRs). These used PIC24F core peripheral modules controlling operation device. SFRs distributed among modules that they control generally grouped together module. Much space contains unused addresses; these read `0'. diagram space, showing where SFRs actually implemented, shown Table 4-2. Each implemented area indicates 32-byte region where least address implemented SFR. complete listing implemented SFRs, including their addresses, shown Tables through 4-29.
TABLE 4-2:
IMPLEMENTED REGIONS DATA SPACE
Space Address xx00 xx20 Core Timers I2CA/D UART A/D/CTMU RTC/Comp SPI/UART System xx40 xx60 Capture SPI/I2C NVM/PMD UART xx80 xxA0 Interrupts Compare xxC0 xxE0
000h 100h 200h 300h 400h 500h 600h 700h
Legend: implemented SFRs this block
DS39905C-page
2009 Microchip Technology Inc.
TABLE 4-3:
File Name WREG0 WREG1 WREG2 WREG3 WREG4 WREG5 WREG6 WREG7 WREG8 WREG9 WREG10 WREG11 WREG12 WREG13 WREG14 WREG15 SPLIM TBLPAG PSVPAG RCOUNT CORCON DISICNT Legend: Addr 0000 0002 0004 0006 0008 000A 000C 000E 0010 0012 0014 0016 0018 001A 001C 001E 0020 002E 0030 0032 0034 0036 0042 0044 0052
CORE REGISTERS
Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 xxxx 0000 Program Counter Register High Byte Table Memory Page Address Register Program Space Visibility Page Address Register IPL2 IPL1 IPL0 IPL3 0000 0000 0000 xxxx 0000 0000 xxxx
2009 Microchip Technology Inc.
Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Stack Pointer Limit Value Register Program Counter Word Register Repeat Loop Counter Register
PIC24FJ256GA110 FAMILY
DS39905C-page
Disable Interrupts Counter Register
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-4:
File Addr Name CNPD1 0054 CNPD2 0056
REGISTER
CN14PDE CN30PDE CN62PDE CN14IE CN30IE CN46IE(2) CN62IE CN78IE(1) CN14PUE CN30PUE CN62PUE CN13PDE CN29PDE CN61PDE CN13IE CN29IE CN45IE(1) CN61IE CN77IE(1) CN13PUE CN29PUE CN61PUE CN12PDE CN28PDE CN60PDE CN12IE CN28IE CN44IE(1) CN60IE CN76IE(2) CN12PUE CN28PUE CN60PUE CN11PDE CN27PDE CN59PDE CN11IE CN27IE CN43IE(1) CN59IE CN75IE(2) CN11PUE CN27PUE CN59PUE CN10PDE CN26PDE CN9PDE CN25PDE CN8PDE CN24PDE CN7PDE CN23PDE CN55PDE CN7IE CN23IE CN39IE(2) CN55IE CN71IE CN7PUE CN23PUE CN55PUE CN6PDE CN5PDE CN4PDE CN3PDE CN2PDE CN1PDE CN17PDE CN0PDE CN16PDE Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
DS39905C-page
PIC24FJ256GA110 FAMILY
CN15PDE CN31PDE
CN22PDE CN21PDE(1) CN20PDE(1) CN19PDE(1) CN18PDE CN54PDE CN6IE CN22IE CN38IE(2) CN54IE CN70IE(1) CN6PUE CN53PDE CN5IE CN21IE(1) CN37IE(2) CN53IE CN69IE CN5PUE CN52PDE CN84PDE CN4IE CN20IE(1) CN36IE(2) CN52IE CN68IE CN84IE CN4PUE CN51PDE CN50PDE
CNPD3 0058 CN47PDE(1) CN46PDE(2) CN45PDE(1) CN44PDE(1) CN43PDE(1) CN42PDE(1) CN41PDE(1) CN40PDE(2) CN39PDE(2) CN38PDE(2) CN37PDE(2) CN36PDE(2) CN35PDE(2) CN34PDE(2) CN33PDE(2) CN32PDE CNPD4 005A CN63PDE CNPD6 005E CNEN1 0060 CNEN2 0062 CNEN3 0064 CNEN4 0066 CNEN5 0068 CNEN6 006A CN15IE CN31IE CN47IE(1) CN63IE CN79IE(2) CN58PDE CN57PDE(1) CN56PDE CN10IE CN26IE CN42IE(1) CN58IE CN74IE(1) CN10PUE CN26PUE CN9IE CN25IE CN41IE(1) CN57IE(1) CN73IE(1) CN9PUE CN25PUE CN8IE CN24IE CN40IE(2) CN56IE CN72IE CN8PUE CN24PUE CN49PDE CN48PDE(2) CN64PDE CN0IE CN16IE CN32IE CN48IE(2) CN64IE CN80IE(2) CN0PUE CN16PUE CNPD5 005C CN79PDE(2) CN78PDE(1) CN77PDE(1) CN76PDE(2) CN75PDE(2) CN74PDE(1) CN73PDE(1) CN72PDE CN71PDE CN70PDE(1) CN69PDE CN68PDE CN67PDE(1) CN66PDE(1) CN65PDE CN3IE CN19IE(1) CN35IE(2) CN51IE CN67IE(1) CN83IE CN3PUE CN2IE CN18IE CN34IE(2) CN50IE CN66IE(1) CN82IE(2) CN2PUE CN1IE CN17IE CN33IE(2) CN49IE CN65IE CN81IE(2) CN1PUE CN17PUE
CN83PDE CN82PDE(2) CN81PDE(2) CN80PDE(2)
CNPU1 006C CN15PUE CNPU2 006E CN31PUE CNPU4 0072 CNPU6 0076 Legend: Note CN63PUE
CN22PUE CN21PUE(1) CN20PUE(1) CN19PUE(1) CN18PUE CN54PUE CN53PUE CN52PUE CN84PUE CN51PUE CN50PUE
2009 Microchip Technology Inc.
CNPU3 0070 CN47PUE(1) CN46PUE(2) CN45PUE(1) CN44PUE(1) CN43PUE(1) CN42PUE(1) CN41PUE(1) CN40PUE(2) CN39PUE(2) CN38PUE(2) CN37PUE(2) CN36PUE(2) CN35PUE(2) CN34PUE(2) CN33PUE(2) CN32PUE CN58PUE CN57PUE(1) CN56PUE CN49PUE CN48PUE(2) CN64PUE CNPU5 0074 CN79PUE(2) CN78PUE(1) CN77PUE(1) CN76PUE(2) CN75PUE(2) CN74PUE(1) CN73PUE(1) CN72PUE unimplemented, read `0'. Reset values shown hexadecimal. Unimplemented 64-pin devices; read `0'. Unimplemented 64-pin 80-pin devices; read `0'. CN71PUE CN70PUE(1) CN69PUE CN68PUE CN67PUE(1) CN66PUE(1) CN65PUE
CN83PUE CN82PUE(2) CN81PUE(2) CN80PUE(2)
TABLE 4-5:
File Name Addr
INTERRUPT CONTROLLER REGISTER
NSTDIS ALTIVT U2TXIF U2TXIE CPUIRQ DISI U2RXIF RTCIF U2RXIE RTCIE T1IP2 T2IP2 CNIP2 IC8IP2 T4IP2 IC5IP2 OC7IP2 CRCIP2 AD1IF INT2IF PMPIF CTMUIF IC9IF AD1IE INT2IE PMPIE CTMUIE IC9IE T1IP1 T2IP1 CNIP1 IC8IP1 T4IP1 IC5IP1 OC7IP1 CRCIP1 U1TXIF T5IF OC8IF OC9IF U1TXIE T5IE OC8IE OC9IE T1IP0 T2IP0 CNIP0 IC8IP0 T4IP0 U2TXIP0 IC5IP0 OC7IP0 CRCIP0 U3TXIP0 SPI3IP0 U1RXIF T4IF OC7IF SPI3IF U1RXIE T4IE OC7IE SPI3IE ILR3 SPI1IF OC4IF OC6IF SPF3IF SPI1IE OC4IE OC6IE SPF3IE OC1IP2 OC2IP2 SPI1IP2 CMIP2 IC7IP2 OC4IP2 IC4IP2 OC6IP2 INT4IP2 RTCIP2 SPF3IP2 ILR2 SPF1IF OC3IF OC5IF U4TXIF SPF1IE OC3IE OC5IE U4TXIE OC1IP1 OC2IP1 SPI1IP1 CMIP1 IC7IP1 OC4IP1 IC4IP1 OC6IP1 INT4IP1 RTCIP1 SPF3IP1 ILR1 T3IF IC6IF LVDIF U4RXIF T3IE IC6IE LVDIE U4RXIE OC1IP0 OC2IP0 SPI1IP0 CMIP0 IC7IP0 OC4IP0 IC4IP0 OC6IP0 INT4IP0 RTCIP0 SPF3IP0 ILR0 T2IF IC8IF IC5IF U4ERIF T2IE IC8IE IC5IE U4ERIE OC2IF IC7IF IC4IF INT4IF OC2IE IC7IE IC4IE INT4IE IC1IP2 IC2IP2 SPF1IP2 AD1IP2 OC3IP2 INT2IP2 SPI2IP2 IC3IP2 OC5IP2 PMPIP2 SI2C2IP2 INT3IP2 U1ERIP2 U3ERIP2 U4TXIP2 IC9IP2 IC2IF IC3IF INT3IF MI2C3IF IC2IE IC3IE INT3IE MI2C3IE IC1IP1 IC2IP1 SPF1IP1 AD1IP1 OC3IP1 INT2IP1 SPI2IP1 IC3IP1 OC5IP1 PMPIP1 SI2C2IP1 INT3IP1 U1ERIP1 U3ERIP1 U4TXIP1 IC9IP1 STKERR INT2EP OC1IF CMIF MI2C2IF U2ERIF U3RXIF OC1IE CMIE MI2C2IE U2ERIE U3RXIE INT0IP2 T3IP2 U1TXIP2 SI2C1IP2 INT1IP2 T5IP2 SPF2IP2 IC6IP2 OC8IP2 LVDIP2 SI2C3IP2 U4RXIP2 OC9IP2 OSCFAIL INT1EP IC1IF MI2C1IF SPI2IF SI2C2IF U1ERIF U3ERIF IC1IE MI2C1IE SPI2IE SI2C2IE U1ERIE U3ERIE INT0IP1 T3IP1 U1TXIP1 SI2C1IP1 INT1IP1 T5IP1 SPF2IP1 IC6IP1 OC8IP1 LVDIP1 SI2C3IP1 U4RXIP1 OC9IP1 INT0EP INT0IF SI2C1IF SPF2IF INT0IE SI2C1IE SPF2IE INT0IP0 T3IP0 U1TXIP0 SI2C1IP0 INT1IP0 T5IP0 SPF2IP0 IC6IP0 OC8IP0 LVDIP0 SI2C3IP0 U4RXIP0 OC9IP0 Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
2009 Microchip Technology Inc.
INTCON1 0080 INTCON2 0082 IFS0 IFS1 IFS2 IFS3 IFS4 IFS5 IEC0 IEC1 IEC2 IEC3 IEC4 IEC5 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC9 IPC10 IPC11 IPC12 IPC13 IPC15 IPC16 IPC18 IPC19 IPC20 0084 0086 0088 008A 008C 008E 0094 0096 0098 009A 009C 009E 00A4 00A6 00A8 00AA 00AC 00AE 00B0 00B2 00B4 00B6 00B8 00BA 00BC 00BE 00C2 00C4 00C8 00CA 00CC 00CE 00D0 00D2
MATHERR ADDRERR INT4EP INT1IF SI2C3IF INT1IE SI2C3IE IC1IP0 IC2IP0 SPF1IP0 AD1IP0 MI2C1IP0 OC3IP0 INT2IP0 SPI2IP0 IC3IP0 OC5IP0 PMPIP0 SI2C2IP0 INT3IP0 U1ERIP0 CTMUIP0 U3ERIP0 MI2C3IP0 U4TXIP0 IC9IP0 INT3EP T1IF CNIF CRCIF U3TXIF T1IE CNIE CRCIE U3TXIE
PIC24FJ256GA110 FAMILY
4444 4440 4444 0044 4444 4404 4440 4444 0044 4440 4444 0044 0440 0440 0400 4440 0004 0040 4440 4044 4444 0044 0000
DS39905C-page
U1RXIP2 U1RXIP1 U1RXIP0
MI2C1IP2 MI2C1IP1
U2TXIP2 U2TXIP1
U2RXIP2 U2RXIP1 U2RXIP0
MI2C2IP2 MI2C2IP1 MI2C2IP0
U2ERIP2 U2ERIP1 U2ERIP0
CTMUIP2 CTMUIP1 MI2C3IP2 MI2C3IP1
U3TXIP2 U3TXIP1 SPI3IP2 SPI3IP1 VHOLD
U3RXIP2 U3RXIP1 U3RXIP0
IPC21 IPC22 IPC23 Legend:
U4ERIP2 U4ERIP1 U4ERIP0
INTTREG 00E0
VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-6:
File Name TMR1 T1CON TMR2 TMR3HLD TMR3 T2CON T3CON TMR4 TMR5HLD TMR5 Addr 0100 0102 0104 0106 0108 010A 010C 010E 0110 0112 0114 0116 0118 011A 011C 011E 0120
TIMER REGISTER
Resets 0000 FFFF TGATE TCKPS1 TCKPS0 TSYNC 0000 0000 0000 0000 FFFF FFFF TGATE TGATE TCKPS1 TCKPS1 TCKPS0 TCKPS0 0000 0000 0000 0000 0000 FFFF FFFF TGATE TGATE TCKPS1 TCKPS1 TCKPS0 TCKPS0 0000 0000
DS39905C-page
PIC24FJ256GA110 FAMILY
Timer1 Register Timer1 Period Register TSIDL Timer2 Register Timer3 Holding Register (for 32-bit timer operations only) Timer3 Register Timer2 Period Register Timer3 Period Register TSIDL TSIDL
Timer4 Register Timer5 Holding Register (for 32-bit operations only) Timer5 Register Timer4 Period Register Timer5 Period Register TSIDL TSIDL
2009 Microchip Technology Inc.
T4CON T5CON Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
2009 Microchip Technology Inc.
TABLE 4-7:
File Name Addr
INPUT CAPTURE REGISTER
ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 IC32 ICTRIG ICI1 TRIGSTAT ICI0 ICOV ICBNE ICM2 ICM1 ICM0 Resets 0000
IC1CON1 0140 IC1CON2 0142 IC1BUF IC1TMR 0144 0146
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D 0000 xxxx
Input Capture Buffer Register Timer Value Register ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 IC32 ICTRIG ICI1 TRIGSTAT ICI0 ICOV ICBNE ICM2 ICM1 ICM0
IC2CON1 0148 IC2CON2 014A IC2BUF IC2TMR 014C 014E
0000
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D 0000 xxxx
Input Capture Buffer Register Timer Value Register ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 IC32 ICTRIG ICI1 TRIGSTAT ICI0 ICOV ICBNE ICM2 ICM1 ICM0
IC3CON1 0150 IC3CON2 0152 IC3BUF IC3TMR 0154 0156
0000
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D 0000 xxxx
Input Capture Buffer Register Timer Value Register ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 IC32 ICTRIG ICI1 TRIGSTAT ICI0 ICOV ICBNE ICM2 ICM1 ICM0
IC4CON1 0158 IC4CON2 015A IC4BUF IC4TMR 015C 015E
0000
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D 0000 xxxx
PIC24FJ256GA110 FAMILY
Input Capture Buffer Register Timer Value Register ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 IC32 ICTRIG ICI1 TRIGSTAT ICI0 ICOV ICBNE ICM2 ICM1 ICM0
DS39905C-page
IC5CON1 0160 IC5CON2 0162 IC5BUF IC5TMR 0164 0166
0000
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D 0000 xxxx
Input Capture Buffer Register Timer Value Register ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 IC32 ICTRIG ICI1 TRIGSTAT ICI0 ICOV ICBNE ICM2 ICM1 ICM0
IC6CON1 0168 IC6CON2 016A IC6BUF IC6TMR 016C 016E
0000
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D 0000 xxxx
Input Capture Buffer Register Timer Value Register ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 IC32 ICTRIG ICI1 TRIGSTAT ICI0 ICOV ICBNE ICM2 ICM1 ICM0
IC7CON1 0170 IC7CON2 0172 IC7BUF IC7TMR 0174 0176
0000
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D 0000 xxxx
Input Capture Buffer Register Timer Value Register ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 IC32 ICTRIG ICI1 TRIGSTAT ICI0 ICOV ICBNE ICM2 ICM1 ICM0
IC8CON1 0178 IC8CON2 017A IC8BUF IC8TMR 017C 017E
0000
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D 0000 xxxx
Input Capture Buffer Register Timer Value Register ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 IC32 ICTRIG ICI1 TRIGSTAT ICI0 ICOV ICBNE ICM2 ICM1 ICM0
IC9CON1 0180 IC9CON2 0182 IC9BUF IC9TMR Legend: 0184 0186
0000
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D 0000 xxxx
Input Capture Buffer Register Timer Value Register
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-8:
File Name Addr
OUTPUT COMPARE REGISTER
OCSIDL OC32 ENFLT0 OCTRIS OCFLT0 TRIGMODE OCM2 OCM1 OCM0 Resets 0000
DS39905C-page
PIC24FJ256GA110 FAMILY
OC1CON1 0190 OC1RS OC1R OC1TMR 0194 0196 0198
OCTSEL2 OCTSEL1 OCTSEL0 OCINV
OC1CON2 0192 FLTMD
FLTOUT FLTTRIEN
OCTRIG TRIGSTAT
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C 0000 0000 xxxx
Output Compare Secondary Register Output Compare Register Timer Value Register OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 OCINV OC32 ENFLT0 OCTRIS OCFLT0 TRIGMODE OCM2 OCM1 OCM0 FLTOUT FLTTRIEN OCTRIG TRIGSTAT
OC2CON1 019A OC2RS OC2R OC2TMR 019E 01A0 01A2
0000
OC2CON2 019C FLTMD
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C 0000 0000 xxxx
Output Compare Secondary Register Output Compare Register Timer Value Register OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 OCINV OC32 ENFLT0 OCTRIS OCFLT0 TRIGMODE OCM2 OCM1 OCM0 FLTOUT FLTTRIEN OCTRIG TRIGSTAT
OC3CON1 01A4 OC3RS OC3R OC3TMR 01A8 01AA 01AC
0000
OC3CON2 01A6 FLTMD
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C 0000 0000 xxxx
Output Compare Secondary Register Output Compare Register Timer Value Register OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 OCINV OC32 ENFLT0 OCTRIS OCFLT0 TRIGMODE OCM2 OCM1 OCM0 FLTOUT FLTTRIEN OCTRIG TRIGSTAT
2009 Microchip Technology Inc.
OC4CON1 01AE OC4RS OC4R OC4TMR 01B2 01B4 01B6
0000
OC4CON2 01B0 FLTMD
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C 0000 0000 xxxx
Output Compare Secondary Register Output Compare Register Timer Value Register OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 OCINV OC32 ENFLT0 OCTRIS OCFLT0 TRIGMODE OCM2 OCM1 OCM0 FLTOUT FLTTRIEN OCTRIG TRIGSTAT
OC5CON1 01B8 OC5RS OC5R OC5TMR 01BC 01BE 01C0
0000
OC5CON2 01BA FLTMD
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C 0000 0000 xxxx
Output Compare Secondary Register Output Compare Register Timer Value Register OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 OCINV OC32 ENFLT0 OCTRIS OCFLT0 TRIGMODE OCM2 OCM1 OCM0 FLTOUT FLTTRIEN OCTRIG TRIGSTAT
OC6CON1 01C2 OC6RS OC6R OC6TMR 01C6 01C8 01CA
0000
OC6CON2 01C4 FLTMD
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C 0000 0000 xxxx
Output Compare Secondary Register Output Compare Register Timer Value Register OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 OCINV OC32 ENFLT0 OCTRIS OCFLT0 TRIGMODE OCM2 OCM1 OCM0 FLTOUT FLTTRIEN OCTRIG TRIGSTAT
OC7CON1 01CC OC7RS OC7R OC7TMR Legend: 01D0 01D2 01D4
0000
OC7CON2 01CE FLTMD
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C 0000 0000 xxxx
Output Compare Secondary Register Output Compare Register Timer Value Register
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-8:
File Name Addr
OUTPUT COMPARE REGISTER (CONTINUED)
OCSIDL OC32 ENFLT0 OCTRIS OCFLT0 TRIGMODE OCM2 OCM1 OCM0 Resets 0000
2009 Microchip Technology Inc.
OC8CON1 01D6 OC8RS OC8R OC8TMR 01DA 01DC 01DE
OCTSEL2 OCTSEL1 OCTSEL0 OCINV
OC8CON2 01D8 FLTMD
FLTOUT FLTTRIEN
OCTRIG TRIGSTAT
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C 0000 0000 xxxx
Output Compare Secondary Register Output Compare Register Timer Value Register OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 OCINV OC32 ENFLT0 OCTRIS OCFLT0 TRIGMODE OCM2 OCM1 OCM0 FLTOUT FLTTRIEN OCTRIG TRIGSTAT
OC9CON1 01E0 OC9RS OC9R OC9TMR Legend: 01E4 01E6 01E8
0000
OC9CON2 01E2 FLTMD
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C 0000 0000 xxxx
Output Compare Secondary Register Output Compare Register Timer Value Register
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-9:
I2C~ REGISTER
I2CEN ACKSTAT I2CEN ACKSTAT I2CEN ACKSTAT TRSTAT TRSTAT TRSTAT I2CSIDL I2CSIDL I2CSIDL SCLREL SCLREL SCLREL IPMIEN IPMIEN IPMIEN A10M A10M A10M DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV ACKDT DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV ACKDT DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV ACKDT Resets 0000 00FF 0000 RSEN 1000 0000 0000 0000 0000 00FF 0000 RSEN 1000 0000 0000 0000 0000 00FF 0000 RSEN 1000 0000 0000 0000
PIC24FJ256GA110 FAMILY
DS39905C-page
File Name I2C1RCV I2C1TRN I2C1BRG I2C1CON I2C1STAT I2C1ADD I2C1MSK I2C2RCV I2C2TRN I2C2BRG I2C2CON I2C2STAT I2C2ADD I2C2MSK I2C3RCV I2C3TRN I2C3BRG I2C3CON I2C3STAT I2C3ADD I2C3MSK Legend:
Addr 0200 0202 0204 0206 0208 020A 020C 0210 0212 0214 0216 0218 021A 021C 0270 0272 0274 0276 0278 027A 027C
Receive Register Transmit Register Baud Rate Generator Register ACKEN RCEN
Address Register Address Mask Register Receive Register Transmit Register Baud Rate Generator Register ACKEN RCEN
Address Register Address Mask Register Receive Register Transmit Register Baud Rate Generator Register ACKEN RCEN
Address Register Address Mask Register
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-10:
File Name U1MODE U1STA U1TXREG U1RXREG U1BRG U2MODE U2STA U2TXREG U2RXREG U2BRG U3MODE U3STA U3TXREG U3RXREG U3BRG U4MODE U4STA U4TXREG U4RXREG U4BRG Legend: Addr 0220 0222 0224 0226 0228 0230 0232 0234 0236 0238 0250 0252 0254 0256 0258 02B0 02B2 02B4 02B6 02B8
UART REGISTER
UARTEN UTXISEL1 UARTEN UTXISEL1 UARTEN UTXISEL1 UARTEN UTXISEL1 UTXINV UTXINV UTXINV UTXINV USIDL UTXISEL0 USIDL UTXISEL0 USIDL UTXISEL0 USIDL UTXISEL0 IREN IREN IREN IREN RTSMD UTXBRK RTSMD UTXBRK RTSMD UTXBRK RTSMD UTXBRK UTXEN UTXEN UTXEN UTXEN UEN1 UTXBF Baud Rate Generator Prescaler UEN1 UTXBF Baud Rate Generator Prescaler UEN1 UTXBF Baud Rate Generator Prescaler UEN1 UTXBF Baud Rate Generator Prescaler UEN0 TRMT WAKE LPBACK ABAUD ADDEN RXINV RIDLE BRGH PERR PDSEL1 FERR PDSEL0 OERR STSEL URXDA URXISEL1 URXISEL0 UEN0 TRMT WAKE LPBACK ABAUD ADDEN RXINV RIDLE BRGH PERR PDSEL1 FERR PDSEL0 OERR STSEL URXDA URXISEL1 URXISEL0 UEN0 TRMT WAKE LPBACK ABAUD ADDEN RXINV RIDLE BRGH PERR PDSEL1 FERR PDSEL0 OERR STSEL URXDA URXISEL1 URXISEL0 UEN0 TRMT WAKE LPBACK ABAUD ADDEN RXINV RIDLE BRGH PERR PDSEL1 FERR PDSEL0 OERR STSEL URXDA Resets 0000 0110 xxxx 0000 0000 0000 0110 xxxx 0000 0000 0000 0110 xxxx 0000 0000 0000 0110 xxxx 0000 0000
DS39905C-page
PIC24FJ256GA110 FAMILY
URXISEL1 URXISEL0
Transmit Register Receive Register
Transmit Register Receive Register
Transmit Register Receive Register
2009 Microchip Technology Inc.
Transmit Register Receive Register
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-11:
File Name SPI1STAT SPI1CON1 SPI1CON2 SPI1BUF SPI2STAT SPI2CON1 SPI2CON2 SPI2BUF SPI3STAT SPI3CON1 SPI3CON2 SPI3BUF Legend: Addr 0240 0242 0244 0248 0260 0262 0264 0268 0280 0282 0284 0288
REGISTER
SPIEN FRMEN SPIEN FRMEN SPIEN FRMEN SPIFSD SPIFSD SPIFSD SPISIDL SPIFPOL SPISIDL SPIFPOL SPISIDL SPIFPOL DISSCK DISSCK DISSCK DISSDO DISSDO DISSDO SRMPT SSEN SRMPT SSEN SRMPT SSEN SPIROV SPIROV SPIROV SRXMPT MSTEN SRXMPT MSTEN SRXMPT MSTEN SISEL2 SPRE2 SISEL2 SPRE2 SISEL2 SPRE2 SISEL1 SPRE1 SISEL1 SPRE1 SISEL1 SPRE1 SISEL0 SPRE0 SISEL0 SPRE0 SISEL0 SPRE0 SPITBF PPRE1 SPIFE SPITBF PPRE1 SPIFE SPITBF PPRE1 SPIFE SPIRBF PPRE0 SPIBEN SPIRBF PPRE0 SPIBEN SPIRBF PPRE0 SPIBEN Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
SPIBEC2 SPIBEC1 SPIBEC0 MODE16
Transmit Receive Buffer SPIBEC2 SPIBEC1 SPIBEC0 MODE16
Transmit Receive Buffer SPIBEC2 SPIBEC1 SPIBEC0 MODE16
Transmit Receive Buffer
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-12:
File Name TRISA PORTA LATA ODCA Legend: Note Addr 02C0 02C2 02C4 02C6
PORTA REGISTER MAP(1)
TRISA10 RA10 LATA10 ODA10 TRISA9 LATA9 ODA9 7(2) TRISA7 LATA7 ODA7 6(2) TRISA6 LATA6 ODA6 5(2) TRISA5 LATA5 ODA5 4(2) TRISA4 LATA4 ODA4 3(2) TRISA3 LATA3 ODA3 Bit2(2) TRISA2 LATA2 ODA2 1(2) TRISA1 LATA1 ODA1 0(2) TRISA0 LATA0 ODA0 Resets 36FF xxxx xxxx 0000
2009 Microchip Technology Inc.
TRISA15 TRISA14 RA15 LATA15 ODA15 RA14 LATA14 ODA14
unimplemented, read `0'. Reset values shown hexadecimal. Reset values shown 100-pin devices. PORTA associated bits unimplemented 64-pin devices read `0'. Bits available 80-pin 100-pin devices only, unless otherwise noted. Bits implemented 100-pin devices only; otherwise, read `0'.
TABLE 4-13:
File Name TRISB PORTB LATB ODCB Legend: Addr 02C8 02CA 02CC 02CE
PORTB REGISTER
TRISB10 RB10 LATB10 ODB10 TRISB9 LATB9 ODB9 TRISB8 LATB8 ODB8 TRISB7 LATB7 ODB7 TRISB6 LATB6 ODB6 TRISB5 LATB5 ODB5 TRISB4 LATB4 ODB4 TRISB3 LATB3 ODB3 TRISB2 LATB2 ODB2 TRISB1 LATB1 ODB1 TRISB0 LATB0 ODB0 Resets FFFF xxxx xxxx 0000
TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 RB15 LATB15 ODB15 RB14 LATB14 ODB14 RB13 LATB13 ODB13 RB12 LATB12 ODB12 RB11 LATB11 ODB11
PIC24FJ256GA110 FAMILY
DS39905C-page
Reset values shown hexadecimal.
TABLE 4-14:
File Name TRISC PORTC LATC ODCC Legend: Note Addr 02D0 02D2 02D4 02D6
PORTC REGISTER
4(1) TRISC4 LATC4 ODC4 3(2) TRISC3 LATC3 ODC3 2(1) TRISC2 LATC2 ODC2 1(2) TRISC1 LATC1 ODC1 Resets F01E xxxx xxxx 0000
TRISC15 TRISC14 TRISC13 TRISC12 RC15(3,4) LATC15 ODC15 RC14 LATC14 ODC14 RC13 LATC13 ODC13 RC12(3) LATC12 ODC12
unimplemented, read `0'. Reset values shown hexadecimal. Reset values shown 100-pin devices. Bits unimplemented 64-pin 80-pin devices; read `0'. Bits unimplemented 64-pin devices; read `0'. RC12 RC15 only available when Primary Oscillator disabled when mode selected (POSCMD<1:0> Configuration bits 00); otherwise, read RC15 only available when POSCMD<1:0> Configuration bits OSCIOFN Configuration
TABLE 4-15:
File Name TRISD PORTD LATD ODCD Legend: Note Addr 02D8 02DA 02DC 02DE
PORTD REGISTER
15(1) 14(1) 13(1) 12(1) TRISD9 LATD9 ODD9 TRISD8 LATD8 ODD8 TRISD7 LATD7 ODD7 TRISD6 LATD6 ODD6 TRISD5 LATD5 ODD5 TRISD4 LATD4 ODD4 TRISD3 LATD3 ODD3 TRISD2 LATD2 ODD2 TRISD1 LATD1 ODD1 TRISD0 LATD0 ODD0 Resets FFFF xxxx xxxx 0000
TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 RD15 LATD15 ODD15 RD14 LATD14 ODD14 RD13 LATD13 ODD13 RD12 LATD12 ODD12 RD11 LATD11 ODD11 RD10 LATD10 ODD10
unimplemented, read `0'. Reset values shown hexadecimal. Reset values shown 100-pin devices. Bits unimplemented 64-pin devices; read `0'.
DS39905C-page
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TABLE 4-16:
File Name TRISE PORTE LATE ODCE Legend: Note Addr 02E0 02E2 02E4 02E6
PORTE REGISTER
9(1) TRISE9 LATE9 ODE9 8(1) TRISE8 LATE8 ODE8 TRISE7 LATE7 ODE7 TRISE6 LATE6 ODE6 TRISE5 LATE5 ODE5 TRISE4 LATE4 ODE4 TRISE3 LATE3 ODE3 TRISE2 LATE2 ODE2 TRISE1 LATE1 ODE1 TRISE0 LATE0 ODE0 Resets 03FF xxxx xxxx 0000
unimplemented, read `0'. Reset values shown hexadecimal. Reset values shown 100-pin devices. Bits unimplemented 64-pin devices; read `0'.
TABLE 4-17:
File Name TRISF PORTF LATF ODCF Addr 02E8 02EA 02EC 02EE
PORTF REGISTER
13(1) TRISF13 RF13 LATF13 ODF13 12(1) TRISF12 RF12 LATF12 ODF12 8(2) TRISF8 LATF8 ODF8 7(2) TRISF7 LATF7 ODF7 TRISF6 LATF6 ODF6 TRISF5 LATF5 ODF5 TRISF4 LATF4 ODF4 TRISF3 LATF3 ODF3 TRISF2 LATF2 ODF2 TRISF1 LATF1 ODF1 TRISF0 LATF0 ODF0 Resets 31FF xxxx xxxx 0000
2009 Microchip Technology Inc.
Legend: Note
unimplemented, read `0'. Reset values shown hexadecimal. Reset values shown 100-pin devices. Bits unimplemented 64-pin 80-pin devices; read `0'. Bits unimplemented 64-pin devices; read `0'.
TABLE 4-18:
File Name TRISG PORTG LATG ODCG Legend: Note Addr 02F0 02F2 02F4 02F6
PORTG REGISTER
15(1) 14(1) 13(1) 12(1) TRISG9 LATG9 ODG9 TRISG8 LATG8 ODG8 TRISG7 LATG7 ODG7 TRISG6 LATG6 ODG6 TRISG3 LATG3 ODG3 TRISG2 LATG2 ODG2 1(2) TRISG1 LATG1 ODG1 0(2) TRISG0 LATG0 ODG0 Resets F3CF xxxx xxxx 0000
TRISG15 TRISG14 TRISG13 TRISG12 RG15 LATG15 ODG15 RG14 LATG14 ODG14 RG13 LATG13 ODG13 RG12 LATG12 ODG12
unimplemented, read `0'. Reset values shown hexadecimal. Reset values shown 100-pin devices. Bits unimplemented 64-pin 80-pin devices; read `0'. Bits unimplemented 64-pin devices; read `0'.
TABLE 4-19:
File Name PADCFG1 Legend: Addr 02FC
CONFIGURATION REGISTER
RTSECSEL PMPTTL Resets 0000
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-20:
File Name ADC1BUF0 ADC1BUF1 ADC1BUF2 ADC1BUF3 ADC1BUF4 ADC1BUF5 ADC1BUF6 ADC1BUF7 ADC1BUF8 ADC1BUF9 ADC1BUFA ADC1BUFB ADC1BUFC ADC1BUFD ADC1BUFE ADC1BUFF AD1CON1 AD1CON2 AD1CON3 AD1CHS AD1PCFGL AD1PCFGH AD1CSSL AD1CSSH Legend: Addr 0300 0302 0304 0306 0308 030A 030C 030E 0310 0312 0314 0316 0318 031A 031C 031E 0320 0322 0324 0328 032C 032A 0330 0332
REGISTER
Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
2009 Microchip Technology Inc.
Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer ADON VCFG2 ADRC CH0NB PCFG15 CSSL15 VCFG1 PCFG14 CSSL14 ADSIDL VCFG0 PCFG13 CSSL13 SAMC4 CH0SB4 PCFG12 CSSL12 SAMC3 CH0SB3 PCFG11 CSSL11 CSCNA SAMC2 CH0SB2 PCFG10 CSSL10 FORM1 SAMC1 CH0SB1 PCFG9 CSSL9 FORM0 SAMC0 CH0SB0 PCFG8 CSSL8 SSRC2 BUFS ADCS7 CH0NA PCFG7 CSSL7 SSRC1 ADCS6 PCFG6 CSSL6 SSRC0 SMPI3 ADCS5 PCFG5 CSSL5 SMPI2 ADCS4 CH0SA4 PCFG4 CSSL4 SMPI1 ADCS3 CH0SA3 PCFG3 CSSL3 ASAM SMPI0 ADCS2 CH0SA2 PCFG2 CSSL2 SAMP BUFM ADCS1 CH0SA1 PCFG1 PCFG17 CSSL1 CSS17 DONE ALTS ADCS0 CH0SA0 PCFG0 PCFG16 CSSL0 CSS16
PIC24FJ256GA110 FAMILY
xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000
DS39905C-page
unimplemented, read `0', reserved, maintain `0'. Reset values shown hexadecimal.
TABLE 4-21:
File Name CTMUCON Legend: Addr
CTMU REGISTER
ITRIM4 Resets 0000 0000
033C CTMUEN ITRIM5
CTMUSIDL TGEN ITRIM3 ITRIM2
EDGEN EDGSEQEN IDISSEN CTTRIG EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT ITRIM1 ITRIM0 IRNG1 IRNG0
CTMUICON 033E
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-22:
File Name PMCON PMMODE PMADDR PMDOUT1 PMDOUT2 0606 PMDIN1 PMDIN2 PMAEN PMSTAT Legend: 0608 060A 060C 060E Addr 0600 0602 0604
PARALLEL MASTER/SLAVE PORT REGISTER
PMPEN BUSY IRQM1 PSIDL IRQM0 ADDR13 CSF1 WAITB1 ADDR7 CSF0 WAITB0 ADDR6 WAITM3 ADDR5 CS2P WAITM2 ADDR4 CS1P WAITM1 ADDR3 WAITM0 ADDR2 WRSP WAITE1 ADDR1 RDSP WAITE0 ADDR0 Resets 0000 0000 0000 0000 0000 0000 0000 PTEN5 PTEN4 PTEN3 OB3E PTEN2 OB2E PTEN1 OB1E PTEN0 OB0E 0000 0000
DS39905C-page
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ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN INCM1 ADDR12 INCM0 ADDR11 MODE16 ADDR10 MODE1 ADDR9 MODE0 ADDR8
Parallel Port Data Register (Buffers Parallel Port Data Register (Buffers Parallel Port Data Register (Buffers Parallel Port Data Register (Buffers PTEN15 PTEN14 IBOV PTEN13 PTEN12 PTEN11 IB3F PTEN10 IB2F PTEN9 IB1F PTEN8 IB0F PTEN7 PTEN6 OBUF
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-23:
File Name Addr 0620
REAL-TIME CLOCK CALENDAR REGISTER
Resets xxxx ARPT5 CAL5 ARPT4 CAL4 ARPT3 CAL3 ARPT2 CAL2 ARPT1 CAL1 ARPT0 CAL0 0000 xxxx xxxx
2009 Microchip Technology Inc.
ALRMVAL RTCVAL RCFGCAL Legend:
Alarm Value Register Window Based ALRMPTR<1:0> ALRMEN RTCEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 RTCOE RTCPTR1 RTCPTR0 ARPT7 CAL7 ARPT6 CAL6 RTCC Value Register Window Based RTCPTR<1:0> RTCWREN RTCSYNC HALFSEC
ALCFGRPT 0622 0624 0626
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-24:
File Name CMSTAT CVRCON CM1CON CM2CON CM3CON Legend: Addr 0630 0632 0634 0636 0638
COMPARATORS REGISTER
CMIDL CPOL CPOL CPOL C3EVT C2EVT CEVT CEVT CEVT C1EVT COUT COUT COUT CVREN EVPOL1 EVPOL1 EVPOL1 CVROE EVPOL0 EVPOL0 EVPOL0 CVRR CVRSS CREF CREF CREF CVR3 C3OUT CVR2 C2OUT CVR1 CCH1 CCH1 CCH1 C1OUT CVR0 CCH0 CCH0 CCH0 Resets 0000 0000 0000 0000 0000
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-25:
File Name CRCCON CRCXOR CRCDAT CRCWDAT Legend: Addr 0640 0642 0644 0646
REGISTER
CSIDL CRCGO PLEN3 PLEN2 PLEN1 PLEN0 Resets 0040 0000 0000 0000
VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT Data Input Register Result Register
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 4-26:
File Name RPINR0 RPINR1 RPINR2 RPINR3 RPINR4 RPINR7 RPINR8 RPINR9 RPINR10 RPINR11 RPINR15 RPINR17 RPINR18 RPINR19 RPINR20 RPINR21 Addr 0680 0682 0684 0686 0688 068E 0690 0692 0694 0696 069E 06A2 06A4 06A6 06A8 06AA 06AC 06AE 06B6 06B8 06BA 06C0 06C2 06C4 06C6 06C8 06CA 06CC 06CE 06D0 06D2 06D4 06D6 06D8 06DA 06DC 06DE 06E2
PERIPHERAL SELECT REGISTER
INT1R5 INT3R5 T1CKR5 T3CKR5 T5CKR5 IC2R5 IC4R5 IC6R5 IC8R5 OCFBR5 IC9R5 INT1R4 INT3R4 T1CKR4 T3CKR4 T5CKR4 IC2R4 IC4R4 IC6R4 IC8R4 OCFBR4 IC9R4 INT1R3 INT3R3 T1CKR3 T3CKR3 T5CKR3 IC2R3 IC4R3 IC6R3 IC8R3 OCFBR3 IC9R3 INT1R2 INT3R2 T1CKR2 T3CKR2 T5CKR2 IC2R2 IC4R2 IC6R2 IC8R2 OCFBR2 IC9R2 INT1R1 INT3R1 T1CKR1 T3CKR1 T5CKR1 IC2R1 IC4R1 IC6R1 IC8R1 OCFBR1 IC9R1 INT1R0 INT3R0 T1CKR0 T3CKR0 T5CKR0 IC2R0 IC4R0 IC6R0 IC8R0 OCFBR0 IC9R0 INT2R5 INT4R5 T2CKR5 T4CKR5 IC1R5 IC3R5 IC5R5 IC7R5 OCFAR5 U1RXR5 U2RXR5 SDI1R5 SS1R5 SDI2R5 SS2R5 U4RXR5 SDI3R5 SS3R5 RP0R5 RP2R5 RP4R5 RP6R5 RP8R5 RP10R5 RP12R5 RP14R5 RP16R5 RP18R5 RP20R5 RP22R5 RP24R5 RP26R5 RP28R5 RP30R5 INT2R4 INT4R4 T2CKR4 T4CKR4 IC1R4 IC3R4 IC5R4 IC7R4 OCFAR4 U1RXR4 U2RXR4 SDI1R4 SS1R4 SDI2R4 SS2R4 U4RXR4 SDI3R4 SS3R4 RP0R4 RP2R4 RP4R4 RP6R4 RP8R4 RP10R4 RP12R4 RP14R4 RP16R4 RP18R4 RP20R4 RP22R4 RP24R4 RP26R4 RP28R4 RP30R4 INT2R3 INT4R3 T2CKR3 T4CKR3 IC1R3 IC3R3 IC5R3 IC7R3 OCFAR3 U1RXR3 U2RXR3 SDI1R3 SS1R3 SDI2R3 SS2R3 U4RXR3 SDI3R3 SS3R3 RP0R3 RP2R3 RP4R3 RP6R3 RP8R3 RP10R3 RP12R3 RP14R3 RP16R3 RP18R3 RP20R3 RP22R3 RP24R3 RP26R3 RP28R3 RP30R3 INT2R2 INT4R2 T2CKR2 T4CKR2 IC1R2 IC3R2 IC5R2 IC7R2 OCFAR2 U1RXR2 U2RXR2 SDI1R2 SS1R2 SDI2R2 SS2R2 U4RXR2 SDI3R2 SS3R2 RP0R2 RP2R2 RP4R2 RP6R2 RP8R2 RP10R2 RP12R2 RP14R2 RP16R2 RP18R2 RP20R2 RP22R2 RP24R2 RP26R2 RP28R2 RP30R2 INT2R1 INT4R1 T2CKR1 T4CKR1 IC1R1 IC3R1 IC5R1 IC7R1 OCFAR1 U1RXR1 U2RXR1 SDI1R1 SS1R1 SDI2R1 SS2R1 U4RXR1 SDI3R1 SS3R1 RP0R1 RP2R1 RP4R1 RP6R1 RP8R1 RP10R1 RP12R1 RP14R1 RP16R1 RP18R1 RP20R1 RP22R1 RP24R1 RP26R1 RP28R1 RP30R1 INT2R0 INT4R0 T2CKR0 T4CKR0 IC1R0 IC3R0 IC5R0 IC7R0 OCFAR0 U1RXR0 U2RXR0 SDI1R0 SS1R0 SDI2R0 SS2R0 U4RXR0 SDI3R0 SS3R0 RP0R0 RP2R0 RP4R0 RP6R0 RP8R0 RP10R0 RP12R0 RP14R0 RP16R0 RP18R0 RP20R0 RP22R0 RP24R0 RP26R0 RP28R0 RP30R0 SCK1CM Resets 3F00 3F3F 3F3F 3F3F 3F3F 3F3F 3F3F 3F3F 3F3F 3F3F 3F00 3F00 3F3F 3F3F 3F3F 3F3F 3F3F 3F3F 3F3F 003F 003F 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxx0
2009 Microchip Technology Inc.
U3RXR5 U3RXR4 U3RXR3 U3RXR2 U3RXR1 U3RXR0 U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 U2CTSR5 U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0 SCK1R5 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 U3CTSR5 U3CTSR4 U3CTSR3 U3CTSR2 U3CTSR1 U3CTSR0 SCK2R5 SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 U4CTSR5 U4CTSR4 U4CTSR3 U4CTSR2 U4CTSR1 U4CTSR0 SCK3R5 RP1R5 RP3R5 RP5R5(1) RP7R5 RP9R5 RP11R5 SCK3R4 RP1R4 RP3R4 RP5R4(1) RP7R4 RP9R4 RP11R4 SCK3R3 RP1R3 RP3R3 RP5R3(1) RP7R3 RP9R3 RP11R3 SCK3R2 RP1R2 RP3R2 RP5R2(1) RP7R2 RP9R2 RP11R2 SCK3R1 RP1R1 RP3R1 RP5R1(1) RP7R1 RP9R1 RP11R1 SCK3R0 RP1R0 RP3R0 RP5R0(1) RP7R0 RP9R0 RP11R0
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RPINR22 RPINR23 RPINR27 RPINR28 RPINR29 RPOR0 RPOR1 RPOR2 RPOR3 RPOR4 RPOR5 RPOR6 RPOR7 RPOR8 RPOR9 RPOR10 RPOR11 RPOR12 RPOR13 RPOR14 RPOR15 ALTRP Legend: Note
RP13R5 RP13R4 RP13R3 RP13R2 RP13R1 RP13R0 RP15R5(1) RP15R4(1) RP15R3(1) RP15R2(1) RP15R1(1) RP15R0(1) RP17R5 RP19R5 RP21R5 RP23R5 RP25R5 RP27R5 RP17R4 RP19R4 RP21R4 RP23R4 RP25R4 RP27R4 RP17R3 RP19R3 RP21R3 RP23R3 RP25R3 RP27R3 RP17R2 RP19R2 RP21R2 RP23R2 RP25R2 RP27R2 RP17R1 RP19R1 RP21R1 RP23R1 RP25R1 RP27R1 RP17R0 RP19R0 RP21R0 RP23R0 RP25R0 RP27R0
RP29R5 RP29R4 RP29R3 RP29R2 RP29R1 RP29R0 RP31R5(2) RP31R4(2) RP31R3(2) RP31R2(2) RP31R1(2) RP31R0(2)
unimplemented, read `0'. Reset values shown hexadecimal. Bits unimplemented 64-pin devices; read `0'. Bits unimplemented 64-pin 80-pin devices; read `0'.
TABLE 4-27:
File Name RCON OSCCON CLKDIV OSCTUN REFOCON Legend: Note Addr 0740 0742 0744 0748 074E
SYSTEM REGISTER
TRAPR ROEN IOPUWR COSC2 DOZE2 COSC1 DOZE1 ROSSLP COSC0 DOZE0 ROSEL DOZEN RODIV3 NOSC2 RCDIV2 RODIV2 NOSC1 RCDIV1 RODIV1 VREGS NOSC0 RCDIV0 RODIV0 EXTR CLKLOCK IOLOCK SWDTEN LOCK TUN5 WDTO TUN4 SLEEP TUN3 IDLE TUN2 TUN1 OSWEN TUN0 Resets Note Note 0100 0000 0000
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POSCEN SOSCEN
unimplemented, read `0'. Reset values shown hexadecimal. Reset value RCON register dependent type Reset event. Section "Resets" more information. Reset value OSCCON register dependent both type Reset event device configuration. Section "Oscillator Configuration" more information.
TABLE 4-28:
File Name NVMCON NVMKEY Legend: Note Addr 0760 0766
REGISTER
WREN WRERR ERASE Resets 0000(1) 0000
NVMOP3 NVMOP2 NVMOP1 NVMOP0
NVMKEY<7:0>
unimplemented, read `0'. Reset values shown hexadecimal. Reset value shown only. Value other Reset states dependent state memory write erase operations time Reset.
2009 Microchip Technology Inc.
TABLE 4-29:
File Name PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 Legend: Addr 0770 0772 0774 0776 0778 077A
REGISTER
T5MD IC8MD T4MD IC7MD T3MD IC6MD T2MD IC5MD T1MD IC4MD IC3MD IC2MD IC1MD IC9MD I2C1MD OC8MD CRCMD U2MD OC7MD U1MD OC6MD U4MD SPI2MD OC5MD SPI1MD OC4MD U3MD OC3MD I2C3MD OC2MD I2C2MD LVDMD ADC1MD OC1MD OC9MD SPI3MD Resets 0000 0000 0000 0000 0000 0000
CMPMD RTCCMD PMPMD
REFOMD CTMUMD
unimplemented, read `0'. Reset values shown hexadecimal.
PIC24FJ256GA110 FAMILY
4.2.5 SOFTWARE STACK
addition working register, register PIC24F devices also used Software Stack Pointer. pointer always points first available free word grows from lower higher addresses. predecrements stack pops post-increments stack pushes, shown Figure 4-4. Note that push during CALL instruction, zero-extended before push, ensuring that always clear. Note: push during exception processing will concatenate register prior push.
Interfacing Program Data Memory Spaces
PIC24F architecture uses 24-bit wide program space 16-bit wide data space. architecture also modified Harvard scheme, meaning that data also present program space. this data successfully, must accessed that preserves alignment information both spaces. Aside from normal execution, PIC24F architecture provides methods which program space accessed during operation: Using table instructions access individual bytes words anywhere program space Remapping portion program space into data space (program space visibility) Table instructions allow application read write small areas program memory. This makes method ideal accessing data tables that need updated from time time. also allows access bytes program word. remapping method allows application access large block data read-only basis, which ideal look-ups from large table static data; only access least significant word program word.
Stack Pointer Limit Value (SPLIM) register, associated with Stack Pointer, sets upper address boundary stack. SPLIM uninitialized Reset. case Stack Pointer, SPLIM<0> forced because stack operations must word-aligned. Whenever generated using source destination pointer, resulting address compared with value SPLIM. contents Stack Pointer (W15) SPLIM register equal, push operation performed, stack error trap will occur. stack error trap will occur subsequent push operation. Thus, example, desirable cause stack error trap when stack grows beyond address 2000h RAM, initialize SPLIM with value, 1FFEh. Similarly, Stack Pointer underflow (stack error) trap generated when Stack Pointer address found less than 0800h. This prevents stack from interfering with Special Function Register (SFR) space. write SPLIM register should immediately followed indirect read operation using W15.
4.3.1
ADDRESSING PROGRAM SPACE
Since address ranges data program spaces bits, respectively, method needed create 23-bit 24-bit program address from 16-bit data registers. solution depends interface method used. table operations, 8-bit Table Memory Page Address (TBLPAG) register used define word region within program space. This concatenated with 16-bit arrive full 24-bit program space address. this format, Most Significant TBLPAG used determine operation occurs user memory (TBLPAG<7> configuration memory (TBLPAG<7> remapping operations, 8-bit Program Space Visibility Page Address (PSVPAG) register used define word page program space. When Most Significant `1', PSVPAG concatenated with lower bits form 23-bit program space address. Unlike table operations, this limits remapping operations strictly user memory area. Table 4-30 Figure show program created table operations remapping accesses from data Here, P<23:0> refers program space word, whereas D<15:0> refers data space word.
FIGURE 4-4:
0000h
CALL STACK FRAME
Stack Grows Towards Higher Address
PC<15:0> 000000000 PC<22:16> <Free Word>
(before CALL) (after CALL) [-W15] PUSH [W15++]
2009 Microchip Technology Inc.
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TABLE 4-30: PROGRAM SPACE ADDRESS CONSTRUCTION
Access Space User User Configuration Program Space Visibility (Block Remap/Read) Note User Program Space Address <23> TBLPAG<7:0> 0xxx xxxx TBLPAG<7:0> 1xxx xxxx PSVPAG<7:0> xxxx xxxx <22:16> <15> PC<22:1> xxxx xxxx xxxx xxxx xxx0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<14:0>(1) xxxx xxxx xxxx <14:1> Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write)
Data EA<15> always this case, used calculating program space address. address PSVPAG<0>.
FIGURE 4-5:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter Bits
Table Operations(2)
TBLPAG Bits Bits Bits
Select Program Space Visibility(1) (Remapping) PSVPAG Bits
Bits Bits
User/Configuration Space Select
Byte Select
Note program space addresses always fixed order maintain word alignment data program data spaces. Table operations required word-aligned. Table read operations permitted configuration memory space.
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4.3.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS
TBLRDH (Table Read High): Word mode, maps entire upper word program address (P<23:16>) data address. Note that D<15:8>, `phantom' byte, will always `0'. Byte mode, maps upper lower byte program word D<7:0> data address, above. Note that data will always when upper `phantom' byte selected (byte select
TBLRDL TBLWTL instructions offer direct method reading writing lower word address within program space without going through data space. TBLRDH TBLWTH instructions only method read write upper bits program space word data. incremented each successive 24-bit program word. This allows program memory addresses directly data space addresses. Program memory thus regarded two, 16-bit word-wide address spaces, residing side side, each with same address range. TBLRDL TBLWTL access space which contains least significant data word, TBLRDH TBLWTH access space which contains upper data byte. table instructions provided move byte word-sized (16-bit) data from program space. Both function either byte word operations. TBLRDL (Table Read Low): Word mode, maps lower word program space location (P<15:0>) data address (D<15:0>). Byte mode, either upper lower byte lower program word mapped lower byte data address. upper byte selected when byte select `1'; lower byte selected when `0'.
similar fashion, table instructions, TBLWTH TBLWTL, used write individual bytes words program space address. details their operation explained Section "Flash Program Memory". table operations, area program memory space accessed determined Table Memory Page Address (TBLPAG) register. TBLPAG covers entire program memory space device, including user configuration spaces. When TBLPAG<7> table page located user memory space. When TBLPAG<7> page located configuration space. Note: Only table read operations will execute configuration memory space, only then, implemented areas, such Device Table write operations allowed.
FIGURE 4-6:
TBLPAG
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
Data EA<15:0> 000000h
00000000
00000000 00000000 00000000
020000h 030000h
`Phantom' Byte
TBLRDH.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.W
address table operation determined data within page defined TBLPAG register. Only read operations shown; write operations also valid user memory area.
800000h
2009 Microchip Technology Inc.
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4.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY
24-bit program word used contain data. upper bits program space locations used data should programmed with `1111 1111' `0000 0000' force NOP. This prevents possible issues should area code ever accidentally executed. Note: access temporarily disabled during table reads/writes.
upper Kbytes data space optionally mapped into word page program space. This provides transparent access stored constant data from data space without need special instructions (i.e., TBLRDL/H). Program space access through data space occurs Most Significant (MSb) data space program space visibility enabled setting Control (CORCON<2>) register. location program memory space mapped into data space determined Program Space Visibility Page Address (PSVPAG) register. This 8-bit register defines possible pages words program space. effect, PSVPAG functions upper bits program memory address, with bits functioning lower bits. Note that incrementing each program memory word, lower bits data space addresses directly lower bits corresponding program space addresses. Data reads this area additional cycle instruction being executed, since program memory fetches required. Although each data space address, 8000h higher, maps directly into corresponding program memory address (see Figure 4-7), only lower bits
operations that executed outside REPEAT loop, MOV.D instructions will require instruction cycle addition specified execution time. other instructions will require instruction cycles addition specified execution time. operations that which executed inside REPEAT loop, there will some instances that require instruction cycles addition specified execution time instruction: Execution first iteration Execution last iteration Execution prior exiting loop interrupt Execution upon re-entering loop after interrupt serviced other iteration REPEAT loop will allow instruction accessing data, using PSV, execute single cycle.
FIGURE 4-7:
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> EA<15>
Program Space
PSVPAG 000000h 010000h 018000h data page designated PSVPAG mapped into upper half data memory space.
Data Space
0000h Data EA<14:0>
8000h
Area .while lower bits specify exact address within area. This corresponds exactly same lower bits actual program space address.
FFFFh
800000h
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2009 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY
Note:
FLASH PROGRAM MEMORY
This data sheet summarizes features this group PIC24F devices. intended comprehensive reference source. more information, refer "PIC24F Family Reference Manual", Section "Program Memory" (DS39715).
RTSP accomplished using TBLRD (table read) TBLWT (table write) instructions. With RTSP, user write program memory data blocks instructions (192 bytes) time erase program memory blocks instructions (1536 bytes) time.
Table Instructions Flash Programming
PIC24FJ256GA110 family devices contains internal Flash program memory storing executing application code. memory readable, writable erasable when operating with over 2.35V. regulator disabled, VDDCORE voltage must over 2.25V. Flash memory programmed three ways: In-Circuit Serial Programming(ICSPTM) Run-Time Self-Programming (RTSP) Enhanced In-Circuit Serial Programming (Enhanced ICSP) ICSP allows PIC24FJ256GA110 family device serially programmed while application circuit. This simply done with lines programming clock programming data (which named PGECx PGEDx, respectively), three other lines power (VDD), ground (VSS) Master Clear (MCLR). This allows customers manufacture boards with unprogrammed devices then program microcontroller just before shipping product. This also allows most recent firmware custom firmware programmed.
Regardless method used, programming Flash memory done with table read table write instructions. These allow direct read write access program memory space from data memory while device normal operating mode. 24-bit target address program memory formed using TBLPAG<7:0> bits Effective Address (EA) from register specified table instruction, shown Figure 5-1. TBLRDL TBLWTL instructions used read write bits<15:0> program memory. TBLRDL TBLWTL access program memory both Word Byte modes. TBLRDH TBLWTH instructions used read write bits<23:16> program memory. TBLRDH TBLWTH also access program memory Word Byte mode.
FIGURE 5-1:
ADDRESSING TABLE REGISTERS
Bits Using Program Counter Program Counter
Working Using Table Instruction TBLPAG Bits Bits
User/Configuration Space Select
24-Bit
Byte Select
2009 Microchip Technology Inc.
DS39905C-page
PIC24FJ256GA110 FAMILY
RTSP Operation JTAG Operation
PIC24F Flash program memory array organized into rows instructions bytes. RTSP allows user erase blocks eight rows (512 instructions) time program time. also possible program single words. 8-row erase blocks single write blocks edge-aligned, from beginning program memory, boundaries 1536 bytes bytes, respectively. When data written program memory using TBLWT instructions, data written directly memory. Instead, data written using table writes stored holding latches until programming sequence executed. number TBLWT instructions executed write will successfully performed. However, TBLWT instructions required write full memory. ensure that data corrupted during write, unused addresses should programmed with FFFFFFh. This because holding latches reset unknown state, addresses left Reset state, they overwrite locations rows which were rewritten. basic sequence RTSP programming Table Pointer, then series TBLWT instructions load buffers. Programming performed setting control bits NVMCON register. Data loaded order holding registers written multiple times before performing write operation. Subsequent writes, however, will wipe previous writes. Note: Writing location multiple times without erasing recommended. PIC24F family supports JTAG programming boundary scan. Boundary scan improve manufacturing process verifying connectivity. Programming performed with industry standard JTAG programmers supporting Serial Vector Format (SVF).
Enhanced In-Circuit Serial Programming
Enhanced In-Circuit Serial Programming uses on-board bootloader, known program executive, manage programming process. Using data frame format, program executive erase, program verify program memory. more information Enhanced ICSP, device programming specification.
Control Registers
There SFRs used read write program Flash memory: NVMCON NVMKEY. NVMCON register (Register 5-1) controls which blocks erased, which memory type programmed when programming cycle starts. NVMKEY write-only register that used write protection. start programming erase sequence, user must consecutively write NVMKEY register. Refer Section "Programming Operations" further details.
Programming Operations
table write operations single-word writes instruction cycles), because only buffers written. programming cycle required programming each row.
complete programming sequence necessary programming erasing internal Flash RTSP mode. During programming erase operation, processor stalls (waits) until operation finished. Setting (NVMCON<15>) starts operation automatically cleared when operation finished.
DS39905C-page
2009 Microchip Technology Inc.
PIC24FJ256GA110 FAMILY
REGISTER 5-1:
R/SO-0(1) Legend: Readable Value Only Writable Unimplemented bit, read cleared unknown R/W-0(1) ERASE R/W-0(1) NVMOP3(2) R/W-0(1) NVMOP2(2) R/W-0(1) NVMOP1(2)
NVMCON: FLASH MEMORY CONTROL REGISTER
R/W-0(1) WRERR R/W-0(1) NVMOP0(2) WREN
R/W-0(1)
Write Control bit(1) Initiates Flash memory program erase operation. operation self-timed cleared hardware once operation complete. Program erase operation complete inactive WREN: Write Enable bit(1) Enable Flash program/erase operations Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag bit(1) improper program erase sequence attempt termination occurred (bit automatically attempt bit) program erase operation completed normally Unimplemented: Read ERASE: Erase/Program Enable bit(1) Perform erase operation specified NVMOP<3:0> next command Perform program operation specified NVMOP<3:0> next command Unimplemented: Read NVMOP<3:0>: Operation Select bits(1,2) 1111 Memory bulk erase operation (ERASE operation (ERASE 0)(3) 0011 Memory word program operation (ERASE operation (ERASE 0010 Memory page erase operation (ERASE operation (ERASE 0001 Memory program operation (ERASE operation (ERASE These bits only reset POR. other combinations NVMOP<3:0> unimplemented. Available ICSPmode only. Refer device programming specification.
12-7
Note
2009 Microchip Technology Inc.
DS39905C-page
PIC24FJ256GA110 FAMILY
5.6.1 PROGRAMMING ALGORITHM FLASH PROGRAM MEMORY
user program Flash program memory time. this, necessary erase 8-row erase block containing desired row. general process follows: Read eight rows program memory (512 instructions) store data RAM. Update program data with desired data. Erase block (see Example implementation assembler): NVMOP bits (NVMCON<3:0>) `0010' configure block erase. ERASE (NVMCON<6>) WREN (NVMCON<14>) bits. Write starting address block erased into TBLPAG registers. Write NVMKEY. Write NVMKEY. (NVMCON<15>). erase cycle begins stalls duration erase cycle. When erase done, cleared automatically. Write first
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