Class Safety Software Library PIC® MCUs dsPIC® DSCs Author: Veena

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Class Safety Software Library PIC® MCUs dsPIC® DSCs
Author: Veena Kudva Microchip Technology Inc.
OVERVIEW 60730 STANDARD
Note: "The author thanks International Electrotechnical Commission (IEC) permission reproduce information from International Standard 60730-1ed.3.2 (2007). such extracts copyright IEC, Geneva, Switzerland. rights reserved. Further information available from www.iec.ch. responsibility placement context which extracts contents reproduced author, responsible other content accuracy therein."
INTRODUCTION
This application note describes Class Safety Software Library routines that detect occurrence Faults single channel CPU. These routines have been developed accordance with 60730 standard support Class certification process. These routines directly integrated with user's application test verify critical functionalities controller without affecting user's application. This application note also describes Application Programming Interface (API) functions that available Class Safety Software Library. Class safety software routines called periodically start-up time test following components: Registers Program Counter Invariable Memory Variable Memory Clock Interrupt Handling Execution
60730 standard defines test diagnostic methods that ensure safe operation controlled equipment used household appliances. Annex 60730 standard classifies software into following categories (see Appendix "IEC 60730-1 Table H.11.12.7"): Class Class Class Class Safety Software Library implements important test diagnostic methods that fall into Class category. These methods various measures detect respond softwarerelated Faults errors. According 60730 standard, controls with functions that fall into Class category should have following structures: Single Channel with Functional Test this structure, Functional test executed prior application firmware execution. Single Channel with Periodic Self-Test this structure, Periodic tests embedded within firmware, self-test occurs periodically while firmware Execution mode. Dual Channel without Comparison this structure, independent methods execute specified operations.
This application note also outlines various techniques, which part Class Safety Software Library, test components such external communication, timing, periphery, analog analog multiplexer. Note: term `IEC 60730 standard' used this document refers "IEC 60730-1 ed.3.2" Copyright 2007 IEC, Geneva, Switzerland. www.iec.ch.
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SYSTEM REQUIREMENTS
following system requirements recommended Class Safety Software Library: tests that require independent time slot monitoring, system hardware must provided with least independent clock sources (e.g., crystal oscillator line frequency). user application determines whether interrupts need enabled disabled during execution Class Safety Software Library. interrupt occurs during execution Class Safety Software Library routine, unexpected change occur registers. Therefore, when Interrupt Service Routine (ISR) executes, contents register will match expected content, will return incorrect result.
Register Test
Register test implements functional test H.2.16.5 defined 60730 standard. detects stuck-at Faults registers. This ensures that bits registers stuck value `1'; this non-destructive test. This test performs following major tasks: contents registers tested saved stack before executing routine. registers tested first successively writing values 0x5555 0xAAAA into registers, then reading values from these registers verification. test returns error code returned values match. contents register (W0) that return error code preserved. contents other registers restored upon completion test. Note: interrupts should disabled during execution Register test that data integrity preserved times.
CLASS SAFETY SOFTWARE LIBRARY
Class Safety Software Library includes several APIs, which intended maximize application reliability through Fault detection. These APIs help meet 60730 standard compliance. following tests implemented using this library: Register Test Program Counter Test Variable Memory Test Invariable Memory (Flash/EEPROM) Test Interrupt Test Clock Test
FUNCTIONS
following implements Register test:
following sections, test description implementation details discussed each test. addition, each section also lists APIs that required execute corresponding test.
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Program Counter Test
Program Counter test implements functional test H.2.16.5 defined 60730 standard. holds address next instruction executed. test performs following major tasks: Program Counter test invokes functions that located Flash memory different addresses. These functions return unique value. returned value verified using test function. values match, branched correct location. Note user application defines address where branches. size program memory varies device. Refer specific device data sheet more details. customized linker script defines addresses where these functions reside Flash memory. functions placed these addresses return unique value, which starting address called function. Example shows modify linker script place function Flash memory. this example, SSL_TestFunction1 function placed address 0x900 SSLTestSection1 section modifying linker script.
Invariable Memory (Flash/EEPROM) Test
Invariable Memory (Flash/EEPROM) test implements periodic modified checksum H.2.19.3.1 defined 60730 standard. detects single Faults invariable memory. invariable memory system, such Flash EEPROM memory, contains data that intended vary during program execution. Flash/EEPROM Invariable Memory test computes periodic checksum using Cyclic Redundancy Check (CRC). Several standards used today calculation. characteristics divisor vary from bits depending polynomial that used. width divisor determines ability detect errors. Some commonly used divisors follows: CRC-16 1000 0000 0000 0101 8005 (hex) CRC-CCITT 0001 0000 0010 0001 1021 (hex) CRC-32 0000 0100 1100 0001 0001 1101 1011 0111 04C11DB7 (hex) Figure shows flowchart Invariable Memory test. function returns final value that used perform following: system start-up, computed checksum used reference checksum CRC_Flag 0x00. reference checksum stored Flash EEPROM memory flag 0xFF. function called periodically flag 0xFF. checksum calculated from step compared with reference checksum. both values match, status user application indicate that invariable memory passed test errors were found.
FUNCTIONS
following implements Program Counter test: SSL_16bitsFamily_PCtest
FUNCTIONS
following APIs implement Invariable Memory test: Note: EEPROM test applies only dsPIC30F devices.
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EXAMPLE LINKER SCRIPT MODIFICATION
modified linker script SslTestSection1 0x900: *(.SslTestSection1); program /*The SSL_TestFunction1 function*/ long SSL_TestFunction1()
FIGURE
FLOWCHART INVARIABLE MEMORY TEST
Start
CRCFlag 0x00
Calculate Reference Checksum
Store Reference Checksum Flash/EEPROM Memory
CRCFlag 0xFF
Calculate Checksum Again
Load Reference Checksum
Reference Calculated
Pass/No Errors Found
Fail/Errors Found
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Variable Memory Test
Variable Memory test implements Periodic Static Memory test H.2.19.6 defined 60730 standard. detects single Faults variable memory. variable memory contains data, which intended vary during program execution. Memory test used determine memory stuck `0'. March Memory test Checkerboard test some widely used static memory algorithms checking Faults. following tests implemented using Class Safety Software Library: March Test March Test March Minus Test March Test
MARCH TEST
March test used detect following types Fault variable memory: Stuck-at Fault Addressing Fault Transition Fault Coupling Fault
complexity this test 11n, where indicates number bits memory. This test destructive test (i.e., memory contents preserved). Therefore, designed system start-up before initializing memory run-time libraries.
EXAMPLE
MarchC
MARCH ALGORITHM
MARCH TEST
March test performs finite operations every memory cell memory array. Each operation performs following tasks: Writes memory cell (w0). Writes memory cell (w1). Reads expected value from memory cell (r0). Reads expected value from memory cell (r1).
Example shows pseudocode that demonstrates implementation March test.
FUNCTIONS
following APIs implement March test: SSL_16bitsFamily_RAMtest_MarchC
March Test Notations
Example illustrates notations that used March test:
EXAMPLE
order.
MARCH TEST NOTATIONS
Arranges address sequence ascending Arranges address sequence descending
order.
Arranges address sequence either
ascending descending order.
Indicates read operation (reads from
memory cell).
Indicates read operation (reads from
memory cell).
Indicates write operation (writes
memory cell).
Indicates write operation (writes
memory cell). Note: Except "SSL_16bitsFamily_RAM_STACKtest _MarchC" function, remaining March memory test functions test Stack area RAM.
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EXAMPLE PSEUDOCODE MARCH TEST
/*write background zero*/ for(i=0;i<=(n-1);i++) x(i)=0; for(i=0;i<=(n-1);i++) (x(i)==0) x(i) else return fail; for(i=0;i<=(n-1);i++) if(x(i)==1) x(i)=0; else return fail; for(i=(n-1);i>=0;i-) if(x(i)==0) x(i)=1; else return fail; for(i=(n-1);i>=0;i-) if(x(i)==1) x(i)=0; else return fail; for(i=(n-1);i>=0;i-) if(x(i)==0) else return fail return pass;
MARCH MINUS TEST
March Minus test performs finite operations every memory location RAM. memory locations first tested ascending order then descending order. When memory locations tested ascending order, each operation performs following tasks every memory location: Writes 0xAAAA memory location. Reads 0xAAAA from memory location. Writes 0x5555 memory location. Reads 0x5555 from memory location. Writes 0xAAAA memory location
When memory locations tested descending order, each operation performs following tasks every memory location: Reads 0xAAAA from memory location. Writes 0x5555 memory location. Reads 0x5555 from memory location. Writes 0xAAAA memory location.
This test destructive test. Therefore, designed system start-up before initializing memory run-time libraries. Example shows pseudocode that demonstrates implementation March Minus test.
FUNCTIONS
following implements March Minus test:
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EXAMPLE PSEUDOCODE MARCH MINUS TEST
for(ptr=ramStartAddress; ptr<ramEndAddress; ptr++) 0xAAAA; for(ptr=ramStartAddress; ptr<ramEndAddress; ptr++) tempData=*ptr; if(tempData!=0xAAAA) return TEST_FAIL; else *ptr=0x5555; for(ptr=ramStartAddress; ptr<ramEndAddress; ptr++) tempData=*ptr; if(tempData!=0x5555) return TEST_FAIL; else *ptr=0xAAAA; for(ptr= ramEndAddress ptr>=(ramStartAddress);ptr-) tempData=*ptr; if(tempData!=0xAAAA) return TEST_FAIL; else *ptr=0x5555; for(ptr=ramEndAddress ptr>=(ramStartAddress);ptr-) tempData=*ptr; if(tempData!=0x5555) return TEST_FAIL; else *ptr=0xAAAA; return TEST_PASS;
//read 0xAAAA //Check 0xAAAA
//write 0X5555
//read 0x5555 //Check 0x5555
//write 0AAAA
//read 0xAAAA //Check 0xAAAA
//write 0x5555
//read 0x5555 //Check 0x5555
//write 0xAAAA
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MARCH TEST
March non-redundant test that detect following types Fault: Stuck-at Linked Idempotent Coupling Inversion Coupling This test complexity 17n, where indicates number bits memory.
CHECKERBOARD TEST
Checkerboard test writes checkerboard pattern memory location, `N', inverted pattern memory location, `N+1'. This non-destructive memory test. This test performs following major tasks: Saves contents memory locations tested registers. Writes value, 0xAAAA, memory location, `N', inverted value, 0x5555, memory location, `N+1'. Reads memory locations (`N' `N+1') verifies contents. values match, function returns `1'; otherwise returns `0'. Step repeated writing inverted pattern same locations.
EXAMPLE
March
MARCH ALGORITHM
w1); w0);
Example shows pseudocode that demonstrates implementation March test.
FUNCTIONS
following implements Checkerboard test:
FUNCTIONS
following implements March test: SSL_16bitsFamily_RAMtest_MarchB Note user application should allocate 0x50 bytes stack before executing March tests. stack must allocated appropriate address that does overwritten during test execution. recommended that stack should placed beginning data memory. user application should specify address such that does overlap other statically allocated resources (e.g., MPLAB® space which starts from address, 0x800). following changes made .gld file before executing March March test:
.stack 0x850: /*Stack Starting Address\* _SP_init 0x50; Stack length*/ _SPLIM_init >data
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EXAMPLE PSEUDOCODE MARCH TEST
/*write background zero*/ for(i=0;i<=(n-1);i++) x(i)=0; for(i=0;i<=(n-1);i++) if(x(i)=0) x(i)=1; else return fail; if(x(i)==1) x(i)=0; else return fail; if(x(i)==0) x(i)=1; else return fail; for(i=0;i<=(n-1);i++) if(x(i)==1) x(i)=0; x(i)=1; else return fail; for(i=(n-1);i>=0;i-) if(x(i)=1) x(i)=0; x(i)=1; x(i)=0; else return fail; for(i=(n-1);i>=0;i-) if(x(i)==0) x(i)=1; x(i)=0; else return fail; return pass;
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Interrupt Test
Interrupt test implements independent time slot monitoring H.2.18.10.4 defined 60730 standard. checks whether number interrupts that occurred within predefined range. goal Interrupt test verify that interrupts occur regularly. Interrupt test function invoked specified time intervals. triggered timer line frequency interrupt monitor verify interrupt operation. keep track interrupts that occur frequently, dedicated counter each decremented when interrupt occurs. example, Serial Peripheral Interface (SPI) configured generate interrupt every will generate least five interrupts When interrupt occurs, counter dedicated keep track interrupt decremented. Thus, counter initialized five, counter decremented zero This verified Interrupt test function that triggered after every keep track interrupts that occur rarely, dedicated counter within Interrupt test function decremented specific interrupt occur during last time interval. Refer example code, which available download from Microchip site (see Appendix "Source Code" details.).
CLOCK TEST USING SECONDARY OSCILLATOR
SSL_16bitsFamily_CLOCKtest function used verify proper operation clock when secondary oscillator used reference clock. This test performs following major tasks: secondary oscillator used independent clock source reference clock source. This oscillator used clock Timer1. primary oscillator with Phased-Lock Loop (PLL) clock source CPU. Timer2 runs clock frequency. Timer1 configured generate interrupt specified time intervals (e.g., ms). register Timer2 module holds time period value. must initialized value greater than that Timer2 does time-out before occurrence Timer1 interrupt. TMR2 value Timer2 saved within Timer1 interrupt handler. This value represents number clock cycles elapsed time period secondary oscillator. number clock cycles beyond defined boundary, function sets error flag.
Clock Test
According 60730 standard, only harmonics subharmonics clock need tested. Clock test implements independent time slot monitoring H.2.18.10.4 defined 60730 standard. verifies reliability system clock (i.e., system clock should neither fast slow): Depending choice reference clock, following Clock tests used: Clock Test Using Secondary Oscillator Clock Test Using Line Frequency
example, following parameters used calculate CLK_MIN_TIME CLK_MAX_TIME values dsPIC30F device: Primary Oscillator: XT_PLL8 FOSC: 7.37 FCY: FOSC/4: (7.37 10^6 8)/4 FCY: 14740000 Secondary Oscillator: Timer1 Period Register (PR1):
Therefore, with tolerance, number clock cycles (14740 cycles) are: CLK_MIN_TIME: 14150 CLK_MAX_TIME: 15330
FUNCTIONS
following implements Clock test: SSL_16bitsFamily_CLOCKtest
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CLOCK TEST USING LINE FREQUENCY
function used verify proper operation clock. Hz/60 line frequency used independent clock source reference clock source. input capture module used period measurement. Hz/60 line frequency Input Capture (IC1) respective device. This test performs following major tasks: IC1CON register configured follows: Timer2 selected time base. interrupt generated every second capture event. capture event generated every rising edge line frequency. Timer2 prescaler configured operate mode that timer count does time-out within ms/16.66 capture event generated every rising edge line frequency. period measurement, capture interrupt generated after taking time-stamps (see Figure difference between time-stamps provides timer period value. number cycles ms/16.66 line frequency computed follows: Number Clock Cycles ((V1 Timer2 Prescaler)
FUNCTIONS
following implements Clock test:
FIGURE
TIMER VALUE CAPTURE
TMR2 TMR3
Capture Event
Capture Interrupt (ICI<1:0> Read Captured Value
xxxx xxxx xxxx Capture xxxx xxxx Capture xxxx xxxx Capture
Read Captured Value
xxxx xxxx Capture
Capture FIFO
Note:
this illustration, timer ramp scale.
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Addressing Variable Invariable Memory Internal Data Path
single chip microcontrollers digital signal controllers, such MCUs dsPIC DSCs, Periodic Static Memory test used test variable memory, periodic checksum used test invariable memory. These tests detect stuck-at Fault internal address internal data path.
Timing
MCUs dsPIC DSCs have several dedicated communication interfaces, such UART, I2Cand modules. 60730 Class specifications suggest that these modules should time slot monitoring ensure that communication occurs correct point time.
Plausibility Check Addressing Wrong Address
This test required only microcontrollers with external memory device. plausibility checks periphery, analog multiplexer convertor performed follows:
External Communication
60730 Class specifications suggest following measures ensure reliable communication between components:
PERIPHERY
plausibility check performed toggling checking state pin.
ANALOG MULTIPLEXER
verify operation analog multiplexer, known voltage values applied channels. These values read compared with applied voltage verification.
TRANSFER REDUNDANCY
transfer redundancy Fault/error control technique that protects against coincidental and/or systematic errors input output information. achieved transferring data between transmitter receiver. data transferred least twice succession then compared.
CONVERTER
test analog functions converter, known external voltage applied analog inputs. conversion results then compared with applied voltage.
PROTOCOL TEST
Protocol test Fault/error control technique which data transferred from computer components detect errors internal communication protocol.
Functions
This section lists describes Application Programming Interface (API) functions that available Class Safety Software Library. functions listed below followed their individual detailed descriptions: SSL_16bitsFamily_PCtest SSL_16bitsFamily_RAMtest_MarchC SSL_16bitsFamily_RAMtest_MarchB SSL_16bitsFamily_CLOCKtest
SINGLE WORD
polynomial used calculate checksum transmitted message. transmitting end, this checksum appended message before transmitting receiving end, receiver uses same polynomial compute checksum, compares computed value with received value.
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Description
This function implements Register test. test successively writes values 0x5555 0xAAAA into registers then reads values from these registers verification. function returns error code values match. contents register (W0) that returns error code preserved. contents registers tested saved stack before executing routine restored upon completion test.
Include
None.
Prototype
Arguments
None.
Return Value
CPU_REGISTER_TEST_FAIL: return value CPU_REGISTER_TEST_PASS: return value
Remarks
None.
Source File
None.
TABLE
RESOURCE REQUIREMENTS
Parameter Requirements 1308 bytes (dsPIC30F/dsPIC33F) bytes (PIC24H/PIC24F) bytes (dsPIC30F/dsPIC33F) bytes (PIC24H/PIC24F) cycles (dsPIC30F/dsPIC33F) cycles (PIC24H/PIC24F)
Program Memory Stack Execution Time
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SSL_16bitsFamily_PCtest
Description
This function implements Program Counter test, which functional test Program Counter (PC). test invokes functions that located Flash memory different addresses. customized linker script defines addresses, where these functions reside Flash memory. functions placed these addresses return unique value, which starting address called function. This returned value verified using SSL_16bitsFamily_PCtest function.
Include
SSL_PcTest.h
Prototype
SSL_16bitsFamily_PCtest();
Arguments
None.
Return Value
PC_TEST_FAIL: return value PC_TEST_PASS: return value
Remarks
None.
TABLE
RESOURCE REQUIREMENTS
Parameter Requirements bytes bytes cycles
Program Memory Stack Execution Time
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Description
This function implements Invariable Memory test. computes data located between address FLASH_STARTADDRESS address FLASH_ENDADDRESS. This function returns final value.
Include
SSL_Flash_CRC.h
Prototype
unsigned (uReg32 startAddress,uReg32 endAddress, unsigned init_CrcValue);
ARGUMENTS
startAddress endAddress init_CrcValue Indicates starting address data tested Indicates ending address data tested Indicates initial value
Return Value
crc_Result Holds result
Remarks
None.
TABLE
RESOURCE REQUIREMENTS
Parameter Requirements bytes bytes cycles(1) execution time specified here single Flash memory location.
Program Memory Stack Execution Time Note
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Description
This function implements Invariable Memory test. computes data located between address, EEPROM_STARTADDRESS, address, EEPROM_ENDADDRESS. This function returns final value.
Include
SSL_EEPROM_CRC.h
Prototype
unsigned (uReg32 startAddress,uReg32 endAddress ,unsigned init_CrcValue);
Arguments
startAddress endAddress init_CrcValue Indicates starting address data tested Indicates ending address data tested Indicates initial value
Return Value
crc_Result Holds result
Remarks
None.
Source File
None.
TABLE
RESOURCE REQUIREMENTS
Parameter Requirements bytes bytes cycles(1) execution time specified here single EEPROM location.
Program Memory Stack Execution Time Note
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SSL_16bitsFamily_RAMtest_MarchC
Description
This function implements March test. This test accesses 16-bit word from memory. address must aligned data type length must integral multiple data width. This destructive test; therefore, this test executed system start-up before initializing memory run-time libraries. memory will cleared when control returns from SSL_16bitsFamily_RAMtest_MarchC function.
Include
SSL_MarchC.h
Prototype
ramStartAddress,int ramSize);
Arguments
ramStartAddress ramSize Indicates starting address from where March algorithm starts reading data Indicates number bytes that tested; size must even number
Return Value
MARCHC_RAM_TEST_FAIL: return value MARCHC_RAM_TEST_PASS: return value
Remarks
None.
Source File
SSL_MarchCRamTest.c
TABLE
RESOURCE REQUIREMENTS
Parameter Requirements bytes bytes 1254 cycles(1) execution time specified here single location.
Program Memory Stack Execution Time Note
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Description
This function implements March test memory stack. This test accesses 16-bit word from memory. address must aligned data type length must integral multiple data width. first tests memory then stack area transferring stack contents into tested area. After stack tested, restores contents stack. This destructive test; therefore, this test executed system start-up before initializing memory run-time libraries. memory will cleared when control returns from function.
Include
SSL_MarchC.h
Prototype
ramStartAddress,int ramSize);
Arguments
ramStartAddress ramSize Indicates starting address from where March algorithm starts reading data Indicates number bytes that tested; size must even number
Return Value
MARCHC_RAM_STACK_TEST_FAIL: MARCHC_RAM_STACK_TEST_PASS: return value return value
Remarks
None.
Source File
SSL_MarchCRamAndStackTest.c
TABLE
RESOURCE REQUIREMENTS
Parameter Requirements bytes bytes 1576 cycles(1) execution time specified here single location.
Program Memory Stack Execution Time Note
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Description
This function implements March Minus test. This test accesses 16-bit word from memory. address must aligned data type length must integral multiple data width. This destructive test (i.e., memory contents preserved); therefore, this test executed system start-up before initializing memory run-time libraries. memory will contain 0xAAAA when control returns from function.
Include
SSL_MarchC_Minus.h
Prototype
ramStartAddress,int ramSize);
Arguments
ramStartAddress ramSize Indicates starting address from where March algorithm starts reading data Indicates number bytes that tested; size must even number
Return Value
MARCHC_RAM_TEST_FAIL: MARCHC_RAM_TEST_PASS: return value return value
Remarks
None.
Source File
SSL_MarchC_MinusRamTest.c
TABLE
RESOURCE REQUIREMENTS
Parameter Requirements bytes bytes cycles(1) execution time specified here single location.
Program Memory Stack Execution Time Note
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SSL_16bitsFamily_RAMtest_MarchB
Description
This function implements March test. This test accesses 16-bit word from memory. address must properly aligned data type length must integral multiple data width. This destructive test; therefore, this test executed system start-up before initializing memory run-time library. memory will cleared when control returns from SSL_16bitsFamily_RAMtest_MarchB function.
Include
SSL_MarchB.h
Prototype
ramStartAddress,int ramSize);
Arguments
ramStartAddress ramSize Indicates starting address from where March algorithm starts reading data Indicates number bytes that tested; size must even number
Return Value
MARCHB_TEST_FAIL: return value MARCHB_TEST_PASS: return value
Remarks
None.
Source File
SSL_MarchBRamTest.c
TABLE
RESOURCE REQUIREMENTS
Parameter Requirements bytes bytes 1183 cycles(1) execution time specified here single location.
Program Memory Stack Execution Time Note
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Description
This function implements Checkerboard test memory. test performed memory space specified variable, RamSize. execution begins from address defined variable, RAMSTARTADDRESS. number specified locations must even.
Include
SSL_CBram.h
Prototype
*ramStartAddress,int RamSize);
Arguments
RamStartAddress RamSize Indicates starting address from where Checkerboard test performed Indicates number locations that tested; size must even number
Return Value
CB_TEST_FAIL: return value CB_TEST_PASS: return value
Remarks
None.
Source File
SSL_CheckerBoard.s
TABLE
RESOURCE REQUIREMENTS
Parameter Requirements bytes bytes cycles(1) execution time specified here single location.
Program Memory Stack Execution Time Note
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SSL_16bitsFamily_CLOCKtest
Description
This function implements Clock test. used verify proper operation clock. TMR2 value Timer2 saved within Timer1 interrupt handler. This value represents number clock cycles elapsed time period secondary oscillator. number clock cycles beyond defined boundary, function sets error flag.
Include
SSL_ClockTest.h SSL_ClockSwitch.h This file required only when PIC24F device used
Prototype
unsigned
Arguments
None.
Return Value
CLOCK_NO_ERROR CLOCK_ERROR clock operating within specified range clock operating within specified range
Remarks
None.
Source File
SSL_ClockTest.c
TABLE
RESOURCE REQUIREMENTS
Parameter Requirements bytes bytes cycles
Program Memory Stack Execution Time
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Description
This function implements line frequency Clock test. used verify proper operation clock. uses following procedure configure IC1CON register: Timer2 module selected time base. interrupt generated every second capture event. capture event generated every rising edge line frequency.
generates interrupt after every line frequency after every 16.66 line frequency Timer2 prescaler configured operate mode that timer count does time-out within ms/16.66 capture event generated every rising edge line frequency. period measurement, capture interrupt generated after taking time-stamps, (see Figure total number clock cycles calculated using following formula: Total Number Clock Cycles Timer Count Timer Prescaler. number clock cycles beyond defined boundary, function sets error flag.
Include
SSL_ClockTest_LineFreq.h SSL_ClockSwitch.h This file required only when PIC24F device used
Prototype
Arguments
None.
Return Value
CLOCK_NO_ERROR CLOCK_ERROR clock operating within specified range clock operating within specified range
Remarks
None.
Source File
SSL_ClockTest_LineFreq.c
TABLE
RESOURCE REQUIREMENTS
Parameter Requirements bytes bytes cycles
Program Memory Stack Execution Time
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SUMMARY
This application note describes implement various diagnostic measures proposed 60730 standard. These measures ensure safe operation controlled equipment that falls under Class category. addition, this application note also describes different APIs that available Class Safety Software Library. These APIs directly integrated with user's application test verify critical functionalities controller intended maximize application reliability through Fault detection. When implemented dsPIC microcontroller, these APIs help meet 60730 standard's requirements. Microchip developed Class Safety Software Library assist implementing safety software routines. Contact your Microchip sales application engineer would like further support.
REFERENCES
60730 Standard, "Automatic Electrical Controls Household Similar Use", 60730-1 Edition 3.2, 2007-03 Bushnell, Agarwal, "Essentials Electronic Testing Digital, Memory, Mixed-Signal VLSI Circuits" York: Springer, 2000. Corr. printing, 2005 "Memory Testing" "RAM Fault Models Memory Testing" Suk, D.S. Reddy, S.M. March Test Functional Faults Semiconductor Random-Access Memories", lEEE Trans. Computers, Vol. C-30, 1981, 982-985
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APPENDIX SOURCE CODE
Software License Agreement
software supplied herewith Microchip Technology Incorporated (the "Company") intended supplied you, Company's customer, solely exclusively with products manufactured Company. software owned Company and/or supplier, protected under applicable copyright laws. rights reserved. violation foregoing restrictions subject user criminal sanctions under applicable laws, well civil liability breach terms conditions this license. THIS SOFTWARE PROVIDED CONDITION. WARRANTIES, WHETHER EXPRESS, IMPLIED STATUTORY, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE APPLY THIS SOFTWARE. COMPANY SHALL NOT, CIRCUMSTANCES, LIABLE SPECIAL, INCIDENTAL CONSEQUENTIAL DAMAGES, REASON WHATSOEVER.
software covered this application note available single WinZip archive file. This archive downloaded from Microchip corporate site www.microchip.com
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APPENDIX 60730-1 TABLE H.11.12.7
following table reproduced with permission International Electrotechnical Commission (IEC). 60730-1 ed.3.2 "Copyright 2007 IEC, Geneva, Switzerland. www.iec.ch".
TABLE B-1:
H.11.12.7
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TABLE B-1: H.11.12.7 (CONTINUED)
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TABLE B-1: H.11.12.7 (CONTINUED)
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TABLE B-1: H.11.12.7 (CONTINUED)
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TABLE B-1: H.11.12.7 (CONTINUED)
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Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
Code protection constantly evolving. Microchip committed continuously improving code protection features products. Attempts break Microchip's code protection feature violation Digital Millennium Copyright Act. such acts allow unauthorized access your software other copyrighted work, have right relief under that Act.
Information contained this publication regarding device applications like provided only your convenience superseded updates. your responsibility ensure that your application meets with your specifications. MICROCHIP MAKES REPRESENTATIONS WARRANTIES KIND WHETHER EXPRESS IMPLIED, WRITTEN ORAL, STATUTORY OTHERWISE, RELATED INFORMATION, INCLUDING LIMITED CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY FITNESS PURPOSE. Microchip disclaims liability arising from this information use. Microchip devices life support and/or safety applications entirely buyer's risk, buyer agrees defend, indemnify hold harmless Microchip from damages, claims, suits, expenses resulting from such use. licenses conveyed, implicitly otherwise, under Microchip intellectual property rights.
Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt UNI/O registered trademarks Microchip Technology Incorporated U.S.A. other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2008, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
2008 Microchip Technology Inc.
DS01229A-page
WORLDWIDE SALES SERVICE
AMERICAS
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ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 China Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049
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01/02/08
DS01229A-page
2008 Microchip Technology Inc.

Class Safety Software Library PIC® MCUs dsPIC® DSCs Author: Veena

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