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Using External Data Memory with PIC24F/24H/dsPIC33F Devices Autho


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AN1210
Using External Data Memory with PIC24F/24H/dsPIC33F Devices
Author: Vidyadhar Vivekananda Microchip Technology Inc.
Signals Required Interfacing Memory Devices
Table provides signals required interface different types memory devices.
INTRODUCTION
This application note describes methodology Parallel Master Port (PMP) module interface with external data memory; either external Flash external RAM. This application note also lists APIs describes implement different types interfaces. Using module, memory devices with locations (Kbytes words) interfaced with extra I/Os software. This application note describes interface memory devices with more than locations using some pins provides required APIs. This application note describes following topics: "External Data Memory Interface Overview" "Functional Implementation" "Expansion External Memory" "Reference Code"
TABLE
Name
TYPICAL MEMORY DEVICE INTERFACE CONNECTIONS
Function number lines required address memory locations Kbytes/K words memory device. Data Lines required read/write data byte word memory device. Chip Enable signal each memory device. Write Enable signal, which should active whenever data written into memory device. Output Enable signal, which should active whenever data read from memory device.
Address Lines
Data Lines (I/O Chip Enable (CE) Write Enable (WE)
EXTERNAL DATA MEMORY INTERFACE OVERVIEW
PIC24F/24H/dsPIC33F architecture supports Kbytes internal data memory. internal memory insufficient, external memory used. But, this external memory cannot directly accessed controller. access through module. This section describes topics: Signals Required Interfacing Memory Devices Signals Generated Module Registers Associated with Module
Output Enable (OE)
Byte Enable signal Word/Byte signal, Byte Enable (A-1) memory device 16-bit Word/Byte device supports both Word Byte modes.
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Signals Generated Module
module enables interfacing with many types parallel devices. module configured either master slave. There mainly ways interfacing read write signals: Read write signals generated different pins (most memory devices this type interface). Read write signals generated same with separate enable signals. module Master mode allows selection different wait states suit electrical characteristics particular memory device signals used interface with memory devices address bus, data bus, read signal, write signal, chip select (optional), address latch signal required) byte enable case 16-bit data).
DATA LINES
PMD0 PMD7 data lines): 8-bit operation, 8-bit data transmitted/received through these lines. 16-bit operation, 16-bit data divided into Least Significant Byte (LSB) Most Significant Byte (MSB). First transmitted/received through these lines, then MSB.
CONTROL LINES
PMCS1 PMCS2 chip select lines) These lines multiplexed with PMA14 PMA15. chip select signals selected, address lines necessarily reduced. PMWR used write line enable signal. interface with memory device, should used write line. PMRD used read line read/write line. interface with memory device, should used read line. PMBE byte enable line, used during 16-bit data operation. goes active inactive LSB. PMALL PMALH address latch lines required only when address multiplexed with data bus. There methods multiplexing: Multiplexing only lower 8-bit address lines with 8-bit data lines. this method, PMALL generated PMA0 line. This used latch lower byte address. Multiplexing both lower 8-bit higher 8-bit address lines with 8-bit data lines. this method, PMA0 becomes PMALL PMA1 becomes PMALH. PMALH used latch higher byte address. Figure illustrates signals generated module that useful when interfacing with memory device.
ADDRESS LINES
PMA0 PMA15 address lines available): PMA14 multiplexed with PMCS1 pin. PMA15 multiplexed with PMCS2 pin. locations accessed when Chip Select mode selected. locations memory accessed when only Chip Select mode selected. locations (i.e., locations memory accessed when Chip Select modes selected.
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FIGURE MEMORY INTERFACE PINS
16-Bit Address (PMA<15:0>) 8/16-Bit Data (PMD<7:0>) Write (PMWR) Read (PMRD) Chip Selects (PMCS1 PMCS2) Address Latch (PMALL) Address Latch High (PMALH) Byte Enable (PMBE)
PIC24F
Control Signals
Address Data Control Lines
TABLE
MEMORY INTERFACE PINS
Pins Associated with Module PMA0 PMAn PMA15) PMALL PMALH case address multiplexed with data) PMD0 PMD7 PMCS2 PMCS1 PMWR PMRD PMBE
Memory Device Pins Address Lines Data Lines (I/O Chip Enable (CE) Write Enable (WE) Output Enable (OE) Byte Enable (A-1)
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Registers Associated with Module
following registers associated with module Master mode: PMCON Parallel Master Port Control register PMMODE Parallel Master Port Mode Selection register PMAEN Parallel Master Port Address Enable register PMADDR Parallel Master Port Address register PMDIN1 Parallel Master Port Data register
PMAEN REGISTER
PMAEN register controls these functions: Enables Chip Select 2/Address (PMCS2/PMA15) port Enables Chip Select 1/Address (PMCS1/PMA14) port Enables Address 13:2 (PMA<13:2>) ports Enables Address 1/Address High Latch (PMA1/PMALH) port Enables Address 0/Address Latch (PMA0/PMALL) port
PMCON REGISTER
PMCON register controls these functions: Enables module Selects/deselects module Idle mode Selects different modes data address multiplexing Enables disables byte enable signal (PMBE) (byte enable signal used only 16-Bit Data mode) Enables write signal (PMWR) Enables read signal (PMRD) Selects chip select signal higher address lines Selects polarity address latch signals, PMALL PMALH, used when address data lines multiplexed. (The signal polarity state that signal when active; signal will have opposite state when Idle.) Selects polarity Chip Select signal (PMCS2) when Chip Select used Selects polarity Chip Select signal (PMCS1) when Chip Select used Selects polarity byte enable signal (PMBE) when 16-Bit Data mode opted Selects polarity write signal (PMWR) Selects polarity read signal (PMRD)
PMADDR REGISTER
This register holds address memory location accessed. This either remains unchanged, increments decrements data access PMMODE configuration.
PMDIN1 REGISTER
This register holds data read while reading, holds data written while writing. When configured 8-Bit Data mode, only PMDIN1 register valid. Note: more information these registers, refer specific device data sheet.
Wait States Their Usage
memory devices have setup time, hold time control signal width specifications. meet these specifications, three Wait states configured module. Setup time configured between TCY, setup time independently configurable only when address lines data lines multiplexed. When address lines data lines multiplexed, setup time width address phase data both configured using common bits. Hold time also configured between TCY. control signals (read write) pulse width (control signal width) configured between TCY. When Wait states disabled, setup time TCY, hold time TCY, control signal width address width data lines (when address data multiplexed) TCY. Figure Figure depict effect using Wait states.
PMMODE REGISTER
PMMODE register controls these functions: Determines status, whether module busy Selects when interrupt flag Selects either auto-increment decrement address Selects 8-Bit 16-Bit Data mode Selects between Master Slave modes. (For memory interface, select Master mode with separate read write signals.) Selects different Wait periods (For more information, refer "Wait States Their Usage" section.)
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FUNCTIONAL IMPLEMENTATION
This section describes interfaces implemented this application note. following topics described: Interfacing 8-bit memory device (with chip select permanently activated) Interfacing 8-bit memory device Interfacing 8-bit memory devices Interfacing 16-bit word memory device
Interfacing 8-Bit Memory Device (with Chip Enable Permanently Activated)
interface 8-bit memory device, address lines required. module generate 16-bit address (16-bit address available only when chip select enabled). Figure illustrates 8-bit memory device would connected. Figure provides timing diagram (PMCS2 should ignored chip enable permanently activated). observed that each read write operation takes instruction cycle. Table provides register configurations associated registers. APIs provided with this application note this configuration, uncomment following lines MIDefn.h file: #define Single64KBChipNoCS #define NoAddressDataMux
FIGURE
BLOCK DIAGRAM 8-BIT MEMORY DEVICE INTERFACE
PIC24F PMA<15:0> PMD<7:0> Memory A<15:0> D<7:0>
PMRD
Address Data Control Lines
PMWR
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TABLE CONFIGURATION REGISTERS INTERFACING 8-BIT MEMORY DEVICE USING ADDRESS LINES CHIP ENABLE PERMANENTLY ACTIVATED
Value 10x0001100xxxx00 PMMOD 00xxx010xxxxxxxx Description module enabled Select run/stop Idle mode Address data separate pins PMBE port disabled PMWR port enabled PMRD port enabled PMCS1 PMCS2 functioning PMA15 PMA14 Address latch signal polarity irrelevant address latch signals used) PMCS2 polarity irrelevant PMCS2 used) PMCS1 polarity irrelevant PMCS1 used) Byte enable irrelevant byte enable used) Write strobe polarity, active-low Read strobe polarity, active-low Busy status Whether interrupted read/write Auto-increment/decrement auto-change address 8-Bit Data mode Master mode with separate read write strobes Required data setup time Required read/write strobe width Required data hold time after strobe
Register PMCON
PMAEN PMADDR PMDIN1
1111111111111111 xxxxxxxxxxxxxxxx
Enable many address line ports required Address register Data register
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Interfacing 8-Bit Memory Device
While interfacing 8-bit memory device, chip enable memory device connected ground. chip select generated used connect chip enable memory device, then only address lines will left, hence, only 8-bit memory device interfaced. this interface three multiplexing modes described. These three modes also used during other interfaces described this application note. three multiplexing modes are: Multiplex mode (address data demultiplexed) Partially Multiplexed mode (lower address multiplexed with data) Fully Multiplexed mode (both lower higher bytes address multiplexed with data)
DEMULTIPLEXED MODE
this mode, address data lines have separate pins. Figure illustrates interface between 8-bit memory device PIC24F device. Figure provides timing diagram. Demultiplex mode, each read write operation takes instruction cycle. Table provides register configurations associated registers. APIs provided with this application note this configuration, uncomment following lines MIDefn.h file: #define Single32KBChip #define NoAddressDataMux
FIGURE
8-BIT MEMORY DEVICE INTERFACE (DEMULTIPLEXED MODE)
PIC24F PMA<14:0> PMD<7:0> Memory A<14:0> D<7:0>
PMCS2 PMRD PMWR
Address Data Control Lines
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TABLE
Register PMCON
CONFIGURATION REGISTERS INTERFACING 8-BIT MEMORY DEVICE (DEMULTIPLEXED MODE)
Value 10x0001101x0xx00 Description module enabled Select run/stop Idle mode Address data separate pins PMBE port disabled PMWR port enabled PMRD port enabled PMCS1 functioning PMA14 PMCS2 chip select Address latch signal polarity irrelevant address latch signal used) PMCS2 polarity PMCS1 polarity irrelevant PMCS1 used) Byte enable polarity irrelevant byte enable used) Write strobe polarity, active-low Read strobe polarity, active-low Busy status Whether interrupted read/write Auto-increment/decrement auto-change address 8-Bit Data mode Master mode with separate read write strobes Required data setup time Required read/write strobe width Required data hold time after strobe
PMMODE
00xxx010xxxxxxxx
PMAEN PMADDR PMDIN1
1111111111111111 1xxxxxxxxxxxxxxx
Enable PMCS2 port Enable many address line ports required Address register (bit enables PMCS2 bits<14:0> address bits) Data register
FIGURE
READ WRITE TIMING WHEN ADDRESS DATA DEMULTIPLEXED
PMCS2
PMA<14:0>
PMD<7:0>
PMRD
PMWR
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PARTIALLY MULTIPLEXED MODE
Partially Multiplexed mode, lower address byte lines multiplexed with PMD<7:0> pins. higher address byte lines PMA<14:8> pins. PMA0 becomes PMALL pin; this latches lower address byte. Therefore, seven pins (PMA<7:1>) available (free from module) other purposes. Figure illustrates interface 8-bit memory device with lower address byte lines multiplexed with data lines. Figure provides timing diagram. Partially Multiplexed mode, each read write operation takes instruction cycles. Table provides register configurations associated registers. APIs provided with this application note this configuration, uncomment following lines MIDefn.h file: #define Single32KBChip #define LowAddressDataMux
FIGURE
PIC24F
8-BIT MEMORY DEVICE INTERFACE USING PARTIALLY MULTIPLEXED MODE
Memory A<14:0>
PMD<7:0> PMALL A<14:8> PMA<14:8> D<7:0> D<7:0> Address Data Control Lines Address/Data Multiplexed
PMCS2 PMRD PMWR
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TABLE
Register PMCON
CONFIGURATION REGISTERS INTERFACING 8-BIT MEMORY DEVICE USING PARTIAL MULTIPLEXED MODE
Value 10x010110110xx00(1) Description module enabled Select run/stop Idle mode Higher address byte separate pins lower address byte multiplexed with data pins PMBE port disabled PMWR port enabled PMRD port enabled PMCS1 functioning PMA14 PMCS2 chip select(1) Address latch signal high (for latch) PMCS2 polarity PMCS1 polarity irrelevant PMCS1 used) Byte enable polarity irrelevant byte enable used) Write strobe polarity, active-low Read strobe polarity, active-low Busy status Whether interrupted read/write Auto-increment/decrement auto-change address 8-Bit Data mode Master mode with separate read write strobes Required width address data lines Required read/write strobe width Required data hold time after strobe
PMMODE
00xxx010xxxxxxxx
PMAEN
1111111100000001
Enable PMCS2 port Enable many higher address line ports required Enable PMALL port Address register (bit enables PMCS2 bits<14:0> address bits) Data register
PMADDR PMDIN1
1xxxxxxxxxxxxxxx(1)
Note chip select used, PMCON 10x01011001xxx00 PMADDR xxxxxxxxxxxxxxxx.
FIGURE
READ WRITE TIMING WHEN ADDRESS DATA LINES PARTIALLY MULTIPLEXED
PMCS PMA<14:8>
PMD<7:0>
PMD<7:0> PMRD
PMA<7:0>
PMA<7:0>
PMD<7:0>
PMWR PMALL
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FULLY MULTIPLEXED MODE
fully multiplexed mode, lower higher address byte lines multiplexed with PMD<7:0>. PMA0 becomes PMALL pin; this latches lower address byte. PMA1 becomes PMALH pin; this latches higher address byte. Therefore, pins (PMA<14:2>) available (free from module) other purposes. Figure illustrates interface 8-bit memory device, with lower address byte lines higher address byte lines, multiplexed with data lines. Figure provides timing diagram. this mode, each read write takes three instruction cycles. Table provides register configurations associated registers. APIs provided with this application note this configuration, uncomment following lines MIDefn.h file: #define Single32KBChip #define FullAddressDataMux
FIGURE
8-BIT MEMORY DEVICE INTERFACE USING FULLY MULTIPLEXED MODE
PIC24F Memory PMD<7:0> PMALL A<7:0> D<7:0> A<14:0> D<7:0>
PMALH PMCS2 PMRD PMWR A<14:8> Address Data Control Lines Address/Data Multiplexed
FIGURE
READ WRITE TIMING WHEN ADDRESSES FULLY MULTIPLEXED WITH DATA
PMD<7:0> PMD<7:0> PMA<7:0> PMA<14:8> PMA<7:0> PMA<14:8> PMD<7:0>
PMRD PMWR PMALL PMALH
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TABLE
Register PMCON
CONFIGURATION REGISTERS INTERFACING 8-BIT MEMORY DEVICE USING FULLY MULTIPLEXED MODE
Value 10x100110110xx00(1) Description module enabled Select run/stop Idle mode Lower address higher address multiplexed with data pins PMBE port disabled PMWR port enabled PMRD port enabled PMCS1 functioning PMA14 PMCS2 chip select(1) Address latch signal polarity high (for latch) PMCS2 polarity PMCS1 polarity irrelevant PMCS1 used) Byte enable polarity irrelevant byte enable used) Write strobe polarity, active-low Read strobe polarity, active-low Busy status Whether interrupted read/write Auto-increment/decrement auto-change address 8-Bit Data mode Master mode with separate read write strobes Required width address data lines Required read/write strobe width Required data hold time after strobe
PMMODE
00xxx010xxxxxxxx
PMAEN
1000000000000011(1)
Enable PMCS2 port Enable PMALH port Enable PMALL port Address register (bit enables PMCS2 bits<14:0> address bits) Data register
PMADDR PMDIN1
1xxxxxxxxxxxxxxx(1)
Note chip select used, PMCON 10x10011001xxx00, PMAEN 0000000000000011 PMADDR xxxxxxxxxxxxxxxx.
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Interfacing 8-Bit Memory Devices
interface memory devices, chip selects required; therefore, only address bits generated module. this configuration, only memory devices 8-bit) connected. Figure illustrates interface 16-Kbyte memory devices. Figure provides timing diagram. timing diagram illustrates only PMCS2. Similarly, when first chip accessed, PMCS1 becomes active instead PMCS2. Table provides register configurations associated registers. APIs provided with this application note this configuration, uncomment following lines MIDefn.h file: #define Two16KBChips #define FullAddressDataMux
FIGURE
INTERFACING 8-BIT MEMORY DEVICES
<7:0> <7:0> <13:8> PMALH PMRD PMWR PMCS1 Memory A<13:0> D<7:0>
PIC24F PMD<7:0> PMALL
Memory A<13:0> D<7:0>
PMCS2 Address Data Control Lines Address/Data Multiplexed
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TABLE
Register PMCON
CONFIGURATION REGISTERS INTERFACING 8-BIT MEMORY DEVICES USING FULLY MULTIPLEXED MODE
Value 10x1001110100x00(1,2) Description module enabled Select run/stop Idle mode Address data fully multiplexed(1,2) PMBE port disabled PMWR port enabled PMRD port enabled PMCS1 PMCS2 chip selects Address latch signal polarity high(2) PMCS2 polarity PMCS1 polarity Byte enable polarity irrelevant byte enable used) Write strobe polarity, active-low Read strobe polarity, active-low Busy status Whether interrupted read/write Auto-increment/decrement auto-change address 8-Bit Data mode Master mode with separate read write strobes Required data setup time Required read/write strobe width Required data hold time after strobe Enable PMCS2 port Enable PMCS1 port Enable PMALL port Enable PMALH port
PMMODE
00xxx010xxxxxxxx
PMAEN
1100000000000011(1,2)
PMADDR PMDIN1
xxxxxxxxxxxxxxxx
Address register (bit enables PMCS2, enables PMCS1 bits<13:0> address bits) Data register
Note partial address multiplexed with data lines, PMCON 10x0101110100x00 PMAEN 1111111100000001. address data separate lines, PMCON 10x0001110000x00 PMAEN 1111111111111111.
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Interfacing 16-Bit Word Memory Device
interface 16-bit memory device, data lines required. module only data lines. 16-bit data split into 8-bit data phases, first phase then phase. Figure Figure illustrate interface 16-bit memory device. Some 16-bit memory devices support both word byte access. These devices will have pin, which decides byte accessed while Byte mode. should noted that using Byte Access mode. PMBE should connected this pin, illustrated Figure memory device supports only Word Access mode, connections made illustrated Figure Figure provides timing diagram. 16-bit mode, each read write takes extra instruction cycle same operation 8-bit mode. Hence, Fully Multiplexed mode with 16-bit data, each read write takes four instruction cycles. Table provides register configurations associated registers. APIs provided with this application note this configuration, uncomment following lines MIDefn.h file: #define Data16bit #define HighByteEnb, polarity byte enable signal should high #define FullAddressDataMux
FIGURE
16-BIT MEMORY DEVICE (EXAMPLE
PIC24F PMD<7:0> PMALL D<7:0> D<7:0> A<14:8> PMBE PMRD PMWR PMCS2 Address Data Control Lines Address/Data Multiplexed Word/Byte A<7:0> Memory A<14:0>
PMALH
FIGURE
16-BIT MEMORY DEVICE, ADDRESS DATA MULTIPLEXED (EXAMPLE
PIC24F PMD<7:0> PMALL Parallel 16-Bit Device A<7:0> A<14:0> D<15:0> PMALH D<7:0> PMBE A<14:8>
D<15:8> PMRD PMWR PMCS2 Address Data Control Lines Address/Data Multiplexed
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TABLE
Register PMCON
CONFIGURATION REGISTERS INTERFACING 16-BIT MEMORY DEVICE USING FULLY MULTIPLEXED MODE
Value 10x101110110x100(1,2,3,4,5) Description module enabled Select run/stop Idle mode Address data fully multiplexed(1,2,4,5) PMBE port enabled PMWR port enabled PMRD port enabled PMCS1 functioning PMA14 PMCS2 chip select(3,4,5) Address latch signal polarity high(2,5) PMCS2 polarity PMCS1 polarity irrelevant(3,4,5) Byte enable polarity active-high Write strobe polarity active-low read strobe polarity active-low Busy status interrupted read/write Auto-increment/decrement auto-change address 16-Bit Data mode Master mode with separate read write strobes Required width address data lines Required read/write strobe width Required data hold time after strobe
PMMODE
00xxx110xxxxxxxx
PMAEN
1000000000000011(1,2,3,4,5)
Enable PMCS2 port Enable PMALH port Enable PMALL port Address register (bit enables PMCS2 bits<14:0> address bits) Data register
PMADDR PMDIN1
1xxxxxxxxxxxxxxx(3,4,5)
Note partial address multiplexed with data lines, PMCON 10x011110110x100 PMAEN 1111111100000001 (this full 15-bit address). address data separate lines, PMCON 10x001110100x100 PMAEN 1111111111111111 (this full 15-bit address). full address multiplexed with data lines with chip selects, PMCON 10x1011110100100, PMAEN 1100000000000011 (this full 14-bit address) PMADDR 11xxxxxxxxxxxxxx. partial address multiplexed with data lines with chip selects, PMCON 10x0111110100100, PMAEN 1111111100000011 (this full 14-bit address) PMADDR 11xxxxxxxxxxxxxx. address data separate lines with chip selects, PMCON 10x0011110000100, PMAEN 1111111111111111 (this full 14-bit address) PMADDR 11xxxxxxxxxxxxxx.
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FIGURE READ TIMING WHEN ADDRESSES FULLY MULTIPLEXED WITH DATA 16-BIT DATA MODE
PMCS2 PMD<7:0> PMRD PMWR PMALL PMALH PMBE PMA<7:0> PMA<14:0> PMD<7:0> PMD<15:0>
FIGURE
WRITE TIMING WHEN ADDRESSES FULLY MULTIPLEXED WITH DATA 16-BIT DATA MODE
PMCS2 PMD<7:0> PMRD PMWR PMALL PMALH PMBE PMA<7:0> PMA<14:0> PMD<7:0> PMD<15:0>
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FIGURE READ WRITE TIMING WHEN ADDRESS DATA MULTIPLEXED WAIT STATES ENABLED
TCY(2) TCY(1) PMCS2 PMA<14:0> PMD<7:0> PMRD PMWR TCY(1) TCY(2) TCY(3)
Note Depends setup time settings. Depends control signal width settings. Depends hold time settings.
FIGURE
READ WRITE TIMING WHEN ADDRESS DATA FULLY MULTIPLEXED WAIT STATES ENABLED
TCY(1)
TCY(2)
TCY(1) TCY(1) TCY(2) TCY(1)
TCY(3)
PMCS2
TCY(1)
PMD<7:0> PMRD
PMA<7:0> PMA<14:8>
PMD<7:0>
PMA<7:0> PMA<14:8>
PMD<7:0>
PMWR
PMALL
PMALH
Note Depends setup time settings. Depends control signal width settings. Depends hold time settings.
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EXPANSION EXTERNAL MEMORY
External data memory expanded ways: Interfacing single memory device sizes more than Kbytes (APIs support Mbytes) Interfacing multiple memory devices Kbytes each (APIs support devices) Table provides register configurations associated registers. APIs provided with this application note this configuration, uncomment following lines MIDefn.h file: #define SingleMorethan32KBChip #define AddressHighPort LATx (where LATx LATA, LATB, LATC, LATD LATE) #define NumberofAddedAdrsLine (where anything between Note: APIs support expansion interface Mbytes memory (generating address lines A22:A15).
Interfacing Single Memory Device More than Kbytes Mbytes)
this interface, address lines generated module. higher address byte lines should generated software using general purpose pins. implement this: Define variable Address_High, which would have Select port output higher address byte content Address_High variable. sequential read write, increment variable, Address_High, every overflow address generated module.
Figure illustrates interface single chip with memory size more than Kbytes.
FIGURE
PIC24F
INTERFACING SINGLE CHIP MORE THAN Kbytes MEMORY
Memory PMD<7:0> PMALL D<7:0> A<7:0> A<14:0>
D<7:0>
PMALH PMCS2 PMRD PMWR
A<14:8>
Address Data Control Lines Address/Data Multiplexed
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TABLE
Register PMCON
CONFIGURATION INTERFACING SINGLE CHIP MORE THAN Kbytes MEMORY
Value 10x100110110xx00(1,2,3) Description module enabled Select stop/run Idle mode Address data fully multiplexed(1,2) PMBE port disabled PMWR port enabled PMRD port enabled PMCS1 functioning PMA14 PMCS2 chip select(3) Address latch signal polarity, active-high(2) PMCS2 polarity active-low(3) PMCS1 polarity irrelevant PMCS1 used) Byte enable polarity irrelevant byte enable used) Write strobe polarity, active-low Read strobe polarity, active-low Busy status Whether interrupted read/write Auto-increment/decrement auto-change address 16-Bit Data mode Master mode with separate read write strobes Required width address data lines Required read/write strobe width Required data hold time after strobe
PMMODE
00xxx110xxxxxxxx
PMAEN
1000000000000011(1,2)
Enable PMCS2 port Enable PMALH port Enable PMALL port Address register Address register (bit enables PMCS2 bits<14:0> address bits) Data Register
Address_High Higher PMADDR PMDIN1
1xxxxxxxxxxxxxxx
Note partial address multiplexed with data lines, PMCON 10x01011001xxx00 PMAEN 1111111100000001. address data separate lines, PMCON 10x00011000xxx00 PMAEN 1111111111111111. chip select used, then PMCON 10x10011001xxx00.
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Interfacing Multiple Memory Devices Kbytes Each devices)
technique address multiple memory devices discrete demultiplexer chip select signal. Port provide binary encoded value select desired memory device. This implemented defining variable hold desired demultiplexer channel. Moving this value Port Latch register will activate selected memory chip. sequential read write operations, variable incremented every address overflow. implement this, perform following steps: Define variable, Chip_Select, selectively enable disable different chips. Select port output contents variable, Chip_Select. sequential read write, increment variable, Chip_Select, every overflow address generated module. Figure illustrates interface multiple chips Kbytes memory size. using this method, number pins required generate chip selects reduced. Table provides register configurations associated registers. APIs provided with this application note this configuration, uncomment following lines MIDefn.h file: #define More32KBChips #define ChipSelectPort LATx (where LATx LATA, LATB, LATC, LATD LATE) #define NumberofAddedCSLine (where anything between Note: APIs provide support expansion Mbytes memory (generating select signals, Sel<3:1>, demultiplexer).
FIGURE
INTERFACING MULTIPLE Kbytes MEMORY DEVICES
PIC24F PMD<7:0> PMALL A<7:0> D<7:0> A<14:8> PMALH PMRD PMWR PMCS2 Memory A<14:0> D<7:0>
Demultiplexer
Memory A<14:0> D<7:0>
Address Data Control Lines Address/Data Multiplexed
Note: number select signals required enable number memory devices where `n'=2m.
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TABLE
Register PMCON
CONFIGURATION REGISTERS INTERFACING MULTIPLE Kbytes MEMORY DEVICES
Value 10x10011010xxx00(1,2) Description module enabled Select stop/run Idle mode Address data fully multiplexed(1,2) PMBE port disabled PMWR port enabled PMRD port enabled PMCS1 functioning PMA14 PMCS2 chip select Address latch signal polarity active-high(2) PMCS2 polarity active-low PMCS1 polarity irrelevant PMCS1 used) Byte enable polarity irrelevant byte enable used) Write strobe polarity, active-low Read strobe polarity, active-low Busy status Whether interrupted read/write Auto-increment/decrement auto-change address 16-Bit Data mode Master mode with separate read write strobes Required data setup time Required read/write strobe width Required data hold time after strobe
PMMODE
00xxx110xxxxxxxx
PMAEN
1000000000000011(1,2)
Enable PMCS2 port Enable PMALH port Enable PMALL port Address register (bit enables PMCS2 bits<14:0> address bits) Data register Current Chip_Select information
PMADDR PMDIN1 Chip_Select
1xxxxxxxxxxxxxx
Note partial address multiplexed with data lines, PMCON 10x01011001xxx00 PMAEN 1111111100000001. address data separate lines, PMCON 10x00011000xxx00 PMAEN 1111111111111111.
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REFERENCE CODE
This section describes APIs provided reference code interface different types memory devices. implement interfaces described this application note, following APIs provided: PMPInit() Initializes module macros defined MIDefn.h file. MemByteRead() Returns byte read from specified memory address location. MemBulkRead() Reads specified length sequential data from specified memory location stores specified array. MemByteWrite() Writes byte passed into specified memory location. MemBulkWrite() Writes specified length data stored array into memory locations from specified address. these APIs, MemInterface.c, MemInterface.h MIDefn.h files your project. Edit MIDefn.h file required. selections are: Memory size number chips: #define #define #define #define #define Single64KBChipNoCS Single32KBChip Two16KBChips SingleMorethan32KBChip More32KBChips Memory chip width 8-bit/16-bit: #define Data16bit Comment 8-bit chip used; uncomment 16-bit chip used. #define HighByteEnb (applicable only when 16-bit mode) Comment this active-low byte enable signal required. Address/Data Multiplex mode: #define AddressDataNoMux #define LowAddressDataMux #define FullAddressDataMux Keep required macro uncommented comment other two. example: generate address data separate pins, uncomment #define AddressDataNoMux comment rest. multiplex only lower address byte with data pins, uncomment #define LowAddressDataMux comment rest. multiplex both lower higher address bytes with data pins, uncomment #define FullAddressDataMux comment rest. Setup time, hold time control signal width: #define SetDataSetupWait_TCY (where 1/2/3/4) #define SetControlWidthWait_TCY (where 0/1/./15) #define SetDataHoldWait_TCY (where 1/2/3/4) Select setup time from four options TCY). Select hold time from four options TCY). select required setup time, write count (number TCY) against #define SetDataSetupWait_TCY. select required hold time, write count (number TCY) against #define SetDataHoldWait_TCY. Select control signal width from options TCY). select required control signal width, write count (number TCY) against #define SetControlWidthWait_TCY.
Select required macros uncommenting macro name comment remaining four. example: interface 64-Kbyte memory chip, uncomment #define Single64KBChipNoCS comment rest. interface 32-Kbyte memory chip, uncomment #define Single32KBChip comment rest. interface 16-Kbyte memory chips, uncomment #define Two16KBChips, comment rest. interface memory chip more than Kbytes, uncomment #define SingleMorethan32KBChip comment rest. interface more 32-Kbyte memory, uncomment #define More32KBChips comment rest.
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Port selection memory extension: single chip higher memory device select port generating higher address byte, #define AddressHighPort LATx (where LATx LATA/LATB/LATC/LATD/LATE) specify number additional address lines required, #define NumberofAdded AdrsLine (where anything between multiple 32-Kbyte devices select port generating select signal demultiplexer, #define ChipSelectPort LATx (where LATx LATA/LATB/LATC/LATD/LATE) specify number select lines required, #define NumberofAddedCSLine (where anything between Table provides describes APIs. Note: While using single memory device, higher than Kbytes, additional address lines (above A14) should generated software general purpose pins; while using multiple memory devices Kbytes, select signals demultiplexer should generated software general purpose pins.
TABLE
Function PMPInit()
APIs PROVIDED MemInterface.c FILE
Description Initializes module also None port directions required, defined MIDefn.h file. Reads byte from specified location. Reads specified number bytes starting from specified location saves them from specified pointer location. Memory location address (unsigned long) Memory location address (unsigned long) Number bytes read (unsigned int) Destination pointer (unsigned char Memory location address (unsigned long) Data (unsigned char) Inputs Outputs None
MemByteRead() MemBulkRead()
Read data (char) None
MemByteWrite()
Writes byte specified location.
None
MemBulkWrite()
Writes specified number bytes Memory location address starting from specified location. (unsigned long) Number bytes written (unsigned int) Source Pointer (unsigned char
None
Note:
flowcharts these APIs, refer Figure through Figure
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2008 Microchip Technology Inc.
AN1210
Memory Interface Application File Example
these APIs: Write application file. Call API. APIs MemInterface.c file. this file project folder with application file. Uncomment required definitions MIDefn.h file. Include header file, MemInterface.h, application file. example file, MemIntfExample.c, provided along with this application note. This file describes APIs access (read write) external memory device. Figure illustrates flow this example file.
FIGURE
MEMORY INTERFACE EXAMPLE FLOWCHART
Start
Initialize Module Interface with Memory
Write into Memory Device
Write till Write Time Over
Read from Memory Device
Stop
2008 Microchip Technology Inc.
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AN1210
PMPInit
API, PMPInit, initializes module definitions file, MIDefn.h. There inputs this API; this returns nothing. This takes inputs from MIDefn.h file. Figure illustrates flow PMPInit API.
FIGURE
PMPInit FLOWCHART
PMPInit
Select mode have read write strobes different pins. Select required setup time, hold time strobe width. Enable read write strobe ports. Select address/data multiplexing defined macros Memdefn.h file. 16-bit data selected, enable byte enable port. address data multiplexed, select polarity high Address Latch Enable signals (ALEL/ALEH). Select polarity chip select, read write signals low. Byte enable used; otherwise, select polarity high. Enable required ports address, chip select, address latch enable.
Drive ports used chip select high those used address low. Configure these ports outputs. these pins have analog function, configure them digital.
Return
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2008 Microchip Technology Inc.
AN1210
MemByteRead
API, MemByteRead, reads byte from specified address. inputs this memory address bits) from where data read. This returns data read bits). Figure illustrates flow MemByteRead API.
FIGURE
MemByteRead FLOWCHART
MemByteRead
Load address_low Address register (PMADDR) address_high Address High register. Enable chip select port respective chip select.
Busy?
Read Data (Dummy Read)
Busy?
Read Data
Return Read High
2008 Microchip Technology Inc.
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MemBulkRead
MemBulkRead reads sequence specified length data from specified address, stores specified array. inputs this starting memory address bits) from where data read, number data bytes (maximum Kbytes) read address array char) where read data needs stored. This returns nothing; stores read data passed array. Figure illustrates flow MemBulkRead API.
FIGURE
MemBulkRead FLOWCHART
MemBulkRead
Select address auto-increment. Load address_low Address register (PMADDR) address_high Address High register. Enable chip select port respective chip select.
Busy?
Read Data (Dummy Read)
Buffer Full?
Return
Busy?
Read Data Save Buffer
Load address_high Address High register. Enable chip select port respective chip select.
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2008 Microchip Technology Inc.
AN1210
MemByteWrite
API, MemByteWrite, writes byte specified address. inputs this memory address bits) where data written data bits) that needs written. This returns nothing. Figure illustrates flow MemByteWrite API.
FIGURE
MemByteWrite FLOWCHART
MemByteWrite
Load address_low Address register (PMADDR) address_high Address High register. Enable chip select port respective chip select.
Busy?
Write Data
Return
2008 Microchip Technology Inc.
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AN1210
MemBulkWrite
API, MemBulkWrite, writes sequence specified length bytes which stored array from specified address. inputs this are, starting memory address bits) from where data written, number data bytes written (maximum Kbytes) address array char) where data written stored. This returns nothing. Figure illustrates flow MemBulkWrite API.
FIGURE
MemBulkWrite FLOWCHART
MemBulkWrite
Load address_low Address register (PMADDR) address_high Address High register. Enable chip select port respective chip select.
Buffer Empty?
Return
Busy?
Write Data
Load address_high Address High register. Enable chip select port respective chip select.
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2008 Microchip Technology Inc.
AN1210
CONCLUSION
This application note discusses different ways interfacing memory device with module. There merits demerits each interface type. should select appropriate interface type that suits application most. APIs provided easily used interface memory with PMP. definitions requirements MIDefn.h file. MemIntfExample.c file example file that describes APIs. APIs provided MemInterface.c file. Refer Section "Parallel Master Port (PMP)" "PIC24F Family Reference Manual" more information.
2008 Microchip Technology Inc.
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NOTES:
DS01210A-page
2008 Microchip Technology Inc.
Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
Code protection constantly evolving. Microchip committed continuously improving code protection features products. Attempts break Microchip's code protection feature violation Digital Millennium Copyright Act. such acts allow unauthorized access your software other copyrighted work, have right relief under that Act.
Information contained this publication regarding device applications like provided only your convenience superseded updates. your responsibility ensure that your application meets with your specifications. MICROCHIP MAKES REPRESENTATIONS WARRANTIES KIND WHETHER EXPRESS IMPLIED, WRITTEN ORAL, STATUTORY OTHERWISE, RELATED INFORMATION, INCLUDING LIMITED CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY FITNESS PURPOSE. Microchip disclaims liability arising from this information use. Microchip devices life support and/or safety applications entirely buyer's risk, buyer agrees defend, indemnify hold harmless Microchip from damages, claims, suits, expenses resulting from such use. licenses conveyed, implicitly otherwise, under Microchip intellectual property rights.
Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC SmartShunt registered trademarks Microchip Technology Incorporated U.S.A. other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2008, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
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