Switch Mode Power Supply (SMPS) Topologies (Part Author: Antonio
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AN1207
Switch Mode Power Supply (SMPS) Topologies (Part
Author: Antonio Bersani Microchip Technology Inc.
REQUIREMENTS RULES
following requirements rules were used determine various component values used design power converter. general design requirements listed follows: Nominal input voltage (VDC) Minimum input voltage (VDC, min) Maximum input voltage (VDC, max) Output voltage (VOUT) Nominal average output current (IO, nom) Nominal minimum output current (IO, min) Maximum ripple voltage (VR, max)
INTRODUCTION
This application note second two-part series Switch Mode Power Supply (SMPS) topologies. first application note this series, AN1114 "Switch Mode Power Supply (SMPS) Topologies (Part I)", explains basics different SMPS topologies, while guiding reader selecting appropriate topology given application. Part this series expands previous material Part presents basic tools needed design power converter. topologies introduced Part covered, after brief overview basic functionality each, equations design real systems presented analyzed. Before continuing, recommended that read become familiar with Part this series.
addition, common rules were used component selection: MOSFETs switches) must able Withstand maximum voltage Withstand maximum current Operate efficiently correctly frequency Operate (dependant dissipation) Diodes must able Withstand maximum reverse voltage Withstand average current Arrows used circuit schematics represent voltages. voltage polarity directly reflected arrow itself (meaning voltage reverses, arrow reversed, that value voltage negative).
CONTENTS
This application note contains following major sections: Requirements Rules. Buck Converter Boost Converter Forward Converter Two-Switch Forward Converter. Half-Bridge Converter Push-Pull Converter Full-Bridge Converter Flyback Converter Voltage Current Topologies Conclusion References. Source Code
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BUCK CONVERTER
Buck Converter converts high input voltage into lower output voltage. preferred over linear regulators higher efficiency.
FIGURE
BUCK CONVERTER TOPOLOGY: PERIOD
Topology Equations
Figure shows basic topology Buck Converter. switch operated with fixed frequency variable duty cycle signal.
VOUT
FIGURE
BUCK CONVERTER TOPOLOGY
Based Figure voltage inductor shown Equation
VOUT
EQUATION
inductor current (having constant time derivative value) ramp:
Accordingly, voltage square-wave s(t). Fourier series such signal shown Equation
time TON, equals:
EQUATION
Where duration time interval when switch closed.
where: duty cycle period square-wave amplitude
OPEN (TOFF PERIOD)
shown Figure when switch opens, inductor will keep current flowing before.
This means that square-wave represented value number sine waves different, increasing (multiple) frequencies. this signal processed through low-pass filter (Equation resulting output value only) received.
FIGURE
BUCK CONVERTER TOPOLOGY: TOFF PERIOD
EQUATION
const LoCo low-pass filter extracts from square-wave value attenuates fundamental harmonics desired level.
VOUT
CLOSED (TON PERIOD)
this configuration, circuit redrawn shown Figure diode reverse-biased that becomes open circuit.
result, voltage intersection will abruptly become very negative support continuous flow current same direction (see Figure
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FIGURE INDUCTOR BEHAVIOR
INPUT/OUTPUT RELATIONSHIP DUTY CYCLE
What been described until called Continuous mode. understand what importance, refer Figure 5(G), which represents inductor current. previously seen, there ramp-up during ramp-down during TOFF. average current computed easily using Equation
During TON, inductor storing energy into magnetic field
During TOFF, inductor releasing energy previously stored
EQUATION
average inductor current also current flowing output, output average current equal Equation
Equation shows resulting inductor voltage, while Equation shows current.
EQUATION
EQUATION
EQUATION
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FIGURE
Command
BUCK CONVERTER WAVEFORMS
(-VDC
VOUT
-VOUT
TOFF
Command signal MOSFET gate Voltage MOSFET Current flowing into MOSFET Voltage diode Current diode Voltage inductor Current inductor
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Supposing output load (connected parallel output capacitor changes increasing, this change effect reducing average output current. shown Figure current moves from line nominal load, line larger load. What should noted that slopes ramps, both during TOFF, change because, they only depend VDC, VOUT they have been changed. consequence, increasing load results becoming greater. Since equals constant (the control loop explained earlier handles this) increases, current diminishes.
FIGURE
INDUCTOR CURRENT DIFFERENT LOADS
Increasing load (reducing TOFF
Using value IL(TON) derived from Equation Equation creates relationship shown Equation
CONTINUOUS MODE
Operating Continuous mode named since current inductor never stops flowing (goes zero). shown Figure load continues increase (reducing av), some time inductor current plot will touch x-axis (line This means initial final current beginning switching period) inductor zero. this point, inductor current enters what considered Critical mode. load further increased, current during down-ramp will reach zero before period (line which known Discontinuous mode. Note: Discontinuous mode, only further decrease inductor current reduce time (TON).
EQUATION
OUT)T on)TOFF Neglecting Equation solved VOUT, shown Equation
EQUATION
where (duty cycle),
maximum duty cycle achieved when input voltage minimum, shown Equation
point that inductor current TOFF period must equal inductor current beginning period, meaning change current period must zero. This must true Steady state, when transients have finished, circuit behavior longer changing.
EQUATION
Therefore, must obviously between `1'.
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DISCONTINUOUS MODE
Discontinuous mode, inductor current goes zero before period ends. inductor (output) average current (IO, min) that determines edge between Continuous Discontinuous mode easily determined, shown Figure
FIGURE
INDUCTOR CURRENT EDGE DISCONTINUOUS MODE
peak
limit
TOFF
Based Figure inductor current limit equal Equation
EQUATION
limit peak From this point behavior Buck Converter changes radically. load continues increase, only possibility system reduce current, reduce duty cycle (Figure However, this means that linear relationship, shown Equation longer exists between input output.
relationship between VDC, VOUT obtained with some additional effort, shown Equation
EQUATION
limit Figure illustrates this relationship.
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FIGURE
DUTY CYCLE CONTINUOUS DISCONTINUOUS REGIONS
VDC/VOUT 1.25
VDC/VOUT
Discontinuous region
Continuous region VDC/VOUT IO/IO, limit
shown Figure starting from continuous region moving along line (A), where 0.5, soon boundary between continuous discontinuous regions (dotted line) crossed, keep same output voltage (VDC/VOUT changes according nonlinear relation Equation
Design Equations Component Selection
This section determines equations that enable design Continuous mode Buck Converter.
INDUCTOR
average minimum current (IO, min) average output current boundary Discontinuous mode (Figure This way, current larger than min, system will operate Continuous mode. Usually percentage nom, where common value 10%, shown Equation
EQUATION
OOUT limit Solving Equation with respect results Equation
Power Losses Inductor
Power losses inductor represented Equation
EQUATION
where FPWM frequency (FPWM =1/T)
EQUATION
LOSS, inductor
where equivalent inductor resistance
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OUTPUT CAPACITOR
current ripple generates output voltage ripple having components, shown Figure
Power Losses Capacitor
Power losses dissipated capacitor shown Equation
FIGURE
MODEL OUTPUT CAPACITOR
EQUATION
LOSS, capacitor
DIODE
RESR (ESR)
LESL (ESL)
Referring Figure 5(E), current flowing through diode during TOFF inductor current. easy then compute average diode current using Equation
EQUATION
maximum reverse voltage diode withstand during (see Figure 5(D)), shown Equation
first component ripple voltage (VR) caused effect series resistance (ESR) output capacitor. This resistance shown Figure RESR. second component, VR,CO, comes from voltage drop caused current flowing through capacitor, which results Equation
EQUATION
EQUATION
where ripple current flowing inductor output edge Discontinuous mode, which limit),
Power Dissipation Computation Diode
Because voltage diode non-zero (VR), current zero, dissipation during equal Equation
contributions phase; however, considering worst case, they summed phase, this results switching period, shown Equation
EQUATION
Dissipation during TOFF equal Equation
EQUATION
total rearranging terms, required capacitor value needed guarantee specified output voltage ripple shown Equation
EQUATION
MOSFET
maximum voltage switch (see Figure 5(B)) during TOFF shown Equation
EQUATION
total
EQUATION
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average current (Figure 5(C)) during shown Equation During TOFF, voltage (Figure 5(B)), current zero. shown Equation there contribution dissipated power.
EQUATION
EQUATION
static, Switching Dissipation Figure illustrates what occurs during switching. There events consider: turn-on closes) turn-off opens). both cases, voltage current change abruptly, have linear behavior. representation Figure worst-case possibility where turnon voltage remains constant VDC, while current ramping from zero maximum value. Only this moment does voltage start falling minimum value reality, ramps will somehow overlap; however, since this worst case, this depicted situation considered current switching event. Therefore, turn-on power equal Equation
MOSFET Power Losses Computation
Static Dissipation During TON, average current flowing voltage switch forward voltage, which results Equation This value small since relatively small.
EQUATION
static,
This same loss expressed using RDS(ON) MOSFET, taking care determine from component data sheet value RDS(ON) expected junction temperature (RDS(ON) grows with temperature). This term written shown Equation
EQUATION
static,
hightemp
FIGURE
MOSFET SWITCHING LOSS COMPUTATION WAVEFORMS
Turn-on Turn-off TOFF
EQUATION
switching, turnon
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equal Equation result Equation simplified, shown Equation
EQUATION
EQUATION
switching, turnon turn-off switching loss calculated using Equation
EQUATION
switching, turn
Again, equal Equation this computation results Equation
EQUATION
EQUATION
switching, turn total dissipation MOSFET shown Equation
EQUATION
total static,
switching, turn switching, turn
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Buck Converter Design Example
This section shows equations previously discussed used design process Buck Converter. addition, typical design requirements they influence design also discussed.
DESIGN REQUIREMENTS.
design requirements are: Input voltage: ±30% Output voltage: VOUT nominal limit 0.2A limit 0.4A Switching frequency Output ripple voltage Input ripple voltage
DESIGN PROCESS Duty Cycle Computation
converter supposed operate Continuous mode, that Equation holds and: Dnominal VOUT/VDC 5/12 0.42. addition, maximum minimum available input voltages will computed: Minimum input voltage 8.5V Maximum input voltage 15.5V
Inductor
According Equation nominal value inductor (Continuous mode) equal Equation
EQUATION
200K inductor required place system Continuous mode with maximum input voltage shown Equation
EQUATION
15.5 0.2I 15.5 200K
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required inductor with minimum input voltage shown Equation
EQUATION
0.2I 200K inductor least will prevent converter from going discontinuous over full input voltage range. fact, smallest inductor, selected, maximum input voltage (VDC 15.5V) would result current ripple 0.85A. Conversely, inductor with input voltage 8.5V gives current ripple 0.17A. This means that inductor greater than will fit.
Output Capacitance
Equation supposing select capacitance having
EQUATION
0.42 RIPPLE 200K
Input Capacitor
Using same approach compute output capacitance, input capacitance then calculated using Equation
EQUATION
0.42 4.5F RIPPLE 200K
Free-Wheeling Diode Selection
Based Equation (see also Figure 5(D)), maximum reverse voltage diode during then calculated, shown Equation
EQUATION
15.5V According Equation average current diode calculated, shown Equation
EQUATION
0.42 1.16A
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MOSFET selection
parameters selection MOSFET average current maximum voltage (referring Equation Equation 25). resulting calculations shown Equation Equation
EQUATION
15.5V
EQUATION
0.42 0.84A power dissipated MOSFET computed with Equation which results Equation where typical values used.
EQUATION
100ns LOSS, 0.42 15.5V 0.84 1.24 2.08W
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BOOST CONVERTER
Boost Converter converts lower input voltage higher output voltage.
OPEN (TOFF PERIOD)
When switch opens (Figure 13), since inductor current cannot change abruptly, voltage must change polarity. Current then begins flowing through diode, which becomes forward-biased.
Topology Equations
Figure shows essential topology Boost Converter.
FIGURE
BOOST CONVERTER TOPOLOGY: TOFF PERIOD
FIGURE
BOOST CONVERTER TOPOLOGY
VOUT
VOUT
VOUT
resulting inductor voltage shown Equation
EQUATION CLOSED (TON PERIOD)
this configuration, circuit redrawn shown Figure current flowing into inductor during TOFF, which ramping down, computed using Equation
FIGURE
BOOST CONVERTER TOPOLOGY: PERIOD
VOUT
EQUATION
VOUT
OPERATING MODES
Like Buck Converter, Boost Converter also operated Continuous Discontinuous modes. difference between modes inductor current. Continuous mode never goes zero, whereas Discontinuous mode, falling inductor current TOFF period reaches zero before start following period. case Buck Converter, Boost Converter used both modes. either case, control loop must considered. solution mode does necessarily work well with other.
resulting voltage inductor shown Equation
EQUATION
Based inductor equation (Equation current results shown Equation
Continuous Operating Mode
usual, areas below inductor voltage during TOFF must equal. This means that current beginning period equals current (Steady state condition) period. Using Equation Equation relation shown Equation made.
EQUATION
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EQUATION
-1-D
where duty cycle signal.
EQUATION
where inductor peak current
important note that this nonlinear relationship (Figure 14), unlike Buck transfer function. lossless circuit assumed, PDC, VOIO VDCIDC, resulting Equation
power delivered load input during TOFF shown Equation
EQUATION
EQUATION
where indicated Figure 15(G), portion TOFF period from when inductor current reaches zero.
Discontinuous Operating Mode
find relationship, different approach used where energy considered, which differs from approach used Buck Converters. total power (PT) delivered load comes from contribution magnetic field inductor and, during TOFF, from input voltage VDC. power delivered from inductor (assuming 100% efficiency) shown Equation
total power delivered load Equation Equation peak current derived from Equation results that Equation
EQUATION
where output load resistor
FIGURE
VO/VDC
Series1
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FIGURE BOOST CONVERTER WAVEFORMS (DISCONTINUOUS MODE)
Command TOFF
VOUT
-VOUT
VOUT
Command signal MOSFET gate Voltage MOSFET Current flowing into MOSFET Voltage diode Current diode Voltage inductor Current inductor
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Design Equations Component Selection
previously discussed, Continuous mode, input/output relationship equal Equation Discontinuous mode, this relationship equal Equation maximum time will correspond minimum input voltage, VDC. duty cycle chosen that Equation with Combining Equation Equation using previous definition gives equation TON, max, shown Equation resulting maximum duty cycle shown Equation
EQUATION
DROP, RIPPLE simplified representation shown Equation
EQUATION
RIPPLE
DIODE
During TON, diode open with maximum reverse voltage, shown Equation
EQUATION
EQUATION
EQUATION
average current during TOFF shown Equation
EQUATION INDUCTOR.
possible compute inductor using Equation maximum TON, minimum minimum assumed, which results Equation
MOSFET
average current represented Figure shown Equation
EQUATION
EQUATION
maximum voltage represented Figure shown Equation
OUTPUT CAPACITOR
output capacitor must able supply output current during TON, without having voltage drop greater than maximum allowed output ripple. Since capacitor large, possible approximate exponential discharge with linear behavior. current drawn from capacitor average output current (IO, nom) charge lost during equal Equation Therefore, voltage drop equal Equation
EQUATION
EQUATION
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FORWARD CONVERTER
topology Forward Converter, shown Figure considered direct derivative Push-Pull Converter, where switches replaced diode. consequence, cost usually lower, which makes this topology very common.
FIGURE
FORWARD CONVERTER TOPOLOGY
VOUT
Topology Equations
Referring section Forward Converters AN1114 (see "Introduction"), behavior system quickly summarized. switch driven waveform, whose duty cycle must less than 50%, shown Figure
FIGURE
MOSFET COMMAND SIGNAL TIMING
TOFF
Command
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(INTERVAL TON)
this configuration, circuit redrawn shown Figure
FIGURE
FORWARD CONVERTER TOPOLOGY: INTERVAL
VOUT
Input Circuit Behavior
input voltage directly connected winding consequently, this winding positive respect non-dot end. Similarly higher voltage than non-dot end. Diode reverse-biased current flows into winding voltage winding shown Equation
total current flowing into magnetizing current output current reflected primary through transformer.
Output Circuit Behavior
Because voltage polarity primary windings, secondary winding positive compared non-dot end. Consequently, forward-biased, while reverse-biased. secondary Equation winding voltage shown
EQUATION
voltage winding shown Equation
EQUATION
voltage right rectifying diode shown Equation
EQUATION
magnetizing current flowing into windings switch circuit (current that would flowing into transformer secondary winding were open), equal Equation
EQUATION
voltage output inductor shown Equation
EQUATION
positive-slope ramp whose maximum value reached shown Equation
EQUATION
current flowing through output inductor through shown Equation
EQUATION
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EQUATION
this point, total current flowing into primary computed. contributions: magnetizing current (see Equation load current reflected back into primary, shown Equation
EQUATION
total
[INTERVAL (TON TR)]
Based this configuration, circuit redrawn, shown Figure
FIGURE
FORWARD CONVERTER TOPOLOGY: INTERVAL (TON
VOUT
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Input Circuit Behavior
Before switch opened, magnetizing current flowing When switch opens, reverses voltages continue flow. becomes negative respect non-dot end, similar behavior experienced winding Because polarity diode becomes forward-biased keeps voltage diode drop below ground. Magnetizing current flow through diode into power supply VDC, shown Figure voltage shown Equation
Output Circuit Behavior
previously mentioned, magnetizing current reverses voltages when switch turns off. result, secondary winding more negative than non-dot diode becomes reverse-biased. secondary voltage shown Equation
EQUATION
keep current flowing into inductor voltage reverses that left inductor more negative than right end, would continuously decrease; however, freewheeling diode becoming forward-biased sets diode voltage drop below ground. voltage inductor equal Equation
EQUATION
voltage shown Equation
EQUATION
EQUATION
When TON, current reset winding equals magnetizing current multiplied windings ration, shown Equation
Consequently inductor current will decrease according Equation
EQUATION
During this current down-slope reaches zero when
EQUATION
This current same current that flowing into free-wheeling diode
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[INTERVAL (TON
this configuration, circuit redrawn shown Figure
FIGURE
FORWARD CONVERTER TOPOLOGY: INTERVAL (TON
VOUT
Input Circuit Behavior
soon magnetizing current reaches zero TR), energy that been stored into transformer when been released diode opens. Consequently, voltage drop becomes zero voltages both non-dot equal VDC. voltage drop equally becomes zero, that voltage applied switch VDC.
EQUATION
magnetizing current, time zero Steady state). Therefore, during must equal during which represented Equation (refer Equation Equation 75).
Output Circuit Behavior
Nothing changes compared previous time interval.
EQUATION
circuit running maximum duty cycle when equals TOFF, which means full TOFF period needed nullify magnetizing current. this case, Equation replaced with maximum theoretical value TOFF, that TON, max, shown Equation derived from Equation
Design Equations Component Selection
INPUT/OUTPUT RELATIONSHIP DUTY CYCLE
output, steady state, current inductor must equal current Expressing inductor voltage function inductor current based Equation Equation results Equation which turn solves Equation
EQUATION
EQUATION
EQUATION
max, theoretical case Dmax, theoretical 0.5.
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TRANSFORMER: PRIMARY
core transformer during operation moves first quadrant hysteresis curve. change flux, according Faraday law, shown Equation proportional product applied voltage time during which this voltage present. general, maximum value chosen TON, kT/2 when indicated Figure maximum value also dependent ration NP/NR. Based characteristics transformer core, defined. From Equation primary number turns determined, considering minimum value consequently, maximum duty cycle shown Equation
EQUATION
core
where units Tesla Acore
EQUATION
core Replacing Equation neglecting results Equation
During TON, this product equals (VDCTON), while during product NPVDC(TR)/NR, based Equation Equation neglecting Figure 22(F), product (VDCTON) equals area while VDCNPTR/NR equals area preferable have that hysteresis plane, operating point period come back initial point. This guarantees that system will never drift toward saturation. point that condition easily fulfilled, with different values ratio NP/NR selecting different number turns windings (see Figure 21). This provides additional degree freedom design system.
EQUATION
core determined considering behavior described Figure
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FIGURE FORWARD CONVERTER: VOLTAGE MOSFET DIFFERENT VALUES PRIMARY RESET WINDING TURNS
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FIGURE FORWARD CONVERTER WAVEFORMS NR): PRIMARY SIDE
Command
Command signal MOSFET gate Voltage primary winding Magnetizing current Voltage reset winding Reset winding current, equal diode current Voltage MOSFET Primary winding current, equal MOSFET current
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TRANSFORMER: PRIMARY, WIRE SIZE
shown Figure 22(G) total current flowing into primary contributions: magnetizing current (Equation load current (Equation reflected back into primary, resulting Equation
EQUATION
total
primary wire size then computed first referring Figure 22(G), then replacing real current waveform with pulse having square shaped waveform, with same width whose amplitude value middle ramp (IQ, mr). current expressed function known (design requirements) data. Note that these computations, magnetizing current neglected since transformer designed make about one-tenth load reflected current. Therefore, input power equals Equation
TRANSFORMER: SECONDARY, WIRE SIZE
shown Figure 24(C), secondary current equals inductor current (IO, during TON. Again, primary current, actual current waveform replaced with current pulse having square shaped wave form whose amplitude equals mid-ramp inductor current up-slope, nom. Therefore, secondary average current equal Equation
EQUATION
output power shown Equation
EQUATION
value computed Equation
EQUATION
where converter efficiency
EQUATION
TRANSFORMER: RESET WINDING, WIRE SIZE
reset winding involved carrying current reflected back into primary from secondary. only current carry magnetizing current, which plotted Figure 22(C). magnetizing peak current computed Equation shown Equation
Solving Equation results Equation
EQUATION
This equivalent current flowing primary wires when maximum allowed value. value computed Equation
EQUATION
value peak value multiplied square root duty cycle divided radix shown Equation
EQUATION
correct (wire size) determined accordingly.
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EQUATION
MOSFET
During TOFF, voltage switch equal Equation
EQUATION
TON, spike leakage current appears. safely estimated peak value, shown Equation
EQUATION
off, average current flowing through switch been computed Equation
DIODES
Table summarizes values average current voltage diodes have cope with.
TABLE
Diode
DIODE CURRENT VOLTAGE
Configuration VDC, (TON VDC, (TON
Legend: diode forward voltage.
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OUTPUT FILTER INDUCTOR
other topologies with low-pass filter output, inductor selected operate system Discontinuous mode. inductor calculated just edge between Continuous Discontinuous mode (i.e., Critical mode), where inductor current starts from zero beginning period returns zero before period ends. this condition, average current equals peak current current ripple), shown Figure
FIGURE
INDUCTOR CURRENT: PEAK CURRENT, RIPPLE CURRENT AMPLITUDE OUTPUT CURRENT EDGE DISCONTINUOUS MODE
Inductor
IRIPPLE
Critical mode, minimum acceptable output current (defined design requirements) made coincident with average current, shown Equation
EQUATION 101:
OUT, ripple ripple
where ripple computed Equation
EQUATION
ripple Using Equation compute ripple, results Equation 100.
capacitor value itself then computed with Equation 102, which describes value voltage ripple taking into account components.
EQUATION 102:
FPWM ripple ripple Neglecting ESL, since normally very small least frequencies less than kHz), results Equation 103.
EQUATION 100:
OUTPUT CAPACITOR
output voltage ripple mainly capacitor ESR. inductor current ripple flowing through determines voltage drop. Therefore, capacitor with equal Equation must selected.
EQUATION 103:
ripple OUT, ripple ripple
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FIGURE FORWARD CONVERTER WAVEFORMS: SECONDARY SIDE
Command TOFF
Command signal MOSFET gate Voltage secondary winding Secondary winding current, equal diode current Voltage node Voltage diode Voltage inductor Current inductor Current diode
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TWO-SWITCH FORWARD CONVERTER
Clearly derived from single-ended topology (Forward Converter), this circuit significant advantages over single-ended forward converters. schematic this topology shown Figure
FIGURE
TWO-SWITCH FORWARD CONVERTER TOPOLOGY
VOUT
Topology Equations
Referring section Two-Switch Forward Converters AN1114 (see "Introduction"), basic equations reviewed first followed selection circuit components. Both switches, simultaneously driven square wave signal with duty cycle less than 0.5, shown Figure
FIGURE
SIGNAL DRIVING SWITCHES
Command Command
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(INTERVAL TON)
this configuration, circuit redrawn, shown Figure
FIGURE
TWO-SWITCH FORWARD CONVERTER TOPOLOGY: INTERVAL
IPRIMARY VOUT
Input Circuit Behavior
transformer connected between ground; more positive than non-dot magnetizing current flowing through Both diodes primary reverse-biased contribute operation. voltage primary equal Equation 104.
secondary voltage equal Equation 106.
EQUATION 106:
Equation shows voltage inductor.
EQUATION 104:
magnetizing current transformer positive slope increase shown Figure 30(C):
EQUATION 107:
shown Equation 108, current inductor linearly growing behavior (see also Figure 31(E)).
EQUATION 105:
total current primary this magnetizing current plus secondary current reflected transformer back primary.
EQUATION 108:
this point, total current primary windings computed magnetizing current secondary current reflected back into primary (see Figure 30(F)), shown Equation 109.
Output Circuit Behavior
Similar primary, secondary winding experiences voltage that higher compared non-dot end. Therefore, diode forwardbiased conducting current inductor, while diode reversed-biased.
EQUATION 109:
total
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(INTERVAL (TON TR))
When both switches turn off, magnetizing current reverses voltages system. primary, non-dot part inductor becomes more positive than (see Figure 28). Both diodes forward-biased, which provides path leakage current, from non-dot primary, through into positive negative wire, through diode back again transformer.
FIGURE
TWO-SWITCH FORWARD CONVERTER TOPOLOGY: INTERVAL (TON
VOUT
voltage primary equal Equation 110.
EQUATION 110:
magnetizing current expressed Equation 111.
becomes reverse-biased. inductor current path through diode into load output capacitor. Equation shows secondary voltage.
EQUATION 112:
Equation shows inductor voltage.
EQUATION 111:
magnetizing current reaches zero (that energy stored into transformer primary during been delivered back input) time being (TON
EQUATION 113:
Equation shows current.
Output Circuit Behavior
Because change polarity voltages magnetizing current, polarity induced secondary voltage such that non-dot winding more positive than end. meanwhile, voltage output inductor changes polarity well, left side tries very negative, clamped diode voltage drop below ground diode which forward-biased. contrary
EQUATION 114:
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(INTERVAL (TON
seen previously from (TON there more energy transformer primary, magnetizing current zero consequently diodes conducting more, they reverse-biased. this configuration, circuit redrawn shown Figure Voltage both zero voltage switch will less than VDC. Nothing changes secondary.
FIGURE
TWO-SWITCH FORWARD CONVERTER TOPOLOGY: INTERVAL (TON
VOUT
Design Equations Component Selection
INPUT/OUTPUT RELATIONSHIP DUTY CYCLE
input/output relationship shown Equation 115, obtained equating Equation with Equation 114, where TOFF, respectively.
EQUATION 117:
max, theoretical
course real duty cycle will somewhat smaller than maximum, theoretical value, take into account tolerances computations.
EQUATION 115:
TRANSFORMER: PRIMARY
number primary turns determined from Faraday equation shown Equation 118, which results Equation 119.
Neglecting duty cycle determined, shown Equation 116.
EQUATION 118:
core
EQUATION 116:
maximum theoretical duty cycle (Equation 117) obtained equating magnetizing currents (Equation Equation 111), considering that maximum TOFF.
EQUATION 119:
core
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TRANSFORMER: PRIMARY, WIRE SIZE
current flowing through transformer computed replacing current Figure 30(F), with equivalent waveform having constant amplitude (IP, mr), corresponding mid-ramp value. Considering relationship Equation (between input power) Equation (the output power), this results Equation 122. Therefore, value then equal Equation 123.
TRANSFORMER: SECONDARY, WIRE SIZE
referring Figure 31(C), current flowing into secondary winding determined, ramp step current waveform approximated with constant amplitude signal, being amplitude nom. Based these, corresponding value equal Equation 125.
EQUATION 125:
SECONDARY,
EQUATION 120:
MOSFET
maximum voltage switches must able withstand during TOFF, shown Equation 126.
EQUATION 121:
EQUATION 126:
EQUATION 122:
maximum current during shown Equation 127, which same current flowing into transformer.
EQUATION 123:
EQUATION 127:
TRANSFORMER: SECONDARY
number turns determined Equation Equation results Equation 124.
EQUATION 124:
core
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FIGURE TWO-SWITCH FORWARD CONVERTER WAVEFORMS: PRIMARY SIDE
Command Command
Command signal MOSFET gates Voltage primary winding Magnetizing current Voltage MOSFETS Voltage diodes Total primary current (magnetizing current load current reflected back primary side transformer)
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FIGURE TWO-SWITCH FORWARD CONVERTER WAVEFORMS: SECONDARY SIDE
Command Command
Command signal MOSFET gates Voltage secondary winding Current flowing into secondary winding Voltage inductor Current inductor Current flowing diode Voltage diode Current diode
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DIODES
Table provides calculations determining diode voltage.
TABLE
Diode
DIODE VOLTAGE
Configuration (TON (TON
D,on
Q,on
Legend: diode forward voltage. Table provides calculations determining average diode current.
TABLE
Diode
DIODE CURRENT
Configuration (TON (TON
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OUTPUT INDUCTANCE
output inductor computed that output inductor edge Discontinuous mode when output current minimum required (IO, min). Using same approach used Forward Converter (see Figure Equations 100), from Equation Equation (neglecting voltage drops MOSFETS diodes) results Equation 129.
EQUATION 129:
OUTPUT CAPACITANCE
capacitance should present lowest possible impedance frequency current ripple, achieve lowest output voltage ripple. voltage ripple determined output capacitor voltage drop current flowing through (see Equation 130).
EQUATION 128:
ripple
EQUATION 130:
OUT, ripple ripple ripple output capacitor value determined from Equation 131.
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HALF-BRIDGE CONVERTER
Design Equations
Figure presents schematic Half-Bridge Converter. Please refer section Half-Bridge Converters AN1114 (see "Introduction") detailed description operation system. waveforms (two pulses, with adjustable width 180° phase delay) used drive gates transistors represented Figure Some margin needed after falling edge pulse before rising edge other. These time intervals called implemented, short circuit exists switches will destroyed very high current flowing through path from ground. Initially, replaced with short circuit.
FIGURE
HALF-BRIDGE CONVERTER TOPOLOGY
VDC/2 VDC/2
VOUT
FIGURE
COMMAND SIGNALS
Signal Driving
T1ON
Signal Driving
T2ON
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this configuration, circuit redrawn shown Figure
FIGURE
HALF-BRIDGE CONVERTER TOPOLOGY:
VOUT
VDC/2
VDC/2
Input Circuit Behavior
voltage capacitor develops voltage primary circuit where more positive than non-dot end. Equation shows voltage primary.
Output Circuit Behavior
Because voltage polarity primary, dotend edge secondary more positive than non-dot end. Diode then reverse-biased forward-biased. Equation shows voltage secondary.
EQUATION 132:
EQUATION 134:
Equation shows voltage inductor.
Equation shows magnetizing current.
EQUATION 133:
EQUATION 135:
Equation shows current.
EQUATION 136:
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OFF,
this configuration, circuit redrawn shown Figure
FIGURE
HALF-BRIDGE CONVERTER TOPOLOGY: OFF,
VOUT
VDC/2
VDC/2
Input Circuit Behavior
this instance, primary winding voltage that more negative than non-dot end. Equation shows primary winding voltage.
Output Circuit Behavior
with primary, secondary winding voltage more negative than nondot end. consequence, open forward-biased. Equation shows secondary voltage.
EQUATION 137:
Equation shows magnetizing current.
EQUATION 139:
Equation shows inductor voltage.
EQUATION 138:
EQUATION 140:
Equation shows current.
EQUATION 141:
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OFF, (PERIOD
this configuration, circuit redrawn shown Figure
FIGURE
HALF-BRIDGE CONVERTER TOPOLOGY: OFF,
VOUT
VDC/2
VDC/2
Input Circuit Behavior
this instance, current path primary side when turns (Figure when turns (Figure 38).
Output Circuit Behavior
When both switches off, voltage secondary windings such that both forward-biased conducting. current split equally between them, that each them conducing half current flowing into inductor. resulting current waveforms shown Figure Equation shows inductor voltage.
FIGURE
HALF-BRIDGE CONVERTER: CURRENT PATH PRIMARY SIDE WHEN TURNS
EQUATION 142:
VDC/2 VDC/2
Equation shows current flowing through
EQUATION 143:
FIGURE
HALF-BRIDGE CONVERTER: CURRENT PATH PRIMARY SIDE WHEN TURNS
VDC/2
VDC/2
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FIGURE HALF-BRIDGE CONVERTER WAVEFORMS: PRIMARY SIDE
Command
Command
VDC/2 -VDC/2 VDC/2
VDC/2
Command signal MOSFET gate Command signal MOSFET gate Voltage primary winding Voltage MOSFET
Current flowing MOSFET Voltage MOSFET Current flowing MOSFET
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FIGURE HALF-BRIDGE CONVERTER WAVEFORMS: SECONDARY SIDE
Command Command NP/NS VDC/2 -NS/NP VDC/2 NS/NP
Command signal MOSFET gate Command signal MOSFET gate Voltage secondary winding Voltage diode Current flowing diode Voltage diode Current flowing diode Voltage inductor Current inductor
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Design Equations Component Selection
INPUT/OUTPUT RELATIONSHIP DUTY CYCLE
Steady state, increase inductor current during must equal decrease during (neglecting forward drop diode), shown Equation 144. Equation shows input power.
EQUATION 147:
Equation shows output power.
EQUATION 148:
where efficiency
EQUATION 144:
where -Consequently, knowing that there pulses period, maximum theoretical duty cycle Dmax, theoretical 0.5. course, avoid shootthrough switches, maximum duty cycle corresponding minimum input voltage, will less.
Operating Equation 149.
these
equations
results
EQUATION 149:
Equation shows value.
TRANSFORMER: PRIMARY
soon transformer core been defined, primary turns number computed from Faraday's shown Equation 145, resulting Equation 146.
EQUATION 150:
EQUATION 145:
core
TRANSFORMER: SECONDARY, NUMBER TURNS, WIRE SIZE
secondary turns number shown Equation 151, obtained from Equation Equation 146.
EQUATION 146:
core
EQUATION 151:
core average output current, shown Figure 40(I), average output current converter designed for. secondary current (IS) results Equation 152.
TRANSFORMER: PRIMARY, WIRE SIZE
Current flowing primary windings plotted Figure 39(E magnetizing current flowing into primary windings secondary load current reflected back transformer turn ratio. make computations simpler, real current waveforms replaced with mid-ramp value (IP, determine value considering input (PI) output (PO) power.
EQUATION 152:
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SWITCHES
Referring section Half-Bridge Converters AN1114 (see "Introduction"), main advantages Half-Bridge Converter topology that switches must withstand maximum voltage that VDC, compared push-pull topologies. During switches subject maximum voltage VDC, max. maximum current flowing through switches already been computed Equation 150.
OUTPUT CAPACITOR
output voltage ripple mainly ESR, which results Equation 155.
EQUATION 155:
OUT, ripple ripple ripple previously seen other topologies, output capacitor value determined from relation shown Equation 156.
OUTPUT INDUCTANCE
inductor selected such prevent output inductor current from becoming discontinuous. computations performed edge between continuous discontinuous operation, when output starts from zero beginning period goes back zero period. other words, inductor current peak (which also current ripple, twice output average current (see Equation 153).
EQUATION 156:
ripple OUT, ripple ripple
CAPACITOR
Capacitor (see Figure used block component current flowing into transformer avoid core saturation. Small differences between create unbalance voltage point between them causes core walk along hysteresis loop onto saturation. presence small capacitor causes droop primary voltage. voltage during will decay almost linearly with time. Assuming maximum acceptable droop voltage, which results Equation 157.
EQUATION 153:
ripple
Equation shows results.
EQUATION 154:
EQUATION 157:
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PUSH-PULL CONVERTER
Push-Pull Converter uses transformer isolate input from output circuit. waveforms (two pulses, with adjustable width with 180° phase delay) used drive gates transistors shown Figure period waveform, with pulses second This means that duty cycle must less than prevent overlap pulses. Some margin needed after falling edge pulse before rising edge other. These time intervals called
Topology Equations
Figure shows schematic Push-Pull Converter. Refer AN1114 (see "Introduction") detailed description system operation.
FIGURE
PUSH-PULL CONVERTER TOPOLOGY
VOUT
FIGURE
SIGNALS DRIVING MOSFET GATES
Signal Driving
T1ON
Signal Driving
T2ON
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this configuration, circuit redrawn shown Figure
FIGURE
PUSH-PULL CONVERTER:
VOUT
Input Circuit Behavior
input voltage gives place voltage primary winding where non-dot ends more positive than dot-ends. Equation shows voltage primary.
Output Circuit Behavior
Because voltage polarity primary, ends secondary more negative that nondot end. Diode then reverse-biased forward-biased. Equation shows voltage secondary.
EQUATION 158:
This same voltage present lower primary winding (supposing NP2), that total voltage switch equal Equation 159.
EQUATION 161:
Equation shows voltage inductor.
EQUATION 159:
Equation shows magnetizing current.
EQUATION 162:
Equation shows current.
EQUATION 160:
EQUATION 163:
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OFF,
this configuration, circuit redrawn shown Figure
FIGURE
PUSH-PULL CONVERTER: OFF,
VOUT
Input Circuit Behavior
this instance, primary windings voltage more positive than non-dot end. Equation shows primary winding voltage.
Output Circuit Behavior
with primary, secondary windings voltage more positive than nondot end. consequence, open forward-biased. Equation shows secondary voltage.
EQUATION 164:
Equation shows magnetizing current.
EQUATION 166:
Equation shows inductor voltage.
EQUATION 165:
EQUATION 167:
Equation shows current.
EQUATION 168:
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OFF, (PERIOD
this configuration, circuit redrawn shown Figure
FIGURE
PUSH-PULL CONVERTER: OFF,
VOUT
Input Circuit Behavior
Equation shows voltage each switch.
Design Equations Component Selection
INPUT/OUTPUT RELATIONSHIP DUTY CYCLE
EQUATION 169:
Output Circuit Behavior
When both switches off, since current inductor continues flow same direction before, voltage secondary windings such that: -Vs1, forwardbiased conducting. They split current equally, that each them conducting half current flowing into inductor. resulting current waveforms plotted Figure 47(G secondary windings currents. Equation shows inductor voltage.
Steady state, increase inductor current during must equal decrease during Using Equation Equation (neglecting forward drop diode) since (TON T/2, results Equation 172.
EQUATION 172:
where Consequently, knowing there pulses period, maximum theoretical duty cycle Dmax 0.5. Starting from input/output relationship shown Equation 173, feedback control loop keeps output voltage VOUT constant against changes input voltage VDC, decreases, will increase compensate.
EQUATION 170:
where times resistance windings (almost zero).
Based Equation 170, current flowing through inductor equal Equation 171.
EQUATION 173:
Therefore, system design, maximum duty cycle (Dmax) defined that corresponds minimum input voltage (VDC, min) less than maximum, theoretical equal Equation 174.
EQUATION 171:
EQUATION 174:
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TRANSFORMER: PRIMARY, NUMBER TURNS
clearly stated Push-Pull Converter section AN1114 (see "Introduction"), operating point core transformer moves between points that first third quadrant hysteresis loop. Once maximum allowable been defined (based frequency geometrical dimensions core bobbins), using Faraday equation shown Equation Equation 175, results number primary turns, shown Equation 176.
TRANSFORMER: PRIMARY, WIRE SIZE
Current flowing primary windings into switches plotted Figure 46(G simplify computations, real current waveforms replaced with mid-ramp value (IP, determine value considering input (PI) output (PO) power. input power shown Equation 177.
EQUATION 177:
where duty cycle
EQUATION 175:
core
output power shown Equation 178.
EQUATION 178:
where efficiency
EQUATION 176:
core
Operating Equation 179.
these
equations
results
EQUATION 179:
value shown Equation 180.
EQUATION 180:
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FIGURE PUSH-PULL CONVERTER WAVEFORMS: PRIMARY SIDE
Command
Command
2VDC
Command signal MOSFET gate Command signal MOSFET gate Voltage primary winding (upper half) Voltage primary winding (lower half)
Voltage MOSFET Voltage MOSFET Current flowing MOSFET Current flowing MOSFET
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TRANSFORMER: SECONDARY, NUMBER TURNS
Once primary number turns been defined, determined using Equation Equation 176, shown Equation 181.
MOSFETS
Equation (repeated Equation 184) voltage switch must able withstand (considering maximum input voltage) twice maximum input voltage.
EQUATION 181:
core
EQUATION 184:
maximum voltage switches have withstand must also take into account spike that generated leakage inductance falling edges switch control signal. spike generally estimated higher than voltage switch. Therefore, time interval, maximum voltage equal Equation 185.
TRANSFORMER: SECONDARY, WIRE SIZE
previously seen, secondary current waveform quite complex (refer Figure 47(G However, simplify computations, contribution current only during considered. average current, shown nom, average output current converter designed for. secondary current (IS) results Equation 182.
EQUATION 185:
2.6V maximum current flowing through switches been already computed Equation 179. maximum obtained. Therefore, almost that needed make best device choice known. that remains analysis power dissipated switch, which switching losses.
EQUATION 182:
DIODES
During OFF), diode reversebiased. maximum voltage tolerate equal Equation 183.
EQUATION 183:
average current flowing same current that flowing into inductor, value nom. During other period OFF, ON), things reversed; reverse-biased conducting. same values before apply.
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FIGURE PUSH-PULL CONVERTER WAVEFORMS: SECONDARY SIDE
Command
Command
nom/2 (upper)
nom/2 (lower) Command signal MOSFET gate Command signal MOSFET gate Current flowing diode Current flowing diode Voltage inductor Current inductor Current flowing secondary winding (upper half) Current flowing secondary winding (lower half)
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Switching Losses
Figure plots current voltage switch switching instance. When switch turned voltage falls rapidly, while current smooth up-slope since current cannot change abruptly inductor. seen Figure power dissipation zero. Things completely different when switch turned off. Both voltage current have smooth slope up-slope former, down-slope latter), there significant overlap some non-zero power dissipated.
FIGURE
PUSH-PULL CONVERTER: SWITCHES, CURRENT VOLTAGE
2VDC
value easily computed using Equation 186.
EQUATION 186:
where equals rise fall times
losses then computed, shown Equation 187.
EQUATION 187:
total power dissipated switch then equal Equation 188.
EQUATION 188:
total,
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OUTPUT INDUCTOR
inductor selected such prevent output inductor current from becoming discontinuous. computations performed edge between continuous discontinuous operation, meaning when output current starts from zero beginning period goes back zero period. other words, inductor current peak, which also current ripple twice output average current, shown Equation 189.
OUTPUT CAPACITOR
with Buck Converter design, output voltage ripple mainly ESR, resulting Equation 191.
EQUATION 191:
OUT, ripple ripple seen previous topologies, output capacitor value determined from relationship shown Equation 192.
EQUATION 189:
ripple
EQUATION 192:
ripple OUT, ripple ripple
Solving Equation results Equation 190.
EQUATION 190:
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FULL-BRIDGE CONVERTER
Full-Bridge Converter, which capable managing higher power levels, requires some additional components compared Half-Bridge Converter.
Topology Equations
basic Full-Bridge Converter topology shown Figure Transistors always operated together, driven waveform shown Figure Care must taken that same time; otherwise, impedance path created from ground. This imposes maximum value interval discussed later section.
FIGURE
FULL-BRIDGE CONVERTER TOPOLOGY
VOUT
FIGURE
FULL-BRIDGE CONVERTER WAVEFORM
TOFF
TOFF
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OFF, (INTERVAL 0-TON)
shown Figure current flows through transformer primary back input. transformer more positive than non-dot end.
FIGURE
FULL-BRIDGE TOPOLOGY:
VOUT
Input Circuit Behavior
voltage primary shown Equation 193.
secondary voltage computed shown Equation 195.
EQUATION 193:
EQUATION 195:
Equation shows current flowing into inductor.
magnetizing current increases according shown Equation 194.
EQUATION 194:
EQUATION 196:
voltage output capacitor shown Equation 197.
Output Circuit Behavior
primary winding, ends secondary windings more positive that non-dot ends. This implies that diode conducting while diode conducting.
EQUATION 197:
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OFF, (INTERVAL 0-TON)
shown Figure current flows through transformer, back input. transformer more negative than non-dot end.
FIGURE
FULL-BRIDGE CONVERTER TOPOLOGY:
VOUT
Input Circuit Behavior
primary voltage shown Equation 198.
Output Circuit Behavior
this instance, primary, ends more negative than non-dot ends, which results Equation 200.
EQUATION 198:
magnetizing current shown Equation 199.
EQUATION 200:
output inductor voltage shown Equation 201.
EQUATION 199:
EQUATION 201:
current flowing Equation 202. through shown
EQUATION 202:
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HAVE JUST SWITCHED OFF;
When switches open, magnetizing current continues flow, reversing voltages. primary, becomes more negative than non-dot end. magnetizing current flows through transformer, seen Figure voltage primary zero, shown Equation voltage secondary voltage inductor shown Equation 204.
EQUATION 204:
Since very low, magnitude given voltage drop secondary winding resistance half inductor current flowing through
EQUATION 203:
HAVE JUST SWITCHED OFF;
behavior similar previous condition. current path primary shown Figure
Consequently, both diodes inductor current split half between diode paths (see Figure Figure 54).
FIGURE
FULL-BRIDGE TOPOLOGY: HAVE JUST SWITCHED OFF; (PRIMARY CURRENT PATH)
VOUT
FIGURE
FULL-BRIDGE TOPOLOGY: HAVE JUST SWITCHED OFF; (PRIMARY CURRENT PATH)
VOUT
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Design Equations Component Selection
INPUT/OUTPUT RELATIONSHIP DUTY CYCLE
product primary voltage multiplied must equal product voltage multiplied TOFF. Computing Equation Equation results Equation 205. primary winding turn computed from equation that relates core flux change (B), voltage across winding (VP) geometrical entity (Ae), shown Equation 209.
EQUATION 209:
BFPWM
TRANSFORMER: PRIMARY, WIRE SIZE
Since design specification POUT known, input power computed considering converter efficiency shown Equation 210.
EQUATION 205:
where TON/T relationship TOFF used (see Figure
EQUATION 210:
where IIN, average input current (see Figure (E,G,I,K))
guarantee that switches never same time, limited maximum percentage shown Equation 206.
EQUATION 206:
where, equals
Solving Equation results Equation 211.
EQUATION 211:
With some approximation, replacing real current waveform (ramp step) with constant value equal IIN, results Equation 212.
resulting maximum duty cycle shown Equation 207.
EQUATION 207:
EQUATION 212:
TRANSFORMER WINDING TURN RATIO
maximum period will occur when input voltage minimum. Using Equation Equation results Equation 207.
EQUATION 208:
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FIGURE FULL-BRIDGE CONVERTER TOPOLOGY: INPUT CIRCUIT
Command Command TOFF TOFF
VQ2,
VQ3,
VQ1,
IIN, VQ4,
IIN, switch command signal switch command signal Primary voltage Voltage MOSFET Current flowing into MOSFET Voltage MOSFET Current flowing into MOSFET Voltage MOSFET Current flowing into MOSFET Voltage MOSFET Current flowing into MOSFET
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TRANSFORMER: SECONDARY, NUMBER TURNS, WIRE SIZE
secondary number turns computed from Equation Equation (see also Figure 56(D E)). simplify computation secondary current value, consider that contribution current value during TOFF calculated (this relatively short interval small value currents). average value medium value during ramp current considered (see Figure 56(D E)). Using previous Equation 213. approximation results
SWITCHES
During TON, maximum voltage drop that Equation 214.
EQUATION 214:
off,
off, Similarly, maximum voltage drop that Equation 215.
EQUATION 215:
off,
EQUATION 213:
off, Equation shows maximum voltage drop more general terms.
EQUATION 216:
off,
DIODES
Equation shows voltage drop diode when Similarly, Equation shows maximum drop when
EQUATION 217:
off,
EQUATION 218:
off,
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FIGURE FULL-BRIDGE CONVERTER TOPOLOGY: OUTPUT CIRCUIT
Command Command TOFF TOFF
switch command signal switch command signal Secondary voltage Diode current
Diode current Inductor voltage Output inductor voltage
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OUTPUT INDUCTOR
minimum inductor computed, considering system edge discontinuous mode, shown Equation 219.
OUTPUT CAPACITOR
output capacitor selected specified output ripple. greatest contribution voltage ripple comes from capacitor ESR, inductor current ripple, flowing through determines voltage drop. capacitor value itself then computed using Equation 221, which describes value voltage ripple taking into account components.
EQUATION 219:
peak
Solving Equation results Equation 220.
EQUATION 221:
RIPPLE RIPPLE Neglecting ESL, since normally very small, results Equation 222.
EQUATION 220:
EQUATION 222:
ripple ripple ripple
where,
ripple
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FLYBACK CONVERTER
presented AN1114 (see "Introduction"), Flyback Converters widely used applications where isolated conversion required, low-power ranges 150W), since high output voltages quite easily obtained because there inductor output section.
Topology Equations Discontinuous Mode
Flyback Converter easily used either Continuous Discontinuous mode. Discontinuous mode, output winding current goes zero before TOFF period, that stored energy transferred load. Continuous mode, there some residual energy stored transformer periods. Both these modes will analyzed, starting with Discontinuous mode. Figure shows basic flyback circuit. switch driven signal like presented Figure
FIGURE
BASIC FLYBACK CONVERTER TOPOLOGY
VOUT
FIGURE
SWITCH COMMAND SIGNAL
TOFF
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(INTERVAL TON)
Figure shows topology this circuit. stored energy easily computed using Equation 226.
Input Circuit Behavior
Equation shows voltage primary when switch closed.
EQUATION 226:
peak
EQUATION 223:
more negative than non-dot end. transformer behaves inductor accumulating energy windings. current flowing primary shown Equation 224.
Output Circuit Behavior
voltage secondary winding shown Equation 227.
EQUATION 227:
where minus sign fact that more negative than non-dot terminal.
EQUATION 224:
increasing current, starting from zero with peak value reached TON, equal Equation 225.
Therefore, diode reverse-biased current flows into output circuit. output current supplied output capacitor
EQUATION 225:
peak
FIGURE
FLYBACK CONVERTER TOPOLOGY: INTERVAL
VOUT
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(INTERVAL (TON TR))
circuit topology shown Figure
EQUATION 229:
peak peak voltage secondary shown Equation 230.
Input Circuit Behavior
open current longer flow primary winding. described AN1114 (see "Introduction"), some circuitry dissipate energy winding required (snubber network); however, will analyzed here. voltage primary computed Equation 228, which given Equation 230, minus sign conversion.
EQUATION 230:
EQUATION 228:
(INTERVAL (TON +TR)
previously stated, time current secondary reached zero. keep system working Discontinuous mode, some time (TF) must added, shown Equation 232.
Output Circuit Behavior
described AN1114 (see "Introduction"), voltages change sign that secondary, becomes more positive that non-dot diode starts conducting current. current that flowing into primary longer flows because open, transfers secondary initial current equal Equation with down slope, that reaches zero time
EQUATION 231:
This because interval depends input voltage output load instance, decreases output current increases, duration must longer. will consequently reduced, will allow system discontinuous.
FIGURE
FLYBACK CONVERTER TOPOLOGY: INTERVAL
VOUT
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Design Equations Component Selection
INPUT/OUTPUT RELATIONSHIP DUTY CYCLE
input/output relationship computed considering power flow from input output. From Equation power stored primary computed, shown Equation 232.
EQUATION 236:
peak
EQUATION 237:
speak
EQUATION 232:
-2TL relationship between input output power shown Equation 233.
TRANSFORMER WINDINGS TURN RATIO
determine ratio (NP/NS) have look maximum voltage MOSFET able sustain. Considering Figure maximum voltage switch equal that Equation 238.
EQUATION 233:
combining Equation Equation 233, output voltage function input voltage determined, shown Equation 234.
EQUATION 238:
off, primary voltage, calculated using Equation Equation 230, which results Equation 239.
EQUATION 234:
EQUATION 239:
off, MOSFET selected with sufficiently high voltage rating, VQ1, considered datum that Equation 239, only unknown value (NP/NS); therefore, NP/NS equal that Equation 240.
Since interval function input voltage VDC, maximum (TON, max) corresponds minimum input voltage (VDC, min). Using these values, (VDC, design spec TON, usually some value that TON, 0.8T), Equation revised, shown Equation 235.
EQUATION 240:
off,
EQUATION 235:
other equations, primary peak current (Equation 225) secondary peak current (Equation 229), revised take into account VDC, TON, relationship, shown Equation Equation 237, respectively.
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MAXIMUM ALLOWABLE
determine maximum TON, fact that core should never saturate considered. This means voltage-time interval product during energy storage must equal voltage-time interval product during delivery energy load. simpler terms, area must equal area shown Figure Considering that TON, with shown Equation 241, which after computation, results Equation 242.
EQUATION 241:
EQUATION 242:
TRANSFORMER PRIMARY
value transformer primary inductance easily computed using Equation 235, replacing TON, with computed value from Equation 242, where design specification, POUT, VO2/RO, results that Equation 243.
EQUATION 243:
OUT,
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FIGURE FLYBACK CONVERTER TOPOLOGY WAVEFORMS: DISCONTINUOUS OPERATION
command
VQ1,
(NP/NS)(VO VD1,
peak
VD1,
Command voltage MOSFET gate Voltage primary winding transformer Current flowing primary winding transformer Voltage secondary winding transformer Current flowing secondary winding transformer
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TRANSFORMER: PRIMARY, WIRE SIZE
seen Figure 61(C), current primary triangular shape, with peak TON. Based this, value computed shown Equation 244.
EQUATION 244:
peak PRIMARY, Equation 244, peak calculated from Equation 225, TON, max, calculated from Equation 242, which results that Equation 245.
EQUATION 245:
peak
TRANSFORMER: SECONDARY, WIRE SIZE
From Figure 61(E), current secondary similarly triangular shape. value then calculated using Equation 246.
EQUATION 246:
peak peak SECONDARY,
OUTPUT DIODE
current flowing through output diode same current flowing into secondary, with peak value computed Equation 228. average current computed shown Equation 247.
OUTPUT CAPACITOR
output capacitor computed considering that supply whole current load during TON. criteria used that voltage droop should less than acceptable output voltage ripple. Since voltage droop equal Equation 249, capacitor value computed shown Equation 250.
EQUATION 247:
peak maximum reverse voltage diode, during computed shown Equation 248.
EQUATION 249:
DROOP
EQUATION 248:
off,
EQUATION 250:
ACCEPTABLE_RIPPLE
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Topology Equations Continuous Mode
Continuous mode applications, basic circuit does change (refer Figure 57); however, essential difference that current (both primary winding secondary winding) will start reaches zero during period, This means that some energy still stored system when period over. period made TOFF only. basic topology equations exactly same before, they presented without repeating previous explanations.
Output Circuit Behavior
Equation shows voltage transformer secondary winding.
EQUATION 256:
initial current (reflected from primary), shown Equation 257.
(INTERVAL TON) Input Circuit Behavior
Equation shows voltage primary winding.
EQUATION 257:
peak peak
EQUATION 251:
current primary shown Equation 252.
Design Equations Component Selection
INPUT/OUTPUT RELATIONSHIP DUTY CYCLE
Looking Figure 62(B), areas must equal that initial final points transformer core hysteresis curve coincide, shown Equation 258.
EQUATION 252:
Equation shows peak current TON.
EQUATION 258: EQUATION 253:
peak shown maximum TON/T value, computed from Equation occur with VDC, (where NP/NS computed Equation 260), which results Equation 259.
Output Circuit Behavior
voltage Equation 254. secondary
EQUATION 254:
EQUATION 259:
(INTERVAL Input Circuit Behavior
voltage primary shown Equation 255.
EQUATION 255:
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FIGURE FLYBACK CONVERTER TOPOLOGY WAVEFORMS: CONTINUOUS OPERATION
TOFF
command
VQ1, (NP/NS)(VO VD1,
peak
VD1,
(NS/NP)(VDC VQ1,
peak
Command voltage MOSFET gate Voltage primary winding transformer Current flowing primary winding transformer Voltage secondary winding transformer Current flowing secondary winding transformer
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TRANSFORMER WINDINGS TURN RATIO
determine ratio (NP/NS), maximum voltage MOSFET sustain must calculated, shown Equation 260.
TRANSFORMER: SECONDARY, WIRE SIZE
output average current (IO, must determined. output power (which design data) considered, shown Equation 263.
EQUATION 260:
off,
EQUATION 263:
Correspondingly value that Equation 264.
TRANSFORMER: PRIMARY, WIRE SIZE
Considering desired output power shown Equation 261, value computed replacing real current (RAM step) with constant value, equal value then equal Equation 262.
EQUATION 264:
EQUATION 261:
TRANSFORMER: PRIMARY INDUCTANCE
minimum inductance easily computed system edge Discontinuous mode considered. This means that peak exactly half increment primary current during TON. Therefore, minimum average input current that Equation 265.
EQUATION 262:
EQUATION 265:
Solving results Equation 266.
EQUATION 266:
OUTPUT CAPACITOR
output capacitor computed Discontinuous mode, shown Equation 267.
EQUATION 267:
ACCEPTABLE_RIPPLE
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VOLTAGE CURRENT TOPOLOGIES
this section, control loops voltage current modes analyzed. Buck Converter used, these techniques valid topology. topologies, been seen that input/output relationship easily obtained. long desired input output voltages known, that remains compute duty cycle. perfect world, this would more than enough. Unfortunately, real world, things behave differently. input voltage change, load vary (i.e., switching output load Off), components have their tolerances, aging temperature drift and, course, noise always present. result, performances differ from expectations. keep behavior system under control during unexpected situations, "control loop" (hardware and/or firmware) must added perform operation "controlling" output voltage. Control loops allow design circuit where output voltage will vary little possible when environmental condition changes. Moreover, some cases, control loops help preventing dangerous operational situations. Current control loops prevent flux walking transformers. following sections, voltage current modes operation will described each topology, keeping following basic questions mind: What happens system output voltage when input voltage suddenly changes? What happens output voltage when load changes?
Voltage Loop
Figure presents Buck Converter previously studied detail, with some additional circuitry. couple series resistors connected output take reduced amplitude copy (VFB) VOUT. This voltage compared error amplifier (EA) with reference voltage (VREF voltage value desired output). output signal (VX) used trim duty cycle signal that drives switch. understand block works, technique that commonly used analog implementation such systems will used initially. This does mean that this only possible implementation. Later, digitally implement same features with dsPIC® device discussed. analog version instead quite easy intuitive allows simple explanation things work. block replaced comparator that compares voltage sawtooth signal, generated local oscillator (see Figure 64). frequency frequency.
FIGURE
BUCK CONVERTER BASIC VOLTAGE LOOP
VREF
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FIGURE BUCK CONVERTER BASIC ANALOG VOLTAGE LOOP
VCTRL
VREF
Note: VREF
Sawtooth Oscillator
Here system works. voltage, representing current output voltage, subtracted error amplifier from reference voltage VREF. least now, function block just perform subtraction. Signal represents error between desired voltage "real" voltage system generating that instant time. signal Steady state, very slow moving average value. comparator, this signal compared locally generated sawtooth, shown Figure which results VCTRL VCTRL
FIGURE
CONTROL VOLTAGE (VCTRL) GENERATED COMPARISON BETWEEN ERROR VOLTAGE (VX) SAWTOOTH WAVEFORM
VOUT decrease VOUT increase
VCTRL
Note: VREF
Since VCTRL signal used drive switches, based value duty cycle will either small large. operation such that when output voltage increases, voltage decreases, that duty cycle reduced vice versa. falling edge VCTRL moves according position relative VST.
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LINE REGULATION
question does this system react when input voltage changes? answering this question, consider that ultimate goal keep output stable possible against variation input. addition, couple basic equations, derived previously must taken into consideration, which describe behavior Buck Converter. Equation shows current inductor during TON, While during TOFF current equal Equation 269.
EQUATION 270:
peak what happens input voltage increases? Since up-slope inductor current proportional VDC, slope will increase during TON. With some delay, low-pass filter, output voltage will change (increase), with some additional delay introduced signal will decrease. Therefore, duty cycle VCTRL will then smaller (see Figure 65). This will reduce time, reducing consequence VOUT after some time, output will again nominal value, with shorter duty cycle. Note that only slope during changes. slope during TOFF, Steady state condition, must equal original one, since system keeping VOUT constant. Figure presents inductor current before change (dashed line) after transients have settled down Steady state (solid line). initial final current values lower, same time peak (point higher. average current (IO, changed expected since average output voltage changed. course, point corresponds shorter period (TON).
EQUATION 268:
EQUATION 269:
Steady state, current value equals current value This represented Figure event Continuous operating mode. output average current (IO, (see Equation 270) also plotted.
FIGURE
INDUCTOR CURRENT CONTINUOUS MODE
peak
IL(O) IL(T)
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FIGURE
VOLTAGE MODE CONTROL LINE REGULATION
Initial Final
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LOAD REGULATION
question what happens load changes? example, value changes diminishing, very beginning (because delays system) output current will remain before. This means that output voltage will decrease only slightly. consequence, referring again Figure Figure signal will higher duty cycle will increase. behavior system analyzed using Figure which again represents inductor currents, before (dashed line) after (solid line) load change. This time both slopes, during TOFF, will remain same, since input voltage changed output voltage kept constant loop itself. beginning, since increases, duty cycle will increase, moving from original point point This means that current period (point current will larger than initial current (point current effect that each period, current step greater than zero, shown Equation 271.
EQUATION 271:
When transient ends, loop managed bring output voltage VOUT back nominal value consequently, duty cycle back initial value (there change input voltage VDC). This means that, Figure point moved point Steady state. output average current correspondingly increased from initial final, supposed since load diminished.
FIGURE
VOLTAGE MODE CONTROL LOAD REGULATION
final initial
IL(T)
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ADVANTAGES DISADVANTAGES VOLTAGE MODE
clearly seen from previous explanation, implementation voltage mode control quite straightforward. mechanisms line load regulation also quite easy understand. This certainly main advantages this approach. Moreover, large amplitude signals usually being dealt with, which benefit because their good noise margin. disadvantage this mode delay, which always added reacting change operating conditions. change only detected because influence output voltage, that from original event (change VDC), detection makes necessary wait group delay low-pass filter. Moreover, once change output detected, additional delay introduced these delays must taken into account; otherwise, system built that functional. change load immediately detected, again, there delay introduced before countermeasure effective switch timing. also some very specific advantages when needing keep current flowing into inductor/transformer winding under control. typical example application where current mode efficiently used PFC, which circuit whose task force current drawn from voltage source sinusoidal. this case, current mode control directly operates variable (current) interest. seen Figure current mode implementation reality loops: external controlling output voltage (like studied previous paragraph) second (internal) controlling inductor current. basic idea current mode directly monitor quantity that more directly responsible power conversion. Moreover, controlling current allows have much faster response time. Referring Figure before, monitors output voltage. output used reference signal second amplifier that compares peak current flowing into inductor reference signal from previous stage. Remember that when switch closed, inductor current positive slope waveform (Figure 70). beginning period (t0), output active inductor current continues grow until current reaches value When they match TON), signal reset remains until next period starts. This system keeps peak inductor current under control. However, this only possible approach, will seen later.
Current Mode
current mode been introduced solve disadvantages voltage control and, specifically, reduce reaction time system.
FIGURE
CURRENT MODE CONTROL LOOP
Imeas
VREF
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FIGURE INDUCTOR CURRENT
point that Buck Converter, inductor current also output current, that controlling direct control quantity relevance (VOUT). previously seen other systems, instance, PFC, inductor current input current should shaped sinusoidal way. this configuration, externally generated sawtooth signal that used voltage mode control replaced inductor current signal peak value controlled (limited). system relatively simple also couple drawbacks: preferred able control average output current, peak current (this because output voltage proportional average current, peak current) There some stability issues
LINE REGULATION
What happens when, being Steady state, input voltage changes? does system respond?
This behavior best understood looking Figure (dashed lines represent original Steady state). example, soon changes increasing, slope inductor current changes (see Equation 268). this case will increase. Meanwhile, output changed, because delay output LOCO filter. Consequently, changed same before. loop still imposing same inductor peak current before. This means that up-slope current signal will cross signal before, point compared Steady state point (the transient behavior inductor current shown with line from point point duty cycle reduced should because increased input voltage. final, Steady state condition point still line (the peak current always same), having steeper up-slope same down-slope. important thing that reaction input voltage change immediate, without having wait change propagate along loop. other words, system response much faster.
FIGURE
PEAK CURRENT MODE CONTROL LINE REGULATION
initial final
TON, initial TON, final during transient
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PROBLEMS
seen Figure while input voltage regulation works fine increase brings about reduction duty cycle), there drawback seen Equation 272. This fact that peak voltage being kept constant, while output voltage VOUT proportional average inductor voltage.
EQUATION 273:
final initial lower current will develop lower output voltage, which will detected external voltage loop. turn, will increase average (and peak) current. internal loop tries keep peak current constant. oscillatory effect takes place continues some time. Another subtle problem peak current mode that system unstable duty cycles greater than 0.5, which seen Figure Figure
EQUATION 272:
OUT, However, observed Figure condition such that inductor current initial final values (points lower than before This means that final average inductor (output) current lower, shown Equation 273.
FIGURE
PEAK CURRENT MODE CONTROL
FIGURE
CURRENT MODE CONTROL SLOPE COMPENSATION
Down slope Down slope
Inductor current
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seen Figure when 0.5, steady state, reason there pertibation inductor current, period, amplitude pertibation reduced II), that after number cycles, system will back initial condition. contrary, duty cycle greater than (Figure 73), same current pertibation will larger period will grow indefinitely, giving rise oscillatory behavior II). Without going into many details, both problems easily corrected replacing constant peak current limit with down slope signal that equals beginning each period, which down slope proportional half current slope during TOFF (Figure 73).
Load Compensation
What happens when output load changes? example, output load changes decreasing, output voltage will momentarily decrease consequently signal will higher compensate (see Figure 74). slope signal will then last longer will cross point instead original point duty cycle will correspondingly increase. This will cause inductor current level higher period compared value beginning (IF, extremely exaggerated Figure clarity). This unbalance will remain while average current increases equilibrium value. this point, duty cycle back initial value changes input voltage VDC) system reached steady state.
FIGURE
PEAK CURRENT MODE CONTROL LOAD COMPENSATION
during transient steady state
during transientT steady state
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Other Current Mode Techniques
current mode previously described with some detail only available. most obvious technique where loop keeps average (not peak) output current constant. This good, since output voltage proportional average output current. analog, circuitry more complex since some kind low-pass filter must added current loop error amplifier. contrary, from digital point view, technique very easy since average value current directly sampled converted sampling trigger half period duty cycle. special register dsPIC device allows conversion start operation exactly this point (see Figure 75). second possibility implement so-called hysteretic control, where current value change between values, which either fixed dynamically computed dsPIC device itself. this case, internal comparators their threshold DACs allow implement system without intervention from (see Figure 76). seen Figure soon decreasing inductor current reaches threshold one, current limit event dsPIC device takes place, associated with forcing high pin. consequence, current starts rising. soon reaches second threshold, fault event takes place output reset, current decreases, frequency generated constant, will change function line load (remember that slope proportional down slope proportional VOUT).
FIGURE
TRIGGER GENERATED PERIPHERAL
Signal
Inductor Current
Trigger start conversion
SEVTCMP Register
Time Base Counter
FIGURE
HYSTERETIC CONTROL IMPLEMENTATION WITH dsPIC® DEVICE
dsPIC®
DAC1
Output
PWMxH
DAC2
Fault Reset
PWMxL
Inductor Current
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internal comparators also used implement "constant time "constant off" time (see Figure Figure 78), where match between increasing inductor current preset threshold (DAC output) resets timer that controls period. control modes essentially same, only difference being that direct inverted output considered.
FIGURE
"CONSTANT TIME WAVEFORM
External Reset Nominal Period
Time Base Counter
FIGURE
"CONSTANT OFF" TIME WAVEFORM
External Reset Nominal Period
Time Base Counter
TOFF
TOFF
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Control Theory
this point, feedback loops have been considered where output VOUT compared reference value, error signal used change some specific feature (i.e., duty cycle) power modulator. This closed loop system must analyzed with control theory tools. problem here that system could become unstable either current voltage loop used. general circuit, like Figure Figure behavior block, excluding known computed. design challenge then select (and transfer function sure system stable. Before analyzing Buck Converter circuit from control theory perspective, some basic relationships must formulated. Equation shows product terms, G(s) H(s), which called open loop gain (GOL(s)).
EQUATION 276:
Figure represents G(s), H(s), GOL(s) GCL(s). Remember that plot scale, that multiplications correspond sums divisions correspond subtractions.
FIGURE
CONTROL LOOP FUNCTIONS
|G(s)| |GOL(s)| |1/H(s)|
FEEDBACK LOOPS
Figure presents general control loop where G(s) H(s) transfer functions blocks (Laplace transforms impulse responses). x(t) input signal system; y(t) output; y(t) also back input through H(s) block, whose output, r(t) subtracted from input x(t) form error signal e(t).
|GCL(s)|
FIGURE
CONTROL LOOP
Some mathematics understand plot provided Equation 277.
EQUATION 277:
x(t) e(t) r(t) G(s) y(t)
-H(s)
H(s)
Consequently this case, where H(s) const, open loop gain simply obtained moving G(s) plot rigidly toward y-axis amount equal |1/Hs)|. With computation, shown Equation 274, input/output relationship derived, which called closed loop gain (GCL(s)). problem determined whether system represented Equation stable? And, what conditions that make system stable? Both questions answered with approximate analysis. point control theory that determining (and well) closed system, like Figure stable, accomplished just looking behavior open loop gain (GOL(s)). Equation 274, denominator must prevented from becoming zero; otherwise, would infinitely large shown Equation 278.
EQUATION 274:
G(s) GCL(s) simplified using Equation 275.
EQUATION 275:
EQUATION 278:
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Solving Equation results Equation 279.
EQUATION 279:
phase must 180°where Referring Figure recognized that point where |GOL(s)| |G(s)H(s)| (crossover frequency). phase this frequency must different from 180°. safe side, phase about 130°-140° requested, correspondingly phase margin (180° phase fCO) 45°. With some simplifications, criteria stability stated slope GOL(s) must dB/decade and, phase margin must least 45°. These only sufficient conditions stability, widely used because their simplicity. meaning second criteria should clear from previous discussion. first criteria interpreted this way. looking GOL(s) transfer function, observed that ratio polynomials. With some effort this point does really matter difficult be), GOL(s) numerator denominator transformed into product first order terms (eventually complex numbers), shown Equation 280. Each term numerator zero, each term denominator pole. normal conditions, like those encountered power supply units, each zero contributes open loop gain phase with phase contribution, while each pole contributes with phase contribution. From point view loop gain, each zero gives place change slope gain itself dB/decade, while pole gives dB/decade slope change. Therefore, slope GOL(s) criteria previously mentioned interpreted nearby crossover frequency (fCO), total contribution loop gain similar what single pole system would provide.
POWER CONVERTER CONTROL THEORY
that have rough idea meaning stability criteria determine system stable, refer back Buck Converter with voltage mode control loop (Figure 63). imperative match converter functions general control theory block diagram determine transfer functions. Therefore, Figure redrawn Figure where G(s), input output transfer function, made three blocks: GEA(s) error amplifier transfer function GM(s) transfer function generator GLP(s) output low-pass filter transfer function. H(s), transfer function from output input absent, better: H(s)
EQUATION 280:
FIGURE
BUCK CONVERTER VOLTAGE MODE LOOP
VREF GEA(s) GM(s) GLP(s)
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GM(s) transfer function probably immediately intuitive. think this way: input signal value with small amplitude sinusoidal waveform ripple superimposed, output will signal whose duty cycle value follows same sinusoidal around Steady state value. Simplistically, input/ output relationship ratio between output duty cycle range input sinusoidal amplitude frequency preserved. There different techniques that used mathematically determine relationship. Without going into such details important thing that soon topology power system have been decided, GM(s) computed. GLP(s) somehow easier, computed analytically, considering low-pass filter Figure where output capacitor also been taken into account.
FIGURE
ERROR AMPLIFIER TRANSFER FUNCTION
|GEA(s)|
Referring previous equations, GOL(s) G(s)H(s) GEA(s)GM(s)GLP(s), being H(s) Working results Equation 281.
FIGURE
BUCK CONVERTER OUTPUT STAGE
VOUT
EQUATION 281:
known known
unknown unknown
following details preferred gain even |GOL(s)| known: this point, GM(s) GLP(s) known: design effort consists finding function GEA(s) that makes system stable according definition previously given. analog design, this translates into computation passive components standard compensating networks, where used. such circuit shown Figure transfer function shown Figure lower frequency, higher gain should this because very high gain frequencies gives place small Steady state errors higher frequency, smaller gain should reduce effects high frequency noise between frequencies would best have fairly constant gain concluded, known desired |GOL(s)| value stated, resulting Equation 282.
FIGURE
ERROR AMPLIFIER NETWORK
EQUATION 282:
analog implementation, graphical solution easily found. less systematic approach, different capacitor values tested circuit Figure Figure until satisfactory solution found.
GEA(s) VOUT
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Digital Solutions
Until now, only analog solutions (how voltage current mode loops implemented analog) have been considered. This because, beginners, easier understand basic concepts analog domain first then convert them digital world. contrary, many experienced converter designers have great experience analog design presented material foundation upon which digital approach built course, digital solution passive power components will used; what changes generated feedback loop implemented. overview Microchip Switch Mode Power Supply devices follows, which provides understanding their architecture features they provide, which used implement Switch Mode Power Supply. generate triggers that will start operation, fault signals stop operation, currents greater than defined threshold internal comparators inhibit outputs, period counter reset external signals implement constant-off/-on outputs. high-speed 10-bit sample five signals same time will always convert input channels time (usually current voltage). Multiple triggers start converter operation: Individual software trigger Global software trigger Special Event Trigger generators trigger Timer1 Timer2 period match generators current-limit trigger generators Fault trigger
SWITCH MODE POWER SUPPLY (SMPS) dsPIC DEVICES
Microchip's dsPIC SMPS devices have been created specifically designers with implementation digital switching systems. These devices 16-bit processors based well established dsPIC30F dsPIC33F family devices, with three main building blocks: 16-bit Digital Signal Processor core Intelligent Power Peripheral (IPP) superset three peripherals: generator, high-speed 10-bit analog-to-digital converter (ADC), high-speed comparator. Nothing compared many other processors? contrary, features! points are: High performance peripherals High degree interconnection between three mentioned peripherals, that cooperate generation control output waveform without direct intervention signals four complimentary outputs) have same frequency, each operate independently with duty cycle resolution 1.05 operate nine different modes: Standard edge-aligned Complementary Push-pull Multi-phase Variable phase Fixed off-time Current reset Current-limit Independent time base
comparators used detect overcurrent, some current mode loops, used detect when inductor current reached preset value. While takes care greater part generation management PWM, ADC, comparator signals, engine have plenty time perform computations required close control loop digital solution. 16-bit 16-bit, high-speed multiplier 40bit accumulators allow very efficient implementation even high-complexity control algorithms. operations required implement digital loop basically sequence multiply/accumulate instructions. core capable implementing such instructions very efficient way. instruction performs following operations machine cycle dsPIC30F devices, dsPIC33F devices): Multiply values. Accumulate current multiply result previous sums. Update registers containing factors with values following operation. Increment pointers that they point values that will used later.
Efficient usage memory allows implementation fast accesses locations (and Flash) without reducing overall speed processing unit. Specifically, problems executing operation that while multiply/accumulate computational part performed, data must fetched from ready next iteration. This means that must possible make readaccess twice instruction cycle. Multiple solutions available. Microchip's approach split (only class instructions) into parts (XRAM Y-RAM) duplicate address data
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address generating hardware. paths thus available through which factors fetched simultaneously. complete control loop implementation, some additional work needed initial conditions usually, check that results within specified range; however, full control loop computation normally performed microseconds. Figure also shows inserted block diagram representing system. goal block generate output u(t) that drives system hand (the "PLANT") that output [y(t)] matches reference signal [x(t)]. input error between reference signal (ideal desired behavior PLANT) real output behavior. Obviously, target operate such that error that close zero possible results. Comparing Figure Figure recognized that transforms controller, while PLANT product GM(s)GLP(s). following, starting from description analog domain, will transformed into equivalent digital PID. Figure equation that describes behavior continuous time domain shown Equation 283.
both voltage current mode control loops, analog solution, objective design transfer function error amplifier (GEA(s)) make system stable. similar design objective reached digital design. very commonly used building block (proportional, integrative, derivative). normally used also analog domain, found very easy useful application digital domain also. guessed from name, made three basic blocks whose outputs are: Proportional input integral input derivative input Although there number ways these blocks interconnected, most traditional technique will investigated, where three blocks connected parallel, shown Figure
EQUATION 283:
transfer function (Laplace transform impulse response) shown Equation 284.
EQUATION 284:
FIGURE
GENERIC SYSTEM CONTROLLED
Proportional
Up(t)
e(t) x(t) Integrative Ui(t) U(t) PLANT y(t)
Derivative
Ud(t)
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shown Figure there zeros pole origin. high gain frequency preferred reduce errors, while high gain high frequency should avoided (noise spurious signals would enhanced). This very often transfer function slightly changed second pole (fp2, dashed transfer function). next step transform analog equations discrete time version. that, mapping from s-domain z-domain must performed using Equation 285. transformation called Z-transform. most notable features Z-transform that rational transfer function transforms rational transfer function This means that, starting from analog transfer function like Equation 280, transfer function obtained digital domain which strictly resembles shown Equation 286.
EQUATION 286:
EQUATION 285:
where sampling period
z-domain most useful domain where sampled signals analyzed systems synthesized. This discrete systems counterpart Laplace transform. easy move from time domain z-domain vice versa through
There possible variable transformations like Equation that maps s-domain z-domain. Each transformation different characteristics domains each other; however, details beyond scope this application note.
FIGURE
U(s)
ANALOG TRANSFER FUNCTION
Pole origin
db/sec db/sec
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block diagram shown Figure
FIGURE
GENERIC SYSTEM CONTROLLED DIGITAL
Proportional Up(z)
VREF Integrative E(z) Ui(z) U(Z)
PLANT
Derivative
Ud(z)
Using mathematics shown Equation 287, transfer function z-domain easily obtained.
results shown Equation 288.
EQUATION 288:
EQUATION 287:
where
Going back time domain (performing inverse Z-transform) shown Equation 289.
EQUATION 289:
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meaning such expression that current value output [u(n)] this case duty cycle PWM) computed from value output previous instant time [u(n 1)], plus current error times coefficient (KA), plus error from previous step times another coefficient (KB), plus error from steps ago, times third coefficient (KC). This discrete time domain equation dsPIC device requested calculate. Note that this operation performed maximum, once period, terms Equation rearranged, shown Equation 290. comments regarding Equation 290: proportional contribution depends difference between current error previous error. integrative contribution depends current error. derivative contribution depends increment error, which rewritten Equation 291. errors `0', u(n) there constant error: proportional contribution `0'. integrative part presents non-zero contribution. derivative part presents zero contribution. only present when current error very close previous error, u(n) longer changes. This explains residual error received this condition. This residual error then depends also resolution being used computations. only present, there always contribution, even when e(n) constant. Again, total residual error depends computations resolution.
EQUATION 290:
EQUATION 291:
starting from Equation 292, nulling three coefficients results Equation 293, which means that reality, contribution coming from three building blocks.
EQUATION 292:
EQUATION 293:
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Behavior
assumed from Equation Equation 288, changing values changes behavior system, which changes frequency response. easy relationship between coefficients transfer function. Referring Equation z-domain: transfer function constant transfer function zero origin pole transfer function zero pole origin proportional term alone capable sensibly reducing error, cannot nullify because (refer Equation 290) when error almost constant matter absolute value), zero, output from computation constant. This means that proportional term sensibly reduce error, non-zero residual error always results, which cannot completely eliminated proportional factor only. overcome this difficulty, integral term representing memory system, capable reducing proportional residual error zero. integral term should used with caution, since bring system oscillation. continuous accumulation non-zero values bring system saturate side, then other side, derivative component helps system reactive sharp changes error value, since contribution proportional difference between current previous errors. Until now, nothing been said about values three coefficients, There basically methods that used determine their values: empirical approach starting with trimming value until small residual error received, then incrementing until system reaches almost zero final error. finally, term incremented improve performances system against step changes input error. Table useful starting point understand relationship between coefficients system behavior. should noted however, that this table only starting point since dissimilar systems behave differently.
TABLE
RELATIONSHIP BETWEEN COEFFICIENTS SYSTEM BEHAVIOR
Rise Time Decrease Decrease Small change Overshoot Increase Increase Decrease Settling Time Small change Increase Steady State Error Decrease Eliminate
Closed Loop Response
Decrease Small change
second approach more systematic known Ziegler/Nichols method. this technique, start incrementing proportional gain (while other coefficients zero) until system edge stability (step changes applied reference value). this condition output oscillation with period corresponding coefficient other coefficients read from tables that found Control Theory textbooks.
should also noted that full equation often implemented. Often, only proportional-integration part (PI) implemented. This depends system system responses needed.
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DIGITAL CONTROL LOOP WITH dsPIC DEVICE
does into DC-DC converter control loops? Thinking "digital terms" Figure redrawn, shown Figure where sequence operations split between peripherals (hardware) SMPS parts computations (firmware). feedback voltage converted on-board ADC. dsPIC device, 10-bit value returned; reality known that converter always converts signals. This intended make available user, same time, voltage current. this implementation current measurement used. Instead, basic voltage control loop implemented.
FIGURE
BUCK CONVERTER VOLTAGE MODE CONTROL LOOP IMPLEMENTED dsPIC® DEVICE
VOUT
dsPIC®
Duty Cycle Register
Engine Operation
VREF
Coefficients Buffer
Error Samples Buffer e(n)
(discarded)
40-bit Accumulator
Boundary Tests
(Duty Cycle)
Computation
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voltage from subtracted from reference signal resulting error into engine implement PID. engine implements Equation exactly. 40-bit accumulator engine used accumulate previous result values, which value u(n) Equation 294. reverse this delay time determines maximum sampling frequency that reasonable system. Remembering Nyquist sampling theorem, which states that able reconstruct original signal, sampling frequency must least twice maximum frequency signal interest. This value fact only theoretical; real world must higher. Typical values from Correspondingly, maximum signal frequency that correctly operated upon times smaller that sampling frequency. clarify concept, look Figure 89(A), where sampling frequency, maximum signal frequency value. Optimally, trying speed much possible operation digital loop have smallest possible delay loop, which maximum available sampling frequency. why? point that there high sampling frequency, maximum signal frequency high; this means that loop easily respond high frequency changes environmental conditions system. graphical example Figure 89(B) different values (fs1 fs2). Keeping same ratio between sampling frequency maximum allowable signal frequency, results larger bandwidth with compared fs1. further investigate concept, suppose input voltage some ripple added, this ripple sinusoid frequency sinusoid frequency small, system easily adapt parameters converter compensate this sinusoidal change input give stable (without ripple) output. Now, continuously increment sine wave frequency. certain value, system will able follow compensate; some value system will fail correctly compensate situation where system delay will longer than period sinusoid loop will completely fail control output voltage (see Figure 89(C), with some simplifications).
EQUATION 294:
output (u(n)) current duty cycle value written into duty cycle register. This almost that needed implement basic digital loop. reality, some attention must paid fact that, feedback voltage very from reference voltage, large contributions duty cycle accumulated. This results effect that duty cycle become large, with saturation effect. However, recover from this situation, better avoid since response time greatly affected. good practice clamp duty cycle value period (this meaning "boundary tests" Figure 87). digital implementation control loop, there some delays that must taken into account: Analog-to-Digital sample/convert time computations time Some non-zero delay power component response Low-pass filter delay these delays summed this time provides boundary condition sampling frequency, that does make sense sample system faster that reverse this time. other words, this required time change system propagate along loop.
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FIGURE SYSTEM LOOP BANDWIDTH SAMPLING FREQUENCY
finite output possible values. example, 10-bit ADC, only 1024 output values available, while input infinitely continuous range. what effect such discretizations? Both them considered noise that added signals. However, analysis effects such additive noise beyond scope this application note. But, important point regarding discretization introduced: digital resolution will impact behavior system. minimum resolution computed from ratio desired output voltage amplitude required precision volts output voltage, according relationship shown Equation 295.
EQUATION 295:
OUT, requested nominal output when precision required, results Equation 296.
EQUATION 296:
5res bits 0.05
fs1fs2-
System Bandwidth
digital peripheral, there different resolutions. digital frequency resolution depends number bits used generate basic frequency. SMPS devices frequency computed with Equation 297.
EQUATION 297:
-PTPER
where PTPER register setting frequency
represent sinusoidal superimposed signal nominal duty cycle, where: Signal compensated system Signal only partially compensated Signal compensated
minimum change frequency corresponds minimum change value PTPER register. dsPIC30F devices, since three Least Significant bits (LSbs) register available, minimum change which corresponds Table provides frequency resolution that received various values nominal frequency. resolution plotted Figure
main differences between analog digital loop, that while former values time amplitude continuous, latter time amplitude both discretized. Time discrete since, seen above, samples signals have been taken with fixed period repetition rate. Amplitude discrete since maps input values into
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TABLE
Frequency 100000 150000 200000 250000 300000 350000 400000 450000 500000 550000 600000 650000 700000
FREQUENCY RESOLUTION
Maximum Frequency 100085,98 150193,55 200344,23 250538,10 300775,19 351055,58 401379,31 451746,44 502157,03 552611,14 603108,81 653650,11 704235,09 Minimum Frequency 99914,16 149806,95 199656,95 249464,21 299228,79 348950,75 398630,14 448267,01 497861,42 547413,42 596923,08 646390,43 695815,54
FIGURE<br
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