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ADS8285
www.ti.com. SLAS656A 2009 REVISED SEPTEMBER 2009
18-BIT, 1-MSPS, UNIPOLAR SINGLE ENDED WITH ON-CHIP DRIVER (OPA) 8-CHANNEL DIFFERENTIAL MULTIPLEXER
FEATURES
1.0-MHz Sample Rate, Zero Latency Full Speed 18-Bit Resolution Supports Unipolar Single Ended Input Range: Built-In Eight Channel, Single Ended Multiplexer; with Channel Count Selection Auto/Manual Mode On-Board Single Ended Input, Differential Output Driver (OPA) Buffered Reference Output Level Shift Bipolar ±4-V Input with External Resistance Divider Reference/2 Output Offset External Signal Conditioner 18-/16-/8-Bit Parallel Interface SNR: 98dB 2-kHz THD: -117dB 2-kHz Power Dissipation: 331.25 MSPS Including Driver Internal Reference Internal Reference Buffer 64-Pin Package
APPLICATIONS
Medical Imaging/CT Scanners Automated Test Equipment High-Speed Data Acquisition Systems High-Speed Closed-Loop Systems
DESCRIPTION
ADS8285 high-performance analog system-on-chip (SoC) device with 18-bit, 1-MSPS converter, internal reference, on-chip driver (OPA), 8-channel single ended multiplexer. channel count multiplexer auto/manual scan modes device user selectable. driver designed leverage very high noise performance differential optimum power usage levels. ADS8285 outputs buffered reference signal level shifting ±4-V bipolar signal with external resistance divider. Vref/2 output signal available offset signal conditioning circuit. device also includes 18-/16-/8-bit parallel interface. ADS8285 available 64-pin package characterized from -40°C 85°C.
HIGH-SPEED CONVERTER FAMILY
TYPE/SPEED 18-Bit Pseudo-Diff Single Ended ADS8380 ADS8382 18-Bit Pseudo-Bipolar, Fully Diff ADS8482 ADS8327 16-Bit Pseudo-Diff ADS8328 ADS8319 ADS8318 16-Bit Pseudo-Bipolar, Fully Diff ADS8254 14-Bit Pseudo-Diff 12-Bit Pseudo-Diff ADS7886 ADS8406 ADS7890 ADS7883 ADS8413 ADS7891 ADS7881 ADS8372 ADS8472 ADS8402 ADS8412 ADS8422 ADS8370 ADS8371 ADS8471 ADS8255 ADS8401 ADS8405 ADS8411 ADS8410 ADS8285 ADS8284 ADS8484 ADS8383 ~600 ADS8381 ADS8481 1.25 4MHz
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2009, Texas Instruments Incorporated
ADS8285
SLAS656A 2009 REVISED SEPTEMBER 2009. www.ti.com
AUTO, MXCLK
VOLTAGE CLAMP
AGND +VBD BGND
OPA-1 MSPS
D0-D17 LOGIC BUFFER 18/16 BYTE CONVST
OPA-2 VCMI
BUSY
VCM-O VREF/2
REFIN
BUF-REF
REFM
PD-RBUF
INTERNAL
REFOUT
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These devices have limited built-in protection. leads should shorted together device placed conductive foam during storage handling prevent electrostatic damage gates.
ORDERING INFORMATION
MODEL MAXIMUM INTEGRAL LINEARITY (LSB) ±2.5 MAXIMUM DIFFERENTIAL LINEARITY (LSB) +1.5/-1 MISSING CODES RESOLUTION (BIT) 64-pin ADS8285l ±4.5 +1.5/-1 -40°C 85°C PACKAGE TYPE PACKAGE DESIGNATOR TEMPERATURE RANGE ORDERING INFORMATION ADS8285IBRGCT ADS8285IBRGCR ADS8285IRGCT ADS8285IRGCR TRANSPORT MEDIA QUANTITY 2000 2000
ADS8285lB
most current package ordering information, Package Option Addendum this document, website www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE CH(i) AGND (both inputs) AGND +VBD BDGND control digital input voltage control digital output Multiplexer control digital input voltage Power control digital input voltage Operating temperature range Storage temperature range Junction temperature (TJmax) package Lead temperature, soldering Power dissipation Thermal impedance Vapor phase sec) Infrared sec) VEE-0.3 -0.3 -0.3 -0.3 -0.3 (+VBD 0.3) -0.3 (+VBD 0.3) -0.3 (+VA 0.3) -0.3 (+VCC 0.3) Max-TA)/ °C/W UNIT
Stresses beyond those listed under absolute maximum ratings cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under recommended operating conditions implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability.
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SPECIFICATIONS
-40°C 85°C, +VBD Vref fSAMPLE MSPS (unless otherwise noted)
PARAMETER ANALOG INPUT Full-scale input voltage multiplexer input Absolute input range multiplexer input Input common-mode voltage SYSTEM PERFORMANCE Resolution missing codes
TEST CONDITIONS
UNIT
CH(i)P-CH(i)M [CH(i)P CH(i)M]
-Vref -0.2 (Vref)/2 (Vref)/2
Vref Vref (Vref)/2
ADS8285IB ADS8285I ADS8285IB ADS8285I ADS8285IB ADS8285I ADS8285IB ADS8285I 85°C ADS8285IB ADS8285I External reference 3FFF0H output code. VCC, variation individually -0.1 -0.1 18-bit level -2.5 -4.5 ±1.25 ±1.5 ±0.6 ±0.6 ±0.05 ±0.05 ±0.025 ±0.025
Bits Bits
Integral linearity
Differential linearity
Offset error Offset drift Gain error
ppm/°C
power supply rejection ratio SAMPLING DYNAMICS Conversion time
+VBD +VDB +VBD +VDB
Acquisition time Maximum throughput rate Aperture delay Aperture jitter Settling time Over voltage recovery DYNAMIC CHARACTERISTICS ADS8285I ADS8285IB Total harmonic distortion (THD) ADS8285I ADS8285IB ADS8285I ADS8285IB ADS8285I ADS8285IB Signal-to-noise ratio (SNR) ADS8285I ADS8285IB ADS8285I ADS8285IB
only (OP1, OP2) only
kHz, LoPWR kHz, LoPWR
-115 -117 -105 -105 -100 -100 97.5 97.5
Ideal input span, does include gain offset error. This endpoint INL, best fit. means least significant bit. Calculated first nine harmonics input frequency. Measured relative acutal measured reference. Submit Documentation Feedback Product Folder Link(s) :ADS8285
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ADS8285
www.ti.com. SLAS656A 2009 REVISED SEPTEMBER 2009
SPECIFICATIONS (continued)
-40°C 85°C, +VBD Vref fSAMPLE MSPS (unless otherwise noted)
PARAMETER ADS8285I ADS8285IB Signal-to-noise distortion (SINAD) ADS8285I ADS8285IB ADS8285I ADS8285IB ADS8285I ADS8285IB Spurious free dynamic range (SFDR) ADS8285I ADS8285IB ADS8285I ADS8285IB -3dB small signal bandwidth VOLTAGE REFERENCE INPUT (REFIN) Reference voltage REFIN, Vref Reference input current INTERNAL REFERENCE OUTPUT (REFOUT) Internal reference start-up time Reference voltage range, Vref Source current Line regulation Drift BUFFERED REFERENCE OUTPUT (BUF-REF) Output current REFERENCE/2 OUTPUT (VCMO) Output current ANALOG MULTIPLEXER Number channels Channel channel crosstalk Channel selection DIGITAL INPUT-OUTPUT CONTROL PINS Logic Family-CMOS Logic level MULTIPLEXER CONTROL PINS Logic Family CMOS Logic level POWER CONTROL PINS Logic Family CMOS Logic level -0.3 +0.3 -0.3 +0.3 loads loads +VBD-1 +VBD-0.6 +VBD +VBD Auto sequencer with selection channel count manual selection through control lines REFIN +85°C REFIN 85°C Static load 4.75 5.25 From (+VA), with 1-µF storage capacitor 4.081 4.096 4.111 PPM/°C 4.096 TEST CONDITIONS kHz, LoPWR kHz, LoPWR 97.9 97.94 96.7 96.7 93.8 94.5 UNIT
POWER SUPPLY REQUIREMENTS
vary ±20% Submit Documentation Feedback Product Folder Link(s) :ADS8285
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SPECIFICATIONS (continued)
-40°C 85°C, +VBD Vref fSAMPLE MSPS (unless otherwise noted)
PARAMETER +VBD Power supply voltage driver positive supply (VCC) current (for together) -5V, inputs shorted each other connected TEST CONDITIONS 4.75 4.75 -7.5 11.65 VCC= PD-RBUF Quiescent current PD-RBUF 5.25 5.25 UNIT
driver negative supply VEE) current (for VCC= +5V, inputs shorted together) each other connected supply current, 1-MHz sample rate Reference buffer (BUF-REF) supply current (VCC GND) TEMPERATURE RANGE Operating free-air
PD-RBUF powers down reference buffer (BUF-REF), note that does 3-state BUF-REF output.
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TIMING REQUIREMENTS
specifications typical -40°C 85°C, +VBD
PARAMETER t(CONV) t(ACQ) t(HOLD) tpd1 tpd2 tpd3 tsu1 tsu2 tpd4 tsu3 tdis tsu5 Conversion time Acquisition time Sample capacitor hold time CONVST BUSY high Propagation delay time, conversion BUSY Propagation delay time, start convert state rising edge BUSY Pulse duration, CONVST Setup time, CONVST Pulse duration, CONVST high CONVST falling edge jitter Pulse duration, BUSY signal Pulse duration, BUSY signal high Hold time, first data transition low, read cycle, BYTE BUS18/16 input changes) after CONVST Delay time, Setup time, high high Pulse duration, Enable time, read cycle) data valid Delay time, data hold from high Delay time, BUS18/16 BYTE rising edge falling edge data valid Pulse duration, high Pulse duration, high Hold time, last read cycle rising edge CONVST falling edge Propagation delay time, BUSY falling edge next read cycle) falling edge Delay time, BYTE edge BUS18/16 edge skew Setup time, BYTE BUS18/16 transition falling edge Hold time, BYTE BUS18/16 transition falling edge Disable time, high high read cycle) 3-stated data Delay time, BUSY data valid delay Delay time, rising edge BUSY falling edge Delay time, BUSY falling edge rising edge BYTE transition setup time, from BYTE transition next BYTE transition, BUS18/16 transition setup time, from BUS18/16 next BUS18/16. t(ACQ)min
UNIT
tsu(ABORT) Setup time from falling edge CONVST (used start valid conversion) next falling edge CONVST (when CONVST used abort) next falling edge (when used abort).
input signals specified with (10% +VBD) timed from voltage level (VIL VIH)/2. timing diagrams. timing measured with equivalent loads data bits BUSY pins.
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TIMING REQUIREMENTS
specifications typical -40°C 85°C, +VBD
PARAMETER t(CONV) t(ACQ) t(HOLD) tpd1 tpd2 tpd3 tsu1 tsu2 tpd4 tsu3 tdis tsu5 Conversion time Acquisition time Sample capacitor hold time CONVST BUSY high Propagation delay time, conversion BUSY Propagation delay time, start convert state rising edge BUSY Pulse duration, CONVST Setup time, CONVST Pulse duration, CONVST high CONVST falling edge jitter Pulse duration, BUSY signal Pulse duration, BUSY signal high Hold time, first data transition low, read cycle, BYTE BUS18/16 input changes) after CONVST Delay time, Setup time, high high Pulse duration, Enable time, read cycle) data valid Delay time, data hold from high Delay time, BUS18/16 BYTE rising edge falling edge data valid Pulse duration, high Pulse duration, high Hold time, last read cycle rising edge CONVST falling edge Propagation delay time, BUSY falling edge next read cycle) falling edge Delay time, BYTE edge BUS18/16 edge skew Setup time, BYTE BUS18/16 transition falling edge Hold time, BYTE BUS18/16 transition falling edge Disable time, high high read cycle) 3-stated data Delay time, BUSY data valid delay Delay time, rising edge BUSY falling edge Delay time, BUSY falling edge rising edge BYTE transition setup time, from BYTE transition next BYTE transition, BUS18/16 transition setup time, from BUS18/16 next BUS18/16. t(ACQ)min
UNIT
tsu(ABORT) Setup time from falling edge CONVST (used start valid conversion) next falling edge CONVST (when CONVST used abort) next falling edge (when used abort).
input signals specified with (10% +VBD) timed from voltage level (VIL VIH)/2. timing diagrams. timing measured with 20-pF equivalent loads data bits BUSY pins.
MULTIPLEXER TIMING REQUIREMENTS
4.75 -7.5
tsu6 Setup time MXCLK rising edge Multiplexer driver settle time from MXCLK rising edge CONVST falling edge) UNIT
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ASSIGNMENTS
PACKAGE (TOP VIEW)
PD-RBUF AGND VCMI
BUF-REF VCMO AGND REFOUT REFIN REFM REFM AGND CONVST BYTE
ADS8285
BUS18_16 +VBD BUSY BGND +VBD DB10
NAME
MULTIPLEXER INPUT PINS VCMI Analog input multiplexer channel Device performance optimized source impedance this input. Analog input multiplexer channel Device performance optimized source impedance this input. Analog input multiplexer channel Device performance optimized source impedance this input. Analog input multiplexer channel Device performance optimized source impedance this input. Reference two' input buffer, common mode input signal. Device performance optimized source resistance this input. converts (VCHn VVCMI). VCMO output connected VCMI through resistance. Analog input multiplexer channel Device performance optimized source impedance this input. Analog input multiplexer channel Device performance optimized source impedance this input. Analog input multiplexer channel Device performance optimized source impedance this input. Analog input multiplexer channel Device performance optimized source impedance this input.
INPUT PINS inverting input., connect 1-nF capacitor across Inverting input, connect 1-nF capacitor across
REFERENCE INPUT/ OUTPUT PINS REFM REFIN REFOUT VCMO BUF-REF Reference ground. Reference Input. 0.1-µF decoupling capacitor between REFIN REFM. Reference Output. 1-µF capacitor between REFOUT REFM when internal reference used. This outputs REFIN/2 used common-mode voltage differential analog inputs. Buffered reference output. Useful level shift bipolar signals using external resistors.
POWER CONTROL PINS Copyright 2009, Texas Instruments Incorporated
AUTO MXCLK AGND AGND DB17 DB16 DB15 DB14 DB13 DB12
FUNCTIONS
DESCRIPTION
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FUNCTIONS (continued)
NAME PD-RBUF DESCRIPTION High this powers down reference buffer (BUF-REF).
MULTIPLEXER CONTROL PINS AUTO High level this selects auto mode multiplexer scanning. level selects manual mode multiplexer scanning Acts multiplexer address when Auto (manual mode). auto mode (Auto multiplexer channel selection reset rising edge MXCLK while Acts multiplexer address when AUTO (manual mode). auto mode (AUTO select last multiplexer channel (channel count) auto scan sequence. Acts multiplexer address when AUTO (manual mode). auto mode (AUTO select last multiplexer channel (channel count) auto scan sequence. Multiplexer channel selected rising edge MXCLK irrespective whether auto manual mode. Device BUSY output connected MXCLK that device selects next channel every sample. necessary allow three MXCLKs after device power During this period device loads factory settings driver amplifier multiplexer.
MXCLK
DATA 8-BIT 42-49, 52-61 Data BYTE BUS18/16 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 (MSB) (LSB) BYTE BUS18/16 ones ones ones ones ones ones ones ones ones ones BYTE BUS18/16 ones ones ones ones ones ones (LSB) ones ones ones ones ones ones ones ones ones ones 16-BIT BYTE BUS18/16 (MSB) (LSB) BYTE BUS18/16 ones ones ones ones ones ones ones ones ones ones ones ones ones ones (LSB) ones ones 18-BIT BYTE BUS18/16 (MSB) (LSB)
CONTROL PINS BUSY BUS18_16 BYTE CONVST Status output. This held high when device converting. size select input. Used selecting 18-bit 16-bit wide transfer. Refer DATA description above. Byte Select Input. Used 8-bit reading. Refer DATA description above. Convert start. This input active independent input. Synchronization pulse parallel output. Chip select.
DEVICE POWER SUPPLIES Negative supply (OP1, OP2) Positive supply (OP1, OP2, BUF-REF) Analog power supply.
AGND +VBD BGND
Analog ground. Digital power supply bus. Digital ground interface digital supply.
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FUNCTIONS (continued)
NAME DESCRIPTION
CONNECTED PINS connection.
DEVICE OPERATION TIMING DIAGRAMS
ADS8285 analog system-on-chip (SoC) device. device includes multiplexer, single-ended input/differential output driver differential input high-performance ADC, additional internal reference, buffered reference output, REF/2 output. Figure shows basic operation device (including elements). Subsequent sections describe detailed timings individual blocks device (primarily multiplexer ADC).
CONVST
BUSY
SELECTED CHANNEL
(n-1)
(n+1)
(n+2)
(n+3)
Vref differential input assuming alternate channels have+Vref Input SAMPLE, VChi- VCMI) S(m-1) -Vref S(m) +Vref S(m+1) -Vref S(m+2) +Vref
Parallel
(n-2)
(n-1)
(n+1)
Figure Device Operation shown diagram, device controlled with only (CONVST) digital input. falling edge CONVST, BUSY output device goes high. high level BUSY indicates device sampled signal converting sample into digital equivalent. After conversion complete, BUSY output falls logic level device output data corresponding recently converted sample available reading.
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recommended (not mandatory) short BUSY output device MXCLK input. device selects channel every rising edge MXCLK. multiplexer differential. multiplexer driver designed settle 18-bit level before sampling; even maximum conversion speed. control timing: timing diagrams this section describe operation; multiplexer operation described later section.
CONVST tpd1 BUSY tsu1 tpd3 CONVERT t(CONV) t(HOLD) SAMPLING (When Toggle) t(ACQ) tsu(ABORT) BYTE 18/16 tpd4 tsu5 tsu2 tsu5 tsu(ABORT) t(CONV) tpd2
DB[17:12] Hi-Z
D[17:12] D[9:4]
tdis Hi-Z
Hi-Z Hi-Z
DB[11:10]
D[11:10]
D[3:2]
D[1:0]
DB[9:0]
Signal
Hi-Z
D[9:0]
Hi-Z
internal device
Figure Timing Conversion Acquisition Cycles with Toggling
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CONVST tpd1 BUSY tsu1 tpd3 CONVERT t(CONV) t(HOLD) SAMPLING (When Toggle) tpd2
t(CONV)
t(ACQ) tsu(ABORT) BYTE 18/16 tpd4 tsu5 tsu(ABORT)
DB[17:12] Previous Hi-Z D[17:12] tdis Hi-Z
D[17:12] D[9:4]
tdis Hi-Z
Repeated
D[17:12]
DB[11:10]
Hi-Z
Previous
D[11:10]
Hi-Z
D[11:10]
D[3:2]
D[1:0]
Hi-Z
Repeated
D[11:10]
DB[9:0]
Signal
Hi-Z
Previous
[9:0]
Hi-Z
D[9:0]
Hi-Z
Repeated
[9:0]
internal device
Figure Timing Conversion Acquisition Cycles with Toggling, Tied BDGND
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CONVST tpd1 BUSY tpd2
CONVERT t(CONV) t(HOLD) t(CONV)
SAMPLING (When tsu(ABORT) BYTE 18/16 tpd4
t(ACQ)
tsu(ABORT)
tsu5
tsu5
tdis
D[17:12] D[9:4]
DB[17:12]
Hi-Z
Hi-Z
DB[11:10]
Hi-Z
D[11:10]
D[3:2]
D[1:0]
Hi-Z
DB[9:0]
Hi-Z
D[9:0]
Hi-Z
Signal
internal device
Figure Timing Conversion Acquisition Cycles With Tied BDGND, Toggling
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CONVST tpd1 BUSY tpd2
CONVERT tpd3 t(HOLD)
t(CONV) tpd3 t(HOLD) t(ACQ)
t(CONV)
SAMPLING (When
tsu(ABORT) BYTE tsu5 18/16 tsu5 DB[17:12]
D[17:12] D[9:4]
tsu(ABORT)
tsu5
tsu5
Next D[17:12]
DB[11:10]
Previous
D[11:10]
D[3:2]
D[1:0]
Next D[11:10]
DB[9:0]
Signal
D[9:0]
Next D[9:0]
internal device
Figure Timing Conversion Acquisition Cycles With Tied BDGND Auto Read
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BYTE tsu5 18/16
Hi-Z Valid tdis Hi-Z Valid
tdis Hi-Z
DB[17:0]
Valid
Figure Detailed Timing Read Cycles Multiplexer: multiplexer modes sequencing namely auto sequencing manual sequencing. Multiplexer mode selection operation controlled with AUTO, MXCLK pins. Auto sequencing: logic level AUTO selects auto sequencing mode. possible select number channels scanned (always starting from channel zero) auto sequencing mode. Pins select channel count (last channel auto sequence). every rising edge MXCLK while logic zero level, next higher channel ascending order) selected. Channel selection rolls over channel zero rising edge MXCLK after channel selection reaches channel count (last channel auto sequence selected pins C1and C2). time during sequence channel sequence reset channel zero. rising edge MXCLK while logic level resets channel selection channel zero. Table Channel Selection Auto Mode
CHANNEL COUNT PINS CLOCK MXCLK LAST CHANNEL SEQUENCE CHANNEL SEQUENCE 0,1,0,1,0,. 0,1,2,3,0,1,2,. 0,1,2,3,4,5,,0,1,. 0,1,2,3,4,5,6,7,0. (channel reset zero)
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MXCLK
tsu6
Selected Channel
AUTO device operation auto mode
Figure Multiplexer Auto Mode Timing Diagram Manual sequencing: logic zero level AUTO selects manual sequencing mode. Pins C1and channel address. rising edge MXCLK, addressed channel connected driver input. Table Channel Selection Manual Mode
MODE AUTO CHANNEL ADDRESS MXCLK CONNECTED CHANNEL
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MXCLK
tsu6
Selected Channel
AUTO device operation manual mode
Figure Multiplexer Manual Mode Timing Diagram
TYPICAL CHARACTERISTICS
HISTOGRAM (CH0 without switching)
25000 25°C, Vref 4.096, 20000 15000
22583
HISTOGRAM (CH0 with switching, 0-1-0)
25000 25°C, Vref 4.096,
INTERNAL REFERENCE VOLTAGE FREE-AIR TEMPERATURE
4.098 4.0975 +VBD
20000
16744 1377
Reference Voltage
19066 18527
4.097
15000
1241
4.0965
10000
5999
10000
4.096 4.0955 4.095
5000
5000
1078
3400 2337
131086
131087
131088
131089
131090
13109
131092
131093
131094
131095
13108
131082
131083
131084
131085
131086
131087
131088
131089
131090
13109
131096
Free-Air Temperature
Figure
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
INTERNAL REFERENCE VOLTAGE SUPPLY VOLTAGE
4.0972 25°C 4.09719
ANALOG VOLTAGE (+VA) SUPPLY CURRENT (IA) FREE-AIR TEMPERATURE
43.5 Throughput MSPS
43.5
SUPPLY CURRENT (IA) ANALOG VOLTAGE (+VA)
25°C, Throughput MSPS
Supply Current
4.09718 4.09717 4.09716 4.09715 4.09714 4.09713 4.75
Supply Current
Reference Voltage
42.5 41.5 40.5 Free Temperature
42.5 41.5 4.70 4.80 4.90 5.10 5.20 5.30 5.40 Analog Voltage
4.85
4.95 5.05 5.15 Supply Voltage
5.25
Figure
Figure POSITIVE SUPPLY CURRENT (ICC) FREE-AIR TEMPERATURE
Figure POSITIVE SUPPLY CURRENT (ICC) POSITIVE SUPPLY VOLTAGE (+VCC)
13.9
ANALOG SUPPLY CURRENT SAMPLE RATE
25°C
Supply Current
Supply Current
25°C,
13.8 13.7 13.6 13.5 13.4 13.3 13.2
Supply Current
1000 Throughput kSps
Free Temperature
4.75
5.25 5.75 6.75 6.25 VCC+ Supply Voltage
7.25
Figure
Figure NEGATIVE SUPPLY CURRENT (IEE) NEGATIVE SUPPLY VOLTAGE (-VEE)
10.98
Differential Linearity
Figure
SUPPLY CURRENT (IEE) FREE-AIR TEMPERATURE
12.5
DIFFERENTIAL NONLINEARITY FREE-AIR TEMPERATURE
0.75 0.25 -0.25 -0.5 -0.75 Free Temperature Channel Vref 4.096, Throughput MSPS
Supply Current
25°C,
Supply Current
10.96 10.94 10.92 10.9 10.88 10.86 10.84 10.82 10.8
11.5 10.5 Free Temperature
10.78 -7.5 -6.5 -5.5 -4.5 -3.5 -2.5 Supply Voltage
Figure
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL NONLINEARITY ANALOG SUPPLY VOLTAGE (+VA)
DIFFERENTIAL NONLINEARITY REFERENCE VOLTAGE
DIFFERENTIAL NONLINEARITY SUPPLY VOLTAGE (VCC)
Differential Linearity
-0.2 -0.4 -0.6 -0.8 Voltage Supply 25°C, Vref 4.096, -7.5 -2.5 Throughput MSPS
Differential Linearity
Differential Linearity
0.75 0.25 -0.25
0.75 0.25 -0.25
Channel Vref 4.096, 25°C, Throughput MSPS
Channel 25°C, Throughput MSPS
-0.5 -0.75 4.75 4.85 4.95 5.05 5.15 Analog Supply 5.25
-0.5 -0.75 VREF Reference Volyage
Figure DIFFERENTIAL NONLINEARITY MULTIPLEXER CHANNELS
Figure INTEGRAL NONLINEARITY FREE-AIR TEMPERATURE
Integral Linearity
Integral Linearity
Figure INTEGRAL NONLINEARITY ANALOG SUPPLY VOLTAGE (+VA)
-0.5 -1.5 4.75 Channel 25°C, Vref 4.096, Throughput MSPS
Differential Linearity
-0.2 -0.4 -0.6 -0.8
-0.5 -1.5
25°C, Vref 4.096, Throughput MSPS
Channel Vref 4.096, Throughput MSPS
Multiplexer Channnels
Free Temperature
4.85
4.95 5.05 5.15 Suply Voltage
5.25
Figure INTEGRAL NONLINEARITY REFERENCE VOLTAGE
Integral Linearity
Figure INTEGRAL NONLINEARITY SUPPLY VOLTAGE (+VCC)
Channel 25°C, Vref 4.096, 25°C -7.5 -2.5 Throughput MSPS
Figure INTEGRAL NONLINEARITY MULTIPLEXER CHANNELS
Integral Linearity
-0.5 -1.5 Multiplexer Channels 25°C, Vref 4.096, Throughput MSPS
Integral Linearity
-0.5 -1.5 Channel 25°C, Throughput MSPS
-0.5 -1.5 4.75
VREF Reference Voltage
5.25 5.75 6.25 6.75 Supply Voltage
7.25
Figure
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
FULL CHIP OFFSET ERROR FREE-AIR TEMPERATURE
Channel Vref 4.096,
Channel Vref 4.096, 25°C, -VEE
FULL CHIP OFFSET ERROR SUPPLY VOLTAGE (VCC)
FULL CHIP OFFSET ERROR ANALOG SUPPLY VOLTAGE (+VA)
Channel 25°C, Vref 4.096,
FULL CHIP OFFSET
FULL CHIP OFFSET
-100 -150
FULL CHIP OFFSET
Free Temperature
Supply Voltage
4.75
4.85
4.95 5.05 5.15 Supply Voltage
5.25
Figure FULL CHIP OFFSET ERROR REFERENCE VOLTAGE
Channel 25°C,
Figure FULL CHIP OFFSET ERROR CHANNEL
0.08
25°C, Vref 4.096, Throughput MSPS
Figure FULL CHIP GAIN ERROR FREE-AIR TEMPERATURE
0.07
Full chip gain Error
FULL CHIP OFFSET
FULL CHIP OFFSET
0.06 0.05 0.04 0.03 0.02 0.01 Channel Vref 4.096, Free Temperature
-100 -150
VREF Reference Voltage
Multiplexer Channels
Figure FULL CHIP GAIN ERROR SUPPLY VOLTAGE (VCC)
0.08 0.07
Figure FULL CHIP GAIN ERROR ANALOG SUPPLY VOLTAGE (+VA)
0.08 0.07
0.08 0.07
Figure FULL CHIP GAIN ERROR REFERENCE VOLTAGE
Full Chip Gain Error
Full Chip Gain Error
0.06 0.05 0.04 0.03 0.02 0.01 Channel Vref 4.096, 25°C, -VEE Supply Voltage
0.06 0.05 0.04 0.03 0.02 0.01 4.75 Channel Vref 4.096 25°C, 4.85 4.95 5.05 5.15 Supply Voltage 5.25
Full Chip Gain Error
0.06 0.05 0.04 0.03 0.02 0.01 VREF Reference Voltage Channel 25°C,
Figure
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
FULL CHIP GAIN ERROR MULTIPLEXER CHANNELS
0.08
Signal Noise Ratio
97.5 97.4 97.3 97.2 97.1 96.9 96.8 96.7 96.6 Channel Vref 4.096, kHz, Throughput MSPS Free Temperature
SIGNAL-TO-NOISE RATIO FREE-AIR TEMPERATURE
-110
TOTAL HARMONIC DISTORTION FREE-AIR TEMPERATURE
Total Harmonic Distortion
Channel Vref 4.096, kHz, Throughput MSPS
0.07
Full Chip Gain Error
-111 -112 -113 -114 -115 -116
0.06 0.05 0.04 0.03 0.02 0.01 25°C, Vref 4.096, Multiplexer Channels
96.5
Free Temperature
Figure SPURIOUS FREE DYNAMIC RANGE FREE-AIR TEMPERATURE
SFDR Spurious Free Dynamic Range
ENOB Effective Number Bits bits
15.95 15.9 15.85 15.8 15.75 15.7 15.65 15.6 15.55 15.5
Figure EFFECTIVE NUMBER BITS FREE-AIR TEMPERATURE
Signal Noise Ratio
Figure SIGNAL-TO-NOISE RATIO ANALOG SUPPLY VOLTAGE (+VA)
97.5 97.4 97.3 97.2 97.1 96.9 96.8 96.7 96.6
Channel Vref 4.096, kHz, Throughput MSPS Free Temperature
Channel Vref 4.096, kHz, Throughput MSPS Free Temperature
Channel Vref 4.096, kHz, Throughput MSPS 4.85 4.95 5.05 5.15 Supply Voltage 5.25
96.5 4.75
Figure TOTAL HARMONIC DISTORTION ANALOG SUPPLY VOLTAGE (+VA)
Total Harmonic Distortion
Channel Vref 4.096, kHz, Throughput MSPS
SFDR Spurious Free Dynamic Range
Figure SPURIOUS FREE DYNAMIC RANGE ANALOG SUPPLY VOLTAGE (+VA)
ENOB Effective Number Bits bits
Figure EFFECTIVE NUMBER BITS ANALOG SUPPLY VOLTAGE (+VA)
15.95 15.9 15.85 15.8 15.75 15.7 15.65 15.6 15.55 15.5 4.75 4.85 4.95 5.05 5.15 Supply Voltage 5.25 Channel Vref 4.096, kHz, Throughput MSPS
-110 -111 -112 -113 -114 -115 -116 4.75
4.75 Channel Vref 4.096, kHz, Throughput MSPS
4.85
4.95 5.05 5.15 Supply Voltage
5.25
4.85 4.95 5.05 5.15 Supply Voltage
5.25
Figure
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
SIGNAL-TO-NOISE RATIO REFERENCE VOLTAGE
TOTAL HARMONIC DISTORTION REFERENCE VOLTAGE
SFDR Spurious Free Dynamic Range
SPURIOUS FREE DYNAMIC RANGE REFERENCE VOLTAGE
118.5 117.5 116.5 115.5 VREF Reference Voltage Channel kHz, Throughput MSPS
-110
Total Harmonic Distortion
Signal Noise Ratio
97.5 96.5 95.5 94.5
Channel kHz, Throughput MSPS
-111 -112 -113 -114 -115 -116 -117
Channel kHz, Throughput MSPS
VREF Reference Voltage
VREF Reference Voltage
Figure EFFECTIVE NUMBER BITS REFERENCE VOLTAGE
15.95
97.5
Figure SIGNAL-TO-NOISE RATIO SUPPLY VOLTAGE (VCC)
Total Harmonic Distortion
Signal Noise Ratio
97.4 97.3 97.2 97.1 96.9 96.8 96.7 96.6 Channel 25°C, Vref 4.096, kHz, -VEE Throughput MSPS Supply Voltage
Figure TOTAL HARMONIC DISTORTION SUPPLY VOLTAGE (VCC)
-110 -111 -112 -113 -114 -115 -116 -117 Channel 25°C, Vref 4.096, kHz, -VEE Throughput MSPS
ENOB Effective Number Bits bits
Channel 15.9 15.85 15.8 kHz, 15.75 Throughput MSPS 15.7 15.65 15.6 15.55 15.5 15.45 15.4 VREF Reference Voltage
96.5
Supply Voltage
Figure SPURIOUS FREE DYNAMIC RANGE SUPPLY VOLTAGE (VCC)
SFDR Spurious Free Dynamic Range
Figure EFFECTIVE NUMBER BITS SUPPLY VOLTAGE (VCC)
Figure SIGNAL-TO-NOISE RATIO SOURCE RESISTANCE (RIN)
97.5
ENOB Effective Number Bits bits
15.9 15.85 15.8 15.75 15.7 15.65 15.6 15.55 15.5 Channel 25°C, Vref 4.096, kHz, -VEE Throughput MSPS Supply Voltage
Signal Noise Ratio
Channel 25°C, Vref 4.096, kHz, -VEE Throughput MSPS Supply Voltage
15.95
97.4 97.3 97.2 97.1 96.9 96.8 96.7 96.6 96.5
Channel 25°C, Vref 4.096, kHz, Throughput MSPS
Source Resistance
1000
Figure
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
TOTAL HARMONIC DISTORTION SOURCE RESISTANCE (RIN)
Total Harmonic Distortion
-108 -109 -110 -111 -112 -113 -114 Channel 25°C, Vref 4.096, kHz, Throughput MSPS
SPURIOUS FREE DYNAMIC RANGE SOURCE RESISTANCE (RIN)
SFDR Spurious Free Dynamic Range
Channel 25°C, Vref 4.096, kHz, Throughput MSPS Source Resistance 1000
ENOB Effective Number Bits bits
15.8 15.78 15.76 15.74 15.72 15.7 15.68
EFFECTIVE NUMBER BITS SOURCE RESISTANCE (RIN)
-107
Channel 25°C, Vref 4.096, kHz, Throughput MSPS Source Resistance 1000
Source Resistance
1000
Figure SIGNAL-TO-NOISE RATIO MULTIPLEXER CHANNELS
97.5 97.4 97.3 97.2 97.1 96.9 96.8 96.7 96.6 96.5 Multiplexer Channels 25°C, Vref 4.096, kHz, -VEE, Throughput MSPS
Figure TOTAL HARMONIC DISTORTION MULTIPLEXER CHANNEL
SFDR Spurious Free Dynamic Range
-110
Figure SPURIOUS FREE DYNAMIC RANGE MULTIPLEXER CHANNEL
Multiplexer Channels 25°C, Vref 4.096, kHz, -VEE, Throughput MSPS
Total Harmonic Distortion
Signal Noise Ratio
-111 -112 -113 -114 -115 -116 -117
25°C, Vref 4.096, kHz, -VEE, Throughput MSPS
Multiplexer Channels
Figure EFFECTIVE NUMBER BITS MULTIPLEXER CHANNELS
Figure VCM_O VOLTAGE SUPPLY VOLTAGE (VCC)
2.04145 2.0414 2.04135 25°C, Vref 4.096
Figure BUF_REF OUTPUT VOLTAGE SUPPLY VOLTAGE (VCC)
4.0871 4.087
25°C, Vref 4.096
ENOB Effective Number Bits bits
15.95 15.9
BUF_REF Output
VCM_O Voltage
15.85 15.8 15.75 15.7 15.65 15.6 15.55 15.5 Multiplexer Channels 25°C, Vref 4.096, kHz, -VEE, Throughput MSPS
2.0413 2.04125 2.0412 2.04115 2.0411 2.04105
4.0869 4.0868 4.0867 4.0866 4.0865
2.041 2.04095 Supply Voltage
4.0864
Supply Voltage
Figure
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
TYPICAL
-0.2 -0.4 -0.6 -0.8 50000 100000 150000 Codes 200000 250000
Test conditions: +VBD =25°C, MSPS, Vref 4.096 Figure TYPICAL
-0.5 -1.5 -2.5 50000 100000 150000 codes 200000 250000
Test conditions: +VBD =25°C, MSPS, Vref 4.096 Figure TYPICAL
-100 -120 -140 -160 -180 -200
Power
50000
100000
150000 200000 250000 300000 350000 400000 450000 500000 Frequency
Test conditions: kHz, MSPS, Vref 4.096V, 97.8 SFDR Figure
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APPLICATION INFORMATION
discussed before, ADS8285 18-bit analog that includes various blocks like multiplexer, driver, internal reference, internal reference buffer, buffered reference output, Ref/2 output on-board. following diagram shows recommended analog digital interfacing ADS8285.
APPLICATION DIAGRAM
AUTO, MXCLK From Host
Signals Source
VOLTAGE CLAMP BUSY
OPA-
MSPS LOGIC BUFFER
VCM-I: OPA-2
18/16 BYTE CONVST
Host
VREF/2 VCM-O: REFIN
BUF-REF: application board
REFOUT PD-RBUF Connect this power down `Ref-Buffer' REFM
INTERNAL
Figure Analog Digital Interface Diagram shown Figure ADS8285 accepts unipolar single ended analog input range Vref. application require interfacing true bipolar input signals. Figure shows conversion bipolar input signals unipolar differential signals.
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From BUF-REF (Note current o/p)
True Bipolar, Signals Note: Value depends signal kHz. Choose sourcel RC/2
Figure Conversion Bipolar Input Signals Unipolar Differential Signals
MICROCONTROLLER INTERFACING
ADS8285 8-Bit Microcontroller Interface Figure shows parallel interface between ADS8285 typical microcontroller using 8-bit data bus. BUSY signal used falling edge interrupt microcontroller.
Analog
AGND Input Analog Input
REFIN REFM AGND
Micro Controller GPIO GPIO GPIO GPIO AD[7:0]
Digital ADS8285 BYTE BDGND BUS18/16 CONVST +VBD DB[17:10]
BDGND
Data D[17:0]
Figure ADS8285 Application Circuitry
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Analog
AGND
AGND
REFOUT
REFIN
REFM
ADS8285
Figure ADS8285 Using Internal Reference
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AGND
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PRINCIPLES OPERATION
ADS8285 features high-speed successive approximation register (SAR) analog-to-digital converter (ADC). architecture based charge redistribution which inherently includes sample/hold function. Figure application circuit ADS8285. conversion clock generated internally. conversion time capable sustaining throughput. analog input voltage provided input pins AINP AINM. When conversion initiated, differential input these pins sampled internal capacitor array. While conversion progress, both inputs disconnected from internal function.
REFERENCE
ADS8285 operate with external reference with range from reference voltage input (REFIN) converter internally buffered. clean, noise, well-decoupled reference voltage this required ensure good performance converter. noise band-gap reference like REF5040 used drive this pin. 0.1-µF decoupling capacitor required between REFIN REFM pins (pin converter. This capacitor should placed close possible pins device. Designers should strive minimize routing length traces that connect terminals capacitor pins converter. network also used filter reference voltage. 100- series resistor 0.1-µF capacitor, which also serve decoupling capacitor used filter reference voltage.
REFM
REF5040 REFIN
ADS8285
Figure ADS8285 Using External Reference ADS8285 also limited pass filtering capability built into converter. equivalent circuitry REFIN input shown Figure
REFIN REFM CDAC
CDAC
Figure Simplified Reference Input Circuit REFM input ADS8285 should always shorted AGND. 4.096-V internal reference included. When internal reference used, (REFOUT) connected (REFIN) with 0.1-µF decoupling capacitor 1-µF storage capacitor between (REFOUT) REFM) (see Figure 72). internal reference converter double buffered. external reference used, second buffer provides isolation between external reference CDAC. This buffer also used recharge capacitors CDAC during conversion (see Figure 74). (REFOUT) left unconnected (floating) external reference used.
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ANALOG INPUT
device features analog multiplexer, high input impedance single ended into differential driver, high performance ADC. Typically care required driving circuit component selection board layout high resolution driving. However on-board driver simplifies user. that required decouple AINP AINM with 1-nF decoupling capacitor across these terminals close device possible. multiplexer inputs tolerate source impedance specified device performance operating speed 1-MSPS. This relaxes constraints signal conditioning circuit. case true bipolar input signals, possible condition them with resister divider shown Figure device permits 1.2-k resistors divider with effective source impedance signal bandwidth less than kHz. suitable capacitor value used limit signal bandwidth limits noise coming from resistor divider network. Care must taken concerning absolute analog voltage multiplexer input terminals. This voltage should exceed VEE. clamp driver limits voltage applied input.
Reading Data
ADS8285 outputs full parallel data straight binary format shown Table parallel output active when both low. There minimal quiet zone requirement around falling edge CONVST. This prior falling edge CONVST after falling edge. data read should attempted within this zone. other combination sets parallel output 3-state. BYTE BUS18/16 used multiword read operations. BYTE used whenever lower bits output higher byte bus. BUS18/16 used whenever last bits 18-bit output either bytes higher 16-bit bus. Refer Table ideal output codes. Table Ideal Input Voltages Output Codes
DESCRIPTION Full scale range Least significant (LSB) +Full scale Midscale Midscale Zero ANALOG VALUE +Vref +Vref/262144 (+Vref) +Vref/2 +Vref/2-1LSB DIGITAL OUTPUT STRAIGHT BINARY BINARY CODE 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 CODE 1FFFF 00000 3FFFF 20000
output data full 18-bit word (D17-D0) DB17-DB0 pins (MSB-LSB) both BUS18/16 BYTE low. result also read 16-bit using only pins DB17-DB2. this case reads necessary: first before, leaving both BUS18/16 BYTE reading most significant bits (D17-D2) pins DB17-DB2, then bringing BUS18/16 high while holding BYTE low. When BUS18/16 high, lower bits (D1-D0) appear pins DB3-DB2. result also read 8-bit convenience. This done using only pins DB17-DB10. this case three reads necessary: first before, leaving both BUS18/16 BYTE reading most significant bits pins DB17-DB10, then bringing BYTE high while holding BUS18/16 low. When BYTE high, medium bits (D9-D2) appear pins DB17-DB10. last read done bringing BUS18/16 high while holding BYTE high. When BUS18/16 high, lower bits (D1-D0) appear pins DB11-DB10. last read cycle necessary only first most significant bits interest. these multiword read operations performed with multiple active (toggling) with held simplicity. This referred AUTO READ operation. Table Conversion Data Read
DATA READ BYTE High BUS18/16 High High PINS DB17-DB12 One's One's PINS DB11-DB10 D1-D0 One's PINS DB9-DB4 One's One's PINS DB3-DB2 One's D1-D0 PINS DB1-DB0 One's One's
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Table Conversion Data Read (continued)
DATA READ BYTE High BUS18/16 PINS DB17-DB12 D9-D4 D17-D12 PINS DB11-DB10 D3-D2 D11-D10 PINS DB9-DB4 One's D9-D4 PINS DB3-DB2 One's D3-D2 PINS DB1-DB0 One's D1-D0
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device ADS8285IBRGCR ADS8285IBRGCT ADS8285IRGCR ADS8285IRGCT
Status PREVIEW PREVIEW PREVIEW PREVIEW
Package Type VQFN VQFN VQFN VQFN
Package Drawing
Pins Package Plan 2000 2000
Lead/Ball Finish Call Call Call Call
Peak Temp Call Call Call Call
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
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