PIC24HJ12GP201/202 Rev. A2/A3/A4 Silicon Errata PIC24HJ12GP201/20

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PIC24HJ12GP201/202 Rev. A2/A3/A4 Silicon Errata PIC24HJ12GP201/20

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PIC24HJ12GP201/202
PIC24HJ12GP201/202 Rev. A2/A3/A4 Silicon Errata
PIC24HJ12GP201/202 (Rev. A2/A3/A4) devices received were found conform specifications functionality described following documents: "PIC24HJ12GP201/202 Data Sheet" (DS70282) "dsPIC30F/33F Programmer's Reference Manual" (DS70157) exceptions specifications documents listed above described this section. specific devices which these exceptions described listed below: PIC24HJ12GP201 PIC24HJ12GP202 PIC24HJ12GP201/202 Rev. A2/A3/A4 silicon identified performing "Reset Connect" operation device using MPLAB® MPLAB REAL ICEin-circuit emulator, with MPLAB v7.60 later. output window will show successful connection device specified Configure>Select Device. resulting DEVREV register values Rev. A2/A3/A4 silicon 0x3001, 0x3002, 0x3003, respectively. errata described this document will addressed future revisions silicon.
Silicon Errata Summary
following list summarizes errata described further detail remainder this document: JTAG Programming JTAG programming does work. UART UART receptions corrupted Baud Rate Generator (BRG) mode. UART auto-baud feature calculate correct baud rate when mode. UART With auto-baud feature selected, Sync Break character (0x55) loaded into FIFO data. UART auto-baud feature measures baud rate inaccurately certain baud rate clock speed combinations. Traps Idle Mode clock failure occurs when device Idle mode, oscillator failure trap does vector Trap Service Routine (TSR). UART When auto-baud detected, receive interrupt occur twice. UART When UART mode (BRGH using Stop bits (STSEL sample first Stop instead second one. UART Module baud clock signal BCLK present only when module transmitting. Module SPIxCON1 DISSCK does influence port functionality. I2CModule I2CSTAT only cleared with 16-bit operation, corrupted with 1-bit 8-bit operations I2CSTAT.
2008 Microchip Technology Inc.
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PIC24HJ12GP201/202
Module ACKSTAT cleared shortly after being following slave transmit. Module: 10-bit Addressing Mode When module configured 10-bit addressing using same address bits (A10 other devices, bits work expected. Product Identification Revision devices marked extended temperature range devices only support industrial temperature range (I). UART (UxE Interrupt) UART error interrupt occur, occur incorrect time, multiple errors occur during short period time. UART Module When UART module operating 8-bit mode (PDSEL using IrDA® encoder/ decoder (IREN module incorrectly transmits data payload 00h. Internal Voltage Regulator When VREGS (RCON<8>) logic `0', higher sleep current observed. Operations address error trap occurs certain addressing modes when accessing first four bytes page. Module: 10-bit Addressing Mode When module configured 10-bit slave with address 0x102, I2CxRCV register content lower address byte 0x01 rather than 0x02.
Module: JTAG Programming
JTAG programming does work. Work around None.
Module: UART
UART receptions corrupted Baud Rate Generator mode (BRGH Work around baud rate option (BRGH adjust baud rate accordingly.
Module: UART
auto-baud feature calculate correct baud rate when High Baud Rate Enable bit, BRGH, set. With BRGH set, baud rate calculation used same Work around auto-baud feature needed, Baud Rate mode clearing BRGH bit.
Module: UART
With auto-baud feature selected, Sync Break character (0x55) loaded into FIFO data. Work around prevent Sync Break character from being loaded into FIFO, load UxBRG register with either 0x0000 0xFFFF prior enabling auto-baud feature (ABAUD
Module: UART
auto-baud feature miscalculate certain baud rate clock speed combinations, resulting value that greater than less than expected value This result reception transmission failures. Work around Test auto-baud rate various clock speed baud rate combinations that would used application. inaccurate value generated, manually correct baud rate user software.
Module
With module enabled, port bits external interrupt input functions any) associated with pins reflect actual digital logic levels pins. Module: 10-bit Addressing Mode 10-bit slave does flag load I2CxRCV register address match Least Significant bits address same 7-bit reserved addresses. following sections describe errata work around these errata, where they apply.
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Module: Traps Idle Mode
clock failure occurs when device Idle mode, oscillator failure trap does vector Trap Service Routine. Instead, device will simply wake-up from Idle mode continue code execution Fail-Safe Clock Monitor (FSCM) enabled. Work around Whenever device wakes from Idle (assuming FSCM enabled) user software should check state OSCFAIL (INTCON1<1>) determine whether clock failure occurred, then perform appropriate clock switch operation. Regardless, Trap Service Routine must included user application.
Module:
Setting DISSCK SPIxCON1 register does allow user application general purpose pin. Work around None.
Module:
I2CSTAT cleared only with 16-bit operation, corrupted with 1-bit 8-bit operations I2CSTAT. Work around 16-bit operations clear BCL.
Module:
During communication, after device operating Slave mode transmits data master, ACKSTAT I2CxSTAT register cleared depending whether master sent NACK after byte data. ACKSTAT set, will cleared again after some delay. Work around Store value ACKSTAT immediately after interrupt occurs.
Module: UART
When auto-baud detected, receive interrupt occur twice. first interrupt occurs beginning Start second after reception Sync field character. Work around extra interrupt detected, ignore additional interrupt.
Module: UART
When UART mode (BRGH using Stop bits (STSEL sample first Stop instead second one. This issue does affect other UART configurations. Work around baud rate option (BRGH adjust baud rate accordingly.
Module:
there devices bus, them acting Master receiver other Slave transmitter. both devices configured 10-bit addressing mode, have same value bits their addresses, then when Slave select address sent from Master, both Master Slave acknowledge When Master sends read operation, both Master Slave enter into Read mode both them transmit data. resultant data will ANDing transmissions. Work around devices, addresses well bits should different.
Module: UART
When UART configured interface operations (UxMODE<9:8> 11), baud clock signal BCLK present only when module transmitting. idle other times. Work around Configure output compare modules generate required baud clock signal when UART receiving data Idle state.
Module: Product Identification
Revision devices marked extended temperature range devices only support industrial temperature range (I). Work around Revision newer devices marked extended temperature range devices.
2008 Microchip Technology Inc.
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PIC24HJ12GP201/202
Module: UART (UxE Interrupt)
UART error interrupt occur, occur incorrect time, multiple errors occur during short period time. Work around Read error flags UxSTA register whenever byte received verify error status. most cases, these bits will correct, even UART error interrupt fails occur.
Module:
When module configured 10-bit slave with address 0x102, I2CxRCV register content lower address byte 0x01 rather than 0x02; however, module acknowledges both address bytes. Work around None.
Module:
With module enabled, port bits external interrupt input functions any) associated with pins reflect actual digital logic levels pins. Work around and/or pins need polled, these pins should connected other port pins order read correctly. This issue does affect operation module.
Module: UART (IrDA
When UART operating 8-bit mode (PDSEL using IrDA encoder/decoder (IREN module incorrectly transmits data payload 00h. Work around None.
Module: Internal Voltage Regulator
When VREGS (RCON<8>) logic `0', higher sleep current observed. Work around Ensure VREGS (RCON<8>) logic device Sleep mode operation.
Module:
10-bit Addressing mode, some address matches don't flag load receive register, I2CxRCV, lower address byte matches reserved addresses. particular, these include addresses with form XX0000XXXX XX1111XXXX, with following exceptions: 001111000X 011111001X 101111010X 111111011X
Module: Operations
address error trap occurs certain addressing modes when accessing first four bytes page. This only occurs when using following addressing modes: MOV.D Register indirect addressing (word byte mode) with pre/post-decrement Work around perform accesses first four bytes using above addressing modes. applications using language, MPLAB version 3.11 higher, provides following command-line switch that implements work around erratum. -merrata=psv_trap Refer readme.txt file MPLAB v3.11 tool suite further details.
Work around Ensure that lower address byte 10-bit Addressing mode does match 7-bit reserved addresses.
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2008 Microchip Technology Inc.
PIC24HJ12GP201/202
APPENDIX
Revision (5/2007) Initial release this document, which includes silicon issues (JTAG Programming), (UART) through (UART) (Traps Idle Mode). Revision (11/2007) Added silicon issues (UART) (UART). Revision (4/2008) Added silicon issues (UART), (SPI), 11-13 (I2C) (Product Identification). Revision (9/2008) Added reference silicon revision Updated silicon issue (Product Identification). Added silicon issues (UART (UxE Interrupt)), (UART (IrDA®)), (Internal Voltage Regulator), (PSV Operations), 19-21 (I2C).
REVISION HISTORY
2008 Microchip Technology Inc.
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NOTES:
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2008 Microchip Technology Inc.
Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
Code protection constantly evolving. Microchip committed continuously improving code protection features products. Attempts break Microchip's code protection feature violation Digital Millennium Copyright Act. such acts allow unauthorized access your software other copyrighted work, have right relief under that Act.
Information contained this publication regarding device applications like provided only your convenience superseded updates. your responsibility ensure that your application meets with your specifications. MICROCHIP MAKES REPRESENTATIONS WARRANTIES KIND WHETHER EXPRESS IMPLIED, WRITTEN ORAL, STATUTORY OTHERWISE, RELATED INFORMATION, INCLUDING LIMITED CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY FITNESS PURPOSE. Microchip disclaims liability arising from this information use. Microchip devices life support and/or safety applications entirely buyer's risk, buyer agrees defend, indemnify hold harmless Microchip from damages, claims, suits, expenses resulting from such use. licenses conveyed, implicitly otherwise, under Microchip intellectual property rights.
Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt UNI/O registered trademarks Microchip Technology Incorporated U.S.A. other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2008, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
2008 Microchip Technology Inc.
DS80326D-page
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01/02/08
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2008 Microchip Technology Inc.

PIC24HJ12GP201/202 Rev. A2/A3/A4 Silicon Errata PIC24HJ12GP201/20

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