PIC24FJ64GA004 Family Rev. Silicon Errata PIC24FJ64GA004 Family p
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PIC24FJ64GA004 FAMILY
PIC24FJ64GA004 Family Rev. Silicon Errata
PIC24FJ64GA004 Family parts have received conform functionally Device Data Sheet (DS39881C), except anomalies described below. Data Sheet Clarification issues related PIC24FJ64GA004 Family will reported separate. Data Sheet errata. Please check Microchip site existing issues. following silicon errata apply only PIC24FJ64GA family devices with these Device/ Revision IDs: Part Number PIC24FJ16GA002 PIC24FJ32GA002 PIC24FJ48GA002 PIC24FJ64GA002 PIC24FJ16GA004 PIC24FJ32GA004 PIC24FJ48GA004 PIC24FJ64GA004 Device 00444h 00445h 00446h 00447h 0044Ch 0044Dh 0044Eh 0044Fh Revision 3003h 3003h 3003h 3003h 3003h 3003h 3003h 3003h
Module: Low-Voltage Detect
Low-Voltage Detect interrupt will occur device comes Reset low-voltage state. trigger interrupt, voltage must decrease low-voltage range while device running. Work around None. Date Codes that pertain this issue: engineering production devices.
Module: Core
clock failure occurs when device Idle mode, oscillator failure trap does vector Trap Service Routine. Instead, device will simply wake-up from Idle mode continue code execution Fail-Safe Clock Monitor (FSCM) enabled. Work around Whenever device wakes from Idle (assuming FSCM enabled), user software should check status OSCFAIL (INTCON1<1>) determine whether clock failure occurred, then perform appropriate clock switch operation. Date Codes that pertain this issue: engineering production devices.
Module: JTAG
When JTAG disabled, pull-up resistor (pin 35/RA9) will stay enabled 44-pin variants device. This cause device draw extra current when asleep used input held low. Work around: will draw extra current following work around techniques used: used output. driven high input. JTAG enabled. Date Codes that pertain this issue: PIC24FJ16GA004, PIC24FJ32GA004, PIC24FJ48GA004 PIC24FJ64GA004 engineering production devices.
2008 Microchip Technology Inc.
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Module: Core
read performed instruction immediately prior enabling Doze mode, then extra read event will occur when Doze mode enabled. most SFRs user space, this will have visible effect. However, this cause registers which perform actions reads, such auto-incrementing decrementing pointer removing data from FIFO buffer, repeat that action, possibly resulting lost data. Work around instruction prior entering Doze mode, sure read register which performs secondary action. Examples this would UART FIFO buffers, RTCVAL registers. easiest ensure this does occur execute instruction before entering Doze mode. Date Codes that pertain this issue: engineering production devices.
Module:
AD1PCFG AD1CHS registers allow unimplemented channels selected. these channels selected, they will read tied VSS. These channels should disabled. Work around Disable channels AN13 AN14 AD1PCFG register ensuring that bits cleared. Ensure that bits AD1CHS maintained cleared. these bits set, will cause reference channels AN16-31. Date Codes that pertain this issue: engineering production devices.
Module:
module will generate code 511. conversion which should result normally, will instead generate 512. Work around None. Date Codes that pertain this issue: engineering production devices.
Module: Core
Brown-out Reset, both bits set. This cause Brown-out Reset condition indistinguishable from Power-on Reset. Work around None. Date Codes that pertain this issue: engineering production devices.
Module:
With External Interrupt (INT0) selected start conversion (SSRC<2:0> 001), device wake-up from Sleep Idle mode more than conversion selected interrupt (SMPI<3:0> 0000). Interrupts generated correctly device Sleep Idle mode. Work around Configure generate interrupt after every conversion (SMPI<3:0> 0000). another wake-up source, such another interrupt source, exit Sleep Idle mode. Alternatively, perform conversions mode. Date Codes that pertain this issue: engineering production devices.
Module: Core
PIC24FJ16GA002 PIC24FJ16GA004 devices have data implemented instead This will cause address error trap function addresses between 2000h 27FFh. Work around access beyond address 17FFh maintain software compatibility with future device revisions. Date Codes that pertain this issue: PIC24FJ16GA002 PIC24FJ16GA004 engineering production devices.
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2008 Microchip Technology Inc.
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Module: I2C(I2C1, Line State)
When using I2C1, SDA1 line state detected properly unless first held after enabling module. Master mode, this error cause collision occur instead Start transmission. Transmissions after SDA1 been held will occur correctly. Slave mode, device Acknowledge first packet sent after enabling module. this case, will return NACK instead ACK. device will correctly respond packets after detecting level line I2C2 module operates expected does exhibit this issue. Work around Using external device another from microcontroller, drive SDA1 low. external devices additional pins available, sometimes possible perform work around internally, using following steps: With module Master mode, configure output; Clear LATB9 (for default I2C1 assignment) LATB5 (for alternate I2C1 assignment) drive low; Enable I2C1 setting I2CEN (I2C1CON<15>). Note that this action could appear Start slave device RB8/SCL1 driven prior driving RB9/SDA1 low. necessary additional capacitance SDA1 order maintain logic level long enough module detect logic level. Make sure that when adding capacitance, that application does violate timing specifications. Slave mode, master device either must pull SDAx line low, then high again, prior sending first packet device, must resend first packet. Note that absolute maximum time required avoid issue. possible work around issue using shorter delay some devices. Date Codes that pertain this issue: engineering production devices.
Module: UART
When UART High-Speed mode, BRGH (UxMODE<3>) set, some optimal UxBRG values cause reception fail. Work around Test UxBRG values application find UxBRG value that works consistently more high-speed applications. user should verify that UxBRG baud rate error does exceed application limits. possible, recommended comparable baud rate Low-Speed mode. Date Codes that pertain this issue: engineering production devices.
Module: UART
When UART High-Speed mode (BRGH auto-baud sequence calculate baud rate were Low-Speed mode. Work around calculated baud rate modified following equation: Value (Auto-Baud user should verify that baud rate error does exceed application limits. Date Codes that pertain this issue: engineering production devices.
Module: UART
When auto-baud detected, receive interrupt occur twice. first interrupt occurs beginning Start second after reception Sync field character. Work around receive interrupt occurs, check URXDA (UxSTA<0>) ensure that valid data available. first interrupt, data will present. second interrupt will have Sync field character (55h) receive FIFO. Date Codes that pertain this issue: engineering production devices.
2008 Microchip Technology Inc.
DS80316G-page
PIC24FJ64GA004 FAMILY
Module: UART
With auto-baud feature selected, Sync field character (0x55) loaded into FIFO data. Work around prevent Sync field character from being loaded into FIFO, load UxBRG register with either 0x0000 0xFFFF prior enabling auto-baud feature (ABAUD Date Codes that pertain this issue: engineering production devices.
Module:
When using Enhanced Buffer mode, some indicator bits incorrect times: slave transfers, SRMPT (SPIxSTAT<7>) early, after only periods Slave Interrupt modes, SISELx there period delay between interrupt event SPIxIF being There several instruction cycle delay between FIFO full FIFO empty events interrupt flags indicator bits being Work around None this time. Date Codes that pertain this issue: engineering production devices.
Module: UART
auto-baud miscalculate certain baud rates clock speed combinations, resulting value that greater less than expected value. When UxBRG less than this result transmission reception failures introducing error greater than Work around Test auto-baud calculations various clock speed baud rate combinations that would used applications. inaccurate UxBRG value generated, manually correct baud rate user code. Date Codes that pertain this issue: engineering production devices.
Module:
Slave mode (MSTEN with slave select option enabled (SSEN peripheral accept transfers regardless state. received data SPIxBUF will accurate intended device. Work around There work around using peripheral select feature. external interrupts (INT1 INT2) mapped same signal signal mapped with interrupt-on-change (CNx) functionality. signal changes (active), interrupt flag will set. When data received interrupt occurs, interrupt flag tested. interrupt mapped occur, discard data. Date Codes that pertain this issue: engineering production devices.
Module: Output Compare
mode, output compare module miss compare event when current duty cycle register (OCxRS) value 0x0000 duty cycle) OCxRS register updated with value 0x0001. compare event only missed first time value 0x0001 written OCxRS, output remains period. Subsequent high times occur expected. Work around current OCxRS register value 0x0000, avoid writing value 0x0001 OCxRS. Instead, write value 0x0002. this case, however, duty cycle will slightly different from desired value. Date Codes that pertain this issue: engineering production devices.
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2008 Microchip Technology Inc.
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Module:
When using Enhanced Buffer mode, interrupt will occur following conditions exist: Buffer Interrupt mode, SISEL<2:0> (SPIxSTAT<4:2>), interrupt when Shift register empty (SISEL<2:0> 101) Slave Select mode enabled (SSEN This only occurs when Enhanced mode, Slave Select mode interrupt Shift register empty enabled. other modes, interrupt will work correctly. Work around When Slave Select mode enabled, interrupting SPIxSR empty empty will occur same time. Therefore, interrupting FIFO empty (SISEL<2:0> 110) used alternative interrupting when Shift register empty (SISEL<2:0> 101). Date Codes that pertain this issue: engineering production devices.
Module: Ports
outputs, VOH, meet specifications Table below. Work around None. Date Codes that pertain this issue: engineering production devices.
TABLE
CHARACTERISTICS: OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2.0V 3.6V (unless otherwise stated) Operating temperature -40°C +85°C Industrial Typ(1) Units Conditions
CHARACTERISTICS Param DO10 Characteristic Output Voltage Pins
3.6V 3.6V 2.0V 2.0V -3.0 3.6V -6.0 3.6V -1.0 2.0V -3.0 2.0V
DO20
Output High Voltage Pins 1.65
Note
Data "Typ" column 3.3V, 25°C unless otherwise stated. Parameters design guidance only tested.
2008 Microchip Technology Inc.
DS80316G-page
PIC24FJ64GA004 FAMILY
Module: Ports
During Power-on Reset (POR), device drive OSCO/RA3 clock output approximately During this time, will driven high rather than being high-impedance. This cause issues designs that general purpose I/O. Designs should reviewed ensure that their intended operation will disrupted driven during POR. Work around None. Date Codes that pertain this issue: engineering production devices.
Module:
When module operating Slave mode, after ACKSTAT when receiving NACK from master, cleared reception Start Stop bit. Work around Store value ACKSTAT immediately after receiving NACK from master. Date Codes that pertain this issue: engineering production devices.
Module:
byte-based operations have intended affect I2CxSTAT register. possible byte operations performed lower byte I2CxSTAT clear (I2CxSTAT<10>). byte operation performed upper byte I2CxSTAT, directly, able clear bit. Work around Modifications I2CxSTAT register should done using word writes only. This done always writing register itself individual bits. example, code, I2C1STAT 0xFBFF, will force compiler word-based operation clear bit. assembly, done using BSET BCLR instructions instructions with modifier. Date Codes that pertain this issue: engineering production devices.
Module: JTAG
When entering SHIFT_DR state while ICSPCommunications mode, extra clock edge generated, causing JTAG ICSP communications lose synchronization. This prevents device programming using ICSP over JTAG. JTAG boundary scan affected operates expected. Work around None. Date Codes that pertain this issue: engineering production devices.
Module: RTCC
When performing writes ALCFGRPT register, some bits become corrupted. error occurs because desynchronization between clock domain RTCC clock domain. error causes data, from instruction following ALCFGRPT instruction, overwrite data ALCFGRPT. Work around Always follow writes ALCFGRPT register with additional write same data dummy location. These writes performed locations, registers unimplemented space. optimal perform work around: Read ALCFGRPT into location. Modify ALCFGRPT data, required, RAM. Move value into ALCFGRPT, dummy location, back-to-back instructions. Date Codes that pertain this issue: engineering production devices.
Module: UART
When UART configured interface operations (UxMODE<9:8> 11), baud clock signal BCLK will only present when module transmitting. will Idle other times. Work around Configure output compare modules generate required baud clock signal when UART receiving data Idle state. Date Codes that pertain this issue: engineering production devices.
DS80316G-page
2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
Module: (Peripheral Select)
remappable functions multiplexed some pins have higher priority than fixed digital signals assigned those pins. design, remapped digital function should always have priority over other fixed digital function same pin. Using these remappable specific fixed digital functions same time cause conflicts unexpected results RP12 PMD0 RP18 PMA2 (40-pin 44-pin devices only) other fixed digital functions affected. Work around affected pins, enable either remappable peripherals, specific fixed digital peripherals, both same time. Date Codes that pertain this issue: engineering production devices.
Module: UART (FIFO Error Flags)
Under certain circumstances, PERR FERR error bits correct bytes receive FIFO. This only been observed when both following conditions met: UART receive interrupt occur when FIFO full full (UxSTA<7:6> 1x), more than bytes with error received. these cases, only first bytes, with parity framing error, will have corresponding bits indicate correctly. error bits will after this. Work around None. Date Codes that pertain this issue: engineering production devices.
Module: Core (BOR)
When on-chip regulator enabled (DISVREG tied VSS), event spontaneously occur under following circumstances: less than 2.5V, internal band reference being used reference with converter (AD1PCFG<15> Work around select internal band reference converter when on-chip regulator Tracking mode (LVDIF (IFS4<8>) Date Codes that pertain this issue: engineering production devices.
Module: UART (UERIF Interrupt)
UART error interrupt occur, occur incorrect time, multiple errors occur during short period time. Work around Read error flags UxSTA register whenever byte received verify error status. most cases, these bits will correct, even UART error interrupt fails occur. possible exceptions, refer Errata Date Codes that pertain this issue: engineering production devices.
2008 Microchip Technology Inc.
DS80316G-page
PIC24FJ64GA004 FAMILY
Module: Core (Instruction Set)
instruction producing read-after-write stall condition executed inside REPEAT loop, instruction will executed fewer times than intended. example, this loop: repeat #0xf [w1],[++w1] will execute less than times. Work around Avoid using REPEAT repetitively execute instructions that create stall condition. Instead, software loop using conditional branches. MPLAB® Compiler will generate REPEAT loops that cause this erratum. Date Codes that pertain this issue: engineering production devices.
Module: RTCC
Under certain circumstances, value Alarm Repeat Counter (ALCFGRPT<7:0>) unexpectedly decremented. This happens only when byte write upper byte ALCFGRPT performed interval between device POR/ first edge from RTCC clock source. Work around perform byte writes ALCFGRPT, particularly upper byte. Alternatively, wait until period SOSC completed before performing byte writes ALCFGRPT. Date Codes that pertain this issue: engineering production devices.
Module: (Master Mode) Module: Memory (Program Space Visibility)
When accessing data area data RAM, possible generate false address error trap condition reading data located precisely lower address boundary (8000h). data read using instruction with autodecrement, resulting address will below boundary (i.e., 7FFEh); this will result address error trap. This false address error also occur 32-bit instruction used read data location 8000h. Work around first location page (address 8000h). MPLAB Compiler (v3.11 later) supports option, -merrata=psv_trap, prevent from generating code that would cause this erratum. Date Codes that pertain this issue: engineering production devices. Master mode, Interrupt Flag (SPIxIF) SPIRBF (SPIxSTAT<0>) both become one-half clock cycle early, instead clock edge. This occurs only under following circumstances: Enhanced Buffer mode disabled (SPIBEN module configured serial data output changes transition from clock active clock Idle state (CKE application using interrupt flag determine when data transmitted written transmit buffer, data currently buffer overwritten. Work around Before writing buffer, check determine last clock edge passed. Example (below) demonstrates method doing this. this example, functions clock SCK, which configured Idle low. Date Codes that pertain this issue: engineering production devices.
EXAMPLE
CHECKING STATE SPIxIF AGAINST CLOCK
//wait transmission complete //wait last clock finish //write data buffer
while(IFS0bits.SPI1IF 0){} while(PORTDbits.RD1 1){} SPI1BUF 0xFF;
DS80316G-page
2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
Module: (Master Mode)
Under certain circumstances, module operating Master mode Acknowledge command addressed slave device. This happens when following occurs: 10-Bit Addressing mode used (A10M master same upper address bits (I2CADD<9:8>) addressed slave module. these cases, master also Acknowledges address command generates erroneous slave interrupt, well master interrupt. Work around Several options available: When using 10-Bit Addressing mode, make certain that master slave devices share same MSbs their addresses. this cannot avoided: Clear A10M (I2CxCON<10> prior performing Master mode transmit. Read ADD10 (I2CxSTAT<8>) check full 10-bit match whenever slave interrupt occurs master module. Date Codes that pertain this issue: engineering production devices.
Module:
Transmit Buffer Full flag, (I2CxSTAT<0>), cleared hardware collision occurs before first falling clock edge during transmission. Work around None. Date Codes that pertain this issue: engineering production devices.
Module: UART
When UART operating using Stop bits (STSEL sample first Stop instead second one. device being communicated with using Stop communications, this lead framing errors. Work around None. Date Codes that pertain this issue: engineering production devices.
Module: Oscillator (SOSC)
low-power secondary oscillator option, selected SOSCSEL Configuration bits (CW2<12:11>), available this silicon revision. oscillator devices functions Default (high-gain) mode only. Work around None. Date Codes that pertain this issue: engineering production devices.
Module: (Slave Mode)
Under certain circumstances, module operating Slave mode respond correctly some special addresses reserved protocol. This happens when following occurs: 10-Bit Addressing mode used (A10M bits, A7:A1, slave address (I2CADD<7:1>) fall into range reserved 7-bit address ranges `1111xxx' `0000xxx'. these cases, Slave module Acknowledges command triggers slave interrupt; does copy data into I2CxRCV register bit. Work around bits, A7:A1, module's slave address equal `1111xxx' `0000xxx'. Date Codes that pertain this issue: engineering production devices.
Module: Voltage Regulator
Standby mode wake-up option, selected WUTSEL Configuration bits (CW2<14:13>), available this silicon revision. devices default regulator wake-up time Work around None. Date Codes that pertain this issue: engineering production devices.
2008 Microchip Technology Inc.
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REVISION HISTORY
Document (3/2007) First version this document. Silicon issues (Core), (Core Interrupt), (Core), (A/D), (PMP), (I2C), 12-16 (UART), (Output Compare), 18-20 (SPI), (RTCC), (CRC) (I/O Pins). Document (7/2007) Removed silicon issue (Core) (RTCC). Reworded silicon issue (12C). Added silicon issues (Core), (Core), (JTAG) (RTCC). Document (9/2007) Modified silicon issues (A/D), (I2C) (I/O Ports), added silicon issues 25-26 (I2C), removed silicon issue (CRC) corrected revision history Revision Document (9/2007) Modified silicon issue (I2C). Document (10/2007) Modified silicon issues (JTAG) (Low-Voltage Detect). Removed silicon issue (PMP), renumbering subsequent silicon issues through Added silicon issue (UART). Document (3/2008) Modified silicon issues (I2C I2C1, Line State) reflect more specific information since previous update Revision Added silicon issues (I/O Peripheral Select), (Oscillator OSCO SOSC), (UART UERIF Interrupt), (UART FIFO Error Flags) (Core BOR). Corrected revision history reflect renumbering that occurred with Revision Document (7/2008) Removed silicon issue (Oscillator OSCO SOSC), renumbered subsequent issues through Added silicon issues (Core Instruction Set), (Memory Program Space Visibility), (RTCC), (SPI Master Mode), through (I2C), (UART), (Oscillator SOSC) (Voltage Regulator).
DS80316G-page
2008 Microchip Technology Inc.
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