CC430F613x CC430F612x CC430F513x www.ti.com SLAS554 2009 MSP
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ECCN 5E002 TSPA Technology Software Publicly Available.
CC430F613x CC430F612x CC430F513x
www.ti.com SLAS554 2009
MSP430 with Core
FEATURES
High-Performance Sub-1-GHz Transceiver Core Same Core CC1101 Wide Supply Voltage Range: Frequency Bands: MHz, MHz, Programmable Data Rate From kBaud kBaud High Sensitivity (-110 kBaud, MHz, Packet Error Rate) Excellent Receiver Selectivity Blocking Performance Programmable Output Power Supported Frequencies 2-FSK, GFSK, Supported well Flexible Shaping Flexible Support Packet-Oriented Systems: On-Chip Support Sync Word Detection, Address Check, Flexible Packet Length, Automatic Handling Support Automatic Clear Channel Assessment (CCA) Before Transmitting (for Listen-Before-Talk Systems) Digital RSSI Output Suited Systems Targeting Compliance With (Europe) Part (US) CC430F613x CC430F612x Devices Available 64-Pin RoHS-Compliant Package CC430F513x Devices Available 48-Pin RoHS-Compliant Package
True System-on-Chip (SoC) Low-Power Wireless Communication Applications Wide Supply Voltage Range: Ultralow Power Consumption: Active Mode (AM): µA/MHz Standby Mode (LPM3 Mode):1.7 Mode (LPM4 Retention): Radio kbps, MSP430 System Peripherals 16-Bit RISC Architecture, Extended Memory, 37-ns Instruction Cycle Time Wake-Up From Standby Mode Less Than Flexible Power Management System with Brownout Unified Clock System with 16-Bit Timer_A0 With Five Capture/Compare Registers 16-Bit Timer_A1 With Three Capture/Compare Registers Hardware Real-Time Clock Universal Serial Communication Interfaces With Independent Communication Channels Supporting UART, IrDA, SPI, 12-Bit Converter With Internal Reference, Sample-and-Hold, Autoscan Features (Only CC430F613x CC430F513x) On-Chip Comparator Integrated Driver With Contrast Control Segments (Only CC430F6xx1) 128-bit Security Encryption/Decryption Coprocessor 32-Bit Hardware Multiplier Three-Channel Internal Serial Onboard Programming, External Programming Voltage Needed Embedded Emulation Module (EEM)
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. trademark others.
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PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
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CC430F613x CC430F612x CC430F513x
ECCN 5E002 TSPA Technology Software Publicly Available.
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Family Members Include: CC430F6137 (LCD, ADC, Pin) 32KB+512B Flash Memory CC430F6135 (LCD, ADC, Pin) 16KB+512B Flash Memory CC430F6127 (LCD, Pin) 32KB+512B Flash Memory CC430F6126 (LCD, Pin) 32KB+512B Flash Memory CC430F6125 (LCD, Pin) 16KB+512B Flash Memory
CC430F5137 (ADC, Pin) 32KB+512B Flash Memory CC430F5135 (ADC, Pin) 16KB+512B Flash Memory CC430F5133 (ADC, Pin) 8KB+512B Flash Memory
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DESCRIPTION
Texas Instruments CC430 family ultralow-power microcontroller system-on-chip with integrated cores consists several devices featuring different sets peripherals targeted various applications. architecture, combined with five low-power modes optimized achieve extended battery life portable measurement applications. device features powerful 16-bit RISC CPU, 16-bit registers, constant generators that contribute maximum code efficiency. CC430 family provides tight integration between microcontroller core, peripherals, software, transceiver, making these true system-on-chip solutions easy well improving performance. CC430F61xx series microcontroller system-on-chip configurations combining excellent performance state-of-the-art CC1101 <1-GHz transceiver with MSP430 CPUXV2, in-system programmable flash memory, RAM, 16-bit timers, high-performance 12-bit converter with eight external inputs plus internal temperature battery sensors CC430F613x devices, comparator, universal serial communication interfaces (USCI), 128-bit security accelerator, hardware multiplier, DMA, real-time clock module with alarm capabilities, driver, pins. CC430F513x series microcontroller system-on-chip configurations combining excellent performance state-of-the-art CC1101 <1-GHz transceiver with MSP430 CPUXV2, in-system programmable flash memory, RAM, 16-bit timers, high performance 12-bit converter with eight external inputs plus internal temperature battery sensors, comparator, universal serial communication interfaces (USCI), 128-bit security accelerator, hardware multiplier, DMA, real-time clock module with alarm capabilities, pins. Typical applications these devices include wireless analog digital sensor systems, heat cost allocators, thermostats, etc. complete module descriptions, CC430 Family User's Guide, literature number SLAU259.
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CC430F613x CC430F612x CC430F513x
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AVAILABLE OPTIONS
PACKAGED DEVICES PLASTIC 64-PIN (RGC) CC430F6137IRGC CC430F6135IRGC -40°C 85°C CC430F6127IRGC CC430F6126IRGC CC430F6125IRGC most current package ordering information, Package Option Addendum this document, site www.ti.com. Package drawings, thermal data, symbolization available www.ti.com/packaging. PLASTIC 48-PIN (RGZ) CC430F5137IRGZ CC430F5135IRGZ CC430F5133IRGZ
CC430F613x Functional Block Diagram
XOUT (32kHz) P1.x/P2.x P3.x/P4.x P5.x RF_XIN RF_XOUT (26MHz)
MCLK
Unified Clock System
ACLK Comp_B SMCLK ADC12
Voltage Reference
Packet Handler Digital RSSI Carrier Sense
Controller Channel Cntrl Logic CPUXV2 incl. Registers Flash 32kB 16kB CRC16
1x16 I/Os
1x16 I/Os
Sub-1GHz Radio (CC1101)
Watchdog Port Mapping Controller
MODEM Interface
MPY32
3+1)
JTAG Interface
Spy-BiWire
Frequency Synthesizer Power Mgmt SVM/SVS Brownout USCI_A0 (UART, IrDA, SPI) USCI_B0 (SPI, I2C) LCD_B Segments 1,2,3,4 AES128 Security En-/Decryption RF/ANALOG
Timer0_A5 Registers
Timer1_A3 Registers RTC_A
RF_P
RF_N
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Ports P1/P2 I/Os
Ports P3/P4 I/Os
Ports I/Os
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PACKAGE (TOP VIEW)
P1.5/PM_UCA0RXD/PM_UCA0SOMI/R23 LCDCAP/R33 COM0 P5.7/COM1/S26 P5.6/COM2/S25 P5.5/COM3/S24 P5.4/S23 VCORE DVCC P1.4/PM_UCB0CLK/PM_UCA0STE/S22 P1.3/PM_UCB0SIMO/PM_UCB0SDA/S21 P1.2/PM_UCB0SOMI/PM_UCB0SCL/S20 P1.1/PM_RFGDO2/S19 P1.0/PM_RFGDO0/S18
CC430F613x
P2.0/PM_CBOUT1/PM_TA1CLK/CB0/A0 P2.1/PM_TA1CCR0A/CB1/A1 P2.2/PM_TA1CCR1A/CB2/A2 P2.3/PM_TA1CCR2A/CB3/A3 P2.6/PM_ACLK/CB6/A6 P2.7/PM_MODCLK/PM_DMAE0/CB7/A7 AVCC P5.0/XIN P5.1/XOUT AVSS DVCC RST/NMI/SBWTDIO TEST/SBWTCK PJ.3/TCK
PJ.2/TMS PJ.1/TDI/TCLK PJ.0/TDO GUARD R_BIAS AVCC_RF AVCC_RF RF_N RF_P AVCC_RF AVCC_RF RF_XOUT RF_XIN P5.2/S0 P5.3/S1 P4.0/S2/(RF_ATEST)
P3.7/PM_SMCLK/S17 P3.6/PM_RFGDO1/S16 P3.5/PM_TA0CCR4A/S15 P3.4/PM_TA0CCR3A/S14 P3.3/PM_TA0CCR2A/S13 P3.2/PM_TA0CCR1A/S12 P3.1/PM_TA0CCR0A/S11 P3.0/PM_CBOUT0/PM_TA0CLK/S10 DVCC P4.7/S9 P4.6/S8 P4.5/S7 P4.4/S6 P4.3/S5 P4.2/S4 P4.1/S3
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Exposed attached
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ECCN 5E002 TSPA Technology Software Publicly Available.
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CC430F612x Functional Block Diagram
XOUT (32kHz) P1.x/P2.x P3.x/P4.x P5.x RF_XIN RF_XOUT (26MHz)
MCLK
Unified Clock System
ACLK Comp_B SMCLK
Voltage Reference
Ports P1/P2 I/Os 1x16 I/Os
Ports P3/P4 I/Os 1x16 I/Os
Ports I/Os
Packet Handler Digital RSSI Carrier Sense
Controller Channel Cntrl Logic CPUXV2 incl. Registers Flash 32kB 32kB 16kB CRC16
Sub-1GHz Radio (CC1101)
Watchdog Port Mapping Controller
MODEM Interface
MPY32
3+1)
JTAG Interface
Spy-BiWire
Frequency Synthesizer Power Mgmt SVM/SVS Brownout USCI_A0 (UART, IrDA, SPI) USCI_B0 (SPI, I2C) LCD_B Segments 1,2,3,4 AES128 Security En-/Decryption RF/ANALOG
Timer0_A5 Registers
Timer1_A3 Registers RTC_A
RF_P
RF_N
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PACKAGE (TOP VIEW)
P1.5/PM_UCA0RXD/PM_UCA0SOMI/R23 LCDCAP/R33 COM0 P5.7/COM1/S26 P5.6/COM2/S25 P5.5/COM3/S24 P5.4/S23 VCORE DVCC P1.4/PM_UCB0CLK/PM_UCA0STE/S22 P1.3/PM_UCB0SIMO/PM_UCB0SDA/S21 P1.2/PM_UCB0SOMI/PM_UCB0SCL/S20 P1.1/PM_RFGDO2/S19 P1.0/PM_RFGDO0/S18
CC430F612x
P2.0/PM_CBOUT1/PM_TA1CLK/CB0 P2.1/PM_TA1CCR0A/CB1 P2.2/PM_TA1CCR1A/CB2 P2.3/PM_TA1CCR2A/CB3 P2.4/PM_RTCCLK/CB4 P2.5/PM_SVMOUT/CB5 P2.6/PM_ACLK/CB6 P2.7/PM_MODCLK/PM_DMAE0/CB AVCC P5.0/XIN P5.1/XOUT AVSS DVCC RST/NMI/SBWTDIO TEST/SBWTCK PJ.3/TCK
PJ.2/TMS PJ.1/TDI/TCLK PJ.0/TDO GUARD R_BIAS AVCC_RF AVCC_RF RF_N RF_P AVCC_RF AVCC_RF RF_XOUT RF_XIN P5.2/S0 P5.3/S1 P4.0/S2/(RF_ATEST)
P3.7/PM_SMCLK/S17 P3.6/PM_RFGDO1/S16 P3.5/PM_TA0CCR4A/S15 P3.4/PM_TA0CCR3A/S14 P3.3/PM_TA0CCR2A/S13 P3.2/PM_TA0CCR1A/S12 P3.1/PM_TA0CCR0A/S11 P3.0/PM_CBOUT0/PM_TA0CLK/S10 DVCC P4.7/S9 P4.6/S8 P4.5/S7 P4.4/S6 P4.3/S5 P4.2/S4 P4.1/S3
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Exposed attached
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CC430F613x CC430F612x CC430F513x
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CC430F513x Functional Block Diagram
XOUT (32kHz) P1.x/P2.x P3.x P5.x RF_XIN RF_XOUT (26MHz)
MCLK
Unified Clock System
ACLK Comp_B SMCLK ADC12
Voltage Reference
Ports P1/P2 I/Os 1x16 I/Os
Ports I/Os
Ports I/Os
Packet Handler Digital RSSI Carrier Sense
Controller Channel Cntrl Logic CPUXV2 incl. Registers Flash 32kB 16kB CRC16
Sub-1GHz Radio (CC1101)
Watchdog Port Mapping Controller
MODEM Interface
MPY32
3+1)
JTAG Interface
Spy-BiWire
Frequency Synthesizer Power Mgmt SVM/SVS Brownout USCI_A0 (UART, IrDA, SPI) USCI_B0 (SPI, I2C) AES128 Security En-/Decryption RF/ANALOG
Timer0_A5 Registers
Timer1_A3 Registers RTC_A
RF_P
RF_N
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P2.3/PM_TA1CCR2A/CB3/A3
PACKAGE (TOP VIEW)
RST/NMI/SBWTDIO
P5.1/XOUT
TEST/SBWTCK
P5.0/XIN
P2.2/PM_TA1CCR1A/CB2/A2 P2.1/PM_TA1CCR0A/CB1/A1
CC430F513x
DVCC
AVCC
AVSS
PJ.2/TMS
PJ.1/TDI/TCLK PJ.0/TDO GUARD R_BIAS AVCC_RF AVCC_RF RF_N
P2.0/PM_CBOUT1/PM_TA1CLK/CB0/A0 P1.6/PM_UCA0TXD/PM_UCA0SIMO P1.5/PM_UCA0RXD/PM_UCA0SOMI VCORE DVCC P1.4/PM_UCB0CLK/PM_UCA0STE P1.3/PM_UCB0SIMO/PM_UCB0SDA P1.2/PM_UCB0SOMI/PM_UCB0SCL P1.1/PM_RFGDO2
PJ.3/TCK
P3.4/PM_TA0CCR3A
P3.1/PM_TA0CCR0A
P1.0/PM_RFGDO0
P2.7/PM_MODCLK/PM_DMAE0
P3.2/PM_TA0CCR1A
P3.0/PM_CBOUT0/PM_TA0CLK
P2.6/PM_ACLK/(RF_ATEST)
P3.5/PM_TA0CCR4A
P3.7/PM_SMCLK
P3.3/PM_TA0CCR2A
P3.6/PM_RFGDO1
DVCC
PRODUCT PREVIEW
RF_P
AVCC_RF AVCC_RF RF_XOUT RF_XIN
Exposed attached
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CC430F613x CC430F612x Terminal Functions
TERMINAL NAME P1.7/ PM_UCA0CLK/ PM_UCB0STE/ P1.6/ PM_UCA0TXD/ PM_UCB0SIMO/ R13/ LCDREF P1.5/ PM_UCA0RXD/ PM_UCB0SOMI/ LCDCAP/ COM0 P5.7/ COM1/ DESCRIPTION General-purpose digital with port interrupt map-able secondary function Default mapping: USCI_A0 clock input/output USCI_B0 slave transmit enable Input/output port lowest analog voltage (V5) General-purpose digital with port interrupt map-able secondary function Default mapping: USCI_A0 UART transmit data; USCI_A0 slave master Input/output port third most positive analog voltage External reference voltage input regulated voltage General-purpose digital with port interrupt map-able secondary function Default mapping: USCI_A0 UART receive data; USCI_A0 slave master Input/output port second most positive analog voltage (V2) capacitor connection Input/output port most positive analog voltage (V1) common output COM0 backplane General-purpose digital common output COM1 backplane segment output General-purpose digital common output COM2 backplane segment output General-purpose digital common output COM3 backplane segment output General-purpose digital segment output Regulated core power supply Digital power supply General-purpose digital with port interrupt map-able secondary function Default mapping: USCI_B0 clock input/output USCI_A0 slave transmit enable segment output General-purpose digital with port interrupt map-able secondary function Default mapping: USCI_B0 slave master out/USCI_B0 data segment output General-purpose digital with port interrupt map-able secondary function Default mapping: USCI_B0 slave master in/UCSI_B0 clock segment output General-purpose digital with port interrupt map-able secondary function Default mapping: Radio GDO2 output segment output General-purpose digital with port interrupt map-able secondary function Default mapping: Radio GDO0 output segment output General-purpose digital with map-able secondary function Default mapping: SMCLK output segment output General-purpose digital with map-able secondary function Default mapping: Radio GDO1 output segment output General-purpose digital with map-able secondary function Default mapping: CCR4 compare output/capture input segment output General-purpose digital with map-able secondary function Default mapping: CCR3 compare output/capture input segment output General-purpose digital with map-able secondary function Default mapping: CCR2 compare output/capture input segment output
P5.6/ COM2/
P5.5/ COM3/ P5.4/ VCORE DVCC P1.4/ PM_UCB0CLK/ PM_UCA0STE/ P1.3/ PM_UCB0SIMO/ PM_UCB0SDA/ P1.2/ PM_UCB0SOMI/ PM_UCB0SCL/ P1.1/ PM_RFGDO2/
P1.0/ PM_RFGDO0/
P3.7/ PM_SMCLK/
P3.6/ PM_RFGDO1/
P3.5/ PM_TA0CCR4A/
P3.4/ PM_TA0CCR3A/
P3.3/ PM_TA0CCR2A/
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CC430F613x CC430F612x CC430F513x
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CC430F613x CC430F612x Terminal Functions (continued)
TERMINAL NAME P3.2/ PM_TA0CCR1A/ DESCRIPTION General-purpose digital with map-able secondary function Default mapping: CCR1 compare output/capture input segment output General-purpose digital with map-able secondary function Default mapping: CCR0 compare output/capture input segment output General-purpose digital with map-able secondary function Default mapping: Comparator_B output; Timer0_A5 clock input segment output Digital power supply General-purpose digital segment output General-purpose digital segment output General-purpose digital segment output General-purpose digital segment output General-purpose digital segment output General-purpose digital segment output General-purpose digital segment output General-purpose digital segment output General-purpose digital segment output General-purpose digital segment output Input terminal crystal oscillator, external clock input Output terminal crystal oscillator Radio analog power supply Radio analog power supply Positive input receive mode Positive output from transmit mode Negative input receive mode Negative output from transmit mode Radio analog power supply Radio analog power supply External bias resistor radio reference current Power supply connection digital noise isolation General-purpose digital Test data output port General-purpose digital Test data input test clock input General-purpose digital Test mode select General-purpose digital Test clock Test mode select digital JTAG pins Spy-bi-wire input clock
P3.1/ PM_TA0CCR0A/ P3.0/ PM_CBOUT0/ PM_TA0CLK/ DVCC P4.7/ P4.6/ P4.5/ P4.4/
PRODUCT PREVIEW
P4.3/ P4.2/ P4.1/ P4.0/ P5.3/ P5.2/ RF_XIN RF_XOUT AVCC_RF AVCC_RF RF_P RF_N AVCC_RF AVCC_RF RBIAS GUARD PJ.0/ PJ.1/ TDI/ TCLK PJ.2/ PJ.3/ TEST/ SBWTCK
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CC430F613x CC430F612x Terminal Functions (continued)
TERMINAL NAME RST/NMI/ SBWTDIO DVCC AVSS P5.1/ XOUT P5.0/ AVCC P2.7/ PM_ADC12CLK/ PM_DMAE0/ (/A7) Reset input active Non-maskable interrupt input Spy-bi-wire data input/output Digital power supply Analog ground supply ADC12 General-purpose digital Output terminal crystal oscillator General-purpose digital Input terminal crystal oscillator Analog power supply General-purpose digital with port interrupt map-able secondary function Default mapping: ADC12CLK output; external trigger input Comparator_B input Analog input 12-bit (only CC430F613x) General-purpose digital with port interrupt map-able secondary function Default mapping: ACLK output Comparator_B input Analog input 12-bit (only CC430F613x) General-purpose digital with port interrupt map-able secondary function Default mapping: output Comparator_B input Analog input 12-bit (only CC430F613x) Output reference voltage (only CC430F613x) Input external reference voltage (only CC430F613x) General-purpose digital with port interrupt map-able secondary function Default mapping: RTCCLK output Comparator_B input Analog input 12-bit (only CC430F613x) Negative terminal ADC's reference voltage both sources, internal reference voltage, external applied reference voltage (only CC430F613x) General-purpose digital with port interrupt map-able secondary function Default mapping: CCR2 compare output/capture input Comparator_B input Analog input 12-bit (only CC430F613x) General-purpose digital with port interrupt map-able secondary function Default mapping: CCR1 compare output/capture input Comparator_B input Analog input 12-bit (only CC430F613x) General-purpose digital with port interrupt map-able secondary function Default mapping: CCR0 compare output/capture input Comparator_B input Analog input 12-bit (only CC430F613x) General-purpose digital with port interrupt map-able secondary function Default mapping: Comparator_B output; Timer1_A3 clock input Comparator_B input Analog input 12-bit (only CC430F613x) Ground supply exposed attach must connected solid ground plane this ground connection chip! DESCRIPTION
P2.6/ PM_ACLK/ (/A6)
P2.5/ PM_SVMOUT/ (/A5/ VREF+/ VeREF+)
P2.4/ PM_RTCCLK/ (/A4/ VREF-/ VeREF-)
P2.3/ PM_TA1CCR2A/ (/A3)
P2.2/ PM_TA1CCR1A/ (/A2)
P2.1/PM_TA1CCR0A/CB1(/A1)
P2.0/ PM_CBOUT1/ PM_TA1CLK/ (/A0)
Exposed attach
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CC430F513x Terminal Functions
TERMINAL NAME P2.2/ PM_TA1CCR1A/ CB2/ DESCRIPTION General-purpose digital with port interrupt map-able secondary function Default mapping: CCR1 compare output/capture input Comparator_B input Analog input 12-bit General-purpose digital with port interrupt map-able secondary function Default mapping: CCR0 compare output/capture input Comparator_B input Analog input 12-bit General-purpose digital with port interrupt map-able secondary function Default mapping: Comparator_B output; Timer1_A3 clock input Comparator_B input Analog input 12-bit General-purpose digital with port interrupt map-able secondary function Default mapping: USCI_A0 clock input/output USCI_B0 slave transmit enable General-purpose digital with port interrupt map-able secondary function Default mapping: USCI_A0 UART transmit data; USCI_A0 slave master General-purpose digital with port interrupt map-able secondary function Default mapping: USCI_A0 UART receive data; USCI_A0 slave master Regulated core power supply Digital power supply General-purpose digital with port interrupt map-able secondary function Default mapping: USCI_B0 clock input/output USCI_A0 slave transmit enable segment output General-purpose digital with port interrupt map-able secondary function Default mapping: USCI_B0 slave master out/USCI_B0 data segment output General-purpose digital with port interrupt map-able secondary function Default mapping: USCI_B0 slave master in/UCSI_B0 clock segment output General-purpose digital with port interrupt map-able secondary function Default mapping: Radio GDO2 output segment output General-purpose digital with port interrupt map-able secondary function Default mapping: Radio GDO0 output segment output General-purpose digital with map-able secondary function Default mapping: SMCLK output segment output General-purpose digital with map-able secondary function Default mapping: Radio GDO1 output segment output General-purpose digital with map-able secondary function Default mapping: CCR4 compare output/capture input segment output General-purpose digital with map-able secondary function Default mapping: CCR3 compare output/capture input segment output General-purpose digital with map-able secondary function Default mapping: CCR2 compare output/capture input segment output General-purpose digital with map-able secondary function Default mapping: CCR1 compare output/capture input segment output General-purpose digital with map-able secondary function Default mapping: CCR0 compare output/capture input segment output
P2.1/ PM_TA1CCR0A/ CB1/
P2.0/ PM_CBOUT1/ PM_TA1CLK/ CB0/ P1.7/ PM_UCA0CLK/ PM_UCB0STE P1.6/ PM_UCA0TXD/ PM_UCB0SIMO P1.5/ PM_UCA0RXD/ PM_UCB0SOMI VCORE DVCC P1.4/ PM_UCB0CLK/ PM_UCA0STE/ P1.3/ PM_UCB0SIMO/ PM_UCB0SDA/ P1.2/ PM_UCB0SOMI/ PM_UCB0SCL/ P1.1/ PM_RFGDO2/
PRODUCT PREVIEW
P1.0/ PM_RFGDO0/
P3.7/ PM_SMCLK/
P3.6/ PM_RFGDO1/
P3.5/ PM_TA0CCR4A/
P3.4/ PM_TA0CCR3A/
P3.3/ PM_TA0CCR2A/
P3.2/ PM_TA0CCR1A/
P3.1/ PM_TA0CCR0A/
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CC430F513x Terminal Functions (continued)
TERMINAL NAME P3.0/ PM_CBOUT0/ PM_TA0CLK/ DVCC P2.7/ PM_ADC12CLK/ PM_DMAE0 P2.6/ PM_ACLK RF_XIN RF_XOUT AVCC_RF AVCC_RF RF_P RF_N AVCC_RF AVCC_RF RBIAS GUARD PJ.0/ PJ.1/ TDI/ TCLK PJ.2/ PJ.3/ TEST/ SBWTCK RST/NMI/ SBWTDIO DVCC AVSS P5.1/ XOUT P5.0/ AVCC DESCRIPTION General-purpose digital with map-able secondary function Default mapping: Comparator_B output; Timer0_A5 clock input segment output Digital power supply General-purpose digital with port interrupt map-able secondary function Default mapping: ADC12CLK output; external trigger input General-purpose digital with port interrupt map-able secondary function Default mapping: ACLK output Input terminal crystal oscillator, external clock input Output terminal crystal oscillator Radio analog power supply Radio analog power supply Positive input receive mode Positive output from transmit mode Negative input receive mode Negative output from transmit mode Radio analog power supply External bias resistor radio reference current Power supply connection digital noise isolation General-purpose digital Test data output port General-purpose digital Test data input test clock input General-purpose digital Test mode select General-purpose digital Test clock Test mode select digital JTAG pins Spy-bi-wire input clock Reset input active Non-maskable interrupt input Spy-bi-wire data input/output Digital power supply Analog ground supply ADC12 General-purpose digital Output terminal crystal oscillator General-purpose digital Input terminal crystal oscillator Analog power supply General-purpose digital with port interrupt map-able secondary function Default mapping: output Comparator_B input Analog input 12-bit Output reference voltage Input external reference voltage General-purpose digital with port interrupt map-able secondary function Default mapping: RTCCLK output Comparator_B input Analog input 12-bit Negative terminal ADC's reference voltage both sources, internal reference voltage, external applied reference voltage
P2.5/ PM_SVMOUT/ CB5/ VREF+/ VeREF+
P2.4/ PM_RTCCLK/ CB4/ VREF-/ VeREF-
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Radio analog power supply
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CC430F513x Terminal Functions (continued)
TERMINAL NAME P2.3/ PM_TA1CCR2A/ CB3/ DESCRIPTION General-purpose digital with port interrupt map-able secondary function Default mapping: CCR2 compare output/capture input Comparator_B input Analog input 12-bit Ground supply exposed attach must connected solid ground plane this ground connection chip!
Exposed attach
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SHORT-FORM DESCRIPTION Sub-1 Radio
implemented sub-1-GHz radio module based industry-leading CC1101, requiring very external components. Figure shows high-level block diagram implemented radio.
RADIO CONTROL DEMODULATOR
RXFIFO
RF_P RF_N
FREQ SYNTH
MODULATOR
INTERFACE
PACKET HANDLER
BIAS
XOSC
RBIAS
RF_XIN
RF_XOUT
Figure Sub-1 Radio Block Diagram radio features low-IF receiver. received signal amplified low-noise amplifier (LNA) down-converted quadrature intermediate frequency (IF). signals digitized. Automatic gain control (AGC), fine channel filtering, demodulation bit/packet synchronization performed digitally. transmitter part based direct synthesis frequency. frequency synthesizer includes completely on-chip degrees phase shifter generating signals down-conversion mixers receive mode. crystal oscillator generates reference frequency synthesizer, well clocks digital part. memory mapped register interface used data access, configuration status request CPU. digital baseband includes support channel configuration, packet handling data buffering. complete module descriptions, refer CC430 Family User's Guide, literature number SLAU259.
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TXFIFO
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MSP430 16-bit RISC architecture that highly transparent application. operations, other than program-flow instructions, performed register operations conjunction with seven addressing modes source operand four addressing modes destination operand. integrated with registers that provide reduced instruction execution time. register-to-register operation execution time cycle clock. Four registers, dedicated program counter, stack pointer, status register, constant generator, respectively. remaining registers general-purpose registers. Peripherals connected using data, address, control buses, handled with instructions. instruction consists original instructions with three formats seven address modes additional instructions expanded address range. Each instruction operate word byte data.
Operating Modes
MSP430 active mode software selectable low-power modes operation. interrupt event wake device from five low-power modes, service request, restore back low-power mode return from interrupt program. following seven operating modes configured software: Active mode (AM) clocks active Low-power mode (LPM0) disabled ACLK SMCLK remain active, MCLK disabled loop control remains active Low-power mode (LPM1) disabled loop control disabled ACLK SMCLK remain active, MCLK disabled Low-power mode (LPM2) disabled MCLK loop control DCOCLK disabled DCO's dc-generator remains enabled ACLK remains active Low-power mode (LPM3) disabled MCLK, loop control, DCOCLK disabled DCO's dc-generator disabled ACLK remains active Low-power mode (LPM4) disabled ACLK disabled MCLK, loop control, DCOCLK disabled DCO's dc-generator disabled Crystal oscillator stopped Complete data retention
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Interrupt Vector Addresses
interrupt vectors power-up start address located address range 0FFFFh 0FF80h. vector contains 16-bit address appropriate interrupt-handler instruction sequence. Interrupt Sources, Flags, Vectors
INTERRUPT SOURCE System Reset Power-Up External Reset Watchdog Timeout, Violation Flash Memory Violation System Vacant Memory Access JTAG Mailbox User Oscillator Fault Flash Memory Access Violation Comparator_B Watchdog Interval Timer Mode USCI_A0 Receive/Transmit USCI_B0 Receive/Transmit ADC12_A (Reserved CC430F612x) Timer0_A5 Timer0_A5 RF1A CC1101-based Radio Timer1_A3 Timer1_A3 Port Port LCD_B (Reserved CC430F513x) RTC_A Reserved INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
WDTIFG, KEYV (SYSRSTIV)
Reset
0FFFEh
highest
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, JMBOUTIFG (SYSSNIV)
(Non)maskable
0FFFCh
NMIIFG, OFIFG, ACCVIFG (SYSUNIV) Comparator_B Interrupt Flags (CBIV) WDTIFG UCA0RXIFG, UCA0TXIFG (UCA0IV)
(Non)maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable
0FFFAh 0FFF8h 0FFF6h 0FFF4h 0FFF2h 0FFF0h 0FFEEh 0FFECh 0FFEAh 0FFE8h 0FFE6h 0FFE4h 0FFE2h 0FFE0h 0FFDEh 0FFDCh 0FFDAh 0FFD8h 0FF80h
lowest
UCB0RXIFG, UCB0TXIFG, Status Interrupt Flags (UCB0IV) ADC12IFG0 ADC12IFG15 (ADC12IV) TA0CCR0 CCIFG0 TA0CCR1 CCIFG1 TA0CCR4 CCIFG4, TA0IFG (TA0IV) Radio Interface Interrupt Flags (RF1AIFIV) Radio Core Interrupt Flags (RF1AIV) DMA0IFG, DMA1IFG, DMA2IFG (DMAIV) TA1CCR0 CCIFG0 TA1CCR1 CCIFG1 TA1CCR2 CCIFG2, TA1IFG (TA1IV) P1IFG.0 P1IFG.7 (P1IV) P2IFG.0 P2IFG.7 (P2IV)
LCD_B Interrupt Flags (LCDBIV)
Maskable Maskable Maskable
RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV) AESRDYIFG Reserved
Multiple source flags reset generated tries fetch instructions from within peripheral space. (Non)maskable: individual interrupt-enable disable interrupt event, general-interrupt enable cannot disable Reserved interrupt vectors addresses used this device used regular program code necessary. maintain compatibility with other devices, recommended reserve these locations.
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Memory Organization
Memory Organization
CC430F6137/F6127/F513 Main Memory (flash) Main: interrupt vector Main: code memory Main 32kB 00FFFFh-00FF80h 00FFFFh-008000h CC430F6126 32kB 00FFFFh-00FF80h 00FFFFh-008000h CC430F6135/F6125/F512 16kB 00FFFFh-00FF80h 00FFFFh-00C000h CC430F5123 00FFFFh-00FF80h 00FFFFh-00E000h
Sect Sect Info Info
002BFFh-002400h (2kB) 0023FFh-001C00h (2kB) 001AFFh 001A80h 001A7Fh 001A00h 0019FFh 001980h 00197Fh 001900h 0018FFh 001880h 00187Fh 001800h 0017FFh 001600h 0015FFh 001400h 0013FFh 001200h 0011FFh 001000h 000FFFh
available 0023FFh-001C00h (2kB) 001AFFh 001A80h 001A7Fh 001A00h 0019FFh 001980h 00197Fh 001900h 0018FFh 001880h 00187Fh 001800h 0017FFh 001600h 0015FFh 001400h 0013FFh 001200h 0011FFh 001000h 000FFFh
available 0023FFh-001C00h (2kB) 001AFFh 001A80h 001A7Fh 001A00h 0019FFh 001980h 00197Fh 001900h 0018FFh 001880h 00187Fh 001800h 0017FFh 001600h 0015FFh 001400h 0013FFh 001200h 0011FFh 001000h 000FFFh
available 0023FFh-001C00h (2kB) 001AFFh 001A80h 001A7Fh 001A00h 0019FFh 001980h 00197Fh 001900h 0018FFh 001880h 00187Fh 001800h 0017FFh 001600h 0015FFh 001400h 0013FFh 001200h 0011FFh 001000h 000FFFh
(Device Descriptor) Structures
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Information memory (flash)
Info Info
Bootstrap loader (BSL) memory (flash)
Peripherals
mentioned memory regions vacant memory access them will cause Vacant Memory Interrupt.
Bootstrap Loader (BSL)
enables users program flash memory using UART serial interface. Access device memory protected user-defined password. complete description features implementation, application report Features MSP430F5xx Bootstrap Loader, literature number SLAA400. Table Functions
FUNCTION Data transmit Data receive DEVICE OUTPUT SIGNAL P1.6 P1.5
Flash Memory
flash memory programmed JTAG port, Spy-Bi-Wire (SBW), in-system CPU. perform single-byte, single-word, long-word writes flash memory. Features flash memory include: Flash memory segments main memory four segments information memory (Info Info bytes each. Each segment main memory bytes size.
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Segments erased step, each segment individually erased. Segments Info Info erased individually, group with main memory segments. Segments Info Info also called information memory. Segment locked separately.
Memory
memory made sectors. Each sector completely powered down save leakage, however data lost. Features memory include: memory sectors bytes each. Each sector complete disabled, however data retention lost. Each sector automatically enters power retention mode when possible.
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Peripherals
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Peripherals connected through data, address, control busses handled using instructions. complete module descriptions, refer CC430 Family User's Guide, literature number SLAU259. Oscillator System Clock Unified Clock System (UCS) module includes support 32768-Hz watch crystal oscillator, internal very-low-power low-frequency oscillator (VLO), internal trimmed low-frequency oscillator (REFO), integrated internal digitally-controlled oscillator (DCO), high-frequency crystal oscillator. module designed meet requirements both system cost low-power consumption. module features digital frequency locked loop (FLL) hardware that, conjunction with digital modulator, stabilizes frequency programmable multiple watch crystal frequency. internal provides fast turn-on clock source stabilizes less than module provides following clock signals: Auxiliary clock (ACLK), sourced from 32768-Hz watch crystal, high-frequency crystal, internal low-frequency oscillator (VLO), trimmed low-frequency oscillator (REFO). Main clock (MCLK), system clock used CPU. MCLK sourced same sources made available ACLK. Sub-Main clock (SMCLK), subsystem clock used peripheral modules. SMCLK sourced same sources made available ACLK. ACLK/n, buffered output ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32. Power Management Module (PMM) includes integrated voltage regulator that supplies core voltage device contains programmable output levels provide power optimization. also includes supply voltage supervisor (SVS) supply voltage monitoring (SVM) circuitry, well brownout protection. brownout circuit implemented provide proper internal reset signal device during power-on power-off. SVS/SVM circuitry detects supply voltage drops below user-selectable level supports both supply voltage supervision (the device automatically reset) supply voltage monitoring (SVM, device automatically reset). circuitry available primary supply core supply. Digital There five 8-bit ports implemented: ports through individual bits independently programmable. combination input, output, interrupt conditions possible. Programmable pullup pulldown ports. Programmable drive strength ports. Edge-selectable interrupt input capability eight bits ports Read/write access port-control registers supported instructions. Ports accessed byte-wise through word-wise pairs PB).
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Port Mapping Controller port mapping controller allows flexible re-configurable mapping digital functions port pins ports through Table Port Mapping, Mnemonics Functions
Value PxMAPy Mnemonic PM_NONE PM_CBOUT0 PM_TA0CLK PM_CBOUT1 PM_TA1CLK PM_ACLK PM_MCLK PM_SMCLK PM_RTCCLK PM_ADC12CLK PM_DMAE0 PM_SVMOUT PM_TA0CCR0A PM_TA0CCR1A PM_TA0CCR2A PM_TA0CCR3A PM_TA0CCR4A PM_TA1CCR0A PM_TA1CCR1A PM_TA1CCR2A PM_UCA0RXD PM_UCA0SOMI PM_UCA0TXD PM_UCA0SIMO PM_UCA0CLK PM_UCB0STE PM_UCB0SOMI PM_UCB0SCL PM_UCB0SIMO PM_UCB0SDA Timer_A0 clock input Timer_A1 clock input None None None None external trigger input None Timer_A0 CCR0 capture input CCI0A Timer_A0 CCR1 capture input CCI1A Timer_A0 CCR2 capture input CCI2A Timer_A0 CCR3 capture input CCI3A Timer_A0 CCR4 capture input CCI4A Timer_A1 CCR0 capture input CCI0A Timer_A1 CCR1 capture input CCI1A Timer_A1 CCR2 capture input CCI2A Input Function None Output Function DVSS Comparator_B output Timer_A0 clock input) Comparator_B output Timer_A1 clock input) ACLK output MCLK output SMCLK output RTCCLK output ADC12CLK output output CCR0 compare output Out0 CCR1 compare output Out1 CCR2 compare output Out2 CCR3 compare output Out3 CCR4 compare output Out4 CCR0 compare output Out0 CCR1 compare output Out1 CCR2 compare output Out2
USCI_A0 UART (Direction controlled USCI input) USCI_A0 slave master (direction controlled USCI) USCI_A0 UART (Direction controlled USCI output) USCI_A0 slave master (direction controlled USCI) USCI_A0 clock input/output (direction controlled USCI) USCI_B0 slave transmit enable (direction controlled USCI input) USCI_B0 slave master (direction controlled USCI) USCI_B0 clock (open drain direction controlled USCI) USCI_B0 slave master (direction controlled USCI) USCI_B0 data (open drain direction controlled USCI)
Input output function selected corresponding setting port direction register PxDIR. UART functionality determined selected USCI mode. UCA0CLK function takes precedence over UCB0STE function. mapped required UCA0CLK input output USCI_B0 will forced 3-wire mode even 4-wire mode selected. functionality determined selected USCI mode. case functionality selected output mapped drives only logical level. Submit Documentation Feedback
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Table Port Mapping, Mnemonics Functions (continued)
Value (0FFh) PxMAPy Mnemonic PM_UCB0CLK PM_UCA0STE PM_RFGDO0 PM_RFGDO1 PM_RFGDO2 Reserved Reserved Reserved Reserved Reserved PM_ANALOG Input Function Output Function USCI_B0 clock input/output (direction controlled USCI) USCI_A0 slave transmit enable (direction controlled USCI input) Radio GDO0 (direction controlled Radio) Radio GDO1 (direction controlled Radio) Radio GDO2 (direction controlled Radio) None None None None None DVSS DVSS DVSS DVSS DVSS
Disables output driver well input Schmitt-trigger prevent parasitic cross currents when applying analog signals.
UCB0CLK function takes precedence over UCA0STE function. mapped required UCB0CLK input output USCI_A0 will forced 3-wire mode even 4-wire mode selected. value PMPAP_ANALOG mnemonic 0FFh. port mapping registers only bits wide upper bits ignored resulting read value
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Table Default Mapping
P1.0/P1MAP0 P1.1/P1MAP1 P1.2/P1MAP2 P1.3/P1MAP3 P1.4/P1MAP4 P1.5/P1MAP5 P1.6/P1MAP6 P1.7/P1MAP7 P2.0/P2MAP0 P2.1/P2MAP1 P2.2/P2MAP2 P2.3/P2MAP3 P2.4/P2MAP4 P2.5/P2MAP5 P2.6/P2MAP6 P2.7/P2MAP7 P3.0/P3MAP0 P3.1/P3MAP1 P3.2/P3MAP2 P3.3/P3MAP3 P3.4/P3MAP4 P3.5/P3MAP5 P3.6/P3MAP6 P3.7/P3MAP7 PxMAPy Mnemonic PM_RFGDO0 PM_RFGDO2 PM_UCB0SOMI/PM_UCB0SCL PM_UCB0SIMO/PM_UCB0SDA PM_UCB0CLK/PM_UCA0STE PM_UCA0RXD/PM_UCA0SOMI PM_UCA0TXD/PM_UCA0SIMO PM_UCA0CLK/PM_UCB0STE PM_CBOUT1/PM_TA1CLK PM_TA1CCR0A PM_TA1CCR1A PM_TA1CCR2A PM_RTCCLK PM_SVMOUT PM_ACLK PM_ADC12CLK/PM_DMAE0 PM_CBOUT0/PM_TA0CLK PM_TA0CCR0A PM_TA0CCR1A PM_TA0CCR2A PM_TA0CCR3A PM_TA0CCR4A PM_RFGDO1 PM_SMCLK Input Function None None Output Function Radio GDO0 Radio GDO2
USCI_B0 slave master (direction controlled USCI)/USCI_B0 clock (open drain direction controlled USCI) USCI_B0 slave master (direction controlled USCI)/USCI_B0 data (open drain direction controlled USCI) USCI_B0 clock input/output (direction controlled USCI)/USCI_A0 slave transmit enable (direction controlled USCI input) USCI_A0 UART (Direction controlled USCI input)/USCI_A0 slave master (direction controlled USCI) USCI_A0 UART (Direction controlled USCI output)/USCI_A0 slave master (direction controlled USCI) USCI_A0 clock input/output (direction controlled USCI)/USCI_B0 slave transmit enable (direction controlled USCI input) Timer_A1 clock input Timer_A1 CCR0 capture input CCI0A Timer_A1 CCR1 capture input CCI1A Timer_A1 CCR2 capture input CCI2A None None None external trigger input Timer_A0 clock input Timer_A0 CCR0 capture input CCI0A Timer_A0 CCR1 capture input CCI1A Timer_A0 CCR2 capture input CCI2A Timer_A0 CCR3 capture input CCI3A Timer_A0 CCR4 capture input CCI4A None None Comparator_B output CCR0 compare output Out0 CCR1 compare output Out1 CCR2 compare output Out2 RTCCLK output output ACLK output ADC12CLK output Comparator_B output CCR0 compare output Out0 CCR1 compare output Out1 CCR2 compare output Out2 CCR3 compare output Out3 CCR4 compare output Out4 Radio GDO1 SMCLK output
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System Module (SYS)
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module handles many system functions within device. These include power reset power clear handling, source selection management, reset interrupt vector generators, boot strap loader entry mechanisms, well configuration management (device descriptors). also includes data exchange mechanism JTAG called JTAG mailbox that used application. Table System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTER SYSRSTIV System Reset ADDRESS 019Eh INTERRUPT EVENT interrupt pending Brownout (BOR) RST/NMI (POR) DoBOR (BOR) Reserved Security violation (BOR) SVSL (POR) SVSH (POR) SVML_OVP (POR) SVMH_OVP (POR) DoPOR (POR) timeout (PUC) violation (PUC) KEYV flash violation (PUC) unlock (PUC) Peripheral area fetch (PUC) violation (PUC) Reserved SYSSNIV System 019Ch interrupt pending SVMLIFG SVMHIFG DLYLIFG DLYHIFG VMAIFG JMBINIFG JMBOUTIFG VLRLIFG VLRHIFG Reserved SYSUNIV, User 019Ah interrupt pending NMIFG OFIFG ACCVIFG Reserved VALUE Lowest Highest Lowest Highest Lowest Highest PRIORITY
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Watchdog Timer (WDT_A) primary function watchdog timer perform controlled system restart after software problem occurs. selected time interval expires, system reset generated. watchdog function needed application, timer configured interval timer generate interrupts selected time intervals.
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Controller controller allows movement data from memory address another without intervention. Using controller increase throughput peripheral modules. controller reduces system power consumption allowing remain sleep mode, without having awaken move data from peripheral. Table Trigger Assignments
Trigger Channel DMAREQ TA0CCR0 CCIFG TA0CCR2 CCIFG TA1CCR0 CCIFG TA1CCR2 CCIFG Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RFRXIFG RFTXIFG UCA0RXIFG UCA0TXIFG UCB0RXIFG UCB0TXIFG Reserved Reserved Reserved Reserved ADC12IFGx Reserved Reserved Reserved Reserved ready DMA2IFG DMAE0 DMAREQ TA0CCR0 CCIFG TA0CCR2 CCIFG TA1CCR0 CCIFG TA1CCR2 CCIFG Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RFRXIFG RFTXIFG UCA0RXIFG UCA0TXIFG UCB0RXIFG UCB0TXIFG Reserved Reserved Reserved Reserved ADC12IFGx Reserved Reserved Reserved Reserved ready DMA0IFG DMAE0 DMAREQ TA0CCR0 CCIFG TA0CCR2 CCIFG TA1CCR0 CCIFG TA1CCR2 CCIFG Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RFRXIFG RFTXIFG UCA0RXIFG UCA0TXIFG UCB0RXIFG UCB0TXIFG Reserved Reserved Reserved Reserved ADC12IFGx Reserved Reserved Reserved Reserved ready DMA1IFG DMAE0 Reserved
Reserved triggers used other devices family. Reserved triggers will cause trigger event when selected. Only CC430F613x CC430F513x. Reserved CC430F612x.
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CRC16
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CRC16 module produces signature based sequence entered data values used data checking purposes. CRC16 module signature based CRC-CCITT standard. Hardware Multiplier multiplication operation supported dedicated peripheral module. module performs operations with 32-bit, 24-bit, 16-bit, 8-bit operands. module capable supporting signed unsigned multiplication well signed unsigned multiply accumulate operations. AES128 Accelerator accelerator module performs decryption 128-bit data with 128-bit keys according Advanced Encryption Standard (AES) (FIPS 197) hardware. Universal Serial Communication Interface (USCI) USCI module used serial data communication. USCI module supports synchronous communication protocols such pin) I2C, asynchronous communication protocols such UART, enhanced UART with automatic baudrate detection, IrDA. USCI_An module provides support pin), UART, enhanced UART, IrDA. USCI_Bn module provides support pin) I2C. USCI_A0 USCI_B0 module implemented.
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Timer0_A5 Timer0_A3 16-bit timer/counter with three capture/compare registers. Timer0_A3 support multiple capture/compares, outputs, interval timing. Timer0_A3 also extensive interrupt capabilities. Interrupts generated from counter overflow conditions from each capture/compare registers. Table Timer0_A5 Signal Connections
DEVICE INPUT SIGNAL PM_TA0CLK ACLK (internal) SMCLK (internal) RFCLK/192 PM_TA0CCR0A DVSS DVSS DVCC PM_TA0CCR1A CBOUT (internal) DVSS DVCC PM_TA0CCR2A ACLK (internal) DVSS DVCC PM_TA0CCR3A GDO1 from Radio (internal) DVSS DVCC PM_TA0CCR4A GDO2 from Radio (internal) DVSS DVCC MODULE INPUT NAME TACLK ACLK SMCLK INCLK CCI0A CCI0B CCI1A CCI1B CCI2A CCI2B CCI3A CCI3B CCI4A CCI4B CCR4 PM_TA0CCR4A CCR3 PM_TA0CCR3A CCR2 PM_TA0CCR2A CCR1 PM_TA0CCR1A ADC12 (internal) ADC12SHSx CCR0 PM_TA0CCR0A Timer MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL
radio output different RFCLK divider setting selected this divider setting will also used Timer_A INCLK. Only CC430F613x CC430F513x.
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Timer1_A3
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Timer1_A1 16-bit timer/counter with capture/compare registers. Timer1_A1 support multiple capture/compares, outputs, interval timing. Timer1_A1 also extensive interrupt capabilities. Interrupts generated from counter overflow conditions from each capture/compare registers. Table Timer1_A3 Signal Connections
DEVICE INPUT SIGNAL PM_TA1CLK ACLK (internal) SMCLK (internal) RFCLK/192 PM_TA1CCR0A Async. Output (internal) DVSS DVCC MODULE INPUT NAME TACLK ACLK SMCLK INCLK CCI0A CCI0B CCI1A CCI1B CCI2A CCI2B CCR2 PM_TA1CCR2A CCR1 PM_TA1CCR1A CCR0 PM_TA1CCR0A Async. Input (internal) Timer MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL
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PM_TA1CCR1A CBOUT (internal) DVSS DVCC PM_TA1CCR2A ACLK (internal) DVSS DVCC
radio output different RFCLK divider setting selected this divider setting will also used Timer_A INCLK.
Real-Time Clock (RTC_A) RTC_A module used general-purpose 32-bit counter (counter mode) integrated real-time clock (RTC) (calendar mode). counter mode, RTC_A also includes independent 8-bit timers that cascaded form 16-bit timer/counter. Both timers read written software. Calendar mode integrates internal calendar which compensates months with less than days includes leap year correction. RTC_A also supports flexible alarm functions offset-calibration hardware. Voltage Reference reference module (REF) responsible generation critical reference voltages that used various analog peripherals device. These include ADC12_A, LCD_B, COMP_B modules. LCD_B (only CC430F613x CC430F612x) LCD_B driver generates segment common signals required drive Liquid Crystal Display (LCD). LCD_B controller dedicated data memories hold segment drive information. Common segment signals generated defined mode. Static, 2-mux, 3-mux, 4-mux LCDs supported. module provide voltage independent supply voltage with integrated charge pump. possible control level voltage thus contrast software. module also provides automatic blinking capability individual segments. Comparator_B primary function Comparator_B module support precision slope analog-to-digital conversions, battery voltage supervision, monitoring external analog signals.
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ADC12_A (only CC430F613x CC430F513x) ADC12_A module supports fast, 12-bit analog-to-digital conversions. module implements 12-bit core, sample select control, reference generator word conversion-and-control buffer. conversion-and-control buffer allows independent samples converted stored without intervention. Embedded Emulation Module (EEM, Version) Embedded Emulation Module (EEM) supports real-time in-system debugging. version implemented devices following features: Three hardware triggers/breakpoints memory access hardware trigger/breakpoint register write access four hardware triggers combined form complex triggers/breakpoints cycle counter Clock control module level
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Peripheral File
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Table Peripherals
MODULE NAME Special Functions (refer Table (refer Table Flash Control (refer Table CRC16 (refer Table Control (refer Table Watchdog (refer Table (refer Table (refer Table Shared Reference (refer Table Port Mapping Control (refer Table Port Mapping Port (refer Table Port Mapping Port (refer Table Port Mapping Port (refer Table Port P1/P2 (refer Table Port P3/P4 available CC430F513x) (refer Table Port (refer Table Port (refer Table Timer0_A5 (refer Table Timer1_A3 (refer Table RTC_A (refer Table 32-bit Hardware Multiplier (refer Table General Control (refer Table Channel (refer Table Channel (refer Table Channel (refer Table USCI0 (refer Table ADC12 (refer Table only CC430F613x CC430F513x) Comparator_B (refer Table Accelerator (refer Table LCD_B (refer Table only CC430F613x CC430F612x) Radio Interface (refer Table BASE ADDRESS 0100h 0120h 0140h 0150h 0158h 015Ch 0160h 0180h 01B0h 01C0h 01C8h 01D0h 01D8h 0200h 0220h 0240h 0320h 0340h 0380h 04A0h 04C0h 0500h 0500h 0500h 0500h 05C0h 0700h 08C0h 09C0h 0A00h 0F00h OFFSET ADDRESS RANGE 000h 01Fh 000h 00Fh 000h 00Fh 000h 007h 000h 001h 000h 001h 000h 01Fh 000h 01Fh 000h 001h 000h 007h 000h 007h 000h 007h 000h 007h 000h 01Fh 000h 01Fh 000h 01Fh 000h 01Fh 000h 03Fh 000h 03Fh 000h 01Fh 000h 02Fh 000h 00Fh 010h 01Fh 020h 02Fh 030h 03Fh 000h 03Fh 000h 03Fh 000h 00Fh 000h 00Fh 000h 05Fh 000h 03Fh
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Table Special Function Registers
REGISTER DESCRIPTION reset control interrupt flag interrupt enable REGISTER SFRRPCR SFRIFG1 SFRIE1 OFFSET
Table Registers
REGISTER DESCRIPTION Control 0120h0 interrupt enable interrupt flags side control high side control control control PMMIE PMMIFG SVSMLCTL SVSMHCTL PMMCTL1 PMMCTL0 REGISTER PM5CTL0 OFFSET
Table Flash Control Registers
Flash control Flash control Flash control FCTL4 FCTL3 FCTL1
Table CRC16 Registers
REGISTER DESCRIPTION result data input REGISTER CRC16INIRES CRC16DI OFFSET
Table Control Registers
REGISTER DESCRIPTION control REGISTER RCCTL0 OFFSET
Table Watchdog Registers
REGISTER DESCRIPTION Watchdog timer control REGISTER WDTCTL OFFSET
Table Registers
REGISTER DESCRIPTION control control control control control control control control control REGISTER UCSCTL8 UCSCTL7 UCSCTL6 UCSCTL5 UCSCTL4 UCSCTL3 UCSCTL2 UCSCTL1 UCSCTL0 OFFSET
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REGISTER DESCRIPTION
REGISTER
OFFSET
CC430F613x CC430F612x CC430F513x
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Table Registers
REGISTER DESCRIPTION Reset vector generator System vector generator User vector generator Error vector generator JTAG mailbox output JTAG mailbox output JTAG mailbox input JTAG mailbox input JTAG mailbox control Bootstrap loader configuration area System control REGISTER SYSRSTIV SYSSNIV SYSUNIV SYSBERRIV SYSJMBO1 SYSJMBO0 SYSJMBI1 SYSJMBI0 SYSJMBC SYSBSLC SYSCTL OFFSET
Table Shared Reference Registers
REGISTER DESCRIPTION Shared reference control REGISTER REFCTL OFFSET
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Table Port Mapping Registers
REGISTER DESCRIPTION Port mapping password register Port mapping control register Port P1.0 mapping register Port P1.1 mapping register Port P1.2 mapping register Port P1.3 mapping register Port P1.4 mapping register Port P1.5 mapping register Port P1.6 mapping register Port P1.7 mapping register Port P2.0 mapping register Port P2.1 mapping register Port P2.2 mapping register Port P2.3 mapping register Port P2.4 mapping register Port P2.5 mapping register Port P2.6 mapping register Port P2.7 mapping register Port P3.0 mapping register Port P3.1 mapping register Port P3.2 mapping register Port P3.3 mapping register Port P3.4 mapping register Port P3.5 mapping register Port P3.6 mapping register Port P3.7 mapping register REGISTER PMAPPWD PMAPCTL P1MAP0 P1MAP1 P1MAP2 P1MAP3 P1MAP4 P1MAP5 P1MAP6 P1MAP7 P2MAP0 P2MAP2 P2MAP2 P2MAP3 P2MAP4 P2MAP5 P2MAP6 P2MAP7 P3MAP0 P3MAP3 P3MAP2 P3MAP3 P3MAP4 P3MAP5 P3MAP6 P3MAP7 OFFSET
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Table Port Registers
REGISTER DESCRIPTION Port selection Port drive strength Port pullup/pulldown enable Port direction Port output Port input Port selection (not available CC430F513x) Port drive strength (not available CC430F513x) Port pullup/pulldown enable (not available CC430F513x) Port direction (not available CC430F513x) Port output (not available CC430F513x) Port input (not available CC430F513x) Port selection Port drive strength Port pullup/pulldown enable Port direction Port output Port input Port interrupt flag Port interrupt enable Port interrupt edge select Port interrupt vector word Port selection Port drive strength Port pullup/pulldown enable Port direction Port output Port input Port interrupt flag Port interrupt enable Port interrupt edge select Port interrupt vector word Port selection Port drive strength Port pullup/pulldown enable Port direction Port output Port input Port drive strength Port pullup/pulldown enable Port direction Port output Port input P5SEL P5DS P5REN P5DIR P5OUT P5IN P4SEL P4DS P4REN P4DIR P4OUT P4IN P3SEL P3DS P3REN P3DIR P3OUT P3IN P2IFG P2IE P2IES P2IV P2SEL P2DS P2REN P2DIR P2OUT P2IN P1IFG P1IE P1IES P1IV P1SEL P1DS P1REN P1DIR P1OUT P1IN PJDS PJREN PJDIR PJOUT PJIN REGISTER OFFSET
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Table Timer0_A5 Registers
REGISTER DESCRIPTION Timer0_A interrupt vector Timer0_A expansion register Capture/compare register Capture/compare register Capture/compare register Capture/compare register Capture/compare register Timer0_A register Capture/compare control Capture/compare control Capture/compare control Capture/compare control Capture/compare control Timer0_A control TA0IV TA0EX0 TA0CCR4 TA0CCR3 TA0CCR2 TA0CCR1 TA0CCR0 TA0R TA0CCTL4 TA0CCTL3 TA0CCTL2 TA0CCTL1 TA0CCTL0 TA0CTL REGISTER OFFSET
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Table Timer1_A3 Registers
REGISTER DESCRIPTION Timer1_A interrupt vector Timer1_A expansion register Capture/compare register Capture/compare register Capture/compare register Timer1_A register Capture/compare control Capture/compare control Capture/compare control Timer1_A control TA1IV TA1EX0 TA1CCR2 TA1CCR1 TA1CCR0 TA1R TA1CCTL2 TA1CCTL1 TA1CCTL0 TA1CTL REGISTER OFFSET
Table RTC_A Registers
REGISTER DESCRIPTION alarm days alarm week alarm hours alarm minutes year high year month days week/counter register hours/counter register minutes/counter register seconds/counter register interrupt vector word prescaler prescaler prescaler control Submit Documentation Feedback REGISTER RTCADAY RTCADOW RTCAHOUR RTCAMIN RTCYEARH RTCYEARL RTCMON RTCDAY RTCDOW/RTCNT4 RTCHOUR/RTCNT3 RTCMIN/RTCNT2 RTCSEC/RTCNT1 RTCIV RTCPS1 RTCPS0 RTCPS1CTL OFFSET
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Table RTC_A Registers (continued)
REGISTER DESCRIPTION prescaler control control control control control REGISTER RTCPS0CTL RTCCTL3 RTCCTL2 RTCCTL1 RTCCTL0 OFFSET
Table 32-bit Hardware Multiplier Registers
REGISTER DESCRIPTION MPY32 control register result most significant word result result result least significant word 32-bit operand high word 32-bit operand word 32-bit operand signed multiply accumulate high word 32-bit operand signed multiply accumulate word 32-bit operand multiply accumulate high word 32-bit operand multiply accumulate word 32-bit operand signed multiply high word 32-bit operand signed multiply word 32-bit operand multiply high word 32-bit operand multiply word extension register result high word result word 16-bit operand 16-bit operand signed multiply accumulate 16-bit operand multiply accumulate 16-bit operand signed multiply 16-bit operand multiply RES3 RES2 RES1 RES0 OP2H OP2L MACS32H MACS32L MAC32H MAC32L MPYS32H MPYS32L MPY32H MPY32L SUMEXT RESHI RESLO MACS MPYS REGISTER MPY32CTL0 OFFSET
Table Registers
REGISTER DESCRIPTION channel transfer size channel destination address high channel destination address channel source address high channel source address channel control channel transfer size channel destination address high channel destination address channel source address high channel source address channel control channel transfer size
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REGISTER DMA2SZ DMA2DAH DMA2DAL DMA2SAH DMA2SAL DMA2CTL DMA1SZ DMA1DAH DMA1DAL DMA1SAH DMA1SAL DMA1CTL DMA0SZ
OFFSET
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Table Registers (continued)
REGISTER DESCRIPTION channel destination address high channel destination address channel source address high channel source address channel control interrupt vector module control module control module control module control module control REGISTER DMA0DAH DMA0DAL DMA0SAH DMA0SAL DMA0CTL DMAIV DMACTL4 DMACTL3 DMACTL2 DMACTL1 DMACTL0 OFFSET
Table USCI0 Registers
REGISTER DESCRIPTION USCI interrupt vector word USCI interrupt flags USCI interrupt enable USCI slave address USCI address USCI synchronous transmit buffer USCI synchronous receive buffer USCI synchronous status USCI interrupt enable USCI synchronous rate USCI synchronous rate USCI synchronous control USCI synchronous control USCI interrupt vector word USCI interrupt flags USCI interrupt enable USCI IrDA receive control USCI IrDA transmit control USCI control USCI transmit buffer USCI receive buffer USCI status USCI modulation control USCI baud rate USCI baud rate USCI control USCI control REGISTER UCB0IV UCB0IFG UCB0IE UCB0I2CSA UCB0I2COA UCB0TXBUF UCB0RXBUF UCB0STAT UCB0I2CIE UCB0BR1 UCB0BR0 UCB0CTL1 UCB0CTL0 UCA0IV UCA0IFG UCA0IE UCA0IRRCTL UCA0IRTCTL UCA0ABCTL UCA0TXBUF UCA0RXBUF UCA0STAT UCA0MCTL UCA0BR1 UCA0BR0 UCA0CTL0 UCA0CTL1 OFFSET
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Table ADC12 Registers
REGISTER DESCRIPTION ADC12 Conversion memory ADC12 Conversion memory ADC12 Conversion memory Submit Documentation Feedback REGISTER ADC12MEM15 ADC12MEM14 ADC12MEM13 OFFSET
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Table ADC12 Registers (continued)
REGISTER DESCRIPTION ADC12 Conversion memory ADC12 Conversion memory ADC12 Conversion memory ADC12 Conversion memory ADC12 Conversion memory ADC12 Conversion memory ADC12 Conversion memory ADC12 Conversion memory ADC12 Conversion memory ADC12 Conversion memory ADC12 Conversion memory ADC12 Conversion memory ADC12 Conversion memory ADC12 memory-control register ADC12 memory-control register ADC12 memory-control register ADC12 memory-control register ADC12 memory-control register ADC12 memory-control register ADC12 memory-control register ADC12 memory-control register ADC12 memory-control register ADC12 memory-control register ADC12 memory-control register ADC12 memory-control register ADC12 memory-control register ADC12 memory-control register ADC12 memory-control register ADC12 memory-control register ADC12 Interrupt-vector-word register ADC12 Interrupt-enable register ADC12 Interrupt-flag register ADC12 control register ADC12 control register ADC12 control register REGISTER ADC12MEM12 ADC12MEM11 ADC12MEM10 ADC12MEM9 ADC12MEM8 ADC12MEM7 ADC12MEM6 ADC12MEM5 ADC12MEM4 ADC12MEM3 ADC12MEM2 ADC12MEM1 ADC12MEM0 ADC12MCTL15 ADC12MCTL14 ADC12MCTL13 ADC12MCTL12 ADC12MCTL11 ADC12MCTL10 ADC12MCTL9 ADC12MCTL8 ADC12MCTL7 ADC12MCTL6 ADC12MCTL5 ADC12MCTL4 ADC12MCTL3 ADC12MCTL2 ADC12MCTL1 ADC12MCTL0 ADC12IV ADC12IE ADC12IFG ADC12CTL2 ADC12CTL1 ADC12CTL0 OFFSET
Table Comparator_B Registers
REGISTER DESCRIPTION Comparator_B control register Comparator_B control register Comparator_B control register Comparator_B control register Comparator_B interrupt register Comparator_B interrupt vector word REGISTER CBCTL0 CBCTL1 CBCTL2 CBCTL3 CBINT CBIV OFFSET
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Table Accelerator Registers
REGISTER DESCRIPTION accelerator control register Reserved accelerator status register accelerator register accelerator data register accelerator data register AESASTAT AESAKEY AESADIN AESADOUT REGISTER AESACTL0 008h 00Ah OFFSET
Table LCD_B Registers
REGISTER DESCRIPTION LCD_B control register LCD_B control register LCD_B blinking control register LCD_B memory control register LCD_B voltage control register LCD_B port control register REGISTER LCDBCTL0 LCDBCTL1 LCDBBLKCTL LCDBMEMCTL LCDBVCTL LCDBPCTL0 LCDBPCTL1 LCDBCTL0 LCDBIV LCDM1 LCDM2 LCDM14 LCDBM1 LCDBM2 LCDBM14 000h 002h 004h 006h 008h 00Ah 00Ch 012h 01Eh 020h 021h 02Dh 040h 041h 04Dh OFFSET
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LCD_B port control register LCD_B charge pump control register LCD_B interrupt vector word LCD_B memory LCD_B memory LCD_B memory LCD_B blinking memory LCD_B blinking memory LCD_B blinking memory
Table Radio Interface Registers
REGISTER DESCRIPTION Radio interface control register Radio interface control register Radio interface error flag register Radio interface error vector word Radio interface interrupt vector word Radio instruction word register Radio instruction word register, 1-byte auto-read Radio instruction word register, 2-byte auto-read Radio data register Radio status word register Radio status word register, 1-byte auto-read Radio status word register, 2-byte auto-read Radio data register Radio data register, 1-byte auto-read Radio data register, 2-byte auto-read Radio core signal input register Radio core interrupt flag register Submit Documentation Feedback REGISTER RF1AIFCTL0 RF1AIFCTL1 RF1AIFERR RF1AIFERRV RF1AIFIV RF1AINSTRW RF1AINSTR1W RF1AINSTR2W RF1ADINW RF1ASTATW RF1ASTAT1W RF1AISTAT2W RF1ADOUTW RF1ADOUT1W RF1ADOUT2W RF1AIN RF1AIFG
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OFFSET
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Table Radio Interface Registers (continued)
REGISTER DESCRIPTION Radio core interrupt edge select register Radio core interrupt enable register Radio core interrupt vector word REGISTER RF1AIES RF1AIE RF1AIV OFFSET
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Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Voltage applied Voltage applied (except RF_P, RF_N, R_BIAS) Voltage applied RF_P, RF_N, R_BIAS Input level pins RF_P RF_N Diode current device terminal Storage temperature range, Tstg Unprogrammed device Programmed device -0.3 -0.3 max. 4.1V -0.3 10dBm -55°C 150°C -40°C 105°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. voltages referenced VSS. Higher temperature applied during board soldering according current JEDEC J-STD-020 specification with peak reflow temperatures higher than classified device label shipping boxes reels.
Recommended Operating Conditions
Supply voltage range during program execution flash programming (VCC AVCC DVCC) with default settings. Radio operational with PMMCOREVx Supply voltage range during program execution, flash programming radio operation (VCC AVCC DVCC) with default settings. Supply voltage range during program execution, flash programming radio operation (VCC AVCC DVCC) with PMMCOREVx high-side level lowered (SVSHRVLx=SVSHRRRLx=1) high-side disabled (SVSHE=0). Supply voltage (VSS AVSS DVSS) Operating free-air temperature Capacitor VCORE PMMCOREVx MCLK sourced clock source. fSYSTEM Processor (MCLK) frequency PMMCOREVx MCLK sourced clock source. PMMCOREVx MCLK sourced crystal oscillator FLL. 12.0 PMMCOREVx (default after POR) PMMCOREVx PMMCOREVx UNIT
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PMMCOREVx SVSHRVLx=SVSHRRRLx=1 SVSHE=0
CVCORE
25.0
27.0
recommended power AVCC DVCC from same source. maximum difference between AVCC DVCC tolerated during power operation. Lowering high-side level disabling high-side might cause operate regulation core voltage will still stay within it's limits still supervised low-side ensuring reliable operation. Modules have different maximum input clock specification. Refer specification respective module this data sheet.
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INPUT/OUTPUT SCHEMATICS Port P1.0 P1.4 Input/Output With Schmitt Trigger
S18.S22 (n/a CC430F513x) LCDS18.LCDS22 Logic P1REN.x P1MAP PMAP_ANALOG DVSS DVCC P1DIR.x from Port Mapping Direction Input Output
P1OUT.x from Port Mapping P1SEL.x P1IN.x
P1.0/P1MAP0(/S18) P1.1/P1MAP1(/S19) P1.2/P1MAP2(/S20) P1.3/P1MAP3(/S21) P1.4/P1MAP4(/S22)
P1DS.x drive High drive Keeper
Port Mapping
P1IE.x
P1IRQ.x P1IFG.x
P1SEL.x P1IES.x
Interrupt Edge Select
CC430F513x devices don't provide functionality port pins.
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Port (P1.0 P1.4) Functions
CONTROL BITS/SIGNALS NAME (P1.x) P1.0/P1MAP/S18 P1.0 (I/O) Mapped secondary digital function Output driver input Schmitt trigger disabled (not available CC430F513x) P1.1/P1MAP1/S19 P1.1 (I/O) Mapped secondary digital function Output driver input Schmitt trigger disabled (not available CC430F513x) P1.2/P1MAP2/S20 P1.2 (I/O) Mapped secondary digital function Output driver input Schmitt trigger disabled (not available CC430F513x) P1.3/P1MAP3/S21 P1.3 (I/O) Mapped secondary digital function Output driver input Schmitt trigger disabled (not available CC430F513x) P1.4/P1MAP4/S22 P1.4 (I/O) Mapped secondary digital function Output driver input Schmitt trigger disabled (not available CC430F513x) LCDSx available CC430F513x. FUNCTION P1DIR.x P1SEL.x P1MAPx LCDS19.
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Port P1.5 P1.7 Input/Output With Schmitt Trigger
LCD_B (n/a CC430F513x) from LCD_B Logic P1REN.x P1MAP PMAP_ANALOG DVSS DVCC P1DIR.x from Port Mapping Direction Input Output
P1OUT.x from Port Mapping P1SEL.x P1IN.x
P1DS.x drive High drive Keeper P1.5/P1MAP5(/R23) P1.6/P1MAP6(/R13) P1.7/P1MAP7(/R03)
Port Mapping
P1IE.x
P1IRQ.x P1IFG.x
P1SEL.x P1IES.x
Interrupt Edge Select
CC430F513x devices don't provide functionality port pins.
Port (P1.5 P1.7) Functions
NAME (P1.x) P1.5/P1MAP5/R23 P1.5 (I/O) Mapped secondary digital function (not available CC430F513x) P1.6/P1MAP6/R13/LCD P1.6 (I/O) Mapped secondary digital function R13/LCDREF (not available CC430F513x) P1.7/P1MAP7/R03 P1.7 (I/O) Mapped secondary digital function (not available CC430F513x), (ROSC) FUNCTION CONTROL BITS/SIGNALS P1DIR.x P1SEL.x P1MAPx
Setting P1SEL.x together with P1MAPx PM_ANALOG disables output driver well input Schmitt trigger.
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Port P2.0 P2.3, Input/Output With Schmitt Trigger
Logic ADC12 (n/a CC430F612x) INCHx Comparator_B from Comparator_B CBPD.x
P2REN.x P2MAP PMAP_ANALOG DVSS DVCC P2DIR.x from Port Mapping Direction Input Output
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P2OUT.x from Port Mapping P2SEL.x P2IN.x
P2DS.x drive High drive Keeper P2.0/P2MAP0/CB0(/A0) P2.1/P2MAP2/CB1(/A1) P2.2/P2MAP2/CB2(/A2) P2.3/P2MAP3/CB3(/A3)
Port Mapping
P2IE.x
P2IRQ.x P2IFG.x
P2SEL.x P2IES.x
Interrupt Edge Select
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Port P2.4 P2.5, Input/Output With Schmitt Trigger
Logic to/from Reference (n/a CC430F612x) ADC12 (n/a CC430F612x) INCHx Comparator_B from Comparator_B CBPD.x
P2REN.x P2MAP PMAP_ANALOG DVSS DVCC P2DIR.x from Port Mapping Direction Input Output
from Port Mapping P2SEL.x P2IN.x
P2DS.x drive High drive Keeper
Port Mapping
P2IE.x
P2IRQ.x P2IFG.x
P2SEL.x P2IES.x
Interrupt Edge Select
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P2OUT.x
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Port P2.6 P2.7 Input/Output With Schmitt Trigger
Logic ADC12 (n/a CC430F513x) INCHx Comparator_B (n/a CC430F513x) from Comparator_B CBPD.x (n/a CC430F513x) P2REN.x P2MAP PMAP_ANALOG DVSS DVCC P2DIR.x from Port Mapping Direction Input Output
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P2OUT.x from Port Mapping P2SEL.x P2IN.x
P2DS.x drive High drive Keeper P2.6/P2MAP6(/CB6/A6) P2.7/P2MAP7(/CB7/A7)
Port Mapping
P2IE.x
P2IRQ.x P2IFG.x
P2SEL.x P2IES.x
Interrupt Edge Select
CC430F513x devices don't provide analog functionality port P2.6 P2.7 pins.
Port (P2.0 P2.7) Functions
NAME (P2.x) P2.0/P2MAP0/CB0 (/A0) P2.0 (I/O) Mapped secondary digital function (not available CC430F612x) P2.1/P2MAP1/CB1 (/A1) P2.1 (I/O)
FUNCTION
CONTROL BITS/SIGNALS P2DIR.x P2SEL.x P2MAPx CBPD.x
Setting P2SEL.x together with P2MAPx PM_ANALOG disables output driver well input Schmitt trigger. Setting CBPD.x disables output driver well input Schmitt trigger prevent parasitic cross currents when applying analog signals. Selecting input comparator multiplexer with bits automatically disables output driver input buffer that pin, regardless state associated CBPD.x bit. Submit Documentation Feedback
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Port (P2.0 P2.7) Functions (continued)
NAME (P2.x) FUNCTION Mapped secondary digital function (not available CC430F612x) P2.2/P2MAP2/CB2 (/A2) P2.2 (I/O) Mapped secondary digital function (not available CC430F612x) P2.3/P2MAP3/CB3 (/A3) P2.3 (I/O) Mapped secondary digital function (not available CC430F612x) P2.4/P2MAP4/CB4 (/A4/VREF-/VeREF-) P2.4 (I/O) Mapped secondary digital function A4/VREF-/VeREF- (not available CC430F612x) P2.5/P2MAP5/CB5 (/A5/VREF+/VeREF+) P2.5 (I/O) Mapped secondary digital function A5/VREF+/VeREF+ (not available CC430F612x) P2.6/P2MAP6(/CB6) (/A6) P2.6 (I/O) Mapped secondary digital function (not available CC430F612x CC430F513x) (not available CC430F513x) P2.7/P2MAP7(/CB7) (/A7) P2.7 (I/O) Mapped secondary digital function (not available CC430F612x CC430F513x) (not available CC430F513x)
CONTROL BITS/SIGNALS P2DIR.x P2SEL.x P2MAPx CBPD.x
Setting P2SEL.x together with P2MAPx PM_ANALOG disables output driver well input Schmitt trigger. Setting CBPD.x disables output driver well input Schmitt trigger prevent parasitic cross currents when applying analog signals. Selecting input comparator multiplexer with bits automatically disables output driver input buffer that pin, regardless state associated CBPD.x bit.
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Port P3.0 P3.7 Input/Output With Schmitt Trigger
S10.S17 (n/a CC430F513x) LCDS10.LCDS17 Logic P3REN.x P3MAP PMAP_ANALOG DVSS DVCC P3DIR.x from Port Mapping Direction Input Output
P3OUT.x from Port Mapping P3SEL.x P3IN.x
P3DS.x drive High drive Keeper P3.0/P3MAP0(/S10) P3.1/P3MAP1(/S11) P3.2/P3MAP2(/S12) P3.3/P3MAP3(/S13) P3.4/P3MAP4(/S14) P3.5/P3MAP5(/S15) P3.6/P3MAP6(/S16) P3.7/P3MAP7(/S17)
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Port Mapping
CC430F513x devices don't provide functionality port pins.
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Port (P3.0 P3.7) Functions
CONTROL BITS/SIGNALS NAME (P3.x) P3.0/P3MAP0/S10 P3.0 (I/O) Mapped secondary digital function Output driver input Schmitt trigger disabled (not available CC430F513x) P3.1/P3MAP1/S11 P3.1 (I/O) Mapped secondary digital function Output driver input Schmitt trigger disabled (not available CC430F513x) P3.2/P3MAP7/S12 P3.2 (I/O) Mapped secondary digital function Output driver input Schmitt trigger disabled (not available CC430F513x) P3.3/P3MAP3/S13 P3.3 (I/O) Mapped secondary digital function Output driver input Schmitt trigger disabled (not available CC430F513x) P3.4/P3MAP4/S14 P3.4 (I/O) Mapped secondary digital function Output driver input Schmitt trigger disabled (not available CC430F513x) P3.5/P3MAP5/S15 P3.5 (I/O) Mapped secondary digital function Output driver input Schmitt trigger disabled (not available CC430F513x) P3.6/P3MAP6/S16 P3.6 (I/O) Mapped secondary digital function Output driver input Schmitt trigger disabled (not available CC430F513x) P3.7/P3MAP7/S17 P3.7 (I/O) Mapped secondary digital function Output driver input Schmitt trigger disabled (not available CC430F513x) LCDSx available CC430F513x. FUNCTION P3DIR.x P3SEL.x P3MAPx LCDS10.
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Port P4.0 P4.7 Input/Output With Schmitt Trigger (CC430F613x CC430F612x only)
S2.S9 LCDS2.LCDS9 Logic P4REN.x DVSS DVCC P4DIR.x Direction Input Output
P4OUT.x DVSS P4SEL.x P4IN.x
P4DS.x drive High drive Keeper P4.0/S2 P4.1/S3 P4.2/S4 P4.3/S5 P4.4/S6 P4.5/S7 P4.6/S8 P4.7/S9
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Used
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Port (P4.0 P4.7) Functions (CC430F613x CC430F612x only)
NAME (P4.x) P4.0/P4MAP0/S2 P4.0 (I/O) DVSS P4.1/P4MAP1/S3 P4.1 (I/O) DVSS P4.2/P4MAP7/S4 P4.2 (I/O) DVSS P4.3/P4MAP3/S5 P4.3 (I/O) DVSS P4.4/P4MAP4/S6 P4.4 (I/O) DVSS P4.5/P4MAP5/S7 P4.5 (I/O) DVSS P4.6/P4MAP6/S8 P4.6 (I/O) DVSS P4.7/P4MAP7/S9 P4.7 (I/O) DVSS FUNCTION CONTROL BITS/SIGNALS P4DIR.x P4SEL.x LCDS2.7
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Port P5.0, Input/Output With Schmitt Trigger
Logic
P5REN.0
DVSS DVCC P5DIR.0
P5OUT.0
P5DS.x drive High drive Keeper P5.0/XIN
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Module P5SEL.0 P5IN.0
Module
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ECCN 5E002 TSPA Technology Software Publicly Available.
CC430F613x CC430F612x CC430F513x
www.ti.com SLAS554 2009
Port P5.1, Input/Output With Schmitt Trigger
Logic
P5REN.1
DVSS DVCC P5DIR.1
P5OUT.1 Module P5SEL.0 XT1BYPASS P5IN.1
P5DS.x drive High drive Keeper P5.1/XOUT
Module
Port (P5.0 P5.1) Functions
NAME (P5.x) P5.0/XIN P5.0 (I/O) crystal mode bypass mode P5.1/XOUT P5.1 (I/O) XOUT crystal mode P5.1 (I/O) FUNCTION CONTROL BITS/SIGNALS P5DIR.x P5SEL.0 P5SEL.1 XT1BYPASS
Don't care Setting P5SEL.0 causes general-purpose disabled. Pending setting XT1BYPASS, P5.0 configured crystal mode bypass mode. Setting P5SEL.0 causes general-purpose disabled crystal mode. When using bypass mode, P5.1 used general-purpose I/O.
Copyright 2009, Texas Instruments Incorporated
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CC430F613x CC430F612x CC430F513x
ECCN 5E002 TSPA Technology Software Publicly Available.
SLAS554 2009 www.ti.com
Port P5.2 P5.4, Input/Output With Schmitt Trigger (CC430F613x CC430F612x only)
S0(P5.2)/S1(P5.3)/S23(P5.4) Logic P5REN.x
DVSS DVCC P5DIR.x
P5OUT.x Module P5SEL.x P5IN.x
P5DS.x drive High drive Keeper P5.2/S0 P5.3/S1 P5.4/S23
PRODUCT PREVIEW
Module
Port (P5.2 P5.3) Functions (CC430F613x CC430F612x only)
NAME (P5.x) P5.2/S0 P5.2 (I/O) DVSS P5.3/S1 P5.3 (I/O) DVSS FUNCTION CONTROL BITS/SIGNALS P5DIR.x P5SEL.x LCDS0.1
Port (P5.4) Functions (CC430F613x CC430F612x only)
NAME (P5.x) P5.4/S23 P5.4 (I/O) DVSS FUNCTION CONTROL BITS/SIGNALS P5DIR.x P5SEL.x LCDS23
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Copyright 2009, Texas Instruments Incorporated
ECCN 5E002 TSPA Technology Software Publicly Available.
CC430F613x CC430F612x CC430F513x
www.ti.com SLAS554 2009
Port P5.5 P5.7, Input/Output With Schmitt Trigger (CC430F613x CC430F612x only)
S24(P5.5)/S25(P5.6)/S26(P5.7)
Logic P5REN.x
DVSS DVCC P5DIR.x
P5OUT.x P5DS.x drive High drive Keeper P5.5/COM3/S24 P5.6/COM2/S25 P5.7/COM1/S26
P5SEL.x P5IN.x
Port (P5.5 P5.7) Functions (CC430F613x CC430F612x only)
NAME (P5.x) P5.5/COM3/S24 P5.5 (I/O) COM3 P5.6/COM2/S25 P5.6 (I/O) COM2 P5.7/COM1/S26 P5.7 (I/O) COM1 Setting P5SEL.x disables output driver well input Schmitt trigger. FUNCTION CONTROL BITS/SIGNALS P5DIR.x P5SEL.x LCDS24.26
Copyright 2009, Texas Instruments Incorporated
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CC430F613x CC430F612x CC430F513x
ECCN 5E002 TSPA Technology Software Publicly Available.
SLAS554 2009 www.ti.com
Port JTAG TDO, Input/Output With Schmitt Trigger Output
PJREN.0 Logic
DVSS DVCC PJDIR.0 DVCC
PJOUT.0 From JTAG From JTAG PJIN.0
PJDS.0 drive High drive PJ.0/TDO
PRODUCT PREVIEW
Port JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger Output
PJREN.x Logic
DVSS DVCC PJDIR.x DVSS
PJOUT.x From JTAG From JTAG PJIN.x
PJDS.x drive High drive PJ.1/TDI/TCLK PJ.2/TMS PJ.3/TCK
JTAG
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Copyright 2009, Texas Instruments Incorporated
ECCN 5E002 TSPA Technology Software Publicly Available.
CC430F613x CC430F612x CC430F513x
www.ti.com SLAS554 2009
Port (PJ.0 PJ.3) Functions
NAME (PJ.x) PJ.0/TDO PJ.1/TDI/TCLK PJ.2/TMS PJ.3/TCK PJ.0 (I/O) PJ.1 (I/O)
FUNCTION
CONTROL BITS/ SIGNALS PJDIR.x
TDI/TCLK PJ.2 (I/O) PJ.3 (I/O) Don't care Default condition direction controlled JTAG module. JTAG mode, pullups activated automatically TMS, TCK, TDI/TCLK. PJREN.x care.
Copyright 2009, Texas Instruments Incorporated
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PRODUCT PREVIEW
CC430F613x CC430F612x CC430F513x
ECCN 5E002 TSPA Technology Software Publicly Available.
SLAS554 2009 www.ti.com
(Device Descriptor) Structures
Table lists content device descriptor tag-length-value (TLV) structure CC430F613x CC430F613x device types. Table lists content device descriptor tag-length-value (TLV) structure CC430F612x device types. Table Device Descriptor Table
Description Info Block Info length length value Device Device Hardware revision Firmware revision Record Record Record length Lot/Wafer position position Test results ADC12 Calibration ADC12 Calibration ADC12 Calibration length Gain Factor Offset 1.5V Reference Temp. Sensor 30°C 1.5V Reference Temp. Sensor 85°C 2.0V Reference Temp. Sensor 30°C 2.0V Reference Temp. Sensor 85°C 2.5V Reference Temp. Sensor 30°C 2.5V Reference Temp. Sensor 85°C Calibration Calibration Calibration length Address 01A00h 01A01h 01A02h 01A04h 01A05h 01A06h 01A07h 01A08h 01A09h 01A0Ah 01A0Eh 01A10h 01A12h 01A14h 01A15h 01A16h 01A18h 01A1Ah Size bytes 'F6137 Value unit unit unit unit unit unit unit unit 'F6135 Value unit unit unit unit unit unit unit unit 'F5137 Value unit unit unit unit unit unit unit unit 'F5135 Value unit unit unit unit unit unit unit unit 'F5133 Value unit unit unit unit unit unit unit unit
PRODUCT PREVIEW
01A1Ch
unit
unit
unit
unit
unit
01A1Eh
unit
unit
unit
unit
unit
01A20h
unit
unit
unit
unit
unit
01A22h
unit
unit
unit
unit
unit
01A24h
unit
unit
unit
unit
unit
01A26h 01A27h
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Copyright 2009, Texas Instruments Incorporated
ECCN 5E002 TSPA Technology Software Publicly Available.
CC430F613x CC430F612x CC430F513x
www.ti.com SLAS554 2009
Table Device Descriptor Table (continued)
Description 1.5V Reference Factor 2.0V Reference Factor 2.5V Reference Factor Peripheral Descriptor (PD) Peripheral Descriptor Peripheral Descriptor Length Peripheral Descriptors Address 01A28h 01A2Ah 01A2Ch 01A2Eh 01A2Fh 01A30h Size bytes Length 'F6137 Value unit unit unit 'F6135 Value unit unit unit 'F5137 Value unit unit unit 'F5135 Value unit unit unit 'F5133 Value unit unit unit
Table Device Descriptor Table CC430F612x
Description Info Block Info length length value Device Device Hardware revision Firmware revision Record Record Record length Lot/Wafer position position Test results Empty Descriptor Empty Empty Length Calibration Calibration Calibration length 1.5V Reference Factor 2.0V Reference Factor 2.5V Reference Factor Peripheral Descriptor (PD) Peripheral Descriptor Peripheral Descriptor Length Peripheral Descriptors Address 01A00h 01A01h 01A02h 01A04h 01A05h 01A06h 01A07h 01A08h 01A09h 01A0Ah 01A0Eh 01A10h 01A12h 01A14h 01A15h 01A16h 01A26h 01A27h 01A28h 01A2Ah 01A2Ch 01A2Eh 01A2Fh 01A30h Size bytes Length 'F6127 Value unit unit unit unit unit bytes 0FFh unit unit unit 'F6126 Value unit unit unit unit unit bytes 0FFh unit unit unit 'F6125 Value unit unit unit unit unit bytes 0FFh unit unit unit
Copyright 2009, Texas Instruments Incorporated
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PRODUCT PREVIEW
CC430F613x CC430F612x CC430F513x
ECCN 5E002 TSPA Technology Software Publicly Available.
SLAS554 2009 www.ti.com
Data Sheet Revision History
REVISION SLAS554 DESCRIPTION Product Preview data sheet release
PRODUCT PREVIEW
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Copyright 2009, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 16-Nov-2009
PACKAGING INFORMATION
Orderable Device CC430F5133IRGZ CC430F5135IRGZ CC430F5137IRGZ CC430F6137IRGC
Status ACTIVE ACTIVE ACTIVE PREVIEW
Package Type VQFN
Package Drawing
Pins Package Plan 1000 Green (RoHS Sb/Br) 1000 Green (RoHS Sb/Br) 1000 Green (RoHS Sb/Br)
Lead/Ball Finish NIPDAU NIPDAU NIPDAU Call
Peak Temp Level-3-260C-168 Level-3-260C-168 Level-3-260C-168 Call
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
IMPORTANT NOTICE
Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. Customers responsible their products applications using components. minimize risks associated with customer products applications, customers should provide adequate design operating safeguards. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right relating combination, machine, process which products services used. Information published regarding third-party products services does constitute license from such products services warranty endorsement thereof. such information require license from third party under patents other intellectual property third party, license from under patents other intellectual property Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations, notices. Reproduction this information with alteration unfair deceptive business practice. responsible liable such altered documentation. Information third parties subject additional restrictions. Resale products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service unfair deceptive business practice. responsible liable such statements. products authorized safety-critical applications (such life support) where failure product would reasonably expected cause severe personal injury death, unless officers parties have executed agreement specifically governing such use. Buyers represent that they have necessary expertise safety regulatory ramifications their applications, acknowledge agree that they solely responsible legal, regulatory safety-related requirements concerning their products products such safety-critical applications, notwithstanding applications-related information support that provided Further, Buyers must fully indemnify representatives against damages arising products such safety-critical applications. products neither designed intended military/aerospace applications environments unless products specifically designated military-grade "enhanced plastic." Only products designated military-grade meet military specifications. Buyers acknowledge agree that such products which designated military-grade solely Buyer's risk, that they solely responsible compliance with legal regulatory requirements connection with such use. products neither designed intended automotive applications environments unless specific products designated compliant with ISO/TS 16949 requirements. Buyers acknowledge agree that, they non-designated products automotive applications, will responsible failure meet such requirements. Following URLs where obtain information other Texas Instruments products application solutions: Products Amplifiers Data Converters DLP® Products Clocks Timers Interface Logic Power Mgmt Microcontrollers RFID RF/IF ZigBee® Solutions amplifier.ti.com dataconverter.ti.com www.dlp.com dsp.ti.com www.ti.com/clocks interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com www.ti-rfid.com www.ti.com/lprf Applications Audio Automotive Broadband Digital Control Medical Military Optical Networking Security Telephony Video Imaging Wireless www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/medical www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless
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