PIC24FJ64GA004 Family Rev. Silicon Errata PIC24FJ64GA004 Family p
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PIC24FJ64GA004 FAMILY
PIC24FJ64GA004 Family Rev. Silicon Errata
PIC24FJ64GA004 Family parts have received conform functionally Device Data Sheet (DS39881C), except anomalies described below. Data Sheet Clarification issues related PIC24FJ64GA004 Family will reported separate. Data Sheet errata. Please check Microchip site existing issues. following silicon errata apply only PIC24FJ64GA family devices with these Device/ Revision IDs: Part Number PIC24FJ16GA002 PIC24FJ32GA002 PIC24FJ48GA002 PIC24FJ64GA002 PIC24FJ16GA004 PIC24FJ32GA004 PIC24FJ48GA004 PIC24FJ64GA004 Device 00444h 00445h 00446h 00447h 0044Ch 0044Dh 0044Eh 0044Fh Revision 3042h 3042h 3042h 3042h 3042h 3042h 3042h 3042h
Module: Memory (Program Space Visibility)
When accessing data area data RAM, possible generate false address error trap condition reading data located precisely lower address boundary (8000h). data read using instruction with autodecrement, resulting address will below boundary (i.e., 7FFEh); this will result address error trap. This false address error also occur 32-bit instruction used read data location 8000h. Work around first location page (address 8000h). MPLAB® Compiler (v3.11 later) supports option, -merrata=psv_trap, prevent from generating code that would cause this erratum. Date Codes that pertain this issue: engineering production devices.
Module: Core (BOR)
When on-chip regulator enabled (DISVREG tied VSS), event spontaneously occur under following circumstances: less than 2.5V, internal band reference being used reference with converter (AD1PCFG<15> Work around select internal band reference converter when on-chip regulator Tracking mode (LVDIF (IFS4<8>) Date Codes that pertain this issue: engineering production devices.
Module: RTCC
Under certain circumstances, value Alarm Repeat Counter (ALCFGRPT<7:0>) unexpectedly decremented. This happens only when byte write upper byte ALCFGRPT performed interval between device POR/ first edge from RTCC clock source. Work around perform byte writes ALCFGRPT, particularly upper byte. Alternatively, wait until period SOSC completed before performing byte writes ALCFGRPT. Date Codes that pertain this issue: engineering production devices.
2009 Microchip Technology Inc.
DS80384B-page
PIC24FJ64GA004 FAMILY
Module: I2C(Master Mode)
Under certain circumstances, module operating Master mode Acknowledge command addressed slave device. This happens when following occurs: 10-Bit Addressing mode used (A10M master same upper address bits (I2CADD<9:8>) addressed slave module. these cases, master also Acknowledges address command generates erroneous slave interrupt, well master interrupt. Work around Several options available: When using 10-Bit Addressing mode, make certain that master slave devices share same MSbs their addresses. this cannot avoided: Clear A10M (I2CxCON<10> prior performing Master mode transmit. Read ADD10 (I2CxSTAT<8>) check full 10-bit match whenever slave interrupt occurs master module. Date Codes that pertain this issue: engineering production devices.
Module: UART
When UART operating using Stop bits (STSEL sample first Stop instead second one. device being communicated with using Stop communications, this lead framing errors. Work around None. Date Codes that pertain this issue: engineering production devices.
Module: UART (UERIF Interrupt)
UART error interrupt occur, occur incorrect time, multiple errors occur during short period time. Work around Read error flags UxSTA register whenever byte received verify error status. most cases, these bits will correct, even UART error interrupt fails occur. possible exceptions, refer Errata Date Codes that pertain this issue: engineering production devices.
Module: UART (FIFO Error Flags)
Under certain circumstances, PERR FERR error bits correct bytes receive FIFO. This only been observed when both following conditions met: UART receive interrupt occur when FIFO full full (UxSTA<7:6> 1x), more than bytes with error received. these cases, only first bytes, with parity framing error, will have corresponding bits indicate correctly. error bits will after this. Work around None. Date Codes that pertain this issue: engineering production devices.
Module: (Slave Mode)
Under certain circumstances, module operating Slave mode respond correctly some special addresses reserved protocol. This happens when following occurs: 10-Bit Addressing mode used (A10M bits, A<7:1>, slave address (I2CADD<7:1>) fall into range reserved 7-bit address ranges `1111xxx' `0000xxx'. these cases, slave module Acknowledges command triggers slave interrupt; does copy data into I2CxRCV register bit. Work around bits, A<7:1>, module's slave address equal `1111xxx' `0000xxx'. Date Codes that pertain this issue: engineering production devices.
DS80384B-page
2009 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
Module: Core (Code Protection)
When General Segment Code Protection been enabled (GCP Configuration programmed), applications unable write first bytes program memory space (0000h through 0200h). applications that require interrupt vectors changed during time, such bootloaders, modifications Interrupt Vector Tables (IVTs) will possible. Work around Create Interrupt Vector Tables, each AIVT, area program space beyond affected region. addresses vector tables tables. These tables then modified needed actual addresses ISRs. Date Codes that pertain this issue: engineering production devices.
2009 Microchip Technology Inc.
DS80384B-page
PIC24FJ64GA004 FAMILY
REVISION HISTORY
Document (7/2008) First version this document. Silicon issues (Core BOR), (Memory Program Space Visibility), (RTCC), (I2C Master Mode), (I2C Slave Mode) (UART). Document (2/2009) Added silicon issue (Core Code Protection).
DS80384B-page
2009 Microchip Technology Inc.
Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
Code protection constantly evolving. Microchip committed continuously improving code protection features products. Attempts break Microchip's code protection feature violation Digital Millennium Copyright Act. such acts allow unauthorized access your software other copyrighted work, have right relief under that Act.
Information contained this publication regarding device applications like provided only your convenience superseded updates. your responsibility ensure that your application meets with your specifications. MICROCHIP MAKES REPRESENTATIONS WARRANTIES KIND WHETHER EXPRESS IMPLIED, WRITTEN ORAL, STATUTORY OTHERWISE, RELATED INFORMATION, INCLUDING LIMITED CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY FITNESS PURPOSE. Microchip disclaims liability arising from this information use. Microchip devices life support and/or safety applications entirely buyer's risk, buyer agrees defend, indemnify hold harmless Microchip from damages, claims, suits, expenses resulting from such use. licenses conveyed, implicitly otherwise, under Microchip intellectual property rights.
Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt UNI/O registered trademarks Microchip Technology Incorporated U.S.A. other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2009, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
2009 Microchip Technology Inc.
DS80384B-page
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02/04/09
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2009 Microchip Technology Inc.
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