www.ti.com SCLS041H DECEMBER 1982 REVISED NOVEMBER 2009 8-BIT SHI
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SN54HC595 SN74HC595
www.ti.com SCLS041H DECEMBER 1982 REVISED NOVEMBER 2009
8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
Check Samples: SN54HC595 SN74HC595
FEATURES
8-Bit Serial-In, Parallel-Out Shift Wide Operating Voltage Range High-Current 3-State Outputs Drive LSTTL Loads Power Consumption: 80-A (Max) (Typ) ±6-mA Output Drive Input Current: (Max) Shift Register Direct Clear
SN54HC595.J PACKAGE SN74HC595.D, PACKAGE (TOP VIEW)
RCLK SRCLK SRCLR
DESCRIPTION
'HC595 devices contain 8-bit serial-in, parallel-out shift register that feeds 8-bit D-type storage register. storage register parallel 3-state outputs. Separate clocks provided both shift storage register. shift register direct overriding clear (SRCLR) input, serial (SER) input, serial outputs cascading. When output-enable (OE) input high, outputs high-impedance state. Both shift register clock (SRCLK) storage register clock (RCLK) positive-edge triggered. both clocks connected together, shift register always clock pulse ahead storage register.
SN54HC595.FK PACKAGE (TOP VIEW)
RCLK SRCLK
internal connection
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 1982-2009, Texas Instruments Incorporated
SRCLR
SN54HC595 SN74HC595
SCLS041H DECEMBER 1982 REVISED NOVEMBER 2009 www.ti.com
ORDERING INFORMATION
PDIP SOIC PACKAGE
ORDERABLE PART NUMBER SN74HC595N SN74HC595D SN74HC595DR SN74HC595DT SN74HC595DW SN74HC595DWR SN74HC595NSR SN74HC595DBR SN74HC595PW SN74HC595PWR SNJ54HC595J SNJ54HC595W SNJ54HC595FK
TOP-SIDE MARKING SN74HC595N HC595
Tube Tube Reel 2500 Reel Tube Reel 2000 Reel 2000 Reel 2000 Tube Reel 2000 Tube Tube Tube
-40°C 85°C
SOIC SSOP TSSOP CDIP
HC595 HC595 HC595 HC595 SNJ54HC595J SNJ54HC595W SNJ54HC595FK
-55°C 125°C
LCCC
most current package ordering information, Package Option Addendum this document, site www.ti.com. Package drawings, thermal data, symbolization available www.ti.com/packaging.
Table FUNCTION TABLE
INPUTS SRCLK SRCLR RCLK FUNCTION Outputs QA-QH disabled. Outputs QA-QH enabled. Shift register cleared. First stage shift register goes low. Other stages store data previous stage, respectively. First stage shift register goes high. Other stages store data previous stage, respectively. Shift-register data stored storage register.
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Copyright 1982-2009, Texas Instruments Incorporated
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SN54HC595 SN74HC595
www.ti.com SCLS041H DECEMBER 1982 REVISED NOVEMBER 2009
LOGIC DIAGRAM (POSITIVE LOGIC)
RCLK SRCLR SRCLK
numbers shown packages.
Copyright 1982-2009, Texas Instruments Incorporated
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SCLS041H DECEMBER 1982 REVISED NOVEMBER 2009 www.ti.com
TIMING DIAGRAM
SRCLK
RCLK
SRCLR
NOTE: implies that output 3-State mode.
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Copyright 1982-2009, Texas Instruments Incorporated
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www.ti.com SCLS041H DECEMBER 1982 REVISED NOVEMBER 2009
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Supply voltage range Input clamp current Output clamp current
-0.5 package package package package package package 73°C/W 82°C/W 57°C/W 67°C/W 64°C/W 108°C/W -65°C 150°C
Continuous output current Continuous current through
Package thermal impedance
Tstg
Storage temperature range
Stresses beyond those listed under absolute maximum ratings cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under recommended operating conditions implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. input output voltage ratings exceeded input output current ratings observed. package thermal impedance calculated accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS
SN54HC595 Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage Input transition rise/fall time Operating free-air temperature 3.15 1.35 1000 SN74HC595 3.15 1.35 1000 UNIT
unused inputs device must held ensure proper device operation. application report, Implications Slow Floating CMOS Inputs, literature number SCBA004. this device used threshold region (from VILmax VIHmin there potential into wrong state from induced grounding, causing double clocking. Operating with inputs 1000 does damage device; however, functionally, inputs ensured while shift, count, toggle operating modes.
Copyright 1982-2009, Texas Instruments Incorporated
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SCLS041H DECEMBER 1982 REVISED NOVEMBER 2009 www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS QA-QH, -5.2 QA-QH, -7.8 QA-QH, QA-QH, QA-QH 25°C 3.98 3.98 5.48 5.48 1.998 4.499 5.999 0.002 0.001 0.001 0.17 0.17 0.15 0.15 ±0.1 ±0.01 0.26 0.26 0.26 0.26 ±100 ±0.5 SN54HC595 ±1000 SN74HC595 3.84 3.84 5.34 5.34 0.33 0.33 0.33 0.33 ±1000 UNIT
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TIMING REQUIREMENTS
over operating free-air temperature range (unless otherwise noted)
fclock Clock frequency SRCLK RCLK high Pulse duration SRCLR before SRCLK SRCLK before RCLK Setup time SRCLR before RCLK SRCLR high (inactive) before SRCLK Hold time, after SRCLK 25°C SN54HC595 SN74HC595 UNIT
This setup time allows storage register receive stable data from shift register. clocks tied together, which case shift register clock pulse ahead storage register.
Copyright 1982-2009, Texas Instruments Incorporated
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SCLS041H DECEMBER 1982 REVISED NOVEMBER 2009 www.ti.com
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, (unless otherwise noted)
PARAMETER FROM (INPUT) (OUTPUT) fmax SRCLK RCLK QA-QH tPHL SRCLR QA-QH tdis QA-QH QA-QH 25°C SN54HC595 SN74HC595 UNIT
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, (unless otherwise noted)
PARAMETER FROM (INPUT) (OUTPUT) RCLK QA-QH QA-QH QA-QH 25°C SN54HC595 SN74HC595 UNIT
OPERATING CHARACTERISTICS
25°C
PARAMETER Power dissipation capacitance TEST CONDITIONS load UNIT
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www.ti.com SCLS041H DECEMBER 1982 REVISED NOVEMBER 2009
PARAMETER MEASUREMENT INFORMATION
PARAMETER tPZH tPZL tPHZ tPLZ Open Closed Open Closed Open Closed Open Closed Open Open
From Output Under Test (see Note
Test Point
tdis
LOAD CIRCUIT
High-Level Pulse
VOLTAGE WAVEFORMS PULSE DURATIONS
Reference Input Data Input
Low-Level Pulse
VOLTAGE WAVEFORMS SETUP HOLD INPUT RISE FALL TIMES Output Control (Low-Level Enabling) tPZL Output Waveform (See Note tPZH Output Waveform (See Note tPHZ
Input
tPLH tPHL tPHL tPLH
tPLZ
In-Phase Output
Out-ofPhase Output
VOLTAGE WAVEFORMS PROPAGATION DELAY OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES 3-STATE OUTPUTS
NOTES: includes probe test-fixture capacitance. Waveform output with internal conditions such that output low, except when disabled output control. Waveform output with internal conditions such that output high, except when disabled output control. Phase relationships between waveforms were chosen arbitrarily. input pulses supplied generators having following characteristics: MHz, clock inputs, fmax measured when input duty cycle 50%. outputs measured time, with input transition measurement. tPHZ same tdis. tPZL tPZH same ten. tPLH tPHL same tpd.
Figure Load Circuit Voltage Waveforms
Copyright 1982-2009, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
PACKAGING INFORMATION
Orderable Device 5962-86816012A 5962-8681601EA 5962-8681601VEA 5962-8681601VFA SN54HC595J SN74HC595D SN74HC595DBR SN74HC595DBRE4 SN74HC595DBRG4 SN74HC595DE4 SN74HC595DG4 SN74HC595DR SN74HC595DRE4 SN74HC595DRG4 SN74HC595DT SN74HC595DTE4 SN74HC595DTG4 SN74HC595DW SN74HC595DWE4 SN74HC595DWG4 SN74HC595DWR SN74HC595DWRE4 SN74HC595DWRG4 SN74HC595N SN74HC595NE4 SN74HC595NSR SN74HC595NSRE4 Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type LCCC CDIP CDIP CDIP SOIC SSOP SSOP SSOP SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC PDIP PDIP Package Drawing Pins Package Plan Green (RoHS Sb/Br) Lead/Ball Finish Peak Temp
POST-PLATE Type NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU Type Type Type Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Type Type Level-1-260C-UNLIM Level-1-260C-UNLIM
2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) Pb-Free (RoHS) Pb-Free (RoHS)
2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br)
Addendum-Page
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Orderable Device SN74HC595NSRG4 SN74HC595PW SN74HC595PWE4 SN74HC595PWG4 SN74HC595PWR SN74HC595PWRE4 SN74HC595PWRG4 SNJ54HC595FK SNJ54HC595J SNJ54HC595W
Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE
Package Type TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP LCCC CDIP
Package Drawing
Pins Package Plan 2000 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
Lead/Ball Finish NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU
Peak Temp Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM
2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br)
POST-PLATE Type Call Type Call
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Oct-2009
TAPE REEL INFORMATION
*All dimensions nominal
Device
Package Package Pins Type Drawing SSOP SOIC SOIC SOIC TSSOP
Reel Reel Diameter Width (mm) (mm) (mm) 330.0 330.0 330.0 330.0 330.0 330.0 16.4 16.4 16.4 16.4 16.4 12.4 10.75
(mm) 10.3 10.3 10.7 10.5
(mm)
(mm) 12.0 12.0 12.0
Pin1 (mm) Quadrant 16.0 16.0 16.0 16.0 16.0 12.0
SN74HC595DBR SN74HC595DR SN74HC595DR SN74HC595DWR SN74HC595NSR SN74HC595PWR
2000 2500 2500 2000 2000 2000
Pack Materials-Page
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Oct-2009
*All dimensions nominal
Device SN74HC595DBR SN74HC595DR SN74HC595DR SN74HC595DWR SN74HC595NSR SN74HC595PWR
Package Type SSOP SOIC SOIC SOIC TSSOP
Package Drawing
Pins
2000 2500 2500 2000 2000 2000
Length (mm) 346.0 333.2 346.0 346.0 346.0 346.0
Width (mm) 346.0 345.9 346.0 346.0 346.0 346.0
Height (mm) 33.0 28.6 33.0 33.0 33.0 29.0
Pack Materials-Page
MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
(R-PDSO-G**)
PINS SHOWN 0,65 0,38 0,22 0,15
PLASTIC SMALL-OUTLINE
0,25 0,09 5,60 5,00 8,20 7,40
Gage Plane 0,25 0,95 0,55
Seating Plane 2,00 0,05 0,10
PINS
6,50
6,50
7,50
8,50
10,50
10,50
12,90
5,90
5,90
6,90
7,90
9,90
9,90
12,30 4040065 12/01
NOTES:
linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-150
POST OFFICE 655303
DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B OCTOBER 1996
(S-CQCC-N**)
TERMINAL SHOWN
LEADLESS CERAMIC CHIP CARRIER
TERMINALS
0.342 (8,69) 0.442 (11,23) 0.640 (16,26) 0.739 (18,78) 0.938 (23,83) 1.141 (28,99) 0.358 (9,09) 0.458 (11,63) 0.660 (16,76) 0.761 (19,32) 0.962 (24,43) 1.165 (29,59) 0.307 (7,80) 0.406 (10,31) 0.495 (12,58) 0.495 (12,58) 0.850 (21,6) 1.047 (26,6)
0.358 (9,09) 0.458 (11,63) 0.560 (14,22) 0.560 (14,22) 0.858 (21,8) 1.063 (27,0)
0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25)
0.020 (0,51) 0.010 (0,25)
0.055 (1,40) 0.045 (1,14)
0.045 (1,14) 0.035 (0,89)
0.028 (0,71) 0.022 (0,54) 0.050 (1,27)
0.045 (1,14) 0.035 (0,89)
4040140 10/96 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. This package hermetically sealed with metal lid. terminals gold plated. Falls within JEDEC MS-004
POST OFFICE 655303
DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
(R-PDSO-G**)
PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,30 0,19
0,10
0,15 4,50 4,30 6,60 6,20 Gage Plane 0,25 0,75 0,50
Seating Plane 1,20 0,15 0,05 0,10
PINS
3,10
5,10
5,10
6,60
7,90
9,80
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-153
POST OFFICE 655303
DALLAS, TEXAS 75265
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