Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Ou

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Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Ou

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19-4910; 10/09
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Outputs
MAX3638 highly flexible, precision phaselocked loop (PLL) clock generator optimized next generation network equipment that demands low-jitter clock generation distribution robust high-speed data transmission. device features subpicosecond jitter generation, excellent power-supply noise rejection, pin-programmable LVDS/LVPECL output interfaces. MAX3638 provides nine differential outputs LVCMOS output, divided into three banks. frequency output interface each output bank individually programmed, making this device ideal replacement multiple crystal oscillators clock distribution system board, saving cost space. This 3.3V available 7mm, 48-pin TQFN package operates from -40°C +85°C.
Inputs
TION EVALUA
Features
Crystal Interface: 18MHz 33.5MHz LVCMOS Input: 15MHz 160MHz Differential Input: 15MHz 350MHz Outputs LVCMOS Output: 160MHz LVPECL/LVDS Outputs: 800MHz Three Individual Output Banks Pin-Programmable Dividers Pin-Programmable Output Interface Wide Tuning Range (3.83GHz 4.025GHz) Phase Jitter 0.34psRMS (12kHz 20MHz) 0.14psRMS (1.875MHz 20MHz) Excellent Power-Supply Noise Rejection -40NC +85NC Operating Temperature Range +3.3V Supply
MAX3638
Applications
Ethernet Switch/Router Wireless Base Station PCIeM, Network Processors DDR/QDR Memory
Typical Application Circuits Configuration appear data sheet.
Ordering Information
PART MAX3638ETM+ TEMP RANGE -40NC +85NC PIN-PACKAGE TQFN-EP*
+Denotes lead(Pb)-free/RoHS-compliant package. Exposed pad.
Functional Diagram
LVPECL/LVDS
MAX3638
LVPECL/LVDS
LVPECL/LVDS XOUT LVCMOS PLL, DIVIDERS, MUXES LVPECL/LVDS LVPECL/LVDS
LVPECL/LVDS
LVPECL/LVDS LVPECL/LVDS
LVPECL/LVDS
LVCMOS
PCIe registered trademark PCI-SIG Corp.
Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim Direct 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Outputs MAX3638
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range (VCC, VCCA, VCCQA, VCCQB, VCCQC, VCCQCC) .-0.3V +4.0V Voltage Range CIN, IN_SEL, DF[1:0], PLL_BP, DA[1:0], DB[1:0], DC[1:0], QA_CTRL1, QA_CTRL2, QB_CTRL, QC_CTRL, QCC, -0.3V (VCC 0.3V) Voltage Range DIN, (VCC 2.35V) (VCC 0.35V) Voltage Range QA[4:0], QA[4:0], QB[2:0], QB[2:0], when LVDS Output -0.3V (VCC 0.3V) Current into QA[4:0], QA[4:0], QB[2:0], QB[2:0], when LVPECL Output -56mA Current into QCC. Q50mA Voltage Range .-0.3V +1.2V Voltage Range XOUT .-0.3V (VCC 0.6V) Continuous Power Dissipation +70NC) 48-Pin TQFN (derate 40mW/NC above +70NC) .3200mW Operating Junction Temperature Range -55NC +150NC Storage Temperature Range. -65NC +160NC
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC +3.0V +3.6V, -40°C +85°C. Typical values +3.3V, +25°C, unless otherwise noted. Signal applied DIN/DIN only when selected reference clock.) (Note PARAMETER Supply Current with Enabled (Note Supply Current with Bypassed (Note SYMBOL CONDITIONS Configured with LVPECL outputs Configured with LVDS outputs Configured with LVPECL outputs Configured with LVDS outputs UNITS
LVCMOS/LVTTL CONTROL INPUTS (IN_SEL, DF[1:0], DA[1:0], DB[1:0], DC[1:0], PLL_BP, QA_CTRL1, QA_CTRL2, QB_CTRL, QC_CTRL) Input High Voltage Input Voltage Input High Current Input Current Reference Clock Input Frequency Input Amplitude Range Input High Current Input Current Reference Clock Input DutyCycle Distortion Input Capacitance DIFFERENTIAL CLOCK INPUT (DIN, DIN) (Note Differential Input Frequency fREF Input Bias Voltage Input Differential Voltage Swing Single-Ended Voltage Range Input Differential Impedance Differential Input Capacitance VCMI 1800
LVCMOS/LVTTL CLOCK INPUT (CIN) fREF Internally AC-coupled (Note VP-P mVP-P
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VCC +3.0V +3.6V, -40°C +85°C. Typical values +3.3V, +25°C, unless otherwise noted. Signal applied DIN/DIN only when selected reference clock.) (Note PARAMETER SYMBOL CONDITIONS 1.475 0.925 1.125 Short together Short ground enabled bypassed (Note 1.13 1.85 80%, differential load 100I enabled bypassed (Note 0.98 1.70 -12mA 12mA (Note enabled bypassed (Note 0.83 1.55 UNITS LVDS OUTPUTS (QA[4:0], QA[4:0], QB[2:0], QB[2:0], (Note Output Frequency Output High Voltage Output Voltage Differential Output Voltage Change Magnitude Differential Output Complementary States Output Offset Voltage Change Magnitude Output Offset Voltage Complementary States Differential Output Impedance Output Current Output Current When Disabled Output Rise/Fall Time Output Duty-Cycle Distortion |VOD| D|VOD| D|VOS|
MAX3638
LVPECL OUTPUTS (QA[4:0], QA[4:0], QB[2:0], QB[2:0], (Note Output Frequency Output High Voltage Output Voltage Output-Voltage Swing (Single-Ended) Output Current When Disabled Output Rise/Fall Time Output Duty-Cycle Distortion LVCMOS/LVTTL OUTPUT (QCC) Output Frequency Output High Voltage Output Voltage Output Rise/Fall Time Output Duty-Cycle Distortion Output Impedance
VP-P
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Outputs MAX3638
ELECTRICAL CHARACTERISTICS (continued)
(VCC +3.0V +3.6V, -40°C +85°C. Typical values +3.3V, +25°C, unless otherwise noted. Signal applied DIN/DIN only when selected reference clock.) (Note PARAMETER SPECIFICATIONS Frequency Range Phase-Frequency Detector Compare Frequency Jitter Transfer Bandwidth 25MHz crystal input (Note 12kHz 20MHz 1.875MHz 20MHz fVCO fPFD 3830 0.34 0.14 0.34 -111 -113 -119 -136 -147 -117 -119 -125 -142 -151 -124 -125 -131 -147 -153 -126 -127 -133 -148 -152 dBc/ dBc/ dBc/ dBc/ psP-P psRMS 3932 4025 SYMBOL CONDITIONS UNITS
Integrated Phase Jitter
25MHz LVCMOS differential input (Notes (Note (Note LVPECL LVDS (Note (Note fOFFSET 1kHz fOFFSET 10kHz
Supply-Noise Induced Phase Spur LVPECL/LVDS Output Supply-Noise Induced Phase Spur LVCMOS Output Determinisitic Jitter Induced Power-Supply Noise Nonharmonic Subharmonic Spurs
Phase Noise 491.52MHz
fOFFSET 100kHz fOFFSET 1MHz fOFFSET 10MHz fOFFSET 1kHz fOFFSET 10kHz
Phase Noise 245.76MHz
fOFFSET 100kHz fOFFSET 1MHz fOFFSET 10MHz fOFFSET 1kHz fOFFSET 10kHz
Phase Noise 125MHz
fOFFSET 100kHz fOFFSET 1MHz fOFFSET 10MHz fOFFSET 1kHz fOFFSET 10kHz
Phase Noise 100MHz
fOFFSET 100kHz fOFFSET 1MHz fOFFSET 10MHz
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VCC +3.0V +3.6V, -40°C +85°C. Typical values +3.3V, +25°C, unless otherwise noted. Signal applied DIN/DIN only when selected reference clock.) (Note PARAMETER SYMBOL CONDITIONS fOFFSET 1kHz fOFFSET 10kHz Phase Noise 66.67MHz fOFFSET 100kHz fOFFSET 1MHz fOFFSET 10MHz -130 -131 -137 -152 -156 dBc/ UNITS
MAX3638
Note series resistor 10.5I allowed between VCCA filtering supply noise when system power-supply tolerance 3.3V Q5%. Figure Note Measured with outputs enabled unloaded. Note DC-coupled. Figure Input high voltage must 0.3V. Note DC-coupled. Figure Note Measured with 100I differential load. Note Measured with crystal input, with duty cycle LVCMOS differential input. Note Measured with output termination Thevenin equivalent. Note Measured with series resistor load capacitance 3.0pF. Figure Note Measured 125MHz output. Note Measured using LVCMOS/LVTTL input with slew rate 1.0V/ns, differential input with slew rate 0.5V/ns. Note Measured 125MHz output with 200kHz, 50mVP-P sinusoidal signal supply using crystal input power-supply filter shown Figure Typical Operating Characteristics other supply noise frequencies. Deterministic jitter calculated from measured power-supply-induced spurs. more information, refer Application Note 4461: HFAN-04.5.5: Characterizing Power-Supply Noise Rejection Clock Synthesizers. Note Measured with outputs enabled three banks different frequencies.
LVCMOS
0.1µF
OSCILLOSCOPE
MAX3638
Figure LVCMOS Output Measurement Setup
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Outputs MAX3638
Typical Operating Characteristics
(VCC 3.3V, +25NC, unless otherwise noted.)
SUPPLY CURRENT TEMPERATURE (LVPECL OUTPUTS, ENABLED)
MAX3638 toc01
SUPPLY CURRENT TEMPERATURE (LVDS OUTPUTS, ENABLED)
MAX3638 toc02
SUPPLY CURRENT TEMPERATURE (LVPECL OUTPUTS, LOADED)
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
NORMAL, OUTPUTS LOADED
SUPPLY CURRENT (mA)
QA[4:3], QA[2:0], QB[2:0], ENABLED QA[4:3], QA[2:0], QB[2:0] ENABLED QA[4:3] QA[2:0] ENABLED QA[2:0] ENABLED
NORMAL
BYPASS, OUTPUTS LOADED NORMAL, OUTPUTS UNLOADED
BYPASS
OUTPUTS DISABLED
BYPASS, OUTPUTS UNLOADED
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY CURRENT TEMPERATURE (LVDS OUTPUTS)
SUPPLY CURRENT (mA)
DIFFERENTIAL OUTPUT 500MHz (LVPECL)
MAX3638 toc05 MAX3638 toc04
DIFFERENTIAL OUTPUT 245.75MHz (LVPECL)
MAX3638 toc06
QA[4:3], QA[2:0], QB[2:0], ENABLED QA[4:3], QA[2:0], QB[2:0] ENABLED QA[4:3] QA[2:0] ENABLED QA[2:0] ENABLED OUTPUTS DISABLED
200mV/div
200mV/div
300ps/div
600ps/div
TEMPERATURE (°C)
DIFFERENTIAL OUTPUT 125MHz (LVPECL)
MAX3638 toc07
DIFFERENTIAL OUTPUT 125MHz (LVDS)
MAX3638 toc08
OUTPUT 66.67MHz (LVCMOS)
MAX3638 toc09
200mV/div
100mV/div
500mV/div
1.2ns/div
1.2ns/div
2ns/div
MAX3638 toc03
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Outputs
Typical Operating Characteristics (continued)
(VCC 3.3V, +25NC, unless otherwise noted.)
DIFFERENTIAL OUTPUT SWING OUTPUT FREQUENCY
MAX3638 toc10
MAX3638
DIFFERENTIAL OUTPUT SWING TEMPERATURE
MAX3638 toc11
RISE/FALL TIME TEMPERATURE (20% 80%)
LVCMOS
RISE/FALL TIME (ps)
MAX3638 toc12
3500 DIFFERNETIAL OUTPUT SWING (mVP-P) 3000 2500 2000 1500 1000 OUTPUT FREQUENCY (MHz)
3500 DIFFERENTIAL OUTPUT SWING (mVP-P) 3000 2500 2000 1500 1000
LVCMOS LVPECL
LVCMOS LVPECL
LVDS
LVDS
LVDS
LVPECL
TEMPERATURE (°C) TEMPERATURE (°C)
1000
DUTY-CYCLE DISTORTION TEMPERATURE
MAX3638 toc13
PHASE NOISE 491.52MHz
MAX3638 toc14
PHASE NOISE 245.76MHz
PHASE NOISE (dBc/Hz) -100 -110 -120 -130 -140 -150 -160
50.8 DUTY-CYCLE DISTORTION 50.6 50.4 50.2 50.0 49.8 49.6 49.4 49.2 49.0
PHASE NOISE (dBc/Hz) -100 -110 -120 -130 -140 -150 -160
PHASE JITTER 0.28psRMS INTEGRATED 12kHz 20MHz
PHASE JITTER 0.28psRMS INTEGRATED 12kHz 20MHz
LVPECL/LVDS
LVCMOS
100k
100M
100k
100M
TEMPERATURE (°C)
OUTPUT FREQUENCY (Hz)
OUTPUT FREQUENCY (Hz)
PHASE NOISE 125MHz
MAX3638 toc16
PHASE NOISE 100MHz
MAX3638 toc17
PHASE NOISE 66.67MHz
PHASE NOISE (dBc/Hz) -100 -110 -120 -130 -140 -150 -160
PHASE NOISE (dBc/Hz) -100 -110 -120 -130 -140 -150 -160
PHASE JITTER 0.33psRMS INTEGRATED 12kHz 20MHz
PHASE NOISE (dBc/Hz) -100 -110 -120 -130 -140 -150 -160
PHASE JITTER 0.36psRMS INTEGRATED 12kHz 20MHz
PHASE JITTER 0.38psRMS INTEGRATED 12kHz 20MHz
100k
100M
100k
100M
100k
100M
OUTPUT FREQUENCY (Hz)
OUTPUT FREQUENCY (Hz)
OUTPUT FREQUENCY (Hz)
MAX3638 toc18
MAX3638 toc15
51.0
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Outputs MAX3638
Typical Operating Characteristics (continued)
(VCC 3.3V, +25NC, unless otherwise noted.)
INTEGRATED PHASE JITTER (12kHz 20MHz) TEMPERATURE
MAX3638 toc19
JITTER TRANSFER
JITTER TRANSFER (dB)
MAX3638 toc20
0.60 INTEGRATED PHASE JITTER (psRMS) 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20
OUTPUT FREQUENCY 125MHz
LVCMOS
LVPECL
LVDS
100k
TEMPERATURE (°C)
JITTER FREQUENCY (Hz)
SPURS INDUCED POWER-SUPPLY NOISE NOISE FREQUENCY
MAX3638 toc21
DETERMINISTIC JITTER INDUCED POWERSUPPLY NOISE NOISE FREQUENCY
125MHz, NOISE 50mVP-P
DETERMINISTIC JITTER (psP-P)
MAX3638 toc22
SPUR AMPLITUDE (dBc)
125MHz, NOISE 50mVP-P
LVCMOS
LVCMOS
LVDS
LVPECL/LVDS
LVPECL
NOISE FREQUENCY (kHz) 1000
NOISE FREQUENCY (kHz) 1000
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Outputs
Description
NAME XOUT IN_SEL PLL_BP DF1, QC_CTRL VCCA DB1, DA1, DC1, QA_CTRL2 VCCQCC VCCQC VCCQA QA4, QA3, QA2, QA1, QA0, VCCQB QB0, QB1, QB2, QA_CTRL1 QB_CTRL DIN, Crystal Oscillator Input Crystal Oscillator Output Core Power Supply. Connect +3.3V. LVCMOS/LVTTL Input. Three-level control input mux. Table LVCMOS/LVTTL Input. Three-level control bypass mode. Table LVCMOS/LVTTL Inputs. Three-level controls feedback divider Table LVCMOS/LVTTL Input. Three-level control input C-bank output interface. Table Power Supply Internal Voltage-Controlled Oscillators (VCOs). Figure Reserved. Connect normal operation. LVCMOS/LVTTL Input. Three-level control prescale divider Table LVCMOS/LVTTL Inputs. Three-level controls output divider Table LVCMOS/LVTTL Inputs. Three-level controls output divider Table LVCMOS/LVTTL Inputs. Three-level controls output divider Table LVCMOS/LVTTL Input. Three-level control QA[4:3] output interface. Table Power Supply Output. Connect +3.3V. C-Bank LVCMOS Clock Output C-Bank Differential Output. Configured LVPECL LVDS with QC_CTRL pin. Power Supply C-Bank Differential Output. Connect +3.3V. Power Supply A-Bank Differential Outputs. Connect +3.3V. A-Bank Differential Output. Configured LVPECL LVDS with QA_CTRL2 pin. A-Bank Differential Output. Configured LVPECL LVDS with QA_CTRL2 pin. A-Bank Differential Output. Configured LVPECL LVDS with QA_CTRL1 pin. A-Bank Differential Output. Configured LVPECL LVDS with QA_CTRL1 pin. A-Bank Differential Output. Configured LVPECL LVDS with QA_CTRL1 pin. Power Supply B-Bank Differential Outputs. Connect +3.3V. B-Bank Differential Output. Configured LVPECL LVDS with QB_CTRL pin. B-Bank Differential Output. Configured LVPECL LVDS with QB_CTRL pin. B-Bank Differential Output. Configured LVPECL LVDS with QB_CTRL pin. LVCMOS/LVTTL Input. Three-level control QA[2:0] output interface. Table LVCMOS/LVTTL Input. Three-level control B-bank output interface. Table Differential Clock Input. Operates 350MHz. This input accept DC-coupled LVPECL signals, internally biased accept AC-coupled LVDS, CML, LVPECL signals. LVCMOS Clock Input. Operates 160MHz. Exposed Pad. Connect supply ground proper electrical thermal performance. FUNCTION LVCMOS/LVTTL Input. Three-level control input divider Table
MAX3638
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Outputs MAX3638
Detailed Description
MAX3638 low-jitter clock generator designed operate over wide range frequencies. consists selectable reference clock (on-chip crystal oscillator, LVCMOS input, differential input), with on-chip VCO, pin-programmable dividers muxes, three banks clock outputs. Figure output banks include nine pin-programmable LVDS/LVPECL output buffers LVCMOS output buffer. frequency, enabling, output interface each output bank individually programmed. addition A-bank split into banks with programmable enabling
IN_SEL
VCCA
DA[1:0]
PLL_BP
VCCQA
QA_CTRL1
XOUT CRYSTAL OSCILLATOR LVCMOS fREF fVCO 3830MHz 4025MHz LVPECL QA_CTRL2 VCCQB QB_CTRL
0/NC
fPFD 15MHz 42MHz
MAX3638
DIVIDER DIVIDER DIVIDER DIVIDER DIVIDER DIVIDER
0/NC
QC_CTRL 1/NC
DF[1:0]
DB[1:0]
DC[1:0] VCCQC VCCQCC
Figure Detailed Functional Diagram
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Outputs
output interface. bypass mode also available system testing clock distribution. on-chip crystal oscillator provides low-frequency reference clock PLL. This oscillator requires external crystal connected between XOUT. Crystal Selection Layout section more information. XOUT pins left open used. LVCMOS-compatible clock source connected serve reference clock. input internally biased allow DC-coupling (see Applications Information section). designed operate from 15MHz 160MHz. signal should applied used. differential clock source connected serve reference clock. This input operates from 15MHz 350MHz contains internal differential termination. This input accept DC-coupled LVPECL signals, internally biased accept AC-coupled LVDS, CML, LVPECL signals (see Applications Information section). signal should applied used. takes signal from crystal oscillator, LVCMOS clock input, differential clock input synthesizes low-jitter, high-frequency clock. contains phase-frequency detector (PFD), charge pump (CP), phase noise with wide 3.83GHz 4.025GHz frequency range. high-frequency output divided prescale divider then connected input through feedback divider. compares reference frequency divided-down output generates control signal that keeps locked reference clock. high-frequency VCO/P output clock sent output dividers. minimize noise-induced jitter, supply (VCCA) isolated from core logic output buffer supplies. dividers muxes with three-level control inputs. Divider settings routing information given Tables Table example divider configurations used various applications.
MAX3638
Crystal Oscillator
Phase-Locked Loop (PLL)
LVCMOS Clock Input
Differential Clock Input
Dividers Muxes
Table Input
IN_SEL INPUT Crystal Input. circuit disabled when selected. Differential Input. signal should applied selected. LVCMOS Input. signal should applied selected.
Table Bypass
PLL_BP OPERATION Enabled Normal Operation. outputs from banks derived from VCO. Bypassed. Selected input passes directly outputs. disabled minimize power consumption intermodulation spurs. Used system testing clock distribution. outputs from A-bank B-bank derived from VCO, C-bank outputs directly driven from input signal purposes daisy chaining.
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Outputs MAX3638
Table Input Divider
DIVIDER RATIO
Table Prescale Divider
DIVIDER RATIO
Note: When on-chip selected (IN_SEL setting required.
Table A-Bank Output Interface
QA_CTRL1 QA_CTRL2 QA[2:0] OUTPUT QA[2:0] LVDS QA[2:0] LVPECL QA[2:0] disabled high impedance QA[4:3] OUTPUT QA[4:3] LVDS QA[4:3] LVPECL QA[4:3] disabled high impedance
Table Feedback Divider
DIVIDER RATIO
Table B-Bank Output Interface
QB_CTRL QB[2:0] OUTPUT QB[2:0] LVDS QB[2:0] LVPECL QB[2:0] disabled high impedance
Table Output Divider
DA1/DB1 DA0/DB0 DIVIDER RATIO
Table C-Bank Output Interface
QC_CTRL OUTPUT LVDS, LVCMOS LVPECL, LVCMOS disabled high impedance
Table Output Divider
DIVIDER RATIO
differential clock outputs (QA[4:0], QB[2:0], operate 800MHz have pin-programmable LVDS/LVPECL output interface. Tables When configured LVDS, buffers designed drive transmission lines with differential termination. When configured LVPECL, buffers designed drive transmission lines terminated with Unused output banks disabled high impedance unused outputs left open.
LVDS/LVPECL Clock Outputs
LVCMOS clock output operates 160MHz designed drive single-ended high-impedance load. unused, this output left open C-bank disabled high impedance.
LVCMOS Clock Output
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Outputs
During power-on, power-on reset (POR) signal generated synchronize dividers. reset signal also generated control changed. Outputs within bank phase aligned, outputs bank-to-bank phase aligned.
Internal Reset
prescale divider given Table addition, reference clock frequency input divider must also selected compare frequency (fPFD) falls within specified range 15MHz 42MHz. applicable, higher fPFD should selected optimal jitter performance. fPFD
MAX3638
Applications Information
MAX3638 output frequencies (fQA, fQB, fQC) functions reference frequency (fREF) pinprogrammable dividers relationships expressed
Output Frequency Configuration
15MHz fPFD 42MHz Note that reference clock frequency limited fPFD range when bypass mode. Example Frequency Configuration following example find divider ratios valid configuration, given requirement input output frequencies. Select input output frequencies system clocking. fREF 25MHz 125MHz 100MHz 66.67MHz Find input divider valid compare frequency. Using Table equations (7), determined that only valid option. Find feedback divider prescale divider valid fVCO. Using Tables along with equations (5), determined that results fVCO 4000MHz, which within valid range VCO. Find output dividers required output frequencies. Using Tables equations (1), (2), (3), determined that gives 125MHz, gives 100MHz, gives 66.67MHz. Table provides input output frequencies along with valid divider ratios variety applications.
frequency ranges selected reference clocks 18MHz 33.5MHz crystal oscillator input, 15MHz 160MHz LVCMOS input, 15MHz 350MHz differential input. available dividers given Tables given reference frequency fREF, input divider feedback divider prescale divider must configured frequency (fVCO) falls within specified ranges. Invalid configuration leads frequencies beyond specified ranges result loss lock. expression frequency along with specified ranges given fVCO
3830MHz fVCO 4025MHz
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Outputs MAX3638
Table Reference Frequencies Divider Ratios Various Applications
fREF (MHz) 30.72 61.44 122.88 33.3/66.7/ 133.3 INPUT DIVIDER 1/2/4 FEEDBACK DIVIDER 3932.16 FREQUENCY (MHz) PRESCALE DIVIDER 4000 25/50/100 1/2/4 33.3/66.7/ 133.3 25/50/100 1/2/4 1/2/4 4000 31.25/ 62.5/125 1/2/4 32.76 20.82857 41.6571 25.78125 27.392578 20.916 41.8329 3931.2 3999.084 OUTPUT DIVIDER OUTPUT FREQUENCY (MHz) 491.52 245.76 122.88 266.67 133.333 66.67 333.33 166.67 66.67 33.33 131.04 65.52 333.257 166.6285 161.132812 164.355 334.66 167.33 Microwave Radio Link OTU1, 10Gbps SONET with 10Gbps Ethernet with 10Gbps OTU2, 10Gbps SONET with Digital Wrapper Server, FB-DIMM, Network Processor, DDR/ Memory, PCIe, SATA Server, Network Processor, DDR/ Memory, PCIe, SATA APPLICATIONS
Wireless Base Station: WCDMA, cdma2000®, LTE, TD_SCDMA
3867.1875 3944.53125 4015.95949
cdma2000 registered trademark Telecommunications Industry Association.
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Outputs
MAX3638 mixed analog/digital contains analog circuitry susceptible random noise. take full advantage on-board filtering noise attenuation, addition excellent on-chip power-supply rejection, this part provides separate power-supply pin, VCCA, circuitry. Figure illustrates recommended power-supply filter network VCCA. purpose this design technique ensure clean input power supply circuitry improve overall immunity power-supply noise. This network requires that power supply +3.3V ±5%. Decoupling capacitors should used other supply pins best performance. supply connections should driven from same source.
Power-Supply Filtering
48-pin TQFN package features exposed (EP), which provides resistance thermal path heat removal from also electrical ground. proper operation, must connected circuit board ground plane with multiple vias. MAX3638 features integrated on-chip crystal oscillator minimize system implementation cost. crystal oscillator designed drive fundamental mode, AT-cut crystal resonator. Table recommended crystal specifications. Figure crystal equivalent circuit Figure recommended external capacitor connections. crystal, trace, external capacitors should placed board close possible XOUT pins reduce crosstalk active signals into oscillator. total load capacitance crystal combination external on-chip capacitance. layout shown Figure gives approximately 1.7pF trace plus footprint capacitance side crystal. Note ground plane removed under crystal minimize capacitance. There approximately 2.5pF on-chip capacitance between XOUT. With external 27pF capacitor connected 33pF external capacitor connected XOUT, total load capacitance crystal approximately 18pF. XOUT pins left open used.
Ground Connection
MAX3638
Crystal Selection Layout
+3.3V MAX3638 VCCA 0.1µF 10µF 10.5 0.1µF
Figure Power-Supply Filter
Table Crystal Selection Parameters
PARAMETER Crystal Oscillation Frequency Shunt Capacitance Load Capacitance Equivalent Series Resistance (ESR) Maximum Crystal Drive Level SYMBOL fOSC 33.5 UNITS
XTAL
27pF
CRYSTAL 18pF)
MAX3638 XOUT
33pF
Figure Crystal Equivalent Circuit
Figure Crystal, Capacitor Connections
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Outputs MAX3638
equivalent LVCMOS input circuit given Figure This input internally biased allow DC-coupling, 180kI input impedance. Figure interface circuit. signal should applied used. equivalent input circuit given Figure This input operates 350MHz contains internal 100I differential termination well common-mode termination. common-mode termination ensures good signal integrity when connected source with large common-mode signals. input accept DC-coupled LVPECL signals, internally biased accept AC-coupled LVDS, CML, LVPECL signals (Figure 10). signal should applied used.
VBIAS 180k
STRUCTURES
Interfacing with LVCMOS Input
Interfacing with Differential Input
Figure Crystal Layout
1.4V
STRUCTURES
Figure Equivalent Circuit
16pF
1.3V
DC-COUPLED
MAX3638
STRUCTURES
Figure Equivalent Circuit
AC-COUPLED
MAX3638
0.1µF
Figure Interface
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Outputs
LVPECL SOURCE DRIVING MAX3638 DIFFERENTIAL INPUT DC-COUPLED MAX3638 LVPECL +3.3V LVPECL
+3.3V
equivalent LVPECL output circuit given Figure These outputs designed drive pair transmission lines terminated with separate termination voltage (VTT) available, other terminations methods used, shown Figure more information LVPECL terminations interface with other logic families, refer Application Note 291: HFAN-01.0: Introduction LVDS, PECL, CML.
Interfacing with LVPECL Outputs
MAX3638
VCC_ LVPECL SOURCE DRIVING MAX3638 DIFFERENTIAL INPUT AC-COUPLED MAX3638 0.1µF LVPECL STRUCTURES LVDS SOURCE DRIVING MAX3638 DIFFERENTIAL INPUT AC-COUPLED MAX3638 0.1µF LVDS 0.1µF +3.3V LVPECL 0.1µF +3.3V LVPECL
+3.3V
Figure Equivalent LVPECL Output Circuit
Figure Interfacing
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Outputs MAX3638
DC-COUPLED LVPECL DRIVING THEVENIN EQUIVALENT TERMINATION +3.3V +3.3V MAX3638 LVPECL LVPECL +3.3V +3.3V
HIGH IMPEDANCE WITH/WITHOUT BIAS
AC-COUPLED LVPECL DRIVING INTERNAL DIFFERENTIAL TERMINATION +3.3V MAX3638 LVPECL
0.1µF 0.1µF LVPECL
ON-CHIP TERMINATION WITH BIAS
AC-COUPLED LVPECL DRIVING EXTERNAL WITH COMMON-MODE TERMINATION +3.3V MAX3638 LVPECL
0.1µF 0.1µF LVPECL
HIGH IMPEDANCE WITH BIAS
0.1µF
Figure Interface LVPECL Outputs
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Outputs
VREG VCC_
equivalent LVDS output circuit given Figure These outputs provide differential output impedance designed drive differential transmission line terminated with differential load. Example interface circuits shown Figure more information LVDS terminations interface with other logic families, refer Application Note 291: HFAN01.0: Introduction LVDS, PECL, CML. equivalent LVCMOS output circuit given Figure This output provides output impedance designed drive high-impedance load. series resistor recommended LVCMOS output before transmission line. example interface circuit shown Figure
Interfacing with LVDS Outputs
MAX3638
Interfacing with LVCMOS Output
STRUCTURES
Figure Equivalent LVDS Output Circuit
VCCQCC DC-COUPLED LVDS OUTPUT DRIVING LVDS INPUT +3.3V +3.3V MAX3638 LVDS STRUCTURES LVDS*
AC-COUPLED LVDS OUTPUT DRIVING LVDS INPUT +3.3V
Figure Equivalent LVCMOS Output Circuit
MAX3638 LVDS
0.1µF 0.1µF MAX3638 LVDS* LVCMOS HIGH IMPEDANCE
*100 DIFFERENTIAL INPUT IMPEDANCE ASSUMED.
Figure Interface LVCMOS Output
Figure Interface LVDS Outputs
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Outputs MAX3638
inputs outputs most critical paths MAX3638; great care should taken minimize discontinuities transmission lines. Here some suggestions maximizing performance MAX3638: uninterrupted ground plane should positioned beneath clock outputs. ground plane under crystal should removed minimize capacitance. Supply decoupling capacitors should placed close supply pins, preferably same side board MAX3638. Take care isolate input traces from MAX3638 outputs.
Layout Considerations
crystal, trace, external capacitors should placed board close possible XOUT pins reduce crosstalk active signals into oscillator. Maintain differential single-ended) transmission line impedance into part. Provide space between differential output pairs reduce crosstalk, especially outputs operating different frequencies. multilayer boards with uninterrupted ground plane minimize crosstalk. Refer MAX3638 evaluation more information.
Chip Information
PROCESS: BiCMOS
Configuration
VCCQA VCCQA VCCQC VCCQCC QA_CTRL2 XOUT IN_SEL PLL_BP QC_CTRL VCCA
VCCQB QA_CTRL1 QB_CTRL
MAX3638
THIN (7mm 0.8mm)
*THE EXPOSED PACKAGE MUST SOLDERED GROUND PROPER THERMAL ELECTRICAL OPERATION.
VIEW
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Outputs
Typical Application Circuits
+3.3V 10.5 10µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
MAX3638
27pF
VCCA
VCCQA
VCCQB
VCCQC
VCCQCC QA[4:0]
125MHz LVPECL
ASIC WITH LVPECL TERMINATION
25MHz XOUT 33pF IN_SEL MAX3638 PLL_BP +3.3V QA_CTRL1 QA_CTRL2 QB_CTRL QC_CTRL QB[2:0] QB[2:0] QA[4:0]
0.1µF 0.1µF
100MHz LVDS
ASIC WITH LVDS TERMINATION
66.67MHz LVDS
ASIC WITH LVDS TERMINATION
66.67MHz LVCMOS
ASIC WITH LVCMOS TERMINATION HIGH IMPEDANCE
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Outputs MAX3638
Typical Application Circuits (continued)
CLOCK GENERATOR ETHERNET SYSTEM CLOCKING 25MHz XOUT MAX3637 QB[2:0] QA[4:0]
312.5MHz LVPECL LVDS 156.25MHz LVPECL LVDS 25MHz LVCMOS
BACKPLANE TRANSCEIVER 10GbE
ASIC
25MHz LVPECL
QA[4:0]
125MHz LVPECL LVDS 100MHz LVPECL LVDS 66.67MHz LVPECL LVDS 66.67MHz LVCMOS
1GbE
QB[2:0]
PCIe NETWORK PROCESSOR FPGA
MAX3638
FREQUENCY TRANSLATOR BASE STATION QA[4:0] 30.72MHz QB[2:0]
122.88MHz LVPECL LVDS 30.72MHz LVPECL LVDS 30.72MHz LVCMOS 245.76MHz LVPECL LVDS
ASIC CPRI SerDes FPGA
MAX3638
FPGA
Package Information
latest package outline information land patterns, www.maxim-ic.com/packages. Note that "+", "#", package code indicates RoHS status only. Package drawings show different suffix character, drawing pertains package regardless RoHS status.
PACKAGE TYPE TQFN-EP
PACKAGE CODE T4877+4
DOCUMENT 21-0144
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2009 Maxim Integrated Products Maxim registered trademark Maxim Integrated Products, Inc.

Low-Jitter, Wide Frequency Range, Programmable Clock Generator with Ou

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