Low-Jitter, Precision Clock Generator with Three Outputs Crystal

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Low-Jitter, Precision Clock Generator with Three Outputs Crystal

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19-4978; 10/09
Low-Jitter, Precision Clock Generator with Three Outputs
Crystal Oscillator Interface: 24.8MHz 27MHz CMOS Input: 320MHz Output Frequencies Ethernet: 62.5MHz, 125MHz, 156.25MHz, 312.5MHz Fibre Channel: 159.375MHz, 318.75MHz Jitter 0.14psRMS (1.875MHz 20MHz) 0.36psRMS (12kHz 20MHz) Excellent Power-Supply Noise Rejection External Loop Filter Capacitor Required
MAX3625B
MAX3625B low-jitter, precision clock generator optimized networking applications. device integrates crystal oscillator phase-locked loop (PLL) clock multiplier generate high-frequency clock outputs Ethernet, Fibre Channel, other networking applications. Maxim's proprietary design features ultra-low jitter excellent power-supply noise rejection, minimizing design risk network equipment. MAX3625B three LVPECL outputs. Selectable output dividers selectable feedback divider allow range output frequencies.
Applications
Ethernet Networking Equipment Fibre Channel Storage Area Network
Typical Application Circuit appears data sheet.
PART MAX3625BEUG+
Ordering Information
TEMP RANGE -40°C +85°C PIN-PACKAGE TSSOP-EP*
+Denotes lead(Pb)-free/RoHS-compliant package. Exposed pad.
Block Diagram
IN_SEL BYPASS SELA[1:0]
SELA[1:0] SELB[1:0] FB_SEL BYPASS
QA_OE RESET LOGIC/POR RESET DIVIDER LVPECL BUFFER
RESET LVCMOS REF_IN 27pF X_IN CRYSTAL OSCILLATOR X_OUT 33pF DIVIDERS: LVPECL BUFFER DIVIDER DIVIDER FILTER RESET 620MHz 648MHz RESET LVPECL BUFFER QB_OE
MAX3625B
FB_SEL
SELB[1:0]
Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim Direct 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
Low-Jitter, Precision Clock Generator with Three Outputs MAX3625B
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range VCC, VCCA, VCCO_A, VCCO_B .-0.3V +4.0V Voltage Range REF_IN, IN_SEL, FB_SEL, SELA[1:0], SELB[1:0], QA_OE, QB_OE, BYPASS .-0.3V (VCC 0.3V) Voltage Range X_IN .-0.3V +1.2V Voltage Range X_OUT .-0.3V (VCC 0.6V) Current into QB0, QB0, QB1, .-56mA Continuous Power Dissipation +70°C) 24-Pin TSSOP (derate 26.7mW/°C above +70°C) .2133.3mW Operating Junction Temperature Range .-55°C +150°C Storage Temperature Range .-65°C +160°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC +3.0V +3.6V, -40°C +85°C, unless otherwise noted. Typical values +3.3V, +25°C, unless otherwise noted.) (Notes
PARAMETER Power-Supply Current (Note SYMBOL IN_SEL high IN_SEL CONDITIONS UNITS
CONTROL INPUT CHARACTERISTICS (SELA[1:0], SELB[1:0], FB_SEL, IN_SEL, QA_OE, QB_OE, BYPASS Pins) Input Capacitance Input Pulldown Resistor Input Logic Bias Resistor Input Pullup Resistor RPULLDOWN Pins FB_SEL RBIAS RPULLUP Pins SELA[1:0], SELB[1:0] Pins QA_OE, QB_OE, IN_SEL, BYPASS 1.18 1.90 (Note (Note enabled bypassed (Note 0.98 0.72 0.83 1.55
LVPECL OUTPUTS (QA, QB0, QB0, QB1, Pins) Output High Voltage Output Voltage Peak-to-Peak Output-Voltage Swing (Single-Ended) Clock Output Rise/Fall Time Output Duty-Cycle Distortion VP-P
LVCMOS/LVTTL INPUTS (SELA[1:0], SELB[1:0], FB_SEL, IN_SEL, QA_OE, QB_OE, BYPASS Pins) Input-Voltage High Input-Voltage Input High Current Input Current
Low-Jitter, Precision Clock Generator with Three Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VCC +3.0V +3.6V, -40°C +85°C, unless otherwise noted. Typical values +3.3V, +25°C, unless otherwise noted.) (Notes
PARAMETER SYMBOL enabled bypassed enabled -240 RJRMS 12kHz 20MHz 1.875MHz 20MHz (Notes (Note 0.36 0.14 Between output pair 1kHz Clock Output Phase Noise 125MHz (Note 10kHz 100kHz 1MHz 10MHz -124 -127 -131 -145 -153 dBc/Hz CONDITIONS 24.8 27.0 UNITS
MAX3625B
REF_IN SPECIFICATIONS (Input AC-Coupled) Reference Clock Frequency Input-Voltage High Input-Voltage Input High Current Input Current Reference Clock Duty Cycle Input Capacitance CLOCK OUTPUT SPECIFICATIONS Frequency Range Random Jitter (Note Spurs Induced Power-Supply Noise Deterministic Jitter Induced Power-Supply Noise Nonharmonic Subharmonic Spurs Output Skew psRMS psP-P
series resistor 10.5 allowed between VCCA filtering supply noise when system power-supply tolerance 3.3V ±5%. Figure Note LVPECL outputs guaranteed 320MHz. Note outputs enabled unloaded. Note Measured with crystal (see Table AC-coupled, duty-cycle signal REF_IN. Note Measured with crystal source, Table Note Measured using setup shown Figure Note Measured with 40mVP-P, 100kHz sinusoidal signal supply. Note Measured 156.25MHz output. Note Calculated based measured spurs induced power-supply noise (refer Application Note 4461: HFAN-04.5.5: Characterizing Power-Supply Noise Rejection Clock Synthesizers). Note Measured with 25MHz crystal 25MHz reference clock REF_IN with slew rate 0.5V/ns greater. Note
Low-Jitter, Precision Clock Generator with Three Outputs MAX3625B
Typical Operating Characteristics
(Typical values +3.3V, +25°C, crystal frequency 25MHz.)
SUPPLY CURRENT TEMPERATURE
SUPPLY CURRENT (mA) 1ns/div AMBIENT TEMPERATURE (°C) OUTPUTS ACTIVE UNTERMINATED OUTPUTS ACTIVE TERMINATED
MAX3625B toc01
DIFFERENTIAL OUTPUT WAVEFORM 156.25MHz
MAX3625B toc02
PHASE NOISE 312.5MHz CLOCK FREQUENCY
-100 -110 -120 -130 -140 -150 -160 1000 10,000 100,000 OFFSET FREQUENCY (kHz)
MAX3625B toc03
NOISE POWER DENSITY (dBc/Hz)
AMPLITUDE (200mv/div)
PHASE NOISE 125MHz CLOCK FREQUENCY
MAX3625B toc04
PHASE NOISE 156.25MHz CLOCK FREQUENCY
MAX3625B toc05
SPURS INDUCED POWER-SUPPLY NOISE NOISE FREQUENCY
SPUR AMPLITUDE (dBc) -100 156.25MHz NOISE AMPLITUDE 40mVP-P
MAX3625B toc06
NOISE POWER DENSITY (dBc/Hz) -100 -110 -120 -130 -140 -150 -160
NOISE POWER DENSITY (dBc/Hz) -100 -110 -120 -130 -140 -150 -160
1000 10,000 100,000
1000 10,000 100,000
1000
10,000
OFFSET FREQUENCY (kHz)
OFFSET FREQUENCY (kHz)
NOISE FREQUENCY (kHz)
Low-Jitter, Precision Clock Generator with Three Outputs
Configuration
VIEW
VCCO_B REF_IN IN_SEL X_OUT SELB1 SELA1 X_IN
MAX3625B
MAX3625B
SELB0 BYPASS VCCO_A QB_OE QA_OE FB_SEL SELA0 VCCA
TSSOP
*EXPOSED MUST SOLDERED GROUND PROPER THERMAL ELECTRICAL OPERATION.
Description
NAME SELB0, SELB1 BYPASS FUNCTION LVCMOS/LVTTL Inputs. Control divider setting. information. input impedance. Table more
LVCMOS/LVTTL Input (Active Low). Connect bypass internal PLL. Connect high leave open normal operation. When bypass mode output dividers divide internal pullup VCC. LVCMOS/LVTTL Input. Master reset input. Pulse high reset dividers. internal pulldown GND. required normal operation. Power Supply Clock Output. Connect +3.3V. Noninverting Clock Output, LVPECL Inverting Clock Output, LVPECL LVCMOS/LVTTL Input. Enables/disables clock outputs. Connect high leave open enable LVPECL clock outputs QB1. Connect logic internal pullup VCC. LVCMOS/LVTTL Input. Enables/disables clock output. Connect high leave open enable LVPECL clock output Connect logic internal pullup VCC. LVCMOS/LVTTL Input. Controls divider setting. Table more information. internal pulldown GND.
VCCO_A QB_OE
QA_OE FB_SEL
Low-Jitter, Precision Clock Generator with Three Outputs MAX3625B
Description (continued)
NAME VCCA SELA0, SELA1 X_OUT X_IN REF_IN IN_SEL VCCO_B FUNCTION Analog Power Supply VCO. Connect +3.3V. additional power-supply noise filtering, this connect through 10.5 shown Figure (requires 3.3V ±5%). Core Power Supply. Connect +3.3V. LVCMOS/LVTTL Inputs. Control divider setting. Table more information. impedance. Supply Ground Crystal Oscillator Output Crystal Oscillator Input LVCMOS Reference Clock Input. Self-biased allow DC-coupling. LVCMOS/LVTTL Input. Connect high leave open crystal. Connect REF_IN. internal pullup VCC. LVPECL, Inverting Clock Output LVPECL, Noninverting Clock Output LVPECL, Inverting Clock Output LVPECL, Noninverting Clock Output Power Supply Clock Output. Connect +3.3V. Exposed Pad. Supply ground; connect ground proper electrical thermal performance. input
Detailed Description
MAX3625B low-jitter clock generator designed operate Ethernet Fibre Channel frequencies. consists on-chip crystal oscillator, PLL, programmable dividers, LVPECL output buffers. Using low-frequency clock (crystal CMOS input) reference, internal generates high-frequency output clock with excellent jitter performance.
Crystal Oscillator
integrated oscillator provides low-frequency reference clock PLL. This oscillator requires external crystal connected between X_IN X_OUT. crystal frequency 24.8MHz 27MHz.
controlled oscillator (VCO) with 620MHz 648MHz operating range. connected input through feedback divider. Table divider values. compares reference frequency divided-down output (fVCO/M) generates control signal that keeps locked reference clock. high-frequency output clock sent output dividers. minimize noiseinduced jitter, supply (VCCA) isolated from core logic output buffer supplies.
Output Dividers
output dividers programmable allow range output frequencies. Table divider input settings. output dividers automatically divide when MAX3625B bypass mode (BYPASS
+3.3V 0.01F 10.5 VCCA 0.01F
REF_IN Buffer
LVCMOS-compatible clock source connected REF_IN serve reference clock. LVCMOS REF_IN buffer internally biased threshold voltage (1.4V typ) allow DC-coupling, designed operate 320MHz.
takes signal from crystal oscillator reference clock input synthesizes low-jitter, highfrequency clock. contains phase-frequency detector (PFD), lowpass filter, voltage-
Figure Analog Supply Filtering
Low-Jitter, Precision Clock Generator with Three Outputs MAX3625B
Table Output Frequency Determination
CRYSTAL CMOS INPUT FREQUENCY (MHz) FEEDBACK DIVIDER, FREQUENCY (MHz) OUTPUT DIVIDER, 25.78125 644.53125 26.04166 26.5625 637.5 OUTPUT FREQUENCY (MHz) 312.5 156.25 62.5 161.132812 312.5 156.25 62.5 318.75 159.375 Fibre Channel Ethernet 10Gbps Ethernet Ethernet APPLICATIONS
LVPECL Drivers
high-frequency outputs-QA, QB0, QB1-are differential PECL buffers designed drive transmission lines terminated with 2.0V. maximum operating frequency specified 320MHz. outputs disabled, used. outputs logic when disabled.
Output Divider Configuration
Table shows input settings required output dividers. Note that when MAX3625B bypass mode (BYPASS low), output dividers automatically divide
Divider Configuration
Table shows input settings required feedback divider.
Reset Logic/POR
During power-on, power-on reset (POR) signal generated synchronize dividers. external master reset (MR) signal required.
Table Output Divider Configuration
INPUT SELA1/SELB1 SELA0/SELB0 NA/NB DIVIDER
Applications Information
Power-Supply Filtering
MAX3625B mixed analog/digital contains analog circuitry susceptible random noise. addition excellent on-chip power-supply noise rejection, MAX3625B provides separate powersupply pin, VCCA, circuitry. Figure illustrates recommended power-supply filter network purpose this design technique ensure clean power supply circuitry improve overall immunity power-supply noise. This network requires that power supply +3.3V ±5%. Decoupling capacitors should used supply pins best performance.
Table Divider Configuration
FB_SEL INPUT DIVIDER
Low-Jitter, Precision Clock Generator with Three Outputs MAX3625B
Crystal Selection
crystal oscillator designed drive fundamental mode, AT-cut crystal resonator. Table recommended crystal specifications. Figure external capacitance connection.
Crystal Input Layout
crystal, trace, external capacitors should placed board close possible MAX3625B's X_IN X_OUT pins reduce crosstalk active signals into oscillator. example layout shown Figure gives approximately trace plus footprint capacitance side crystal. dielectric material dielectric thickness reference board mils. Using 25MHz crystal capacitor values 27pF 33pF, measured output frequency accuracy -14ppm +25°C ambient temperature.
Table Crystal Selection Parameters
PARAMETER Crystal Oscillation Frequency Shunt Capacitance Load Capacitance Equivalent Series Resistance (ESR) Maximum Crystal Drive Level SYMBOL 24.8 UNITS
Interfacing with LVPECL Outputs
equivalent LVPECL output circuit given Figure These outputs designed drive pair transmission lines terminated with separate termination voltage (VTT) available, other termination methods used such shown Figures Unused outputs should disabled left open. more information LVPECL terminations interface with other logic families, refer Application Note 291: HFAN-01.0: Introduction LVDS, PECL, CML.
+3.3V
HIGH IMPEDANCE
MAX3625B
Figure Crystal Layout Figure Thevenin Equivalent Standard PECL Termination
27pF X_IN CRYSTAL 18pF) X_OUT 33pF
0.1F 0.1F HIGH IMPEDANCE
MAX3625B
Figure Crystal, Capacitors Connection
NOTE: AC-COUPLING OPTIONAL.
Figure AC-Coupled PECL Termination
Low-Jitter, Precision Clock Generator with Three Outputs
Interface Models
Figures show examples interface models.
Layout Considerations
inputs outputs critical paths MAX3625B, care should taken minimize discontinuities these transmission lines. Here some suggestions maximizing MAX3625B's performance: uninterrupted ground plane should positioned beneath clock I/Os. Supply ground vias should placed close input/output interfaces allow return current path MAX3625B receive devices. Supply decoupling capacitors should placed close MAX3625B supply pins. Maintain differential single-ended) transmission line impedance MAX3625B. good high-frequency layout techniques multilayer boards with uninterrupted ground plane minimize crosstalk. 24-pin TSSOP-EP package features exposed (EP), which provides low-resistance thermal path heat removal from must connected circuit board ground plane proper operation. Refer MAX3625B Evaluation more information.
MAX3625B
1.4V
14.5k REF_IN
STRUCTURES
Figure Simplified REF_IN Circuit Schematic
Chip Information
TRANSISTOR COUNT: 10,840 PROCESS: BiCMOS
STRUCTURES
Figure Simplified LVPECL Output Circuit Schematic
Low-Jitter, Precision Clock Generator with Three Outputs MAX3625B
Typical Application Circuit
+3.3V 10.5 0.01F 0.1F
VCCA 0.01F REF_IN
VCCO_A
VCCO_B 312.5MHz
0.1F ASIC 0.1F
IN_SEL FB_SEL QA_OE QB_OE BYPASS SELA0 SELB1 SELB0 SELA1 X_OUT X_IN
0.1F
MAX3625B
ASIC 156.25MHz 0.1F
0.1F ASIC 156.25MHz 0.1F
26.0416MHz 18pF) 33pF 27pF
Package Information
latest package outline information land patterns, www.maxim-ic.com/packages. Note that "+", "#", package code indicates RoHS status only. Package drawings show different suffix character, drawing pertains package regardless RoHS status. PACKAGE TYPE TSSOP-EP PACKAGE CODE U24E+1 DOCUMENT 21-0108
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2009 Maxim Integrated Products Maxim registered trademark Maxim Integrated Products, Inc.

Low-Jitter, Precision Clock Generator with Three Outputs Crystal

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