64/80/100-Pin General Purpose, 16-Bit Flash Microcontrollers 2009
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PIC24FJ128GA010 Family Data Sheet
64/80/100-Pin General Purpose, 16-Bit Flash Microcontrollers
2009 Microchip Technology Inc.
DS39747E
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Trademarks Microchip name logo, Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC UNI/O registered trademarks Microchip Technology Incorporated U.S.A. other countries. FilterLab, Hampshire, HI-TECH Linear Active Thermistor, MXDEV, MXLAB, SEEVAL Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2009, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
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2009 Microchip Technology Inc.
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64/80/100-Pin General Purpose, 16-Bit Flash Microcontrollers
High-Performance CPU:
Modified Harvard Architecture MIPS Operation Internal Oscillator with Option Multiple Divide Options 17-Bit 17-Bit Single-Cycle Hardware Multiplier 32-Bit 16-Bit Hardware Divider 16-Bit Working Register Array Compiler Optimized Instruction Architecture: base instructions Flexible addressing modes Address Generation Units Separate Read Write Addressing Data Memory
Analog Features:
10-Bit, 16-Channel Analog-to-Digital Converter ksps conversion rate Conversion available during Sleep Idle Dual Analog Comparators with Programmable Input/Output Configuration
Peripheral Features:
3-Wire/4-Wire modules, Supporting Frame modes with 8-Level FIFO Buffer I2Cmodules Support Multi-Master/Slave mode 7-Bit/10-Bit Addressing UART modules: Supports RS-232, RS-485 On-chip hardware encoder/decoder IrDA® Auto-wake-up Start Auto-Baud Detect 4-level FIFO buffer Parallel Master Slave Port (PMP/PSP): Supports 8-bit 16-bit data Supports address lines Hardware Real-Time Clock/Calendar (RTCC): Provides clock, calendar alarm functions Programmable Cyclic Redundancy Check (CRC) User-programmable polynomial 8/16-level FIFO buffer Five 16-Bit Timers/Counters with Programmable Prescaler Five 16-Bit Capture Inputs Five 16-Bit Compare/PWM Outputs High-Current Sink/Source mA/18 Pins Configurable, Open-Drain Output Digital Pins External Interrupt Sources 5.5V Tolerant Input (digital pins only)
Special Microcontroller Features:
Operating Voltage Range 2.0V 3.6V Flash Program Memory: 1000 erase/write cycles 20-year data retention minimum Self-Reprogrammable under Software Control Selectable Power Management modes: Sleep, Idle Alternate Clock modes Fail-Safe Clock Monitor Operation: Detects clock failure switches on-chip, low-power oscillator On-Chip 2.5V Regulator JTAG Boundary Scan Programming Support Power-on Reset (POR), Power-up Timer (PWRT) Oscillator Start-up Timer (OST) Flexible Watchdog Timer (WDT) with On-Chip, Low-Power Oscillator Reliable Operation In-Circuit Serial Programming(ICSPTM) In-Circuit Emulation (ICE) Pins
Compare/ Output
Comparators
Device
Pins
Program Memory (Bytes) 128K 128K 128K
PMP/PSP
Capture Input
UART
SRAM (Bytes)
Timers 16-Bit
I2C
10-Bit (ch)
PIC24FJ64GA006 PIC24FJ96GA006 PIC24FJ128GA006 PIC24FJ64GA008 PIC24FJ96GA008 PIC24FJ128GA008 PIC24FJ64GA010 PIC24FJ96GA010 PIC24FJ128GA010
2009 Microchip Technology Inc.
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JTAG
PIC24FJ128GA010 FAMILY
Diagrams
64-Pin TQFP
PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/IC5/CN13/RD4 PMBE/OC4/RD3 OC3/RD2 OC2/RD1
PMD5/RE5 PMD6/RE6 PMD7/RE7 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/EMUC1/VREF-/AN1/CN3/RB1
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/INT4/RD11 IC3/PMCS2/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/RTCC/INT1/RD8 OSC2/CLKO/RC15 OSC1/CLKI/RC12 SCL1/RG2 SDA1/RG3 U1RTS/BCLK1/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3
PIC24FJXXGA006 PIC24FJXXXGA006
PGC2/EMUC2/AN6/OCFA/RB6 PGD2/EMUD2/AN7/RB7 AVDD AVSS U2CTS/C1OUT/AN8/RB8 PMA7/C2OUT/AN9/RB9 TMS/PMA13/CVREF/AN10/RB10 TDO/PMA12/AN11/RB11 TCK/PMA11/AN12/RB12 TDI/PMA10/AN13/RB13 PMA1/U2RTS/BCLK2/AN14/RB14 PMA0/AN15/OCFB/CN12/RB15 PMA9/U2RX/SDA2/CN17/RF4 PMA8/U2TX/SCL2/CN18/RF5
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Diagrams (Continued)
80-Pin TQFP
PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/CN13/RD4 CN19/RD13 IC5/RD12 PMBE/OC4/RD3 OC3/RD2 OC2/RD1
PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T4CK/RC3 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 TMS/INT1/RE8 TDO/INT2/RE9 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/EMUC1/AN1/CN3/RB1 PGD1/EMUD1/AN0/CN2/RB0
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/RD11 IC3/PMCS2/RD10 IC2/RD9 IC1/RTCC/RD8 SDA2/INT4/RA15 SCL2/INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKI/RC12 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3
PIC24FJXXGA008 PIC24FJXXXGA008
2009 Microchip Technology Inc.
PGC2/EMUC2/AN6/OCFA/RB6 PGD2/EMUD2/AN7/RB7 PMA7/VREF-/RA9 PMA6/VREF+/RA10 AVDD AVSS U2CTS/C1OUT/AN8/RB8 C2OUT/AN9/RB9 PMA13/CVREF/AN10/RB10 PMA12/AN11/RB11 TCK/PMA11/AN12/RB12 TDI/PMA10/AN13/RB13 PMA1/U2RTS/BCLK2/AN14/RB14 PMA0/AN15/OCFB/CN12/RB15 U1CTS/CN20/RD14 U1RTS/BCLK1/CN21/RD15 PMA9/U2RX/CN17/RF4 PMA8/U2TX/CN18/RF5
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PIC24FJ128GA010 FAMILY
Diagrams (Continued))
100-Pin TQFP
PMD4/RE4 PMD3/RE3 PMD2/RE2 RG13 RG12 RG14 PMD1/RE1 PMD0/RE0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/CN13/RD4 CN19/RD13 IC5/RD12 PMBE/OC4/RD3 OC3/RD2 OC2/RD1
RG15 PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/RC4 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 TMS/RA0 INT1/RE8 INT2/RE9 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/EMUC1/AN1/CN3/RB1 PGD1/EMUD1/AN0/CN2/RB0
PIC24FJXXGA010 PIC24FJXXXGA010
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/RD11 IC3/PMCS2/RD10 IC2/RD9 IC1/RTCC/RD8 INT4/RA15 INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKI/RC12 TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3
PGC2/EMUC2/AN6/OCFA/RB6 PGD2/EMUD2/AN7/RB7 PMA7/VREF-/RA9 PMA6/VREF+/RA10 AVDD AVSS C1OUT/AN8/RB8 C2OUT/AN9/RB9 PMA13/CVREF/AN10/RB10 PMA12/AN11/RB11 TCK/RA1 U2RTS/BCLK2/RF13 U2CTS/RF12 PMA11/AN12/RB12 PMA10/AN13/RB13 PMA1/AN14/RB14 PMA0/AN15/OCFB/CN12/RB15 U1CTS/CN20/RD14 U1RTS/BCLK1/CN21/RD15 PMA9/U2RX/CN17/RF4 PMA8/U2TX/CN18/RF5
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Table Contents
Device Overview CPU. Memory Organization Flash Program Memory. Resets Interrupt Controller Oscillator Configuration Power-Saving Features. Ports 10.0 Timer1 11.0 Timer2/3 Timer4/5 12.0 Input Capture. 13.0 Output Compare. 14.0 Serial Peripheral Interface (SPI). 15.0 Inter-Integrated Circuit (I2CTM) 16.0 Universal Asynchronous Receiver Transmitter (UART) 17.0 Parallel Master Port (PMP). 18.0 Real-Time Clock Calendar (RTCC). 19.0 Programmable Cyclic Redundancy Check (CRC) Generator 20.0 10-bit High-Speed Converter. 21.0 Comparator Module. 22.0 Comparator Voltage Reference. 23.0 Special Features 24.0 Instruction Summary 25.0 Development Support. 26.0 Electrical Characteristics 27.0 Packaging Information. Appendix Revision History. Index Microchip Site Customer Change Notification Service Customer Support Reader Response Product Identification System
2009 Microchip Technology Inc.
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Most Current Data Sheet
obtain most up-to-date version this data sheet, please register Worldwide site http://www.microchip.com determine version data sheet examining literature number found bottom outside corner page. last character literature number version number, (e.g., DS30000A version document DS30000).
Errata
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DEVICE OVERVIEW
1.1.2 POWER-SAVING TECHNOLOGY
This document contains device-specific information following devices: PIC24FJ64GA006 PIC24FJ64GA008 PIC24FJ64GA010 PIC24FJ96GA006 PIC24FJ96GA008 PIC24FJ96GA010 PIC24FJ128GA006 PIC24FJ128GA008 PIC24FJ128GA010 devices PIC24FJ128GA010 family incorporate range features that significantly reduce power consumption during operation. items include: On-the-Fly Clock Switching: device clock changed under software control Timer1 source internal low-power oscillator during operation, allowing user incorporate power-saving ideas into their software designs. Doze Mode Operation: When timing-sensitive applications, such serial communications, require uninterrupted operation peripherals, clock speed selectively reduced, allowing incremental power savings without missing beat. Instruction-Based Power-Saving Modes: microcontroller suspend operations, selectively shut down core while leaving peripherals active, with single instruction software.
This family introduces line Microchip devices: 16-bit microcontroller family with broad peripheral feature enhanced computational performance. PIC24FJ128GA010 family offers migration option those high-performance applications which outgrowing their 8-bit platforms, don't require numerical processing power digital signal processor.
1.1.1
Core Features
16-BIT ARCHITECTURE
1.1.3
OSCILLATOR OPTIONS FEATURES
Central PIC24F devices 16-bit modified Harvard architecture, first introduced with Microchip's dsPIC® digital signal controllers. PIC24F core offers wide range enhancements, such 16-bit data 24-bit address paths, with ability move information between data memory spaces Linear addressing Mbytes (program space) Kbytes (data) 16-element working register array with built-in software stack support hardware multiplier with support integer math Hardware support 16-bit division instruction that supports multiple addressing modes optimized high-level languages such Operational performance MIPS
devices PIC24FJ128GA010 family offer five different oscillator options, allowing users range choices developing application hardware. These include: Crystal modes using crystals ceramic resonators. External Clock modes offering option divide-by-2 clock output. Fast Internal Oscillator (FRC) with nominal output, which also divided under software control provide clock speeds kHz. Phase Lock Loop (PLL) frequency multiplier, available external oscillator modes oscillator, which allows clock speeds MHz. separate internal oscillator (LPRC) with fixed output, which provides low-power option timing-insensitive applications. internal oscillator block also provides stable reference source Fail-Safe Clock Monitor. This option constantly monitors main clock source against reference signal provided internal oscillator enables controller switch internal oscillator, allowing continued low-speed operation safe application shutdown.
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1.1.4 EASY MIGRATION
Regardless memory size, devices share same rich peripherals, allowing smooth migration path applications grow evolve. consistent pinout scheme used throughout entire family also aids migrating next larger device. This true when moving between devices with same count, even jumping from 64-pin 80-pin 100-pin devices. PIC24F family pin-compatible with devices dsPIC33 family, shares some compatibility with pinout schema PIC18 dsPIC30. This extends ability applications grow from relatively simple, powerful complex, still selecting Microchip device.
Details Individual Family Members
Devices PIC24FJ128GA010 family available 64-pin, 80-pin 100-pin packages. general block diagram devices shown Figure 1-1. devices differentiated from each other ways: Flash program memory Kbytes PIC24FJ64GA devices, Kbytes PIC24FJ96GA devices Kbytes PIC24FJ128GA devices). Available pins ports pins ports 64-pin devices, pins ports 80-pin devices pins ports 100-pin devices). Note also that, since interrupt-on-change inputs available every this family devices, number inputs also differs between package sizes.
Other Special Features
Communications: PIC24FJ128GA010 family incorporates range serial communication peripherals handle range application requirements. devices equipped with independent UARTs with built-in IrDA encoder/decoders. There also independent modules, independent modules that support both Master Slave modes operation. Parallel Master/Enhanced Parallel Slave Port: general purpose ports reconfigured enhanced parallel data communications. this mode, port configured both master slave operations, supports 8-bit 16-bit data transfers with external address lines Master modes. Real-Time Clock/Calendar: This module implements full-featured clock calendar with alarm functions hardware, freeing timer resources program memory space core application. 10-Bit Converter: This module incorporates programmable acquisition time, allowing channel selected conversion initiated without waiting sampling period, well faster sampling speeds.
other features devices this family identical. These summarized Table 1-1. list features available PIC24FJ128GA010 family devices, sorted function, shown Table 1-2. Note that this table shows location individual peripheral features they multiplexed same pin. This information provided pinout diagrams beginning data sheet. Multiplexed features sorted priority given feature, with highest priority peripheral being listed first.
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TABLE 1-1: DEVICE FEATURES PIC24FJ128GA010 FAMILY
PIC24FJ128GA006 PIC24FJ128GA008 PIC24FJ128GA010 128K 44,032 PIC24FJ64GA006 PIC24FJ96GA006 PIC24FJ64GA008 PIC24FJ96GA008 PIC24FJ64GA010 PIC24FJ96GA010 32,768 100-Pin TQFP
Features
Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Interrupt Sources (Soft Vectors/NMI Traps) Ports Total Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART (3-wire/4-wire) I2CParallel Communications (PMP/PSP) JTAG Boundary Scan 10-Bit Analog-to-Digital Module (input channels) Analog Comparators Resets (and Delays) Instruction Packages Ports 22,016 32,768 128K 44,032
32,768 8192 (39/4) Ports Ports 128K 44,032 22,016 22,016
POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, Configuration Word Mismatch, Repeat instruction, Hardware Traps (PWRT, OST, Lock) Base Instructions, Multiple Addressing Mode Variations 64-Pin TQFP 80-Pin TQFP
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PIC24FJ128GA010 FAMILY
FIGURE 1-1: PIC24FJ128GA010 FAMILY GENERAL BLOCK DIAGRAM
Data
PORTA(1) Table Data Access Control Block Data Latch Program Counter Repeat Stack Control Control Logic Logic Data Address Latch Read Write PORTC RC1:RC4, RC12:RC15 PORTB(1) RB0:RB15 RA0:RA7, RA9:RA10, RA14:15
Interrupt Controller
Address Latch Program Memory Data Latch
Address
Inst Latch Inst Register Instruction Decode Control Control Signals Timing Generation FRC/LPRC Oscillators Precision Band Reference ENVREG Voltage Regulator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset(2) Literal Data
PORTD(1) RD0:RD15
PORTE(1) RE0:RE9
Divide Support 17x17 Multiplier
Array PORTF(1) RF0:RF8, RF12:RF13 16-Bit PORTG(1) RG0:RG9, RG12:RG15
OSC2/CLKO OSC1/CLKI
VDDCORE/VCAP
VDD,
MCLR
Timer1
Timer2/3
Timer4/5
RTCC
10-Bit
Comparators
PMP/PSP PWM/ OC1-5
IC1-5
CN1-22(1)
SPI1/2
I2C1/2
UART1/2
Note
pins features implemented device pinout configurations. Table port descriptions. functionality provided when on-board voltage regulator enabled.
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TABLE 1-2:
Function AN10 AN11 AN12 AN13 AN14 AN15 AVDD AVSS BCLK1 BCLK2 C1INC1IN+ C1OUT C2INC2IN+ C2OUT CLKI CLKO CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 Legend:
PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS
Number 64-Pin 80-Pin 100-Pin Input Buffer Schmitt Trigger input buffer I2C= I2C/SMBus input buffer Positive Supply Analog Modules. Ground Reference Analog Modules. UART1 IrDA® Baud Clock. UART2 IrDA® Baud Clock. Comparator Negative Input. Comparator Positive Input. Comparator Output. Comparator Negative Input. Comparator Positive Input. Comparator Output. Main Clock Input Connection. System Clock Output. Interrupt-on-Change Inputs. Analog Inputs. Description
input buffer Analog level input/output
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TABLE 1-2:
Function CN18 CN19 CN20 CN21 CVREF EMUC1 EMUD1 EMUC2 EMUD2 ENVREG INT0 INT1 INT2 INT3 INT4 MCLR OCFA OCFB OSC1 OSC2 PGC1 PGD1 PGC2 PGD2 Legend:
PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number 64-Pin 80-Pin 100-Pin Input Buffer Output Compare Fault Input. Output Compare Fault Input. Main Oscillator Input Connection. Main Oscillator Output Connection. In-Circuit Debugger ICSPProgramming Clock. In-Circuit Debugger ICSP Programming Data. In-Circuit Debugger ICSPProgramming Clock. In-Circuit Debugger ICSP Programming Data. Master Clear (Device Reset) Input. This line brought cause Reset. Output Compare/PWM Outputs. External Interrupt Inputs. Comparator Voltage Reference Output. In-Circuit Emulator Clock Input/Output. In-Circuit Emulator Data Input/Output. In-Circuit Emulator Clock Input/Output. In-Circuit Emulator Data Input/Output. Enable On-Chip Voltage Regulator. Input Capture Inputs. Description Interrupt-on-Change Inputs.
input buffer Analog level input/output
Schmitt Trigger input buffer I2C= I2C/SMBus input buffer
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TABLE 1-2:
Function PMA0 PMA1 PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMBE PMCS1 PMCS2 PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMRD PMWR Legend:
PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number 64-Pin 80-Pin 100-Pin Input Buffer ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL Parallel Master Port Read Strobe. Parallel Master Port Write Strobe. Parallel Master Port Byte Enable Strobe. Parallel Master Port Chip Select Strobe/Address Parallel Master Port Chip Select Strobe/Address Parallel Master Port Data (Demultiplexed Master mode) Address/Data (Multiplexed Master modes). Description Parallel Master Port Address Input (Buffered Slave modes) Output (Master modes). Parallel Master Port Address Input (Buffered Slave modes) Output (Master modes). Parallel Master Port Address (Demultiplexed Master modes).
input buffer Analog level input/output
Schmitt Trigger input buffer I2C= I2C/SMBus input buffer
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PIC24FJ128GA010 FAMILY
TABLE 1-2:
Function RA10 RA14 RA15 RB10 RB11 RB12 RB13 RB14 RB15 RC12 RC13 RC14 RC15 Legend:
PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number 64-Pin 80-Pin 100-Pin Input Buffer Schmitt Trigger input buffer I2C= I2C/SMBus input buffer PORTC Digital I/O. PORTB Digital I/O. PORTA Digital I/O. Description
input buffer Analog level input/output
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TABLE 1-2:
Function RD10 RD11 RD12 RD13 RD14 RD15 RF12 RF13 Legend:
PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number 64-Pin 80-Pin 100-Pin Input Buffer Schmitt Trigger input buffer I2C= I2C/SMBus input buffer PORTF Digital I/O. PORTE Digital I/O. PORTD Digital I/O. Description
input buffer Analog level input/output
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TABLE 1-2:
Function RG12 RG13 RG14 RG15 RTCC SCK1 SCK2 SCL1 SCL2 SDA1 SDA2 SDI1 SDI2 SDO1 SDO2 SOSCI SOSCO T1CK T2CK T3CK T4CK T5CK Legend:
PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number 64-Pin 80-Pin 100-Pin Input Buffer
Description PORTG Digital I/O.
Real-Time Clock Alarm Output. SPI1 Serial Clock Output. SPI2 Serial Clock Output. I2C1 Synchronous Serial Clock Input/Output. I2C2 Synchronous Serial Clock Input/Output. I2C1 Data Input/Output. I2C2 Data Input/Output. SPI1 Serial Data Input. SPI2 Serial Data Input. SPI1 Serial Data Output. SPI2 Serial Data Output. Secondary Oscillator/Timer1 Clock Input. Secondary Oscillator/Timer1 Clock Output. Slave Select Input/Frame Select Output (SPI1). Slave Select Input/Frame Select Output (SPI2). Timer1 Clock. Timer2 External Clock Input. Timer3 External Clock Input. Timer4 External Clock Input. Timer5 External Clock Input. JTAG Test Clock/Programming Clock Input. JTAG Test Data/Programming Data Input. JTAG Test Data Output. JTAG Test Mode Select Input.
input buffer Analog level input/output
Schmitt Trigger input buffer I2C= I2C/SMBus input buffer
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TABLE 1-2:
Function U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX VDDCAP VDDCORE VREFVREF+ Legend:
PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number 64-Pin 80-Pin 100-Pin Input Buffer Description UART1 Clear Send Input. UART1 Request Send Output. UART1 Receive. UART1 Transmit Output. UART2 Clear Send Input. UART2 Request Send Output. UART Receive Input. UART2 Transmit Output. Positive Supply Peripheral Digital Logic Pins. External Filter Capacitor Connection (regulator enabled). Positive Supply Microcontroller Core Logic (regulator disabled). Comparator Reference Voltage (Low) Input. Comparator Reference Voltage (High) Input. Ground Reference Logic Pins.
input buffer Analog level input/output
Schmitt Trigger input buffer I2C= I2C/SMBus input buffer
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NOTES:
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Note:
This data sheet summarizes features this group PIC24F devices. intended comprehensive reference source. Refer Section "CPU" (DS39703) "PIC24F Family Reference Manual" more information.
most instructions, core capable executing data program data) memory read, working register (data) read, data memory write program (instruction) memory read instruction cycle. result, three-parameter instructions supported, allowing trinary operations (that executed single cycle. high-speed, 17-bit 17-bit multiplier been included significantly enhance core arithmetic capability throughput. multiplier supports signed, unsigned Mixed mode 16-bit 16-bit 8-bit 8-bit integer multiplication. multiply instructions execute single cycle. 16-bit been enhanced with integer divide assist hardware that supports iterative, non-restoring divide algorithm. operates conjunction with REPEAT instruction looping mechanism, selection iterative divide instructions, support 32-bit 16-bit) divided 16-bit integer signed unsigned division. divide operations require cycles complete interruptible cycle boundary. PIC24F vectored exception scheme with sources non-maskable traps interrupt sources. Each interrupt source assigned seven priority levels. block diagram shown Figure 2-1.
PIC24F 16-bit (data) modified Harvard architecture with enhanced instruction set, 24-bit instruction word with variable length opcode field. Program Counter (PC) bits wide addresses instructions user program memory space. single-cycle instruction prefetch mechanism used help maintain throughput provides predictable execution. instructions execute single cycle, with exception instructions that change program flow, double-word move (MOV.D) instruction table instructions. Overhead-free program loop constructs supported using REPEAT instructions, which interruptible point. PIC24F devices have sixteen 16-bit working registers programmer's model. Each working registers data, address address offset register. 16th working register (W15) operates Software Stack Pointer interrupts calls. upper Kbytes data space memory optionally mapped into program space word boundary defined 8-bit Program Space Visibility Page (PSVPAG) register. program data space mapping feature lets instruction access program space were data space. Instruction Architecture (ISA) been significantly enhanced beyond that PIC18, maintains acceptable level backward compatibility. PIC18 instructions addressing modes supported either directly through simple macros. Many enhancements have been driven compiler efficiency needs. core supports Inherent operand), Relative, Literal, Memory Direct three groups addressing modes. modes support Register Direct various Register Indirect modes. Each group offers addressing modes. Instructions associated with predefined addressing modes depending upon their functional requirements.
Programmer's Model
programmer's model PIC24F shown Figure 2-2. registers programmer's model memory mapped manipulated directly instructions. description each register provided Table 2-1. registers associated with programmer's model memory mapped.
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FIGURE 2-1:
Table Data Access Control Block Interrupt Controller Program Counter Loop Stack Control Control Logic Logic Data Address Latch RAGU WAGU Data Data Latch
PIC24F CORE BLOCK DIAGRAM
Address Latch
Program Memory Address Data Latch Latch Literal Data
Instruction Decode Control
Instruction
Control Signals Various Blocks
Hardware Multiplier Divide Support
Register Array
16-Bit
Peripheral Modules
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TABLE 2-1:
through SPLIM TBLPAG PSVPAG RCOUNT CORCON
CORE REGISTERS
Description Working Register Array 23-Bit Program Counter STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register Control Register
Register(s) Name
FIGURE 2-2:
PROGRAMMER'S MODEL
(WREG) Frame Pointer Stack Pointer Working/Address Registers
Divider Working Registers
Multiplier Registers
SPLIM TBLPAG PSVPAG RCOUNT
Stack Pointer Limit
Program Counter
Data Table Page Address Program Space Visibility Page Address Repeat Loop Counter STATUS Register (SR)
Core Control Register (CORCON)
IPL3
Registers bits shadowed PUSH.S POP.S instructions.
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Control Registers
STATUS REGISTER
R/W-0 R/W-0(1) IPL1(2) R/W-0(1) IPL0(2) R/W-0 R/W-0 R/W-0 R/W-0
REGISTER 2-1:
R/W-0(1) IPL2(2) Legend: Readable Value 15-9
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read Half Carry/Borrow carry-out from low-order (for byte-sized data) low-order (for word-sized data) result occurred carry-out from low-order result occurred IPL2:IPL0: Interrupt Priority Level Status bits(2) interrupt priority level (15). User interrupts disabled. interrupt priority level (14) interrupt priority level (13) interrupt priority level (12) interrupt priority level (11) interrupt priority level (10) interrupt priority level interrupt priority level REPEAT Loop Active REPEAT loop progress REPEAT loop progress Negative Result negative Result non-negative (zero positive) Overflow Overflow occurred signed (2's complement) arithmetic this arithmetic operation overflow occurred Zero operation which effects some time past most recent operation which effects cleared (i.e., non-zero result) Carry/Borrow carry-out from Most Significant result occurred carry-out from Most Significant result occurred Status bits read-only when NSTDIS (INTCON1<15>) bits concatenated with IPL3 (CORCON<3>) form interrupt priority level. value parentheses indicates when IPL3
Note
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REGISTER 2-2:
Legend: Readable Value 15-4 Clearable Writable Unimplemented bit, read cleared unknown R/C-0 IPL3(1) R/W-0
CORCON: CORE CONTROL REGISTER
Unimplemented: Read IPL3: Interrupt Priority Level Status bit(1) interrupt priority level greater than interrupt priority level less PSV: Program Space Visibility Data Space Enable Program space visible data space Program space visible data space Unimplemented: Read User interrupts disabled when IPL3
Note
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Arithmetic Logic Unit (ALU)
2.3.2 DIVIDER
PIC24F bits wide capable addition, subtraction, shifts logic operations. Unless otherwise mentioned, arithmetic operations complement nature. Depending operation, affect values Carry (C), Zero (Z), Negative (N), Overflow (OV) Digit Carry (DC) Status bits register. Status bits operate Borrow Digit Borrow bits, respectively, subtraction operations. perform 8-bit 16-bit operations, depending mode instruction that used. Data operation come from register array, data memory, depending addressing mode instruction. Likewise, output data from written register array data memory location. PIC24F incorporates hardware support both multiplication division. This includes dedicated hardware multiplier support hardware 16-bit divisor division. divide block supports 32-bit/16-bit 16-bit/16-bit signed unsigned integer divide operation with following data sizes: 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide
quotient divide instructions ends remainder 16-bit signed unsigned instructions specify register both 16-bit divisor (Wn) register (aligned) pair (W(m+1):Wm) 32-bit dividend. divide algorithm takes cycle divisor, both 32-bit/16-bit 16-bit/16-bit instructions take same number cycles execute.
2.3.3
MULTI-BIT SHIFT SUPPORT
2.3.1
MULTIPLIER
contains high-speed, 17-bit 17-bit multiplier. supports unsigned, signed mixed sign operation several multiplication modes: 16-bit 16-bit signed 16-bit 16-bit unsigned 16-bit signed 5-bit (literal) unsigned 16-bit unsigned 16-bit unsigned 16-bit unsigned 5-bit (literal) unsigned 16-bit unsigned 16-bit signed 8-bit unsigned 8-bit unsigned
PIC24F supports both single single-cycle, multi-bit arithmetic logic shifts. Multi-bit shifts implemented using shifter block, capable performing 15-bit arithmetic right shift, 15-bit left shift, single cycle. multi-bit shift instructions only support Register Direct Addressing both operand source result destination. full summary instructions that shift operation provided below Table 2-2.
TABLE 2-2:
Instruction
INSTRUCTIONS THAT SINGLE MULTI-BIT SHIFT OPERATION
Description Arithmetic shift right source register more bits. Shift left source register more bits. Logical shift right source register more bits.
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MEMORY ORGANIZATION
Harvard architecture devices, PIC24F microcontrollers feature separate program data memory spaces busses. This architecture also allows direct access program memory from data space during code execution. either 23-bit Program Counter (PC) during program execution, from table operation data space remapping, described Section "Interfacing Program Data Memory Spaces". User access program memory space restricted lower half address range (000000h 7FFFFFh). exception TBLRD/TBLWT operations, which TBLPAG<7> permit access Configuration bits Device sections configuration memory space. Memory maps PIC24FJ128GA010 family devices shown Figure 3-1.
Program Address Space
program address memory space PIC24FJ128GA010 family devices instructions. space addressable 24-bit value derived from
FIGURE 3-1:
PROGRAM SPACE MEMORY PIC24FJ128GA010 FAMILY DEVICES
PIC24FJ64GA
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory (22K instructions) Flash Config Words
PIC24FJ96GA
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory (32K instructions)
PIC24FJ128GA
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table 000000h 000002h 000004h 0000FEh 000100h 000104h 0001FEh 000200h
User Memory Space
User Flash Program Memory (44K instructions)
00ABFEh 00AC00h 00FFFEh 010000h
Flash Config Words Flash Config Words Unimplemented (Read `0's) Unimplemented (Read `0's) Unimplemented (Read `0's)
0157FEh 015800h
7FFFFEh 800000h
Reserved
Reserved
Reserved
Configuration Memory Space
Device Configuration Registers
Device Configuration Registers
Device Configuration Registers
F7FFFEh F80000h F8000Eh F80010h
Reserved
Reserved
Reserved
DEVID
DEVID
DEVID
FEFFFEh FF0000h FFFFFEh
Note:
Memory areas shown scale.
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3.1.1 PROGRAM MEMORY ORGANIZATION 3.1.3 FLASH CONFIGURATION WORDS
program memory space organized word-addressable blocks. Although treated bits wide, more appropriate think each address program memory lower upper word, with upper byte upper word being unimplemented. lower word always even address, while upper word address (Figure 3-2). Program memory addresses always word-aligned lower word, addresses incremented decremented during code execution. This arrangement also provides compatibility with data memory space addressing makes possible access data program memory space. PIC24FJ128GA010 family devices, words on-chip program memory reserved configuration information. device Reset, configuration information copied into appropriate Configuration registers. addresses Flash Configuration Word devices PIC24FJ128GA010 family shown Table 3-1. Their location memory shown with other memory vectors Figure 3-1. Configuration Words program memory compact format. actual Configuration bits mapped several different registers configuration memory space. Their order Flash Configuration Words reflect corresponding arrangement configuration space. Additional details device Configuration Words provided Section 23.1 "Configuration Bits".
3.1.2
HARD MEMORY VECTORS
PIC24F devices reserve addresses between 00000h 000200h hard coded program execution vectors. hardware Reset vector provided redirect code execution from default value device Reset actual start code. GOTO instruction programmed user 000000h, with actual address start code 000002h. PIC24F devices also have interrupt vector tables, located from 000004h 0000FFh 000100h 0001FFh. These vector tables allow each many device interrupt sources handled separate ISRs. more detailed discussion interrupt vector tables provided Section "Interrupt Vector Table".
TABLE 3-1:
FLASH CONFIGURATION WORDS PIC24FJ128GA010 FAMILY DEVICES
Program Memory (Words) 22,016 32,768 44,032 Configuration Word Addresses 00ABFCh: 00ABFEh 00FFFCh: 00FFFEh 0157FCh: 0157FEh
Device PIC24FJ64GA PIC24FJ96GA PIC24FJ128GA
FIGURE 3-2:
Address 000001h 000003h 000005h 000007h
PROGRAM MEMORY ORGANIZATION
most significant word 00000000 00000000 00000000 00000000 Program Memory `Phantom' Byte (read `0') Instruction Width least significant word 000000h 000002h 000004h 000006h Address (lsw Address)
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Note:
Data Address Space
This data sheet summarizes features this group PIC24F devices. intended comprehensive reference source. Refer Section "Data Memory" (DS39717) "PIC24F Family Reference Manual" more information.
memory space (that when EA<15> used implemented memory addresses, while upper half (EA<15> reserved Program Space Visibility area (see Section 3.3.3 "Reading Data from Program Memory Using Program Space Visibility"). PIC24FJ128GA010 family devices implement total Kbytes data memory. Should point location outside this area, zero word byte will returned.
PIC24F core separate, 16-bit wide data memory space, addressable single linear range. data space accessed using Address Generation Units (AGUs), each read write operations. data space memory shown Figure 3-3. Effective Addresses (EAs) data memory space bits wide, point bytes within data space. This gives data space address range Kbytes, words. lower half data
3.2.1
DATA SPACE WIDTH
data memory space organized byte-addressable, 16-bit wide blocks. Data aligned data memory registers 16-bit words, data space resolve bytes. Least Significant Bytes each word have even addresses, while Most Significant Bytes have addresses.
FIGURE 3-3:
DATA SPACE MEMORY PIC24FJ128GA010 FAMILY DEVICES
Address 0001h 07FFh 0801h Space Address 0000h 07FEh 0800h Space Near Data Space
Implemented Data
Data 1FFFh 2001h 27FFh 2801h Unimplemented Read 7FFFh 8001h 7FFFh 8000h 1FFEh 2000h 27FEh 2800h
Program Space Visibility Area
FFFFh Note: Data memory areas shown scale.
FFFEh
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3.2.2 DATA MEMORY ORGANIZATION ALIGNMENT
maintain backward compatibility with PIC® devices improve data space memory usage efficiency, PIC24F instruction supports both word byte operations. consequence byte accessibility, effective address calculations internally scaled step through word-aligned memory. example, core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result value byte operations word operations. Data byte reads will read complete word which contains byte, using determine which byte select. selected byte placed onto data path. That data memory registers organized parallel byte-wide entities with shared (word) address decode separate write lines. Data byte writes only write corresponding side array register which matches byte address. word accesses must aligned even address. Misaligned word data fetches supported, care must taken when mixing byte word operations, translating from 8-bit code. misaligned read write attempted, address error trap will generated. error occurred read, instruction underway completed; occurred write, instruction will executed write will occur. either case, trap then executed, allowing system and/or user examine machine state prior execution address Fault. byte loads into register loaded into Least Significant Byte. Most Significant Byte modified. sign-extend instruction (SE) provided allow users translate 8-bit signed data 16-bit signed values. Alternatively, 16-bit unsigned data, users clear register executing zero-extend (ZE) instruction appropriate address. Although most instructions capable operating word byte data sizes, should noted that some instructions operate only words.
3.2.3
NEAR DATA SPACE
8-Kbyte area between 0000h 1FFFh referred near data space. Locations this space directly addressable 13-bit absolute address field within memory direct instructions. remainder data space addressable indirectly. Additionally, whole data space addressable using instructions, which support Memory Direct Addressing with 16-bit address field.
3.2.4
SPACE
first Kbytes near data space, from 0000h 07FFh, primarily occupied with Special Function Registers (SFRs). These used PIC24F core peripheral modules controlling operation device. SFRs distributed among modules that they control, generally grouped together module. Much space contains unused addresses; these read `0'. diagram space, showing where SFRs actually implemented, shown Table 3-2. Each implemented area indicates 32-byte region where least address implemented SFR. complete listing implemented SFRs, including their addresses, shown Tables through 3-30.
TABLE 3-2:
IMPLEMENTED REGIONS DATA SPACE
Space Address xx00 xx20 Core Timers
2C
xx40 Capture
xx60 NVM/PMD
xx80 Compare
xxA0 Interrupts
xxC0
xxE0
000h 100h 200h 300h 400h 500h 600h 700h
UART RTC/Comp System
Legend: implemented SFRs this block
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TABLE 3-3:
File Name WREG0 WREG1 WREG2 WREG3 WREG4 WREG5 WREG6 WREG7 WREG8 WREG9 WREG10 WREG11 WREG12 WREG13 WREG14 WREG15 SPLIM TBLPAG PSVPAG RCOUNT CORCON DISICNT Legend: Addr 0000 0002 0004 0006 0008 000A 000C 000E 0010 0012 0014 0016 0018 001A 001C 001E 0020 002E 0030 0032 0034 0036 0042 0044 0052
CORE REGISTERS
Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Stack Pointer Limit Program Counter Word Repeat Loop Counter IPL2 IPL1 IPL0 IPL3 Program Counter High Byte Table Page Address Pointer Program Memory Visibility Page Address Pointer
PIC24FJ128GA010 FAMILY
0000 0000 0000 0800 xxxx 0000 0000 0000 0000 xxxx 0000 0000 xxxx
Disable Interrupts Counter
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-4:
File Name INTCON1 INTCON2 IFS0 IFS1 IFS2 IFS3 IFS4 IEC0 IEC1 IEC2 IEC3 IEC4 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC9 IPC10 IPC11 IPC12 IPC13 Addr 0080 0082 0084 0086 0088 008A 008C 0094 0096 0098 009A 009C 00A4 00A6 00A8 00AA 00AC 00AE 00B0 00B2 00B4 00B6 00B8 00BA 00BC 00BE 00C2 00C4
INTERRUPT CONTROLLER REGISTER
NSTDIS ALTIVT U2TXIF U2TXIE DISI U2RXIF RTCIF U2RXIE RTCIE T1IP2 T2IP2 CNIP2 T4IP2 U2TXIP2 IC5IP2 CRCIP2 AD1IF INT2IF PMPIF AD1IE INT2IE PMPIE T1IP1 T2IP1 CNIP1 T4IP1 U2TXIP1 IC5IP1 CRCIP1 U1TXIF T5IF U1TXIE T5IE T1IP0 T2IP0 CNIP0 T4IP0 U2TXIP0 IC5IP0 CRCIP0 U1RXIF T4IF U1RXIE T4IE SPI1IF OC4IF SPI1IE OC4IE OC1IP2 OC2IP2 SPI1IP2 CMIP2 OC4IP2 IC4IP2 INT4IP2 RTCIP2 SPF1IF OC3IF OC5IF SPF1IE OC3IE OC5IE OC1IP1 OC2IP1 SPI1IP1 CMIP1 OC4IP1 IC4IP1 INT4IP1 RTCIP1 T3IF T3IE OC1IP0 OC2IP0 SPI1IP0 CMIP0 OC4IP0 IC4IP0 INT4IP0 RTCIP0 T2IF IC5IF T2IE IC5IE OC2IF IC4IF INT4IF OC2IE IC4IE INT4IE IC1IP2 IC2IP2 SPF1IP2 AD1IP2 OC3IP2 INT2IP2 SPI2IP2 IC3IP2 OC5IP2 PMPIP2 INT3IP2 IC2IF IC3IF INT3IF IC2IE IC3IE INT3IE IC1IP1 IC2IP1 SPF1IP1 AD1IP1 OC3IP1 INT2IP1 SPI2IP1 IC3IP1 OC5IP1 PMPIP1 INT3IP1 INT0EP INT0IF SI2C1IF SPF2IF INT0IE SI2C1IE SPF2IE INT0IP0 T3IP0 U1TXIP0 INT1IP0 T5IP0 SPF2IP0 Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4440 4444 0044 4444 0004 4440 4444 0044 4440 0040 0040 0440 0440 0400 4440
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MATHERR ADDRERR STKERR OSCFAIL INT4EP INT1IF INT1IE IC1IP0 IC2IP0 SPF1IP0 AD1IP0 OC3IP0 INT2IP0 SPI2IP0 IC3IP0 OC5IP0 PMPIP0 SI2C2IP0 INT3IP0 U1ERIP0 INT3EP T1IF CNIF CRCIF T1IE CNIE CRCIE INT2EP OC1IF CMIF MI2C2IF U2ERIF OC1IE CMIE MI2C2IE U2ERIE INT0IP2 T3IP2 U1TXIP2 INT1IP2 T5IP2 SPF2IP2 INT1EP IC1IF MI2C1IF SPI2IF SI2C2IF U1ERIF IC1IE MI2C1IE SPI2IE SI2C2IE U1ERIE INT0IP1 T3IP1 U1TXIP1 INT1IP1 T5IP1 SPF2IP1
U1RXIP2 U1RXIP1 U1RXIP0
MI2C1IP2 MI2C1IP1 MI2C1IP0
SI2C1IP2 SI2C1IP1 SI2C1IP0
U2RXIP2 U2RXIP1 U2RXIP0
MI2C2IP2 MI2C2IP1 MI2C2IP0
SI2C2IP2 SI2C2IP1
IPC15 IPC16 Legend:
U2ERIP2 U2ERIP1 U2ERIP0
U1ERIP2 U1ERIP1
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-5:
File Name Addr
REGISTER
CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN21IE(1) CN5PUE CN4IE CN20IE(1) CN4PUE CN3IE CN19IE(1) CN3PUE CN2IE CN18IE CN2PUE CN1IE CN17IE CN1PUE CN0IE CN16IE CN0PUE Resets 0000 0000 0000 0000
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CNEN1 0060 CNEN2 0062 CNPU2 006A Legend: Note
CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE unimplemented, read `0'. Reset values shown hexadecimal Implemented 80-pin 100-pin devices only.
CN21PUE(1) CN20PUE(1) CN19PUE(1) CN18PUE CN17PUE CN16PUE
TABLE 3-6:
File Name TMR1 T1CON TMR2 TMR3HLD TMR3 T2CON T3CON TMR4 TMR5HLD TMR5 T4CON T5CON Legend: Addr 0100 0102 0104 0106 0108 010A 010C 010E 0110 0112 0114 0116 0118 011A 011C 011E 0120
TIMER REGISTER
Resets xxxx FFFF
Timer1 Register Period Register TSIDL TGATE TCKPS1 TCKPS0 TSYNC Timer2 Register Timer3 Holding Register (For 32-bit timer operations only) Timer3 Register Period Register Period Register TSIDL TSIDL TGATE TGATE TCKPS1 TCKPS1 TCKPS0 TCKPS0
PIC24FJ128GA010 FAMILY
0000 xxxx xxxx xxxx FFFF FFFF 0000 0000 xxxx xxxx xxxx FFFF FFFF
Timer4 Register Timer5 Holding Register (For 32-bit operations only) Timer5 Register Period Register Period Register TSIDL TSIDL TGATE TGATE TCKPS1 TCKPS1 TCKPS0 TCKPS0
0000 0000
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-7:
File Name IC1BUF IC1CON IC2BUF IC2CON IC3BUF IC3CON IC4BUF IC4CON IC5BUF IC5CON Legend: Addr 0140 0142 0144 0146 0148 014A 014C 014E 0150 0152
INPUT CAPTURE REGISTER
Resets xxxx ICI1 ICI1 ICI1 ICI1 ICI1 ICI0 ICI0 ICI0 ICI0 ICI0 ICOV ICOV ICOV ICOV ICOV ICBNE ICBNE ICBNE ICBNE ICBNE ICM2 ICM2 ICM2 ICM2 ICM2 ICM1 ICM1 ICM1 ICM1 ICM1 ICM0 ICM0 ICM0 ICM0 ICM0 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000
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Input Capture Register ICSIDL ICSIDL ICSIDL ICSIDL ICSIDL ICTMR ICTMR ICTMR ICTMR ICTMR Input Capture Register Input Capture Register Input Capture Register Input Capture Register
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-8:
File Name OC1RS OC1R OC1CON OC2RS OC2R OC2CON OC3RS OC3R OC3CON OC4RS OC4R OC4CON OC5RS OC5R OC5CON Legend: Addr 0180 0182 0184 0186 0188 018A 018C 018E 0190 0192 0194 0196 0198 019A 019C
OUTPUT COMPARE REGISTER
Resets xxxx xxxx OCFLT OCTSEL OCM2 OCM1 OCM0 0000 xxxx xxxx OCFLT OCTSEL OCM2 OCM1 OCM0 0000 xxxx xxxx OCFLT OCTSEL OCM2 OCM1 OCM0 0000 xxxx xxxx OCFLT OCTSEL OCM2 OCM1 OCM0 0000 xxxx xxxx OCFLT OCTSEL OCM2 OCM1 OCM0 0000
Output Compare Secondary Register Output Compare Register OCSIDL Output Compare Secondary Register Output Compare Register OCSIDL Output Compare Secondary Register Output Compare Register OCSIDL Output Compare Secondary Register Output Compare Register OCSIDL Output Compare Secondary Register Output Compare Register OCSIDL
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
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TABLE 3-9:
File Name I2C1RCV I2C1TRN I2C1BRG I2C1CON I2C1STAT I2C1ADD I2C1MSK Legend: Addr 0200 0202 0204 0206 0208 020A 020C
I2C1 REGISTER
I2CEN ACKSTAT TRSTAT I2CSIDL SCLREL IPMIEN A10M DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV ACKDT Resets 0000 00FF 0000 RSEN 1000 0000 0000 0000
Receive Register Transmit Register Baud Rate Generator ACKEN RCEN
Address Register Address Mask
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-10:
File Name I2C2RCV I2C2TRN I2C2BRG I2C2CON I2C2STAT I2C2ADD I2C2MSK Legend: Addr 0210 0212 0214 0216 0218 021A 021C
I2C2 REGISTER
I2CEN ACKSTAT TRSTAT I2CSIDL SCLREL IPMIEN A10M DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2CPOV ACKDT Resets 0000 00FF 0000 RSEN 1000 0000 0000 0000
PIC24FJ128GA010 FAMILY
Receive Register Transmit Register Baud Rate Generator ACKEN RCEN
Address Register Address Mask
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-11:
File Name U1MODE U1STA U1TXREG U1RXREG U1BRG Legend: Addr 0220 0222 0224 0226 0228
UART1 REGISTER
UARTEN UTXISEL1 TXINV USIDL UTXISEL0 IREN RTSMD UTXBRK UTXEN UEN1 UTXBF Baud Rate Generator Prescaler UEN0 TRMT WAKE LPBACK ABAUD ADDEN RXINV RIDLE BRGH PERR PDSEL1 FERR PDSEL0 OERR STSEL URXDA Resets 0000 0110 xxxx 0000 0000
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URXISEL1 URXISEL0
Transmit Register Receive Register
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-12:
File Name U2MODE U2STA U2TXREG U2RXREG U2BRG Legend: Addr 0230 0232 0234 0236 0238
UART2 REGISTER
UARTEN UTXISEL1 TXINV USIDL UTXISEL0 IREN RTSMD UTXBRK UTXEN UEN1 UTXBF Baud Rate Generator Prescaler UEN0 TRMT WAKE LPBACK ABAUD ADDEN RXINV RIDLE BRGH PERR PDSEL1 FERR PDSEL0 OERR STSEL URXDA Resets 0000 0110 xxxx 0000 0000
URXISEL1 URXISEL0
Transmit Register Receive Register
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-13:
File Name SPI1STAT SPI1CON1 SPI1CON2 SPI1BUF Legend: Addr 0240 0242 0244 0248
SPI1 REGISTER
SPIEN FRMEN SPIFSD SPISIDL SPIFPOL DISSCK DISSDO SRMPT SSEN SPIROV SRXMPT MSTEN SISEL2 SPRE2 SISEL1 SPRE1 SISEL0 SPRE0 SPITBF PPRE1 SPIFE SPIRBF PPRE0 SPIBEN Resets 0000 0000 0000 0000
SPIBEC2 SPIBEC1 SPIBEC0 MODE16
SPI1 Transmit Receive Buffer
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-14:
File Name SPI2STAT SPI2CON1 SPI2CON2 SPI2BUF Legend: Addr 0260 0262 0264 0268
SPI2 REGISTER
SPIEN FRMEN SPIFSD SPISIDL SPIFPOL DISSCK DISSDO SRMPT SSEN SPIROV SRXMPT MSTEN SISEL2 SPRE2 SISEL1 SPRE1 SISEL0 SPRE0 SPITBF PPRE1 SPIFE SPIRBF PPRE0 SPIBEN Resets 0000 0000 0000 0000
SPIBEC2 SPIBEC1 SPIBEC0 MODE16
SPI2 Transmit Receive Buffer
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-15:
File Name ADC1BUF0 ADC1BUF1 ADC1BUF2 ADC1BUF3 ADC1BUF4 ADC1BUF5 ADC1BUF6 ADC1BUF7 ADC1BUF8 ADC1BUF9 ADC1BUFA ADC1BUFB ADC1BUFC ADC1BUFD ADC1BUFE ADC1BUFF AD1CON1 AD1CON2 AD1CON3 AD1CHS AD1PCFG AD1CSSL Legend: Addr 0300 0302 0304 0306 0308 030A 030C 030E 0310 0312 0314 0316 0318 031A 031C 031E 0320 0322 0324 0328 032C 0330
REGISTER
Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx SSRC1 ADCS6 PCFG6 CSSL6 SSRC0 SMPI3 ADCS5 PCFG5 CSSL5 SMPI2 ADCS4 PCFG4 CSSL4 SMPI1 ADCS3 CH0SA3 PCFG3 CSSL3 ASAM SMPI0 ADCS2 CH0SA2 PCFG2 CSSL2 SAMP BUFM ADCS1 CH0SA1 PCFG1 CSSL1 DONE ALTS ADCS0 CH0SA0 PCFG0 CSSL0 0000 0000 0000 0000 0000 0000
2009 Microchip Technology Inc. DS39747E-page
Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer ADON VCFG2 ADRC CH0NB PCFG15 CSSL15 VCFG1 PCFG14 CSSL14 ADSIDL VCFG0 PCFG13 CSSL13 SAMC4 PCFG12 CSSL12 SAMC3 CH0SB3 PCFG11 CSSL11 CSCNA SAMC2 CH0SB2 PCFG10 CSSL10 FORM1 SAMC1 CH0SB1 PCFG9 CSSL9 FORM0 SAMC0 CH0SB0 PCFG8 CSSL8 SSRC2 BUFS ADCS7 CH0NA PCFG7 CSSL7
PIC24FJ128GA010 FAMILY
unknown value Reset, unimplemented, read `0', reserved, maintain `0'. Reset values shown hexadecimal.
TABLE 3-16:
File Name TRISA PORTA LATA ODCA Legend: Note Addr 02C0 02C2 02C4 06C0
PORTA REGISTER
TRISA7 LATA7 ODA7) TRISA6 LATA6 ODA6 TRISA5(2)
Resets C6FF xxxx xxxx 0000
TRISA15(1) TRISA14(1) RA15(1) LATA15(1) ODA15(1) RA14
TRISA10(1) TRISA9(1) RA10
TRISA4(2) TRISA3(2) TRISA2(2) TRISA1(2) TRISA0(2) RA4(2) LATA4(2) ODA4(2) RA3(2) LATA3(2) ODA3(2) RA2(2) LATA2(2) ODA2(2) RA1(2) LATA1(2) ODA1(2) RA0(2) LATA0(2) ODA0(2)
LATA14(1) ODA14(1)
LATA10(1) ODA10(1)
LATA9(1) ODA9(1)
LATA5(2) ODA5(2)
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal 100-pin devices. Implemented 80-pin 100-pin devices only. Implemented 100-pin devices only.
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TABLE 3-17:
File Name TRISB PORTB LATB ODCB Legend: Note Addr 02C6 02C8 02CA 06C6
PORTB REGISTER
TRISB15 RB15 LATB15 ODB15 TRISB14 RB14 LATB14 ODB14 TRISB9 LATB9 ODB9 TRISB8 LATB8 ODB8 TRISB7 LATB7 ODB7 TRISB6 LATB6 ODB6 TRISB5 LATB5 ODB5 TRISB4 LATB4 ODB4 TRISB3 LATB3 ODB3 TRISB2 LATB2 ODB2 TRISB1 LATB1 ODB1 TRISB0 LATB0 ODB0 Resets FFFF xxxx xxxx 0000
TRISB13(1) TRISB12(1) TRISB11(1) TRISB10(1) RB13(1) LATB13(1) ODB13(1) RB12(1) LATB12(1) ODB12(1) RB11(1) LATB11(1) ODB11(1) RB10(1) LATB10(1) ODB10(1)
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal 100-pin devices Unimplemented when JTAG enabled.
TABLE 3-18:
File Name TRISC PORTC LATC ODCC Legend: Note Addr 02CC 02CE 02D0 06CC
PORTC REGISTER
Resets F01E xxxx xxxx 0000
TRISC15 TRISC14 TRISC13 TRISC12 RC15 LATC15 ODC15 RC14 LATC14 ODC14 RC13 LATC13 ODC13 RC12 LATC12 ODC12
TRISC4(2) TRISC3(1) TRISC2(2) TRISC1(1) RC4(2) LATC4(2) ODC4(2) RC3(1) LATC3(1) ODC3(1) RC2(2) LATC2(2) ODC2(2) RC1(1) LATC1(1) ODC1(1)
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal 100-pin devices. Implemented 80-pin 100-pin devices only. Implemented 100-pin devices only
TABLE 3-19:
File Name TRISD PORTD LATD ODCD Legend: Note Addr 02D2 02D4 02D6 06D2
PORTD REGISTER
TRISD11 RD11 LATD11 ODD11 TRISD10 RD10 LATD10 ODD10 TRISD9 LATD9 ODD9 TRISD8 LATD8 ODD8 TRISD7 LATD7 ODD7 TRISD6 LATD6 ODD6 TRISD5 LATD5 ODD5 TRISD4 LATD4 ODD4 TRISD3 LATD3 ODD3 TRISD2 LATD2 ODD2 TRISD1 LATD1 ODD1 TRISD0 LATD0 ODD0 Resets FFFF xxxx xxxx 0000
TRISD15(1) TRISD14(1) TRISD13(1) TRISD12(1) RD15(1) LATD15(1) ODD15(1) RD14(1) LATD14(1) ODD14(1) RD13(1) LATD13(1) ODD13(1) RD12(1) LATD12(1) ODD12(1)
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal 100-pin devices. Implemented 80-pin 100-pin devices only.
TABLE 3-20:
File Name TRISE PORTE LATE ODCE Legend: Note Addr 02D8 02DA 02DC 06D8
PORTE REGISTER
TRISE7 LATE7 ODE7 TRISE6 LATE6 ODE6 TRISE5 LATE5 ODE5 TRISE4 LATE4 ODE4 TRISE3 LATE3 ODE3 TRISE2 LATE2 ODE2 TRISE1 LATE1 ODE1 TRISE0 LATE0 ODE0 Resets 03FF xxxx xxxx 0000
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TRISE9(1) TRISE8(1) RE9(1) LATE9(1) ODE9(1) RE8(1) LATE8(1) ODE8(1)
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal 100-pin devices. Implemented 80-pin 100-pin devices only.
TABLE 3-21:
File Name TRISF PORTF LATF ODCF Legend: Note Addr 02DE 02E0 02E2 06DE
PORTF REGISTER
TRISF13(
TRISF12(
TRISF6 LATF6 ODF6
TRISF5 LATF5 ODF5
TRISF4 LATF4 ODF4
TRISF3 LATF3 ODF3
TRISF2 LATF2 ODF2
TRISF1 LATF1 ODF1
TRISF0 LATF0 ODF0
Resets 31FF xxxx xxxx 0000
TRISF8(2 TRISF7(2
RG13(1) ODF13(1)
RG12(1) ODF12(1)
RF8(2) LATF8(2) ODF8(2)
RF7(2) LATF7(2) ODF7(2)
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LATF13(1) LATF12(1)
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal 100-pin devices. Implemented 100-pin devices only. Implemented 80-pin 100-pin devices only.
TABLE 3-22:
File Name TRISG PORTG LATG ODCG Legend: Note Addr 02E4 02E6 02E8 06E4
PORTG REGISTER
TRISG15 RG15 LATG15 ODG15 TRISG9 LATG9 ODG9 TRISG6 LATG6 ODG6 TRISG3 LATG3 ODG3 TRISG2 LATG2 ODG2 Resets F3CF xxxx xxxx 0000
TRISG14(1) TRISG13(1) TRISG12(1 RG14(1) LATG14(1) ODG14(1) RG13(1) LATG13(1) ODG13(1) RG12(1) LATG12(1) ODG12(1)
TRISG8 TRISG7 LATG8 ODG8 LATG7 ODG7
TRISG1(2) TRISG0(2) RG1(2) LATG1(2) ODG1(2) RG0(2) LATG0(2) ODG0(2)
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal 100-pin devices. Implemented 100-pin devices only. Implemented 80-pin 100-pin devices only.
TABLE 3-23:
File Name PADCFG1 Legend: Addr 02FC
CONFIGURATION
RTSECSEL PMPTTL Resets 0000
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal 100-pin devices.
TABLE 3-24:
File Name PMCON PMMODE PMADDR(1) PMDOUT1(1) PMDOUT2 PMDIN1 PMDIN2 PMAEN PMSTAT Legend: Note Addr 0600 0602 0604 0606 0608 060A 060C 060E
PARALLEL MASTER/SLAVE PORT REGISTER
PMPEN BUSY IRQM1 PSIDL IRQM0 CSF1 WAITB1 CSF0 WAITB0 WAITM3 CS2P WAITM2 CS1P WAITM1 WAITM0 WRSP WAITE1 RDSP WAITE0 Resets 0000 0000 0000 0000 0000 0000 0000 PTEN5 PTEN4 PTEN3 OB3E PTEN2 OB2E PTEN1 OB1E PTEN0 OB0E 0000 008F
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ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN INCM1 INCM0 MODE16 MODE1 MODE0
Parallel Port Destination Address<13:0> (Master modes) Parallel Port Data Register (Buffers Parallel Port Data Register (Buffers Parallel Port Data Register (Buffers Parallel Port Data Register (Buffers
PTEN15
PTEN14 IBOV
PTEN13
PTEN12
PTEN11 IB3F
PTEN10 IB2F
PTEN9 IB1F
PTEN8 IB0F
PTEN7
PTEN6 OBUF
unimplemented, read `0'. Reset values shown hexadecimal. PMADDR PMDOUT1 share same physical register. register functions PMDOUT1 only Slave modes, PMADDR only Master modes.
TABLE 3-25:
File Name ALRMVAL ALCFGRPT RTCVAL RCFGCAL(1) Legend: Note Addr 0620 0622 0624 0626
REAL-TIME CLOCK CALENDAR REGISTER
Resets xxxx ARPT5 CAL5 ARPT4 CAL4 ARPT3 CAL3 ARPT2 CAL2 ARPT1 CAL1 ARPT0 CAL0 0000 xxxx 0000
Alarm Value Register Window Based ALRMPTR<1:0> ALRMEN RTCEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 RTCOE ALRMPTR1 ALRMPTR0 RTCPTR1 RTCPTR0 ARPT7 CAL7 ARPT6 CAL6 RTCC Value Register Window Based RTCPTR<1:0> RTCWREN RTCSYNC HALFSEC
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. RCFGCAL register Reset value dependent type Reset.
TABLE 3-26:
File Name CMCON CVRCON Legend: Addr 0630 0632
DUAL COMPARATOR REGISTER
CMIDL C2EVT C1EVT C2EN C1EN C2OUTEN C1OUTEN C2OUT CVREN C1OUT CVROE C2INV CVRR C1INV CVRSS C2NEG CVR3 C2POS CVR2 C1NEG CVR1 C1POS CVR0 Resets 0000 0000
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-27:
File Name CRCCON CRCXOR CRCDAT CRCWDAT Legend: Addr 0640 0642 0644 0646
REGISTER
CSIDL CRCGO PLEN3 PLEN2 PLEN1 PLEN0 Resets 0000 0000 0000 0000
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VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT Polynomial Register Data Input Register Result Register
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-28:
File Name RCON OSCCON CLKDIV OSCTUN Legend: Note Addr 0740 0742 0744 0748
SYSTEM REGISTER
TRAPR IOPUWR COSC2 DOZE2 COSC1 DOZE1 COSC0 DOZE0 DOZEN NOSC2 RCDIV2 NOSC1 RCDIV1 VREGS NOSC0 RCDIV0 EXTR CLKLOCK SWDTEN LOCK WDTO SLEEP IDLE SOSCEN OSWEN Resets xxxx(1) xxxx(2) 0100 0000
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TUN<5:0>
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. RCON register Reset values dependent type Reset. OSCCON register Reset values dependent FOSC Configuration bits type Reset.
TABLE 3-29:
File Name NVMCON NVMKEY Legend: Note Addr 0760 0766
REGISTER
WREN WRERR ERASE Resets 0000(1) 0000
NVMOP3 NVMOP2 NVMOP1 NVMOP0
NVMKEY<7:0>
unimplemented, read `0'. Reset values shown hexadecimal. Reset value shown only. Value other Reset states dependent state memory write erase operations time Reset.
TABLE 3-30:
File Name PMD1 PMD2 PMD3 Legend: Addr 0770 0772 0774
REGISTER
T5MD T4MD T3MD T2MD IC5MD T1MD IC4MD IC3MD IC2MD IC1MD PMPMD I2C1MD CRCPMD U2MD U1MD SPI2MD OC5MD SPI1MD OC4MD OC3MD OC2MD I2C2MD ADC1MD OC1MD Resets 0000 0000 0000
CMPMD RTCCMD
unimplemented, read `0'. Reset values shown hexadecimal.
PIC24FJ128GA010 FAMILY
3.2.5 SOFTWARE STACK
addition working register, register PIC24F devices also used Software Stack Pointer. pointer always points first available free word grows from lower higher addresses. pre-decrements stack pops post-increments stack pushes, shown Figure 3-4. Note that push during CALL instruction, zero-extended before push, ensuring that always clear. Note: push during exception processing will concatenate register prior push.
Interfacing Program Data Memory Spaces
PIC24F architecture uses 24-bit wide program space 16-bit wide data space. architecture also modified Harvard scheme, meaning that data also present program space. this data successfully, must accessed that preserves alignment information both spaces. Aside from normal execution, PIC24F architecture provides methods which program space accessed during operation: Using table instructions access individual bytes words anywhere program space Remapping portion program space into data space (Program Space Visibility) Table instructions allow application read write small areas program memory. This makes method ideal accessing data tables that need updated from time time. also allows access bytes program word. remapping method allows application access large block data read-only basis, which ideal look from large table static data. only access least significant word program word.
Stack Pointer Limit register (SPLIM) associated with Stack Pointer sets upper address boundary stack. SPLIM uninitialized Reset. case Stack Pointer, SPLIM<0> forced because stack operations must word-aligned. Whenever generated using source destination pointer, resulting address compared with value SPLIM. contents Stack Pointer (W15) SPLIM register equal push operation performed, stack error trap will occur. stack error trap will occur subsequent push operation. Thus, example, desirable cause stack error trap when stack grows beyond address 2000h RAM, initialize SPLIM with value, 1FFEh. Similarly, Stack Pointer underflow (stack error) trap generated when Stack Pointer address found less than 0800h. This prevents stack from interfering with Special Function Register (SFR) space. write SPLIM register should immediately followed indirect read operation using W15.
3.3.1
ADDRESSING PROGRAM SPACE
Since address ranges data program spaces bits, respectively, method needed create 23-bit 24-bit program address from 16-bit data registers. solution depends interface method used. table operations, 8-bit Table Page register (TBLPAG) used define word region within program space. This concatenated with 16-bit arrive full 24-bit program space address. this format, Most Significant TBLPAG used determine operation occurs user memory (TBLPAG<7> configuration memory (TBLPAG<7> remapping operations, 8-bit Program Space Visibility register (PSVPAG) used define word page program space. When Most Significant `1', PSVPAG concatenated with lower bits form 23-bit program space address. Unlike table operations, this limits remapping operations strictly user memory area. Table 3-31 Figure show program created table operations remapping accesses from data Here, P<23:0> refers program space word, whereas D<15:0> refers data space word.
FIGURE 3-4:
0000h
CALL STACK FRAME
Stack Grows Towards Higher Address
PC<15:0> 000000000 PC<22:16> <Free Word>
(before CALL) (after CALL) [-W15] PUSH [W15++]
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TABLE 3-31: PROGRAM SPACE ADDRESS CONSTRUCTION
Access Space User User Configuration Program Space Visibility (Block Remap/Read) Note User Program Space Address <23> TBLPAG<7:0> 0xxx xxxx TBLPAG<7:0> 1xxx xxxx PSVPAG<7:0> xxxx xxxx <22:16> <15> PC<22:1> xxxx xxxx xxxx xxxx xxx0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<14:0>(1) xxxx xxxx xxxx <14:1> Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write)
Data EA<15> always this case, used calculating program space address. address PSVPAG<0>.
FIGURE 3-5:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter bits
Table Operations(2)
TBLPAG bits bits bits
Select Program Space Visibility(1) (Remapping) PSVPAG bits
bits bits
User/Configuration Space Select
Byte Select
Note program space addresses always fixed order maintain word alignment data program data spaces. Table operations required word-aligned. Table read operations permitted configuration memory space.
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3.3.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS
TBLRDH (Table Read High): Word mode, maps entire upper word program address (P<23:16>) data address. Note that D<15:8>, "phantom byte", will always `0'. Byte mode, maps upper lower byte program word D<7:0> data address, above. Note that data will always when upper "phantom" byte selected (byte select
TBLRDL TBLWTL instructions offer direct method reading writing lower word address within program space, without going through data space. TBLRDH TBLWTH instructions only method read write upper bits program space word data. incremented each successive 24-bit program word. This allows program memory addresses directly data space addresses. Program memory thus regarded 16-bit word wide address spaces, residing side side, each with same address range. TBLRDL TBLWTL access space which contains least significant data word, TBLRDH TBLWTH access space which contains upper data byte. table instructions provided move byte word-sized (16-bit) data from program space. Both function either byte word operations. TBLRDL (Table Read Low): Word mode, maps lower word program space location (P<15:0>) data address (D<15:0>). Byte mode, either upper lower byte lower program word mapped lower byte data address. upper byte selected when byte select `1'; lower byte selected when `0'.
similar fashion, table instructions, TBLWTH TBLWTL, used write individual bytes words program space address. details their operation explained Section "Flash Program Memory". table operations, area program memory space accessed determined Table Page register (TBLPAG). TBLPAG covers entire program memory space device, including user configuration spaces. When TBLPAG<7> Table Page located user memory space. When TBLPAG<7> page located configuration space. Note: Only table read operations will execute configuration memory space, only then, implemented areas such Device Table write operations allowed.
FIGURE 3-6:
TBLPAG
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
Data EA<15:0> 000000h
00000000 00000000 00000000 00000000
020000h 030000h
`Phantom' Byte
TBLRDH.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.W address table operation determined data within page defined TBLPAG register. Only read operations shown; write operations also valid user memory area.
800000h
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3.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY
24-bit program word used contain data. upper bits program space locations used data should programmed with `1111 1111' `0000 0000' force NOP. This prevents possible issues should area code ever accidentally executed. Note: access temporarily disabled during table reads/writes.
upper Kbytes data space optionally mapped into word page program space. This provides transparent access stored constant data from data space without need special instructions (i.e., TBLRDL/H). Program space access through data space occurs Most Significant data space program space visibility enabled setting Core Control register (CORCON<2>). location program memory space mapped into data space determined Program Space Visibility Page register (PSVPAG). This 8-bit register defines possible pages words program space. effect, PSVPAG functions upper bits program memory address, with bits functioning lower bits. Note that incrementing each program memory word, lower bits data space addresses directly lower bits corresponding program space addresses. Data reads this area additional cycle instruction being executed, since program memory fetches required. Although each data space address, 8000h higher, maps directly into corresponding program memory address (see Figure 3-7), only lower bits
operations that executed outside REPEAT loop, MOV.D instructions will require instruction cycle addition specified execution time. other instructions will require instruction cycles addition specified execution time. operations that which executed inside REPEAT loop, there will some instances that require instruction cycles addition specified execution time instruction: Execution first iteration Execution last iteration Execution prior exiting loop interrupt Execution upon re-entering loop after interrupt serviced other iteration REPEAT loop will allow instruction accessing data, using PSV, execute single cycle.
FIGURE 3-7:
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> EA<15>
Program Space
PSVPAG 000000h 010000h 018000h data page designated PSVPAG mapped into upper half data memory space.
Data Space
0000h Data EA<14:0>
8000h
Area .while lower bits specify exact address within area. This corresponds exactly same lower bits actual program space address.
FFFFh
800000h
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NOTES:
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Note:
FLASH PROGRAM MEMORY
This data sheet summarizes features this group PIC24F devices. intended comprehensive reference source. Refer Section "Program Memory" (DS39715) "PIC24F Family Reference Manual" more information.
controller just before shipping product. This also allows most recent firmware custom firmware programmed. RTSP accomplished using TBLRD (table read) TBLWT (table write) instructions. With RTSP, user write program memory data blocks instructions (192 bytes) time, erase program memory blocks instructions (1536 bytes) time.
PIC24FJ128GA010 family devices contains internal Flash program memory storing executing application code. memory readable, writable erasable during normal operation over entire range. Flash memory programmed four ways: In-Circuit Serial Programming(ICSPTM) Run-Time Self-Programming (RTSP) JTAG Enhanced In-Circuit Serial Programming (Enhanced ICSP)
Table Instructions Flash Programming
Regardless method used, programming Flash memory done with table read table write instructions. These allow direct read write access program memory space from data memory while device normal operating mode. 24-bit target address program memory formed using TBLPAG<7:0> bits Effective Address (EA) from register specified table instruction, shown Figure 4-1. TBLRDL TBLWTL instructions used read write bits<15:0> program memory. TBLRDL TBLWTL access program memory both Word Byte modes. TBLRDH TBLWTH instructions used read write bits<23:16> program memory. TBLRDH TBLWTH also access program memory Word Byte mode.
ICSP allows PIC24FJ128GA010 family device serially programmed while application circuit. This simply done with lines Programming Clock Programming Data (which named PGCx PGDx, respectively), three other lines power (VDD), ground (VSS) Master Clear (MCLR). This allows customers manufacture boards with unprogrammed devices then program micro-
FIGURE 4-1:
ADDRESSING TABLE REGISTERS
Bits Using Program Counter Program Counter
Working Using Table Instruction TBLPAG Bits Bits
User/Configuration Space Select
24-Bit
Byte Select
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RTSP Operation
PIC24F Flash program memory array organized into rows instructions bytes. RTSP allows user erase blocks eight rows (512 instructions) time program time. also possible program single words. 8-row erase blocks single write blocks edge-aligned, from beginning program memory, boundaries 1536 bytes bytes, respectively. When data written program memory using TBLWT instructions, data written directly memory. Instead, data written using table writes stored holding latches until programming sequence executed. number TBLWT instructions executed write will successfully performed. However, TBLWT instructions required write full memory. ensure that data corrupted during write, unused addresses should programmed with FFFFFFh. This because holding latches reset unknown state, addresses left Reset state, they overwrite locations rows which were rewritten. basic sequence RTSP programming Table Pointer, then series TBLWT instructions load buffers. Programming performed setting control bits NVMCON register. Data loaded order holding registers written multiple times before performing write operation. Subsequent writes, however, will wipe previous writes. Note: Writing location multiple times without erasing recommended.
Enhanced In-Circuit Serial Programming
Enhanced In-Circuit Serial Programming uses onboard bootloader, known program executive, manage programming process. Using data frame format, program executive erase, program verify program memory. device programming specification more information Enhanced ICSP
Control Registers
There SFRs used read write program Flash memory: NVMCON NVMKEY. NVMCON register (Register 4-1) controls which blocks erased, which memory type programmed start programming cycle. NVMKEY write-only register that used write protection. start programming erase sequence, user must consecutively write NVMKEY register. Refer Section "Programming Operations" further details.
Programming Operations
complete programming sequence necessary programming erasing internal Flash RTSP mode. During programming erase operation, processor stalls (waits) until operation finished. Setting (NVMCON<15>) starts operation, automatically cleared when operation finished. Configuration Word values stored last locations program memory. Performing page erase operation last page program memory clears these values enables code protection. result, avoid performing page erase operations last page program memory.
table write operations single-word writes instruction cycles), because only buffers written. programming cycle required programming each
JTAG Operation
PIC24F family supports JTAG programming boundary scan. Boundary scan improve manufacturing process verifying connectivity. Programming performed with industry standard JTAG programmers supporting Serial Vector Format (SVF).
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REGISTER 4-1:
R/SO-0(1) Legend: Readable Value Settable-Only Writable Unimplemented bit, read cleared unknown R/W-0(1) ERASE R/W-0(1) NVMOP3
NVMCON: FLASH MEMORY CONTROL REGISTER
R/W-0(1) WREN R/W-0(1) WRERR R/W-0(1) NVMOP2
R/W-0(1) NVMOP1
R/W-0(1) NVMOP0(2)
Write Control Initiates Flash memory program erase operation. operation self-timed cleared hardware once operation complete. Program erase operation complete inactive WREN: Write Enable Enable Flash program/erase operations Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag improper program erase sequence attempt termination occurred (bit automatically attempt bit) program erase operation completed normally Unimplemented: Read ERASE: Erase/Program Enable Perform erase operation specified NVMOP3:NVMOP0 next command Perform program operation specified NVMOP3:NVMOP0 next command Unimplemented: Read NVMOP3:NVMOP0: Operation Select bits(2) 1111 Memory bulk erase operation (ERASE operation (ERASE 0)(3) 0011 Memory word program operation (ERASE operation (ERASE 0010 Memory page erase operation (ERASE operation (ERASE 0001 Memory program operation (ERASE operation (ERASE These bits only reset POR. other combinations NVMOP3:NVMOP0 unimplemented. Available ICSPmode only. Refer device programming specification.
12-7
Note
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4.6.1 PROGRAMMING ALGORITHM FLASH PROGRAM MEMORY
user program program Flash memory time. this, necessary erase 8-row erase block containing desired row. general process Read eight rows program memory (512 instructions) store data RAM. Update program data with desired data. Erase block (see Example 4-1): NVMOP bits (NVMCON<3:0>) `0010' configure block erase. ERASE (NVMCON<6>) WREN (NVMCON<14>) bits. Write starting address block erased into TBLPAG registers. Write NVMKEY. Write NVMKEY. (NVMCON<15>). erase cycle begins stalls duration erase cycle. When erase done, cleared automatically. Write first instructions from data into program memory buffers (see Example 4-2). Write program block Flash memory: NVMOP bits `0001' configure programming. Clear ERASE WREN bit. Write NVMKEY. Write NVMKEY. bit. programming cycle begins stalls duration write cycle. When write Flash memory done, cleared automatically. Repeat steps using next available instructions from block data incrementing value TBLPAG, until instructions written back Flash memory.
protection against accidental operations, write initiate sequence NVMKEY must used allow erase program operation proceed. After programming command been executed, user must wait programming time until programming complete. instructions following start programming sequence should NOPs, shown Example 4-3.
EXAMPLE 4-1:
ERASING PROGRAM MEMORY BLOCK
Initialize NVMCON
NVMCON block erase operation #0x4042, NVMCON Init pointer ERASED #tblpage(PROG_ADDR), TBLPAG #tbloffset(PROG_ADDR), TBLWTL [W0] DISI BSET #0x55, NVMKEY #0xAA, NVMKEY NVMCON,
Initialize Page Boundary Initialize in-page EA[15:0] pointer base address erase block Block interrupts with priority next instructions Write Write Start erase sequence Insert NOPs after erase command asserted
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EXAMPLE 4-2: LOADING WRITE BUFFERS
NVMCON programming operations #0x4001, NVMCON Initialize NVMCON pointer first program memory location written program memory selected, writes enabled #0x0000, TBLPAG Initialize Page Boundary #0x6000, example program memory address Perform TBLWT instructions write latches 0th_program_word #LOW_WORD_0, #HIGH_BYTE_0, TBLWTL [W0] Write word into program latch TBLWTH [W0++] Write high byte into program latch 1st_program_word #LOW_WORD_1, #HIGH_BYTE_1, TBLWTL [W0] Write word into program latch TBLWTH [W0++] Write high byte into program latch 2nd_program_word #LOW_WORD_2, #HIGH_BYTE_2, Write word into program latch TBLWTL [W0] Write high byte into program latch TBLWTH [W0++] 63rd_program_word #LOW_WORD_31, #HIGH_BYTE_31, Write word into program latch TBLWTL [W0] Write high byte into program latch TBLWTH [W0]
EXAMPLE 4-3:
DISI BSET BTSC
INITIATING PROGRAMMING SEQUENCE
Block interrupts with priority next instructions Write Write Start program/erase sequence wait completed #0x55, NVMKEY #0xAA, NVMKEY NVMCON, NVMCON,
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4.6.2 PROGRAMMING SINGLE WORD FLASH PROGRAM MEMORY
Flash location been erased, programmed using table write instructions write instruction word (24-bit) into write latch. TBLPAG register loaded with Most Significant Bytes Flash address. TBLWTL TBLWTH instructions write desired data into write latches specify lower bits program memory address write configure NVMCON register word write, NVMOP bits (NVMCON<3:0>) `0011'. write performed executing unlock sequence setting bit.
EXAMPLE 4-4:
PROGRAMMING SINGLE WORD FLASH PROGRAM MEMORY
Setup pointer data Program Memory #tblpage(PROG_ADDR), TBLPAG ;Initialize Page Boundary #tbloffset(PROG_ADDR), ;Initialize register with program memory address TBLWTL TBLWTH #LOW_WORD_N, #HIGH_BYTE_N, [W0] [W0++] Write word into program latch Write high byte into program latch
Setup NVMCON programming word data Program Memory #0x4003, NVMCON NVMOP bits 0011 DISI BSET #0x55, NVMKEY #0xAA, NVMKEY NVMCON, Disable interrupts while sequence written Write sequence
Start write cycle
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Note:
RESETS
This data sheet summarizes features this group PIC24F devices. intended comprehensive reference source. Refer Section "Reset" (DS39712) "PIC24F Family Reference Manual" more information.
Note:
Refer specific peripheral section this manual register Reset states.
Reset module combines Reset sources controls device Master Reset Signal, SYSRST. following list device Reset sources: POR: Power-on Reset MCLR: Reset SWR: RESET Instruction WDT: Watchdog Timer Reset BOR: Brown-out Reset Configuration Word Mismatch Reset TRAPR: Trap Conflict Reset IOPUWR: Illegal Opcode Reset UWR: Uninitialized Register Reset
types device Reset will corresponding status RCON register indicate type Reset (see Register 5-1). will clear bits except bits (RCON<1:0>), which set. user clear time during code execution. RCON bits only serve status bits. Setting particular Reset status software will cause device Reset occur. RCON register also other bits associated with Watchdog Timer device power-saving states. function these bits discussed other sections this manual. Note: status bits RCON register should cleared after they read that next RCON register value after device Reset will meaningful.
simplified block diagram Reset module shown Figure 5-1. active source Reset will make SYSRST signal active. Many registers associated with peripherals forced known Reset state. Most registers unaffected Reset; their status unknown unchanged other Resets.
FIGURE 5-1:
RESET SYSTEM BLOCK DIAGRAM
RESET Instruction Glitch Filter MCLR Module Sleep Idle Rise Detect Brown-out Reset SYSRST
Enable Voltage Regulator Trap Conflict Illegal Opcode Uninitialized Register Configuration Word Mismatch Reset
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REGISTER 5-1:
R/W-0 TRAPR R/W-0 EXTR Legend: Readable Value
RCON: RESET CONTROL REGISTER(1)
R/W-0 IOPUWR R/W-0 R/W-0 VREGS R/W-1
R/W-0
R/W-0 SWDTEN(2)
R/W-0 WDTO
R/W-0 SLEEP
R/W-0 IDLE
R/W-1
Writable
Unimplemented bit, read cleared unknown
13-10
TRAPR: Trap Reset Flag Trap Conflict Reset occurred Trap Conflict Reset occurred IOPUWR: Illegal Opcode Uninitialized Access Reset Flag illegal opcode detection, illegal address mode uninitialized register used Address Pointer caused Reset illegal opcode uninitialized Reset occurred Unimplemented: Read Configuration Word Mismatch Reset Flag Configuration Word Mismatch Reset occurred Configuration Word Mismatch Reset occurred VREGS: Voltage Regulator Standby Enable Regulator remains active during Sleep Regulator goes standby during Sleep EXTR: External Reset (MCLR) Master Clear (pin) Reset occurred Master Clear (pin) Reset occurred SWR: Software Reset (Instruction) Flag RESET instruction been executed RESET instruction been executed SWDTEN: Software Enable/Disable bit(2) enabled disabled WDTO: Watchdog Timer Time-out Flag time-out occurred time-out occurred SLEEP: Wake From Sleep Flag Device been Sleep mode Device been Sleep mode IDLE: Wake-up From Idle Flag Device Idle mode Device Idle mode BOR: Brown-out Reset Flag Brown-out Reset occurred. Note that also after Power-on Reset. Brown-out Reset occurred POR: Power-on Reset Flag Power-on Reset occurred Power-on Reset occurred Reset status bits cleared software. Setting these bits software does cause device Reset. FWDTEN Configuration (unprogrammed), always enabled, regardless SWDTEN setting.
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Note
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TABLE 5-1: RESET FLAG OPERATION
Setting Event Trap conflict event Illegal opcode uninitialized register access MCLR Reset RESET instruction time-out PWRSAV #SLEEP instruction PWRSAV #IDLE instruction POR, PWRSAV instruction, Clearing Event Flag TRAPR (RCON<15>) IOPUWR (RCON<14>) EXTR (RCON<7>) (RCON<6>) WDTO (RCON<4>) SLEEP (RCON<3>) IDLE (RCON<2>) (RCON<1>) (RCON<0>) Note:
Reset flag bits cleared user software.
Clock Source Selection Reset
Device Reset Times
clock switching enabled, system clock source device Reset chosen shown Table 5-2. clock switching disabled, system clock source always selected according oscillator Configuration bits. Refer "Oscillator Configuration" further details.
Reset times various types device Reset summarized Table 5-3. Note that system Reset signal, SYSRST, released after PWRT delay times expire. time that device actually begins execute code will also depend system oscillator delays, which include Oscillator Start-up Timer (OST) lock time. lock times occur parallel with applicable SYSRST delay times. FSCM delay determines time which FSCM begins monitor system clock source after SYSRST signal released.
TABLE 5-2:
OSCILLATOR SELECTION TYPE RESET (CLOCK SWITCHING ENABLED)
Clock Source Determinant Oscillator Configuration bits (FNOSC2:FNOSC0) COSC Control bits (OSCCON<14:12>)
Reset Type MCLR WDTR
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TABLE 5-3:
Reset Type
RESET DELAY TIMES VARIOUS DEVICE RESETS
Clock Source SYSRST Delay System Clock Delay TLOCK TOST TOST TLOCK TLOCK TOST TOST TLOCK FSCM Delay TFSCM TFSCM TFSCM TFSCM TFSCM TFSCM Notes
FRC, FRCDIV, LPRC TPOR TSTARTUP TRST ECPLL, FRCPLL SOSC XTPLL, HSPLL TPOR TSTARTUP TRST TPOR TSTARTUP TRST TPOR TSTARTUP TRST TSTARTUP TRST TSTARTUP TRST TSTARTUP TRST TSTARTUP TRST TRST TRST TRST TRST TRST TRST
FRC, FRCDIV, LPRC ECPLL, FRCPLL SOSC XTPLL, HSPLL
MCLR Software Illegal Opcode Uninitialized Trap Conflict Note
Clock Clock Clock Clock Clock Clock
TPOR Power-on Reset delay nominal). TSTARTUP TVREG nominal) on-chip regulator enabled TPWRT nominal) on-chip regulator disabled. TRST Internal state Reset time nominal). TOST Oscillator Start-up Timer. 10-bit counter counts 1024 oscillator periods before releasing oscillator clock system. TLOCK lock time. TFSCM Fail-Safe Clock Monitor delay (100 nominal).
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5.2.1 LONG OSCILLATOR START-UP TIMES
Special Function Register Reset States
oscillator start-up circuitry associated delay timers linked device Reset delays that occur power-up. Some crystal circuits (especially low-frequency crystals) will have relatively long start-up time. Therefore, more following conditions possible after SYSRST released: oscillator circuit begun oscillate. Oscillator Start-up Timer expired crystal oscillator used). achieved LOCK used). device will begin execute code until valid clock source been released system. Therefore, oscillator start-up delays must considered when Reset delay time must known.
Most Special Function Registers (SFRs) associated with PIC24F peripherals reset particular value device Reset. SFRs grouped their peripheral function their Reset values specified each section this manual. Reset value each does depend type Reset, with exception four registers. Reset value Reset Control register, RCON, will depend type device Reset. Reset value Oscillator Control register, OSCCON, will depend type Reset programmed values oscillator Configuration bits FOSC Device Configuration register (see Table 5-2). RCFGCAL NVMCON registers only affected POR.
5.2.2
FAIL-SAFE CLOCK MONITOR (FSCM) DEVICE RESETS
FSCM enabled, will begin monitor system clock source when SYSRST released. valid clock source available this time, device will automatically switch oscillator user switch desired crystal oscillator Trap Service Routine.
5.2.2.1
FSCM Delay Crystal Clock Sources
When system clock source provided crystal oscillator and/or PLL, small delay, TFSCM, will automatically inserted after PWRT delay times. FSCM will begin monitor system clock source until this delay expires. FSCM delay time nominally provides additional time oscillator and/or stabilize. most cases, FSCM delay will prevent oscillator failure trap device Reset when PWRT disabled.
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NOTES:
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Note:
INTERRUPT CONTROLLER
This data sheet summarizes features this group PIC24F devices. intended comprehensive reference source. Refer Section "Interrupts" (DS39707) "PIC24F Family Reference Manual" more information.
6.1.1
ALTERNATE INTERRUPT VECTOR TABLE
PIC24F interrupt controller reduces numerous peripheral interrupt request signals single interrupt request signal PIC24F CPU. following features: processor exceptions software traps user-selectable priority levels Interrupt Vector Table (IVT) with vectors unique vector each interrupt exception source Fixed priority within specified user priority level Alternate Interrupt Vector Table (AIVT) debug support Fixed interrupt entry return latencies
Alternate Interrupt Vector Table (AIVT) located after shown Figure 6-1. Access AIVT provided ALTIVT control (INTCON2<15>). ALTIVT set, interrupt exception processes will alternate vectors instead default vectors. alternate vectors organized same manner default vectors. AIVT supports emulation debugging efforts providing means switch between application support environment without requiring interrupt vectors reprogrammed. This feature also enables switching between applications evaluation different software algorithms time. AIVT needed, AIVT should programmed with same addresses used IVT.
Reset Sequence
Interrupt Vector Table
Interrupt Vector Table (IVT) shown Figure 6-1. resides program memory, starting location 000004h. contains vectors, consisting non-maskable trap vectors, plus sources interrupt. general, each interrupt source vector. Each interrupt vector contains 24-bit wide address. value programmed into each interrupt vector location starting address associated Interrupt Service Routine (ISR). Interrupt vectors prioritized terms their natural priority; this linked their position vector table. other things being equal, lower addresses have higher natural priority. example, interrupt associated with vector will take priority over interrupts other vector address. PIC24FJ128GA010 family devices implement nonmaskable traps unique interrupts. These summarized Table Table 6-2.
device Reset true exception because interrupt controller involved Reset process. PIC24F device clears registers response Reset which forces zero. microcontroller then begins program execution location 000000h. user programs GOTO instruction Reset address, which redirects program execution appropriate start-up routine. Note: unimplemented unused vector locations AIVT should programmed with address default interrupt handler routine that contains RESET instruction.
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FIGURE 6-1: PIC24F INTERRUPT VECTOR TABLE
Reset GOTO Instruction Reset GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Start Code 000000h 000002h 000004h
000014h
Decreasing Natural Order Priority
00007Ch 00007Eh 000080h
Interrupt Vector Table (IVT)(1)
0000FCh 0000FEh 000100h 000102h
000114h
Alternate Interrupt Vector Table (AIVT)(1) 00017Ch 00017Eh 000180h
0001FEh 000200h
Note
Table interrupt vector list.
TABLE 6-1:
TRAP VECTOR DETAILS
Address 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h AIVT Address 000104h 000106h 000108h 00010Ah 00010Ch 00010Eh 000110h 0001172h Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved
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Vector Number
Trap Source
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TABLE 6-2: IMPLEMENTED INTERRUPT VECTORS
Vector Number Address 00002Eh 000038h 00009Ah 000014h 00003Ch 00004Eh 00007Eh 000080h 000036h 000034h 000078h 000076h 000016h 00001Eh 00005Eh 000060h 000062h 00003Ah 000018h 000020h 000046h 000048h 000066h 00006Eh 000090h 000026h 000028h 000054h 000056h 00001Ah 000022h 000024h 00004Ah 00004Ch 000096h 00002Ah 00002Ch 000098h 000050h 000052h AIVT Address 00012Eh 000138h 00019Ah 000114h 00013Ch 00014Eh 00017Eh 000180h 000136h 000034h 000178h 000176h 000116h 00011Eh 00015Eh 000160h 000162h 00013Ah 000118h 000120h 000146h 000148h 000166h 00016Eh 000190h 000126h 000128h 000154h 000156h 00011Ah 000122h 000124h 00014Ah 00014Ch 000196h 00012Ah 00012Ch 000198h 000150h 000152h Interrupt Locations Flag IFS0<13> IFS1<2> IFS4<3> IFS0<0> IFS1<4> IFS1<13> IFS3<5> IFS3<6> IFS1<1> IFS1<0> IFS3<2> IFS3<1> IFS0<1> IFS0<5> IFS2<5> IFS2<6> IFS2<7> IFS1<3> IFS0<2> IFS0<6> IFS1<9> IFS1<10> IFS2<9> IFS2<13> IFS3<14> IFS0<9> IFS0<10> IFS2<0> IFS2<1> IFS0<3> IFS0<7> IFS0<8> IFS1<11> IFS1<12> IFS4<1> IFS0<11> IFS0<12> IFS4<2> IFS1<14> IFS1<15> Enable IEC0<13> IEC1<2> IEC4<3> IEC0<0> IEC1<4> IEC1<13> IEC3<5> IEC3<6> IEC1<1> IEC1<0> IEC3<2> IEC3<1> IEC0<1> IEC0<5> IEC2<5> IEC2<6> IEC2<7> IEC1<3> IEC0<2> IEC0<6> IEC1<9> IEC1<10> IEC2<9> IEC2<13> IEC3<13> IEC0<9> IEC0<10> IEC0<0> IEC2<1> IEC0<3> IEC0<7> IEC0<8> IEC1<11> IEC1<12> IEC4<1> IEC0<11> IEC0<12> IEC4<2> IEC1<14> IEC1<15> Priority IPC3<6:4> IPC4<10:8> IPC16<14:12> IPC0<2:0> IPC5<2:0> IPC7<6:4> IPC13<6:4> IPC13<10:8> IPC4<6:4> IPC4<2:0> IPC12<10:8> IPC12<6:4> IPC0<6:4> IPC1<6:4> IPC9<6:4> IPC9<10:8> IPC9<14:12> IPC4<14:12> IPC0<10:8> IPC1<10:8> IPC6<6:4> IPC6<10:8> IPC10<6:4> IPC11<6:4> IPC15<10:8> IPC2<6:4> IPC2<10:8> IPC8<2:0> IPC8<6:4> IPC0<14:12> IPC1<14:12> IPC2<2:0> IPC6<14:12> IPC7<2:0> IPC16<6:4> IPC2<14:12> IPC3<2:0> IPC16<10:8> IPC7<10:8> IPC7<14:12> Interrupt Source ADC1 Conversion Done Comparator Event Generator External Interrupt External Interrupt External Interrupt External Interrupt External Interrupt I2C1 Master Event I2C1 Slave Event I2C2 Master Event I2C2 Slave Event Input Capture Input Capture Input Capture Input Capture Input Capture Input Change Notification Output Compare Output Compare Output Compare Output Compare Output Compare Parallel Master Port Real-Time Clock/Calendar SPI1 Error SPI1 Event SPI2 Error SPI2 Event Timer1 Timer2 Timer3 Timer4 Timer5 UART1 Error UART1 Receiver UART1 Transmitter UART2 Error UART2 Receiver UART2 Transmitter
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Interrupt Control Status Registers
interrupt sources assigned IFSx, IECx IPCx registers same sequence that they listed Table 6-2. example, INT0 (External Interrupt shown having vector number natural order priority Thus, INT0IF status found IFS0<0>, enable IEC0<0> priority bits first position IPC0 (IPC0<2:0>). Although they specifically part interrupt control hardware, control registers contain bits that control interrupt functionality. STATUS register (SR) contains IPL2:IPL0 bits (SR<7:5>). These indicate current interrupt priority level. user change current priority level writing bits. CORCON register contains IPL3 bit, which together with IPL2:IPL0, also indicates current priority level. IPL3 read-only that trap events cannot masked user software. Interrupt registers described Register through Register 6-30, following pages.
PIC24FJ128GA010 family devices implement total registers interrupt controller: INTCON1 INTCON2 IFS0 through IFS4 IEC0 through IEC4 IPC0 through IPC14, IPC16
Global interrupt control functions controlled from INTCON1 INTCON2. INTCON1 contains Interrupt Nesting Disable (NSTDIS) bit, well control status flags processor trap sources. INTCON2 register controls external interrupt request signal behavior Alternate Interrupt Vector Table. registers maintain interrupt request flags. Each source interrupt status which respective peripherals, external signal, cleared software. registers maintain interrupt enable bits. These control bits used individually enable interrupts from peripherals external signals. registers used interrupt priority level each source interrupt. Each user interrupt source assigned eight priority levels.
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REGISTER 6-1:
R/W-0(1) IPL2 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
(2,3)
STATUS REGISTER
R/W-0 DC(1) R/W-0(1) IPL1(2,3) R/W-0(1) IPL0(2,3) RA(1) R/W-0 N(1) R/W-0 OV(1) R/W-0 Z(1) R/W-0 C(1)
IPL2:IPL0: Interrupt Priority Level Status bits(2,3) interrupt priority level (15). User interrupts disabled. interrupt priority level (14) interrupt priority level (13) interrupt priority level (12) interrupt priority level (11) interrupt priority level (10) interrupt priority level interrupt priority level Register description remaining bit(s) that dedicated interrupt control functions. bits concatenated with IPL3 (CORCON<3>) form interrupt priority level. value parentheses indicates interrupt priority level IPL3 Status bits read-only when NSTDIS (INTCON1<15>)
Note
REGISTER 6-2:
Legend: Readable Value
CORCON: CORE CONTROL REGISTER
R/C-0 IPL3(2) R/W-0 PSV(1) Clearable Writable Unimplemented bit, read cleared unknown
IPL3: Interrupt Priority Level Status bit(2) interrupt priority level greater than interrupt priority level less Register description remaining bit(s) that dedicated interrupt control functions. IPL3 concatenated with IPL2:IPL0 bits (SR<7:5>) form interrupt priority level.
Note
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REGISTER 6-3:
R/W-0 NSTDIS Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0 MATHERR R/W-0 ADDRERR R/W-0 STKERR R/W-0 OSCFAIL
INTCON1: INTERRUPT CONTROL REGISTER
NSTDIS: Interrupt Nesting Disable Interrupt nesting disabled Interrupt nesting enabled Unimplemented: Read MATHERR: Arithmetic Error Trap Status Overflow trap occurred Overflow trap occurred ADDRERR: Address Error Trap Status Address error trap occurred Address error trap occurred STKERR: Stack Error Trap Status Stack error trap occurred Stack error trap occurred OSCFAIL: Oscillator Failure Trap Status Oscillator failure trap occurred Oscillator failure trap occurred Unimplemented: Read
14-5
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REGISTER 6-4:
R/W-0 ALTIVT Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0 INT4EP R/W-0 INT3EP R/W-0 INT2EP R/W-0 INT1EP
INTCON2: INTERRUPT CONTROL REGISTER
DISI R/W-0 INT0EP
ALTIVT: Enable Alternate Interrupt Vector Table alternate vector table standard (default) vector table DISI: DISI Instruction Status DISI instruction active DISI active Unimplemented: Read INT4EP: External Interrupt Edge Detect Polarity Select Interrupt negative edge Interrupt positive edge INT3EP: External Interrupt Edge Detect Polarity Select Interrupt negative edge Interrupt positive edge INT2EP: External Interrupt Edge Detect Polarity Select Interrupt negative edge Interrupt positive edge INT1EP: External Interrupt Edge Detect Polarity Select Interrupt negative edge Interrupt positive edge INT0EP: External Interrupt Edge Detect Polarity Select Interrupt negative edge Interrupt positive edge
13-5
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REGISTER 6-5:
R/W-0 T2IF Legend: Readable Value 15-14
IFS0: INTERRUPT FLAG STATUS REGISTER
R/W-0 AD1IF R/W-0 U1TXIF R/W-0 U1RXIF R/W-0 SPI1IF R/W-0 SPF1IF R/W-0 T3IF R/W-0 INT0IF
R/W-0 OC2IF
R/W-0 IC2IF
R/W-0 T1IF
R/W-0 OC1IF
R/W-0 IC1IF
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read AD1IF: Conversion Complete Interrupt Flag Status Interrupt request occurred Interrupt request occurred U1TXIF: UART1 Transmitter Interrupt Flag Status Interrupt request occurred Interrupt request occurred U1RXIF: UART1 Receiver Interrupt Flag Status Interrupt request occurred Interrupt request occurred SPI1IF: SPI1 Event Interrupt Flag Status Interrupt request occurred Interrupt request occurred SPF1IF: SPI1 Fault Interrupt Flag Status Interrupt request occurred Interrupt request occurred T3IF: Timer3 Interrupt Flag Status Interrupt request occurred Interrupt request occurred T2IF: Timer2 Interrupt Flag Status Interrupt request occurred Interrupt request occurred OC2IF: Output Compare Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred IC2IF: Input Capture Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read T1IF: Timer1 Interrupt Flag Status Interrupt request occurred Interrupt request occurred OC1IF: Output Compare Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred IC1IF: Input Capture Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred INT0IF: External Interrupt Flag Status Interrupt request occurred Interrupt request occurred
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REGISTER 6-6:
R/W-0 U2TXIF Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0 INT1IF R/W-0 CNIF R/W-0 CMIF R/W-0 MI2C1IF
IFS1: INTERRUPT FLAG STATUS REGISTER
R/W-0 U2RXIF R/W-0 INT2IF R/W-0 T5IF R/W-0 T4IF R/W-0 OC4IF R/W-0 OC3IF R/W-0 SI2C1IF
U2TXIF: UART2 Transmitter Interrupt Flag Status Interrupt request occurred Interrupt request occurred U2RXIF: UART2 Receiver Interrupt Flag Status Interrupt request occurred Interrupt request occurred INT2IF: External Interrupt Flag Status Interrupt request occurred Interrupt request occurred T5IF: Timer5 Interrupt Flag Status Interrupt request occurred Interrupt request occurred T4IF: Timer4 Interrupt Flag Status Interrupt request occurred Interrupt request occurred OC4IF: Output Compare Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred OC3IF: Output Compare Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read INT1IF: External Interrupt Flag Status Interrupt request occurred Interrupt request occurred CNIF: Input Change Notification Interrupt Flag Status Interrupt request occurred Interrupt request occurred CMIF: Comparator Interrupt Flag Status Interrupt request occurred Interrupt request occurred MI2C1IF: Master I2C1 Event Interrupt Flag Status Interrupt request occurred Interrupt request occurred SI2C1IF: Slave I2C1 Event Interrupt Flag Status Interrupt request occurred Interrupt request occurred
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REGISTER 6-7:
R/W-0 IC5IF Legend: Readable Value 15-14 Writable Unimplemented bit, read cleared unknown R/W-0 IC4IF R/W-0 IC3IF R/W-0 SPI2IF
IFS2: INTERRUPT FLAG STATUS REGISTER
R/W-0 PMPIF R/W-0 OC5IF R/W-0 SPF2IF
Unimplemented: Read PMPIF: Parallel Master Port Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read OC5IF: Output Compare Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read IC5IF: Input Capture Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred IC4IF: Input Capture Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred IC3IF: Input Capture Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read SPI2IF: SPI2 Event Interrupt Flag Status Interrupt request occurred Interrupt request occurred SPF2IF: SPI2 Fault Interrupt Flag Status Interrupt request occurred Interrupt request occurred
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REGISTER 6-8:
Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0 IC4IF R/W-0 IC3IF R/W-0 SPI2IF R/W-0 SPI2IF
IFS3: INTERRUPT FLAG STATUS REGISTER
R/W-0 PMPIF
Unimplemented: Read RTCIF: Real-Time Clock/Calendar Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read INT4IF: External Interrupt Flag Status Interrupt request occurred Interrupt request occurred INT3IF: External Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read MI2C2IF: Master I2C2 Event Interrupt Flag Status Interrupt request occurred Interrupt request occurred SI2C2IF: Slave I2C2 Event Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read
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