DS80C310 High-Speed Microcontroller DS80C310 fast 80C31/80C32-com

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DS80C310 High-Speed Microcontroller DS80C310 fast 80C31/80C32-com

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19-4859; 8/09
DS80C310 High-Speed Microcontroller
DS80C310 fast 80C31/80C32-compatible microcontroller. features redesigned processor core without wasted clock memory cycles. result, executes every 8051 instruction between 1.5x faster than original architecture same crystal speed. Typical applications have speed improvement 2.5x using same code same crystal. DS80C310 offers 25MHz maximum crystal speed, resulting apparent execution speeds 62.5MHz (approximately 2.5x). DS80C310 compatible with standard 80C32 includes standard resources such three timer/counters, bytes RAM, serial port. also provides dual data pointers (DPTRs) speed block data memory moves. also adjust speed MOVX data memory access between nine machine cycles flexibility selecting external memory peripherals. DS80C310 offers upward compatibility with DS80C320.
CONFIGURATIONS
VIEW
FEATURES
80C32 Compatible 8051 Instruction Compatible Full-Duplex Serial Port Three 16-Bit Timer/Counters Bytes Scratchpad Multiplexed Address/Data Addresses 64kB 64kB High-Speed Architecture Clocks/Machine Cycle (8051 Runs 25MHz Clock Rates Single-Cycle Instruction 160ns Dual Data Pointer Optional Variable Length MOVX Access Fast/Slow /Peripherals Total Interrupt Sources with External Internal Power-On Reset Circuit Upwardly Compatible with DS80C320 Available 40-Pin Plastic DIP, 44-Pin PLCC, 44-Pin TQFP
Note: Designers must have documents fully features this device: this data sheet High-Speed Microcontroller User's Guide, available website Data sheets contain descriptions, feature overviews, electrical specifications, whereas user's guide contains detailed information about device features operation.
Note: Some revisions this device incorporate deviations from published specifications known errata. Multiple revisions device simultaneously available through various sales channels. information about device errata, click here: www.maxim-ic.com/errata.
DS80C310
ORDERING INFORMATION
PART DS80C310-MCG DS80C310-MCG+ DS80C310-QCG DS80C310-QCG+ DS80C310-QNG DS80C310-QNG+ DS80C310-ECG DS80C310-ECG+ TEMP RANGE +70C +70C +70C +70C -40C +85C -40C +85C +70C +70C CLOCK SPEED (MHz) PIN-PACKAGE Plastic Plastic PLCC PLCC PLCC PLCC TQFP TQFP
Denotes lead(Pb)-free/RoHS-compliant device.
Figure Block Diagram
DS80C310
DS80C310
DESCRIPTION
PDIP PLCC TQFP NAME FUNCTION Port (I/O). Port functions both 8-bit bidirectional port alternate functional interface Timer external interrupts. reset condition Port with bits logic this state, weak pullup holds port high. This condition also serves input mode, since external circuit that writes port overcomes weak pullup. When software writes port pin, DS80C310 activates strong pulldown that remains until either written reset occurs. Writing after port been causes strong transition driver turn followed weaker sustaining pullup. Once momentary strong driver turns off, port once again becomes output high (and input) state. alternate modes Port outlined follows: PORT ALTERNATE FUNCTION PDIP PLCC TQFP 40-44, P1.0-P1.7
External Timer/Counter Timer/Counter Capture/Reload P1.1 T2EX Trigger DS80C320 serial P1.2 port DS80C320 serial P1.3 port External Interrupt P1.4 INT2 (Positive Edge Detect) External Interrupt P1.5 (Negative Edge INT3 Detect) External Interrupt P1.6 INT4 (Positive Edge Detect) External Interrupt P1.7 (Negative Edge INT5 Detect) Reset (Input). input contains Schmitt voltage input recognize external active-high reset inputs. also employs internal pulldown resistor allow combination wired-OR external reset sources. P1.0
DS80C310
PDIP
PLCC
TQFP
NAME
FUNCTION Port (I/O). Port functions both 8-bit bidirectional port alternate functional interface external Interrupts, Serial Port Timer Inputs, strobes. reset condition Port with bits logic this state, weak pullup holds port high. This condition also serves input mode, since external circuit that writes port will overcome weak pullup. When software writes port pin, DS80C310 will activate strong pulldown that remains until either written reset occurs. Writing after port been will cause strong transition driver turn followed weaker sustaining pullup. Once momentary strong driver turns off, port once again becomes both output high input state. alternate modes Port follows:
PDIP PLCC TQFP PORT P3.0 ALTERNATE RXD0 FUNCTION
10-17
13-19
7-13
P3.0-P3.7
XTAL2, XTAL1 (P2.0) (P2.1) (P2.2) (P2.3) (P2.4) (P2.5) (P2.6) (P2.7)
Serial Port Input Serial Port P3.1 TXD0 Output External Interrupt INT0 P3.2 External Interrupt INT1 P3.3 Timer External P3.4 Input Timer External P3.5 Input External Data Memory Write P3.6 Strobe External Data P3.7 Memory Read Strobe Crystal Oscillator Pins. XTAL1 XTAL2 provide support parallel resonant, AT-cut crystals. XTAL1 also acts input event that external clock source used place crystal. XTAL2 serves output crystal amplifier.
Digital Circuit Ground Address Outputs (Port (Output). Port serves external addressing. P2.7 P2.0 DS80C310 automatically places address external access. Although Port accessed like ordinary port, value stored Port latch never seen pins (due memory access). Therefore, writing Port software only useful instructions MOVX MOVX These instructions Port internal latch supply external address MSB; Port latch value supplied address information.
DS80C310
PDIP
PLCC
TQFP
NAME PSEN
FUNCTION Active-Low Program Store Enable (Output). This signal commonly connected external memory chip enable. PSEN driven high when data memory (RAM) being accessed through during reset condition. Address Latch Enable (Output). output functions clock latch external address from multiplexed address/data Port This signal commonly connected latch enable external family transparent latch. forced high when DS80C310 reset condition. Active-Low External Access (Input). This must connected ground proper operation. Address/Data (Port (I/O). Port multiplexed address/data bus. During time when high, memory address presented. When falls logic port transitions bidirectional data bus. This used read external read/write external memory peripherals. Port true port latch cannot written directly software. reset condition Port high. Power Supply Connection (Reserved). These pins should connected. They reserved with future devices this family.
(P0.7) (P0.6) (P0.5) (P0.4) (P0.3) (P0.2) (P0.1) (P0.0) N.C.
COMPATIBILITY
DS80C310 fully static, CMOS, 8051-compatible microcontroller designed high performance. most cases DS80C310 drop into existing socket 80C31 80C32 significantly improve operation. general, software written existing 8051-based systems works without modification DS80C310. exception critical timing because high-speed microcontroller performs instructions much faster than original given crystal selection. DS80C310 runs standard 8051 family instruction compatible with DIP, PLCC, TQFP packages. DS80C310 streamlined version DS80C320. maintains upward compatibility fewer peripherals. DS80C310 provides three 16-bit timer/counters, full-duplex serial port, bytes direct RAM. ports have same operation standard 8051 product. Timers default clock-percycle operation keep their timing compatible with original 8051 family systems. However, timers individually programmable clocks cycle desired. DS80C310 provides several hardware functions that controlled Special Function Registers (SFRs). Table summarizes SFRs.
PERFORMANCE OVERVIEW
DS80C310 features high-speed 8051-compatible core. Higher speed comes just from increasing clock frequency from newer, more efficient design. This updated core does have dummy memory cycles that exist standard 8051. conventional 8051 generates machine cycles using clock frequency divided DS80C310, same
DS80C310
machine cycle takes clocks. Thus fastest instruction, machine cycle, executes three times faster same crystal frequency. Note that these identical instructions. majority instructions DS80C310 will full 3-to-1 speed improvement. Some instructions will between improvement. instructions faster than original 8051. numerical average codes gives approximately 2.5-to-1 speed improvement. Improvement individual programs depends actual instructions used. Speed-sensitive applications would make most instructions that three times faster. However, sheer number 3-to-1 improved codes makes dramatic speed improvements likely code. These architecture improvements 0.8m CMOS produce peak instruction cycle 160ns (6.25MIPS). dual data pointer feature also allows user eliminate wasted instructions when moving blocks memory.
INSTRUCTION SUMMARY
instructions DS80C310 perform same functions their 8051 counterparts. Their effect bits, flags, other status functions identical. However, timing each instruction different. This applies both absolute relative number clocks. absolute timing real-time events, timing software loops calculated using table High-Speed Microcontroller User's Guide. However, counter/timers default older clocks increment. this way, timer-based events occur standard intervals with software executing higher speed. Timers optionally clocks increment take advantage faster processor operation. relative time instructions might different architecture than previously. example, original architecture "MOVX DPTR" instruction "MOV direct, direct" instruction used machine cycles oscillator cycles. Therefore, they required same amount time. DS80C310, MOVX instruction takes little machine cycles oscillator cycles "MOV direct, direct" uses machine cycles oscillator cycles. While both faster than their original counterparts, they have different execution times. This because DS80C310 usually uses instruction cycle each instruction byte. user concerned with precise program timing should examine timing each instruction familiarity with changes. Note that machine cycle requires just clocks, provides pulse cycle. Many instructions require only cycle, some require original architecture, were cycles except DIV. Refer High-Speed Microcontroller User's Guide details individual instruction timing.
DS80C310
SPECIAL FUNCTION REGISTERS (SFRs)
Special Function Registers control most special features DS80C310. High-Speed Microcontroller User's Guide contains descriptions SFRs. Functions that part standard 80C32 bold. Table Special Function Registers
REGISTER DPL1 DPH1 PCON TCON TMOD CKCON EXIF SCON SBUF SADDR0 SADEN0 STATUS T2CON T2MOD RCAP2L RCAP2H WDCON SMOD GATE P1.7 SMO/FE P2.7 P3.7 SM0D0 P1.6 P2.6 P3.6 EXF2 P1.5 P2.5 P3.5 RCLK P1.4 P2.4 P3.4 TCLK GATE P1.3 P2.3 P3.3 EXEN2 P1.2 P2.2 P3.2 STOP P1.1 P2.1 P3.1 T2OE IDLE P1.0 P2.0 P3.0 DCEN ADDRESS
DS80C310
MEMORY ACCESS
DS80C310 bytes scratchpad RAM, contains on-chip ROM. Off-chip memory accessed using multiplexed address/data address Timing diagrams provided Absolute Maximum Ratings section. Program memory (ROM) accessed fixed rate determined crystal frequency actual instructions. mentioned above, instruction cycle requires clocks. Data memory (RAM) accessed according variable speed MOVX instruction described below.
STRETCH MEMORY CYCLE
DS80C310 allows application software adjust speed data memory access. microcontroller perform MOVX instruction cycles. However, this value stretched needed that both fast memory slow memory peripherals accessed with glue logic. Even high-speed systems, necessary desirable perform data memory access full speed. addition, there variety memory-mapped peripherals such displays UARTs that fast. stretch MOVX controlled Clock Control Register location described below. This allows user select stretch value between stretch results 2-machine-cycle MOVX. stretch results MOVX machine cycles. Software dynamically change this value depending particular memory peripheral. reset, stretch value defaults resulting 3-cycle MOVX. Therefore, access performed full speed. This convenience existing designs that have fast place. When maximum speed desired, software should select stretch value When using very slow peripherals, larger stretch value selected. Note that this affects data memory only only slow program memory (ROM) access slower crystal. Using stretch value between causes microcontroller stretch read/write strobe related timing. This results wider read/write strobe allowing more time memory/peripherals respond. timing variable speed MOVX shown Absolute Maximum Ratings section. Note that full speed access reset default case. Table shows resulting strobe widths each stretch value. memory stretch implemented using Clock Control Special Function Register location 8Eh. stretch value selected using bits CKCON.2-CKCON.0. table, these bits referred through first stretch (default) allows common 120ns 150ns RAMs without dramatically lengthening memory access.
DS80C310
Table Data Memory Cycle Stretch Values
CKCON.2-CKCON.0 MEMORY CYCLES (default) STROBE WIDTH CLOCKS 25MHz STROBE WIDTH (ns) 1120
DUAL DATA POINTER (DPTR)
Data memory block moves accelerated using DS80C310 dual data pointer (DPTR). standard 8032 DPTR 16-bit value that used address off-chip data peripherals. DS80C310, standard data pointer called DPTR located addresses 83h. These standard locations. modification standard code needed DPTR. DPTR located called DPTR1. DPTR select (DPS) chooses active pointer located location 86h. other bits register have effect user switches between data pointers toggling register 86h. increment (INC) instruction fastest accomplish this. DPTR-related instructions currently selected DPTR activity. Therefore, only instruction required switch from source destination address. Using DPTR saves code from needing save source destination addresses when doing block move. Once loaded, software simply switches between DPTR0 relevant register locations follows. DPL1 DPH1 byte original DPTR High byte original DPTR byte DPTR High byte DPTR DPTR Select (lsb)
STOP MODE ENHANCEMENTS
Setting Power Control Register (PCON; 87h) invokes stop mode. Stop mode lowest power state because turns internal clocking. standard stop mode approximately (but specified Absolute Maximum Ratings section). exits stop mode from external interrupt reset condition. Internally generated interrupts useful since they require clocking activity. DS80C310 allows resume from stop using INT2-INT5, which edge-triggered interrupts. internal crystal counter manages startup timing. delay 65,536 clocks occurs allow crystal time stabilize. Software must also insert delay machine cycles following exit from stop mode. This ensures stabilization internal timing prior time-critical software tasks such serial port operations access memory-mapped devices.
DS80C310
PERIPHERAL OVERVIEW
DS80C310 provides same peripheral functions standard 80C32. device compatible with DS80C320, does offer peripherals.
TIMER RATE CONTROL
There important difference between DS80C310 8051 regarding timers. original 8051 used clocks cycle timers machine cycles. DS80C310 architecture normally uses clocks machine cycle. However, area timers serial ports, DS80C310 defaults clocks cycle reset. This allows existing code with real-time dependencies such baud rates operate properly. application needs higher speed timers serial baud rates, user select individual timers 4-clock rate. Clock Control Register (CKCON; 8Eh) determines these timer speeds. When relevant CKCON logic DS80C310 uses clocks cycle generate timer speeds. When DS80C310 uses clocks timer speeds. reset condition CKCON.5 selects speed Timer CKCON.4 selects Timer CKCON.3 selects Timer Note that unless user desires very fast timing, unnecessary alter these bits. Also note that timer controls independent.
POWER-ON RESET
DS80C310 holds itself reset during power-up until 65,536 clock cycles have elapsed. poweron reset used DS80C310 differs somewhat from other members high-speed microcontroller family. crystal oscillator start anywhere between 1.0V 4.5V, specified. This eliminates need reset circuit. voltage-specific precision-brownout detection, external component needed. When device goes through power-on reset, flag WDCON (D8h) register
INTERRUPTS
DS80C310 provides interrupt sources with priority levels. Software assign high priority sources. interrupts that 8051 have lower natural priority than originals.
Table Interrupt Sources Priorities NAME DESCRIPTION VECTOR NATURAL PRIORITY
INT0 INT1 SCON INT2 INT3 INT4 INT5
External Interrupt Timer External Interrupt Timer from serial port Timer External Interrupt External Interrupt External Interrupt External Interrupt
DS80C310
ABSOLUTE MAXIMUM RATINGS
Voltage Range Relative Ground.-0.3V (VCC 0.5V) Voltage Range Relative Ground.-0.3V +6.0V Operating Temperature Range.-40C +85C Storage Temperature Range.-55C +125C Soldering Temperature.See IPC/JEDEC J-STD-020 Specification
This stress rating only functional operation device these other conditions above those indicated operation sections this specification implied. Exposure absolute maximum rating conditions extended periods time affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC 4.5V 5.5V, -40C +85C.) (Note PARAMETER SYMBOL Supply Voltage Supply Current Active Mode 25MHz Supply Current Idle Mode IIDLE 25MHz Supply Current Stop Mode ISTOP Input Level Input High Level (Except XTAL1 RST) Input High Level XTAL1 Output Voltage Ports 1.6mA Output Voltage Port ALE, VIH2 VOL1 VOL2 VOH1 VOH2 VOH3 RRST -300 -650 +300 -0.3 0.15 0.15 +0.8 0.45 0.45 UNITS NOTES
PSEN 3.2mA
Output High Voltage Port ALE,
PSEN -50A
Output High Voltage Ports -1.5mA Output High Voltage Port ALE,
PSEN -8mA
Input Current Ports 0.45V Transition Current from Ports Input Leakage Port Mode Pulldown Resistance
Note Note Note Note Note
parameters apply both commercial industrial temperature operation unless otherwise noted. Specifications -40C guaranteed design product tested. voltages referenced ground. Active current measured with 25MHz clock source driving XTAL1, 5.5V, other pins disconnected. Idle mode current measured with 25MHz clock source driving XTAL1, 5.5V, ground, other pins disconnected. Stop mode current measured with XTAL1 grounded, =5.5V, other pins disconnected.
DS80C310
Note When addressing external memory. This specification applies first clock cycle following transition. subsequent cycles following transitions, typical current sink capability Port Port approximately 150A, minimum current sink capability PSEN approximately 400A. subsequent cycles following transitions, typical current drive capability Port Port approximately 110A. VCC. This condition mimics operation pins mode. During transition, one-shot drives ports hard clock cycles. This measurement reflects port transition mode. Current required from external circuit hold logic-low level while corresponding port latch This only current required hold level; transitions from must also overcome transition current. Ports source transition current when being pulled down externally. current reaches maximum approximately 0.45 <VCC. high-impedance input. This port weak address holding latch because Port dedicated address DS80C310. Peak current occurs near input transition point latch, approximately
Note Note Note
Note Note
Figure Typical Frequency
DS80C310
ELECTRICAL CHARACTERISTICS (Note
PARAMETER Oscillator Frequency External Oscillator External Crystal SYMBOL 1/tCLCL tLHLL tAVLL tLLAX1 tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV1 tAVIV2 tPLAZ (Note 25MHz (Note VARIABLE CLOCK 1.5tCLCL5 0.5tCLCL5 0.5tCLCL(Note 2.5tCLCL20 0.5tCLCL13 2tCLCL-5 2tCLCL20 tCLCL-5 3tCLCL20 3.5tCLCL25 (Note UNITS
Pulse Width Port Address Valid Address Hold after Valid Instruction PSEN PSEN Pulse Width PSEN Valid Instruction Input Instruction Hold after PSEN Input Instruction Float after PSEN Port Address Valid Instruction Port Address Valid Instruction PSEN Address Float
Note
parameters apply both commercial industrial temperature operation unless otherwise noted. Specifications -40C guaranteed design product tested. electrical characteristics assume duty cycle oscillator, 100% tested guaranteed design. signals characterized with load capacitance 80pF except Port ALE, PSEN, with 100pF. Interfacing memory devices with float times (turn-off times) over 25ns cause contention. This does damage parts, rather causes increase operating current. Port timing changes relation duty cycle variation. Address held weak latch until overdriven external memory.
Note
DS80C310
MOVX CHARACTERISTICS
PARAMETER Data Access Pulse Width Port Address Valid
Address Hold after MOVX Write
SYMBOL tLHLL2 tAVLL2 tLLAX2 tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV1
Pulse Width Pulse Width Valid Data Data Hold after Read Data Float after Read Valid Data Port Address Valid Data
Port Address Valid Data Port Address Port Address Data Valid Transition Data Hold after Write Address Float High High
Note
tAVDV2 tLLWL tAVWL1 tAVWL2 tQVWX tWHQX tRLAZ tWHLH
VARIABLE CLOCK 1.5tCLCL-5 2tCLCL-5 0.5tCLCL-5 tCLCL-5 0.5tCLCL-15 tCLCL-7 2tCLCL-5 tMCS-10 2tCLCL-5 tMCS-10 2tCLCL-20 tMCS-20 tCLCL-5 2tCLCL-5 2.5tCLCL-28 tCLCL+tMCS-40 3tCLCL-22 2.0tCLCL+ tMCS 3.5tCLCL-35 2.5tCLCL+ tMCS35 0.5tCLCL-14 0.5tCLCL+5 tCLCL-8 tCLCL+5 tCLCL-9 2tCLCL-8 1.5tCLCL-10 2.5tCLCL-10 tCLCL-11 2tCLCL-10 (Note tCLCL-5 tCLCL+9
UNITS
STRETCH (Note tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0
tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0
tMCS time period related stretch memory cycle selection. following table shows value tMCS each stretch selection. MOVX CYCLES machine cycles machine cycles (default) machine cycles machine cycles machine cycles machine cycles machine cycles machine cycles tMCS tCLCL tCLCL tCLCL tCLCL tCLCL tCLCL tCLCL
DS80C310
Note Address held weak latch until overdriven external memory.
EXTERNAL CLOCK CHARACTERISTICS
PARAMETER Clock High Time Clock Time Clock Rise Time Clock Fall Time SYMBOL tCHCX tCLCX tCLCL tCHCL UNITS
SERIAL PORT MODE TIMING CHARACTERISTICS
PARAMETER Serial Port Clock Cycle Time Output Data Setup Clock Rising SYMBOL tXLXL CONDITIONS clocks cycle clocks cycle clocks cycle tQVXH clocks cycle clocks cycle tXHQX clocks cycle clocks cycle tXHDX clocks cycle tXHDV clocks cycle clocks cycle tCLCL 11tCLCL 3tCLCL tCLCL tCLCL 3tCLCL 2tCLCL 12tCLCL 4tCLCL 10tCLCL UNITS
Output Data Hold from Clock Rising
Input Data Hold after Clock Rising Clock Rising Edge Input Data Valid
DEFINITION SYMBOLS
effort remain compatible with original 8051 family, this device specifies same parameters such devices, using same symbols. completeness, following description symbols. Time Address Clock Input Data Logic Level High Logic Level Instruction
PSEN
Output Data Signal Valid Signal longer valid logic level Tri-State
DS80C310
EXTERNAL PROGRAM MEMORY READ CYCLE
DS80C310
EXTERNAL DATA MEMORY READ CYCLE
DS80C310
DATA MEMORY WRITE CYCLE
DATA MEMORY WRITE WITH STRETCH
DS80C310
DATA MEMORY WRITE WITH STRETCH
EXTERNAL CLOCK DRIVE
DS80C310
SERIAL PORT MODE TIMING
DS80C310
PACKAGE INFORMATION
latest package outline information land patterns, www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT 21-0293 21-0044 21-0049
TQFP PDIP PLCC
C44+2 P40+1 Q44+1
DS80C310
REVISION HISTORY
REVISION DATE DESCRIPTION PAGES CHANGED
090198
012401
102405
042106
8/09
Added note clarify specification. Changed serial port mode timing diagram label from tQVXL tQVXH Changed minimum oscillator frequency 1MHz when using external crystal. Corrected "Data memory write with stretch" diagrams show falling edge coincident with rising edge clock. Added errata disclaimer page Device moved qualified status. Removed "Preliminary" status from data sheet. Removed references 33MHz versions device. Added note requiring machine cycles delay following stop mode exit. This edit transfers existing erratum from errata sheet into data sheet. Updated Absolute Maximum Ratings table match current format. Displayed Electrical Characteristics test conditions. Added notation that -40C specifications guaranteed design tested. Clarified Electrical Characteristics note that specification only applies first clock cycle following transition. Added lead-free part numbers Ordering Information table. Added tAVLL2 specification. Updated timing characteristics with full characterization data. Changed lead-free ordering information part numbers correctly reflect that comes after part numbers (e.g., DS80C310-MCG+). Added Note Electrical Characteristics MOVX Characteristics tables. Removed additional references 33MHz versions device.
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600
2009 Maxim Integrated Products Maxim registered trademark Maxim Integrated Products, Inc.

DS80C310 High-Speed Microcontroller DS80C310 fast 80C31/80C32-com

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