Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DS4422 DS4424 c

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Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DS4422 DS4424 c

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19-4744; 7/09
Two-/Four-Channel, I2C, 7-Bit Sink/Source Current
DS4422 DS4424 contain four programmable current DACs that each capable sinking sourcing current 200µA. Each output sink source settings that programmed using interface. current outputs power high-impedance state. Full-Scale Current 50µA 200µA Full-Scale Range Each Determined External Resistors Settings Each Sink Source Modes I2C-Compatible Serial Interface Address Pins Allow Four Devices Same Cost Small Package (14-Pin, TDFN) -40°C +85°C Temperature Range 2.7V 5.5V Operating Range
Features
(DS4422) Four (DS4424) Current DACs
DS4422/DS4424
Applications
Power-Supply Adjustment Power-Supply Margining Adjustable Current Sink Source
Ordering Information
PART DS4422N+ DS4422N+T&R DS4424N+ DS4424N+T&R OUTPUTS TEMP RANGE -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C PINPACKAGE TDFN-EP TDFN-EP TDFN-EP TDFN-EP
Configuration appears data sheet.
+Denotes lead(Pb)-free/RoHS-compliant package. Tape reel. Exposed pad.
Typical Operating Circuit
VOUT0 VOUT1 DC-DC CONVERTER DC-DC CONVERTER
DS4422/ DS4424
OUT0 OUT1
RFS0
RFS1
Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim Direct 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DS4422/DS4424
ABSOLUTE MAXIMUM RATINGS
Voltage Range VCC, SDA, Relative Ground.-0.5V +6.0V Voltage Range FS0, FS1, FS2, FS3, OUT0, OUT1, OUT2, OUT3 Relative Ground .-0.5V (VCC 0.5V) (Not exceed 6.0V.) Operating Temperature Range .-40°C +85°C Storage Temperature Range .-55°C +125°C Soldering Temperature .Refer IPC/JEDEC J-STD-020 Specification.
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
RECOMMENDED OPERATING CONDITIONS
-40°C +85°C.)
PARAMETER Supply Voltage Input Logic (SDA, SCL, Input Logic (SDA, SCL, Full-Scale Resistor Values SYMBOL RFS0, RFS1, (Note RFS2, RFS3 (Note CONDITIONS -0.3 UNITS
ELECTRICAL CHARACTERISTICS
(VCC +2.7V +5.5V, -40°C +85°C.)
PARAMETER Supply Current Input Leakage (SDA, SCL) Output Leakage (SDA) Output Current (SDA) Voltage Capacitance SYMBOL VRFS CI/O 0.4V 0.6V 0.976 5.5V (Note 5.5V CONDITIONS DS4422 DS4424 UNITS
OUTPUT CURRENT SOURCE CHARACTERISTICS
(VCC +2.7V +5.5V, -40°C +85°C.)
PARAMETER Output Voltage Sinking Current Output Voltage Sourcing Current Full-Scale Sink Output Current Output Current Full-Scale Accuracy Output Current Temperature Coefficient SYMBOL VOUT:SINK (Note CONDITIONS -200 0.75 UNITS ppm/°C
VOUT:SOURCE (Note IOUT:SINK (Notes +25°C, 3.3V; using 0.1% resistor (Note VOUT0 VOUT1 1.2V (Note
Full-Scale Source Output Current IOUT:SOURCE (Notes OUT:FS OUT:TC
Two-/Four-Channel, I2C, 7-Bit Sink/Source Current
OUTPUT CURRENT SOURCE CHARACTERISTICS (continued)
(VCC +2.7V +5.5V, -40°C +85°C.)
PARAMETER Output Current Variation Power-Supply Change Output Current Variation Output-Voltage Change Output Leakage Current Zero Current Setting Output Current Differential Linearity Output Current Integral Linearity ZERO (Notes (Notes SYMBOL source sink source, measure 1.2V sink, VOUT measure 1.2V -0.5 CONDITIONS 0.32 0.42 0.16 0.16 +0.5 UNITS
DS4422/DS4424
ELECTRICAL CHARACTERISTICS
(VCC +2.7V +5.5V, -40°C +85°C.)
PARAMETER Clock Frequency Free Time Between STOP START Conditions Hold Time (Repeated) START Condition Period High Period Data Hold Time Data Setup Time START Setup Time Rise Time Fall Time STOP Setup Time Capacitive Loading SYMBOL tBUF tHD:STA tLOW tHIGH tDH:DAT SU:DAT SU:STA SU:STO (Note (Note (Note (Note CONDITIONS 0.1CB 0.1CB UNITS
Note Note Note
voltages with respect ground. Currents entering specified positive, currents exiting negative. Input resistors (RFS) must between speciifed values ensure device meets accuracy linearity specifications. Supply current specified with outputs zero current setting. connected GND. connected VCC. Excludes current through resistors (IRFS). Total current including IRFS IRFS). Note output-voltage range must satisfied ensure device meets accuracy linearity specifications. Note Temperature drift excludes drift caused external resistor. Note Differential linearity defined difference between expected incremental current increase with respect position actual increase. expected incremental increase full-scale range divided 127. Note Guaranteed design. Note Integral linearity defined difference between expected value function setting actual value. expected value straight line between zero full-scale values proportional setting. Note Timing shown fast-mode (400kHz) operation. This device also backward compatible with standard-mode timing. Note CB-total capacitance line
Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DS4422/DS4424
Typical Operating Characteristics
+25°C, unless otherwise noted.)
SUPPLY CURRENT SUPPLY VOLTAGE
DS4422/4 toc01
SUPPLY CURRENT TEMPERATURE
DS4422/4 toc02
VOLTCO (SOURCE)
LOAD FS0, FS1, FS2, -175 IOUT
DS4422/4 toc03
5.0V SUPPLY CURRENT
-150
SUPPLY CURRENT
3.3V 2.7V DOES INCLUDE CURRENT DRAWN RESISTORS CONNECTED FS0, FS1, FS2,
-200
DOES INCLUDE CURRENT DRAWN RESISTORS CONNECTED FS0, FS1, FS2,
-225
SUPPLY VOLTAGE
TEMPERATURE (°C)
-250 VOUT
VOLTCO (SINK)
DS4422/4 toc04
TEMPERATURE COEFFICIENT SETTING (SOURCE)
DS4422/4 toc05
TEMPERATURE COEFFICIENT SETTING (SINK)
TEMPERATURE COEFFICIENT (°C/ppm) +25°C -40°C -100 -150 -200 -250
DS4422/4 toc06
LOAD FS0, FS1, FS2, IOUT
TEMPERATURE COEFFICIENT (°C/ppm) -100 200A CURRENT SOURCE RANGE
+25°C -40°C
+25°C +85°C
+25°C +85°C
VOUT
200A CURRENT SINK RANGE
SETTING (DEC)
SETTING (DEC)
INTEGRAL LINEARITY
DS4422/4 toc07
DIFFERENTIAL LINEARITY
(LSB) -0.2 -0.4 -0.6 -0.8 -1.0 200A CURRENT SOURCE SINK RANGE
DS4422/4 toc08
1.00 0.75 0.50 (LSB) 0.25 -0.25 -0.50 -0.75 -1.00 200A CURRENT SOURCE SINK RANGE
SETTING (DEC)
SETTING (DEC)
Two-/Four-Channel, I2C, 7-Bit Sink/Source Current
Description
DS4424 DS4422 NAME OUT0 OUT1 OUT2 OUT3 N.C. Address Select Inputs. Determines slave address connecting GND. Detailed Description section available device addresses. Power Supply Connection Exposed Pad. Connect leave unconnected. Current Output. Sinks sources current determined interface resistance connected FSx. (The DS4422 only outputs: OUT0 OUT1.) Full-Scale Calibration Input. resistor ground these pins determines full-scale current each output. controls OUT0, controls OUT1, etc. (The DS4422 only inputs: FS1.) FUNCTION Serial Data. Input/output data. Serial Clock. Input clock. Ground
DS4422/DS4424
Block Diagram
I2C-COMPATIBLE SERIAL INTERFACE
DS4422/DS4424
SOURCE SINK MODE CURRENT DAC0 POSITIONS EACH SINK SOURCE MODE
CURRENT DAC1
CURRENT DAC2
CURRENT DAC3
RFS0 OUT0
RFS1 OUT1
RFS2 OUT2
RFS3 OUT3
DS4424 ONLY
Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DS4422/DS4424
Detailed Description
DS4422/DS4424 contain four adjustable current sources that each capable sinking sourcing current. Each output (OUT0, OUT1, OUT2, OUT3) sink source settings that controlled interface. full-scale ranges corresponding step sizes outputs determined external resistors, connected pins FS0, FS1, FS2, FS3, that adjust output current over range. Pins OUT2, OUT3, FS2, only available DS4424. formula determine (connected pins) attain desired full-scale current range Equation Where desired full-scale current value, VRFS voltage (see Electrical Characteristics table), external resistor value. calculate output current value (IOUT) based corresponding value (see Table corresponding memory addresses), equation Equation IOUT Value(dec)
Slave Address DS4422/DS4424 respond four slave addresses determined address inputs, address inputs should connected either ground. Table lists slave addresses determined address input combinations.
Table Slave Addresses
SLAVE ADDRESS (HEX)
Memory Organization
control DS4422/DS4424's current sources, write memory addresses listed Table
Table Memory Addresses
MEMORY ADDRESS (HEX) FAh* FBh* CURRENT SOURCE OUT0 OUT1 OUT2* OUT3*
power-up DS4422/DS4424 output zero current. This done prevent them from sinking sourcing incorrect amount current before system host controller chance modify device's setting. source biasing instrumentation other circuits, DS4422/DS4424 provide simple inexpensive current source with interface control. adjustable full-scale range allows application most 7-bit sink source resolution. When used adjustable power-supply applications (see Typical Operating Circuit), DS4422/DS4424 affect initial power-up voltage supply because they default providing zero output current power-up. devices source sink current into feedback-voltage node, they change amount output voltage required regulator reach steadystate operating point. Using external resistor, RFS, output current range, DS4422/DS4424 provide some flexibility adjusting impedances feedback network range over which power supply controlled margined.
*Only DS4424.
format each output control register given
Where:
NAME Sign FUNCTION Determines sources sinks current. sink source 7-Bit Data Controlling Output. Setting 0000000b outputs zero current regardless state sign bit. POWER-ON DEFAULT
Data
0000000b
Two-/Four-Channel, I2C, 7-Bit Sink/Source Current
Example: RFS0 register 0xF8h written value 0xAAh. Calculate output current. (0.976V/80k) (127/16) 96.838µA output register output sourcing value corresponding position decimal). magnitude output current equal 96.838µA (42/127) 32.025µA STOP Condition: STOP condition generated master data transfer with slave. Transitioning from high while remains high generates STOP condition. Figure applicable timing. Repeated START Condition: master repeated START condition data transfer indicate that will immediately initiate data transfer following current one. Repeated STARTs commonly used during read operations identify specific memory address begin data transfer. repeated START condition issued identically normal START condition. Figure applicable timing. Write: Transitions must occur during state SCL. data must remain valid unchanged during entire high pulse SCL, plus setup hold time requirements (Figure Data shifted into device during rising edge SCL. Read: write operation, master must release line proper amount setup time (Figure before next rising edge during read. device shifts each data falling edge previous pulse data valid rising edge current pulse. Remember that master generates clock pulses, including when reading bits from slave. Acknowledgement (ACK NACK): Acknowledgement (ACK) Acknowledge (NACK) always ninth transmitted during byte transfer. device receiving data (the master during read slave during write operation) performs transmitting zero during ninth bit. device performs
DS4422/DS4424
Serial Interface Description
Definitions following terminology commonly used describe data transfers: Slave Address: slave address DS4422/DS4424 determined state pins (see Table Master Device: master device controls slave devices bus. master device generates clock pulses START STOP conditions.
Slave Devices: Slave devices send receive data master's request. Idle Busy: Time between STOP START conditions when both inactive their logic-high states. When idle often initiates low-power mode slave devices. START Condition: START condition generated master initiate data transfer with slave. Transitioning from high while remains high generates START condition. Figure applicable timing.
tBUF tLOW
tHD:STA
tHD:STA STOP START tHD:DAT NOTE: TIMING REFERENCED VIL(MAX) VIH(MIN). tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
Figure Timing Diagram
Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DS4422/DS4424
TYPICAL WRITE TRANSACTION START SLAVE SLAVE SLAVE STOP
SLAVE ADDRESS*
READ/ WRITE
REGISTER/MEMORY ADDRESS *THE SLAVE ADDRESS DETERMINED ADDRESS PINS
DATA
EXAMPLE TRANSACTIONS (WHEN GROUNDED) SINGLE BYTE WRITE -WRITE REGISTER SINGLE BYTE READ -READ REGISTER SLAVE SLAVE REPEATED START SLAVE STOP
START SLAVE
DATA MASTER NACK STOP
START SLAVE SLAVE
Figure Communication Examples
NACK transmitting during ninth bit. Timing NACK identical other writes (Figure acknowledgment that device properly receiving data. NACK used terminate read sequence indication that device receiving data. Byte Write: byte write consists bits information transferred from master slave (most significant first) plus 1-bit acknowledgement from slave master. bits transmitted master done according bit-write definition, acknowledgement read using bit-read definition. Byte Read: byte read 8-bit information transfer from slave master plus 1-bit NACK from master slave. bits information that transferred (most significant first) from slave master read master using bit-read definition above, master transmits using write definition receive additional data bytes. master must NACK last byte read terminated communication slave will return control master. Slave Address Byte: Each slave responds slave address byte sent immediately following START condition. slave address byte contains slave address most significant bits least significant bit. DS4422/DS4424 slave address determined
state address pins. Table describes addresses corresponding state When (such A0h), master indicating that will write data slave. (A1h this case), master indicating that wants read from slave. incorrect slave address written, DS4422/DS4424 assume master communicating with another device ignore communication until next START condition sent. Memory Address: During write operation, master must transmit memory address identify memory location where slave store data. memory address always second byte transmitted during write operation following slave address byte.
Communication Writing Slave: master must generate START condition, write slave address byte (R/W write memory address, write byte data, generate STOP condition. Remember that master must read slave's acknowledgement during byte-write operations. Reading from Slave: read from slave, master generates START condition, writes slave address byte with reads data byte with NACK indicate transfer, generates STOP condition.
Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DS4422/DS4424
VOUT* 2.0V 4.7k 4.7k DC-DC CONVERTER R0B= 2.67k 4.00k VFB* 0.8V
DS4422/ DS4424
OUT0
RFS0 IOUT0
*VOUT VALUES DETERMINED DC-DC CONVERTER SHOULD CONFUSED WITH VOUT VRFS DS4422/DS4424.
Figure Example Application Circuit
Applications Information
Example Calculations Adjustable Power Supply
this example, Typical Operating Circuit used base create Figure DC-DC output voltage 2.0V with ±20% margin. adjustable power supply DC-DC converter output voltage, VOUT, 2.0V DC-DC converter feedback voltage, VFB, 0.8V. determine relationship R0B, start with equation: VOUT
And: IR0A create margin supply voltage, value VOUT 2.4V. With these values place, calculated 2.67k, calculated 4.00k. current this configuration allows output voltage moved linearly from 1.6V 2.4V using settings. This corresponds resolution 6.3mV/step.
Substituting 0.8V VOUT 2.0V, relationship between determined IOUT0 chosen 100µA (midrange source/sink current DS4422/DS4424). Summing currents into feedback node produces following: IOUT0 IR0B IR0A Where: IR0B
Decoupling achieve best results when using DS4422/ DS4424, decouple power supply with 0.01µF 0.1µF capacitor. high-quality ceramic surfacemount capacitor possible. Surface-mount components minimize lead inductance, which improves performance, ceramic capacitors tend have adequate high-frequency response decoupling applications. Power Rail Considerations
Given that absolute maximum rating pins 0.5V, recommended that DS4424 power rail brought before same time power rail source controlling.
Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DS4422/DS4424
Configuration
VIEW
Package Information
latest package outline information, www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE T1433+2 DOCUMENT 21-0137
(N.C.) (N.C.)
OUT3 (N.C.) OUT2 (N.C.) OUT1 OUT0
TDFN-EP
DS4422/ DS4424
INDICATES DS4422 ONLY. *EXPOSED
Two-/Four-Channel, I2C, 7-Bit Sink/Source Current
Revision History
REVISION NUMBER REVISION DATE 3/08 7/09 Initial release. Added Power Rail Considerations section. DESCRIPTION PAGES CHANGED
DS4422/DS4424
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600
2009 Maxim Integrated Products Maxim registered trademark Maxim Integrated Products, Inc.

Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DS4422 DS4424 c

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