DS2482-800 Eight-Channel 1-Wire Master DS2482-800 1-Wire bridge d
|
|
|
Top Searches for this datasheet
19-4932; 11/09
DS2482-800 Eight-Channel 1-Wire Master
DS2482-800 1-Wire bridge device that interfaces directly standard (100kHz max) fast (400kHz max) masters perform bidirectional protocol conversion between master downstream 1-Wire slave devices. Relative attached 1-Wire slave device, DS2482-800 1-Wire master. Internal factorytrimmed timers relieve system host processor from generating time-critical 1-Wire waveforms, supporting both standard Overdrive 1-Wire communication speeds. optimize 1-Wire waveform generation, DS2482-800 performs slew-rate control rising falling 1-Wire edges programmable feature mask fast presence pulse edge that some 1-Wire slave devices generate. Programmable strong pullup features support 1-Wire power delivery 1-Wire devices such EEPROMs sensors. DS2482-800 combines these features with eight independent 1Wire channels. slave address assignment controlled three binary address inputs, resolving potential conflicts with other slave devices system.
GENERAL DESCRIPTION
FEATURES
Host Interface, Supports 100kHz 400kHz Communication Speeds 1-Wire Master with Selectable Active Passive 1-Wire Pullup Provides Reset/Presence, 8-Bit, Single-Bit, Three-Bit 1-Wire Sequences Eight Channels Independently Operated 1-Wire Standard Overdrive 1-Wire Communication Speeds Slew Controlled 1-Wire Edges Supports Low-Impedance 1-Wire Strong Pullup EEPROMs, Temp Sensors, Other 1-Wire Slaves That Have Momentary High Current Modes Three Address Inputs Address Assignment Wide Operating Range: 2.9V 5.5V, -40°C +85°C 16-Pin Package (150 mil)
PART DS2482S-800+ DS2482S-800+T&R TEMP RANGE +85C +85C PIN-PACKAGE (150 (150
ORDERING INFORMATION
APPLICATIONS
Wireless Base Stations Central Office Switches PBXs Rack-Based Servers Medical Clinical Diagnostic Equipment
+Denotes lead(Pb)-free/RoHS-compliant package. Tape reel.
CONFIGURATION
TYPICAL OPERATING CIRCUIT
1-Wire registered trademark Maxim Integrated Products, Inc.
Note: Some revisions this device incorporate deviations from published specifications known errata. Multiple revisions device simultaneously available through various sales channels. information about device errata, click here: www.maxim-ic.com/errata.
DS2482-800: Eight-Channel 1-Wire Master
ABSOLUTE MAXIMUM RATINGS
Voltage Range Relative Ground Maximum Current Into Operating Temperature Range Junction Temperature Storage Temperature Range Soldering Temperature -0.5V, 20mA -40°C +85°C +150°C -55°C +125°C
IPC/JEDEC J-STD-020A
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device.
ELECTRICAL CHARACTERISTICS
(VCC 2.9V 5.5V, -40°C +85°C.) PARAMETER Supply Voltage Operating Current 1-Wire Input High 1-Wire Input 1-Wire Weak Pullup Resistor 1-Wire Output Active Pullup Time Strong Pullup Voltage Drop 3.3V Pulldown Slew Rate (Note Pulldown Slew Rate (Note 3.3V Pullup Slew Rate (Note Pullup Slew Rate (Note Power-On Reset Trip Point SYMBOL VIH1 VIL1 RWPU VOL1 tAPUOT
VSTRPU
CONDITIONS 3.3V (Note 3.3V (Notes (Notes 3.3V (Notes (Notes (Note load Standard (Notes Overdrive (Notes 3.2V, 1.5mA load load Standard (3.3V 10%) Overdrive (3.3V 10%) Standard (5.0V 10%) Overdrive (5.0V 10%) Standard (3.3V 10%) Overdrive (3.3V 10%) Standard (5.0V 10%) Overdrive (5.0V 10%)
0.75
UNITS
0.75 1675 22.1
V/µs V/µs V/µs V/µs
PDSRC PDSRC PUSRC PUSRC VPOR
1-Wire TIMING (Note Figures Write 1/Read Time Read Sample Time 1-Wire Time Slot Fall Time High-to-Low Standard Speed (Note Fall Time High-to-Low Overdrive Speed (Note tW1L tMSR tslot Standard Overdrive Standard Overdrive Standard Overdrive 3.3V (Note 5.0V (Note 3.3V (Note 5.0V (Note 13.3 65.8 0.54 0.55 0.10 0.09 69.3 10.5 72.8 11.0 0.59 0.44
DS2482-800: Eight-Channel 1-Wire Master PARAMETER Write Time Write Recovery Time Reset Time Presence-Detect Sample Time Sampling Short Interrupt Reset High Time (Note Figure Level Input Voltage HIGH Level Input Voltage Hysteresis Schmitt Trigger Inputs Level Output Voltage Sink Current Output Fall Time from VIhmin VILmax with Capacitance from 10pF 400pF Pulse Width Spikes that Suppressed Input Filter Input Current Each with Input Voltage Between 0.1VCCmax 0.9VCCmax Input Capacitance Clock Frequency Hold Time (Repeated) START Condition. After this Period, First Clock Pulse Generated. Period Clock HIGH Period Clock Setup Time Repeated START Condition Data Hold Time Data Setup Time Setup Time STOP Condition Free Time Between STOP START Condition Capacitive Load Each Line
Oscillator Warm-Up Time
SYMBOL tW0L tREC0 tRSTL tMSP tRSTH
CONDITIONS Standard Overdrive Standard Overdrive Standard Overdrive Standard Overdrive Standard Overdrive Standard Overdrive
68.4 66.5 554.8 70.3
0.75
75.6 73.5 613.2 77.7 0.25 0.22 0.5V
UNITS
Vhys fSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tSU:STO tBUF tOSCWUP
2.9V 3.7V 4.5V 5.5V
-0.5 0.05
pins only (Notes (Note (Notes (Note (Note (Note
DS2482-800: Eight-Channel 1-Wire Master Note Note Note Note Note Note Note Note Note Note Note Note Operating current with 1-Wire write byte sequence followed continuous Read Status Register 400KHz Overdrive. With standard speed total capacitive load 1-Wire should exceed 1nF, otherwise passive pullup threshold VIL1 reached available time. With Overdrive speed capacitive load 1-Wire must exceed 300pF. Active pullup guaranteed turn between VIL1MAX VIH1MIN. Active resistive pullup choice configurable. Fall time high (tF1) derived from PDSRC, referenced from VCC. These values apply full load, standard speed 0.3nF Overdrive speed. reduced load, pulldown slew rate slightly faster. timing values referred VIHmin VILmax levels. Applies SDA, SCL, AD0, AD1, AD2. pins DS2482 obstruct lines switched off. DS2482 provides hold time least 300ns signal (referred VIHmin signal) bridge undefined region falling edge SCL. maximum tHD:DAT only device does stretch period (tLOW) signal. Fast-mode device used standard-mode system, requirement tSU:DAT 250ns must then met. This automatically case device does stretch period signal. such device does stretch period signal, must output next data line tSU:DAT 1000 1250ns (according standard-mode specification) before line released. total capacitance line mixed with HS-mode devices, faster fall-times according Specification v2.1 allowed. communication should take place tOSCWUP time following power-on reset. Except tF1, 1-Wire timing specifications tAPUOT derived from same timing circuit. Therefore, these parameters found typical value, safe assume that these parameters deviate from their typical value same direction same degree.
Note Note Note
DESCRIPTION
NAME FUNCTION Driver 1-Wire Line Serial Clock Input; must tied through pullup resistor. Serial Data Input/Output; must tied through pullup resistor. Power Supply Input Connected Address Inputs; must tied GND. These inputs determine slave address device, Figure Driver 1-Wire Line Driver 1-Wire Line Driver 1-Wire Line Driver 1-Wire Line Ground Reference Driver 1-Wire Line Driver 1-Wire Line Driver 1-Wire Line
DS2482-800: Eight-Channel 1-Wire Master
Figure Block Diagram
Line XCVR T-Time Line XCVR Line XCVR Line XCVR Line XCVR Line XCVR Line XCVR Line XCVR
Config Register
Controller Channel Select
Interface Controller
Status Register Read Data Register
DETAILED DESCRIPTION
DS2482-800 self-timed 8-channel 1-Wire master, which supports advanced 1-Wire waveform features including standard Overdrive speeds, active pullup, strong pullup power delivery. Once supplied with command data, controller DS2482 performs time-critical 1-Wire communication functions such reset/presence detect cycle, read-byte, write-byte, single-bit triplet Search, without requiring interaction with host processor. host obtains feedback (completion 1-Wire function, presence pulse, 1Wire short, search direction taken) through Status Register data through Read Data register. DS2482 communicates with host processor through interface standard-mode fast-mode. logic state three address pins address pins with 1-channel version) determines slave address DS2482, allowing devices operating same segment without requiring hub.
DEVICE REGISTERS
DS2482 four registers that host read: Channel Selection, Configuration, Status, Read Data. These registers addressed read pointer. position read pointer, i.e., register that host will read subsequent read access, defined instruction that DS2482 executed last. host read write access Channel Selection Configuration Registers select several 1Wire channels enable certain 1-Wire features.
DS2482-800: Eight-Channel 1-Wire Master Channel Selection Register content Channel Selection Register specifies which channels selected will target subsequent 1-Wire communication commands. DS2482-800 supports eight 1-Wire communication channels IO7. Only these channels active/selected time. Once selected, 1-Wire channel remains selected until different channel selected through Channel Select command initiating device reset. After device reset (power-up cycle initiated Device Reset command) channel selected. Configuration Register DS2482 supports allows three 1-Wire features that enabled selected through Configuration Register. These features are: Active Pullup (APU) Strong Pullup (SPU) 1-Wire Speed (1WS) These features selected combination. They apply equally 1-Wire channels. While APU, maintain their state, returns inactive state soon strong pullup ended. Configuration Register Assignment
After device reset (power-up cycle initiated Device Reset command) Configuration Register reads 00h. When writing Configuration Register, data accepted only upper nibble (bits one's complement lower nibble (bits When read, upper nibble always Active Pullup (APU) controls whether active pullup (controlled slew-rate transistor) passive pullup (RWPU resistor) will used drive 1-Wire line from high. When active pullup disabled (resistor mode). Active Pullup should always selected unless there only single slave 1-Wire line. active pullup does apply rising edge presence pulse recovery after short 1-Wire line. circuit that controls rising edges (Figure operates follows: pulldown (from DS2482 1-Wire slave) ends. From this point 1-Wire pulled high through RWPU internal DS2482. capacitive load 1-Wire line determine slope. case that active pullup disabled (APU resistive pullup continues, represented solid line. With active pullup enabled (APU when voltage reached level between VIL1max VIH1min, DS2482 actively pulls 1-Wire line high applying controlled slew rate, represented dashed line. active pullup continues until tAPUOT expired From that time resistive pullup will continue.
Figure Rising Edge Pullup
VIH1MIN
VIL1MAX 1-Wire discharged tAPUOT
DS2482-800: Eight-Channel 1-Wire Master Strong Pullup (SPU) controls whether DS2482 applies low-impedance pullup 1-Wire line after last either 1-Wire Write Byte command after 1-Wire Single command completed. strong pullup feature commonly used with 1-Wire EEPROM devices when copying scratchpad data main memory when performing SHA-1 computation, with parasitically powered temperature sensors A-to-D converters. respective device data sheets specify location communications protocol after which strong pullup should applied. configuration register DS2482 must immediately prior issuing command that puts 1-Wire device into state where needs extra power. DS2482 applies active pullup rising edge time slot which strong pullup starts, regardless setting. However, contrast setting active pullup, low-impedance pullup will after tAPUOT expired. Instead, shown Figure low-impedance pullup remains active until: next 1-Wire communication command (the typical case), writing Configuration Register with being (alternative), issuing Device Reset command. Additionally, when pullup ends, automatically reset Using strong pullup does change state Configuration Register.
Figure Low-Impedance Pullup Timing
Last 1-Wire Write Byte 1-Wire Single Function Write
Edges with active pull-up Write
tSLOT
Pull-up DS2482 Pull-down
Next Time Slot DS2482 Impedance Pull-up
DS2482-800: Eight-Channel 1-Wire Master 1-Wire Speed (1WS) determines timing 1-Wire communication generated DS2482. 1-Wire slave devices support standard speed (1WS where transfer single (tSLOT Figure completed within 65µs. Many 1-Wire device also communicate higher data rate, called Overdrive speed. change from standard Overdrive speed, 1-Wire device needs receive Overdrive Skip Overdrive Match command, explained device data sheets. change speed occurs immediately after 1-Wire device received speed-changing command code. DS2482 must take part this speed change stay synchronized. This accomplished writing Configuration Register with being immediately after 1-Wire Byte command that changes speed 1-Wire device. Writing Configuration Register with being followed 1-Wire Reset command changes DS2482 1-Wire devices active 1-Wire line back standard speed. Status Register read-only Status Register general means DS2482 report bit-type data from 1-Wire side, 1Wire busy status reset status host processor. 1-Wire communication commands Device Reset command position read pointer Status Register host processor read with minimal protocol overhead. Status information updated during execution certain commands only. Details given description various status bits below. Status Register Assignment
1-Wire Busy (1WB) reports host processor whether 1-Wire line busy. During 1-Wire communication once command completed, returns default Details when changes state long remains found Function Commands section. Presence Pulse Detect (PPD) updated with every 1-Wire Reset command. DS2482 detects presence pulse from 1-Wire device tMSP during Presence Detect cycle, will This will return default there presence pulse 1-Wire line shorted during subsequent 1-Wire Reset command. Short Detected (SD) updated with every 1-Wire Reset command. DS2482 detects logic 1-Wire line during Presence Detect cycle, will This will return default with subsequent 1Wire Reset command provided that short been removed. will DS2482 cannot distinguish between short DS1994 DS2404 signaling 1-Wire interrupt. this reason, DS2404/DS1994 used application, interrupt function must disabled. interrupt signaling explained respective device data sheets. Logic Level (LL) reports logic state active 1-Wire line without initiating 1-Wire communication. 1-Wire line sampled this purpose every time Status Register read. sampling updating takes place when host processor addressed DS2482 read mode (during acknowledge cycle), provided that Read Pointer positioned Status Register. Device Reset (RST) DS2482 performed internal reset cycle, either caused power-on reset from executing Device Reset command. cleared automatically when DS2482 executes Write Configuration command restore selection desired 1-Wire features.
DS2482-800: Eight-Channel 1-Wire Master Single Result (SBR) reports logic state active 1-Wire line sampled tMSR 1-Wire Single command first 1-Wire Triplet command. power-on default 1-Wire Single command sends 0-bit, should With 1-Wire Triplet command, could well depending response 1-Wire devices connected. same result applies 1-Wire Single command that sends 1-bit. Triplet Second (TSB) reports logic state active 1-Wire line sampled tMSR second 1-Wire Triplet command. power-on default This updated only with 1-Wire Triplet command function with other commands. Branch Direction Taken (DIR) Whenever 1-Write Triplet command executed, this reports host processor search direction that chosen triplet. power-on default This updated only with 1-Wire Triplet command function with other commands. additional information description 1Wire Triplet command Dallas Application Note 187, "1-Wire Search Algorithm".
FUNCTION COMMANDS
DS2482 understands function commands, which fall into four categories: device control, communication, 1-Wire setup 1-Wire communication. feedback path host controlled read pointer, which automatically each function command host efficiently access relevant information. host processor sends these commands applicable parameters strings bytes using interface. protocol requires that each byte acknowledged receiving party confirm acceptance acknowledged indicate error condition (invalid code parameter) communication. Details protocol including acknowledge found interface description this document.
Device Reset
Command Code Command Parameter Description Typical Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected None Performs global reset device state machine logic, which turn selects active 1-Wire channel. Terminates ongoing 1-Wire communication. Device initialization after power-up; re-initialization (reset) desired. None (can executed time) None Maximum 525ns, counted from falling edge command code acknowledge bit. Ends maximum 262.5ns after falling edge command code acknowledge bit. Status Register (for busy polling) 1WB, PPD, SBR, TSB, 1WS, APU,
DS2482-800: Eight-Channel 1-Wire Master
Read Pointer
Command Code Command Parameter Description Typical Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected Valid Pointer Codes Register Selection Status Register Read Data Register Channel Selection Register Configuration Register Code Pointer Code Sets read pointer specified register. Overwrites read pointer position 1-Wire communication command progress. prepare reading result from 1-Wire Byte command; random read access registers. None (can executed time) pointer code valid, pointer code will acknowledged command will ignored. None; read pointer updated rising edge pointer code acknowledge bit. Affected Specified Pointer Code None None
Write Configuration
Command Code Command Parameter Description Typical Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected Configuration Byte Writes configuration byte. settings take effect immediately. NOTE: When writing Configuration Register, data accepted only upper nibble (bits one's complement lower nibble (bits When read, upper nibble always Defining features subsequent 1-Wire communication. 1-Wire activity must have ended before DS2482 process this command. Command code parameter will acknowledged time command code received command will ignored. None; configuration register updated rising edge configuration byte acknowledge bit. None Configuration Register verify write) 1WS, SPU, updated
DS2482-800: Eight-Channel 1-Wire Master
Channel Select
Command Code Command Parameter Description Typical Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected Valid Channel Selection Codes Channel Selection Channel (default) Channel Channel Channel Channel Channel Channel Channel Code written) Code (read back) Selection Code Sets 1-Wire channel subsequent 1-Wire communication commands. NOTE: selection code read back different from code written. table below respective values. Selecting 1-Wire channel other that IO0; randomly selecting available 1-Wire channels. 1-Wire activity must have ended before DS2482 process this command. Command code parameter will acknowledged time command code received command will ignored. selection code valid, selection code will acknowledged command will ignored. None; channel selection register updated rising edge selection code acknowledge bit. None Channel Selection Register verify write) None None
Figure 1-Wire Reset/Presence Detect Cycle
RESET PULSE PRESENCE/SHORT DETECT PRESENCE PULSE
VIH1 VIL1
CONTROLLED EDGE
tMSP
tRSTL Pullup DS2482 Pulldown
tRSTH
RESISTIVE PULLUP
Slave Pulldown
DS2482-800: Eight-Channel 1-Wire Master
1-Wire Reset
Command Code Command Parameter Description Typical Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected None Generates 1-Wire Reset/Presence Detect cycle (Figure selected channel. state 1-Wire line sampled tMSP result reported host processor through status register, bits initiate 1-Wire communication sequence. 1-Wire activity must have ended before DS2482 process this command. Command code will acknowledged time command code received command will ignored. tRSTL tRSTH maximum 262.5ns, counted from falling edge command code acknowledge bit. Begins maximum 262.5ns after falling edge command code acknowledge bit. Status Register (for busy polling) (set tRSTL tRSTH), updated tRSTL tMSP, updated tRSTL 1WS, apply
1-Wire Single
Command Code Command Parameter Description Byte Generates single 1-Wire time slot with value specified byte selected 1-Wire channel. value will generate write-zero time slot (Figure value will generate write slot, which also functions read data time slot (Figure either case logic level 1-Wire line tested tMSR updated. perform single writes reads 1-Wire channel when single communication necessary (the exception). 1-Wire activity must have ended before DS2482 process this command. Command code byte will acknowledged time command code received command will ignored. tSLOT maximum 262.5ns, counted from falling edge first bit) byte. Begins maximum 262.5ns after falling edge byte. Status Register (for busy polling data reading) (set tSLOT) updated tMSR (may change state) 1WS, APU, apply
Typical Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected Allocation Byte don't care
DS2482-800: Eight-Channel 1-Wire Master
Figure Write-0 Time Slot
VIH1 VIL1 tREC0 tMSR tW0L
Pullup (see Fig.
tSLOT DS2482 Pulldown
Figure Write-1 Read-Data Time Slot
VIH1 VIL1 tSLOT Pullup (see Fig. DS2482 Pulldown Slave Pulldown tW1L tMSR
NOTE Figure Depending internal state, 1-Wire slave device will transmit data master (e.g., DS2482). When responding with 1-Wire slave will start pulling line during tW1L; internal timing generator determines when this pulldown ends voltage starts rising again. When responding with 1Wire slave will hold line all, voltage starts rising soon tW1L over. 1-Wire device data sheets term instead tW1L describe read-data time slot. Technically, tW1L have identical specifications cannot distinguished from each other.
1-Wire Write Byte
Command Code Command Parameter Description Typical Restriction Error Response Command Duration Data Byte Writes single data byte selected 1-Wire channel. write commands data 1-Wire channel; equivalent executing eight 1-Wire Single commands, faster less traffic. 1-Wire activity must have ended before DS2482 process this command. Command code data byte will acknowledged time command code received command will ignored. tSLOT maximum 262.5ns, counted from falling edge last bit) data byte. Begins maximum 262.5ns after falling edge data byte (i.e., before data byte acknowledge). NOTE: order 1-Wire line different. (1-Wire: LS-bit first; MS-bit first) Therefore, 1-Wire activity cannot begin before DS2482 received full data byte. Status Register (for busy polling) (set tSLOT) 1WS, SPU, apply
1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected
DS2482-800: Eight-Channel 1-Wire Master
1-Wire Read Byte
Command Code Command Parameter Description Typical Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected None Generates eight read data time slots selected 1-Wire channel stores result Read Data Register. read data from 1-Wire channel; equivalent executing eight 1Wire Single commands with (write time slot), faster less traffic. 1-Wire activity must have ended before DS2482 process this command. Command code will acknowledged time command code received command will ignored. tSLOT maximum 262.5ns, counted from falling edge command code acknowledge bit. Begins maximum 262.5ns after falling edge command code acknowledge bit. Status Register (for busy polling) NOTE: read data byte received from 1-Wire channel, issue Read Pointer command select Read Data Register. Then access DS2482 read mode. (set tSLOT) 1WS, apply
1-Wire Triplet
Command Code Command Parameter Direction Byte Generates three times slots, read-time slots one-write time slot, selected 1-Wire channel. type write-time slot depends result read-time slots direction byte. direction byte determines type write-time slot both read-time slots typical case). this case DS2482 will generate write-1 time slot write-0 time slot read-time slots there will follow write time slot. read-time slots there will follow write time slot. read-time slots both (error case), subsequent write time slot will write perform 1-Wire Search sequence; full sequence requires this command executed times identify address device. 1-Wire activity must have ended before DS2482 process this command. Command code direction byte will acknowledged time command code received command will ignored. tSLOT maximum 262.5ns, counted from falling edge first bit) direction byte. Begins maximum 262.5ns after falling edge direction byte. Status Register (for busy polling) (set tSLOT) updated first tMSR updated second tMSR (i.e., tSLOT tMSR) 1WS, apply
Description
Typical Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected
DS2482-800: Eight-Channel 1-Wire Master Allocation Direction Byte don't care
INTERFACE
General Characteristics uses data line (SDA) plus clock signal (SCL) communication. Both bidirectional lines, connected positive supply voltage through pullup resistor. When there communication, both lines HIGH. output stages devices connected must have open-drain open-collector perform wired-AND function. Data transferred rates 100kbps Standard-mode, 400kbps Fast-mode. DS2482 works both modes. device that sends data defined transmitter, device receiving data receiver. device that controls communication called "master." devices that controlled master "slaves." individually accessed, each device must have slave address that does conflict with other devices bus. Data transfers initiated only when busy. master generates serial clock (SCL), controls access, generates START STOP conditions, determines number data bytes transferred between START STOP (Figure Data transferred bytes with most significant being transmitted first. After each byte follows acknowledge allow synchronization between master slave.
Figure Protocol Overview
MS-bit Slave Address Acknowledgment from Receiver Repeated more bytes transferred
Idle START Condition
STOP Condition Repeated START Condition
Slave Address slave address which DS2482 responds shown Figure logic states address pins AD0, determine value address bits address pins allow device respond eight possible slave addresses. slave address part slave-address/control byte. last slave-address/control byte (R/W) defines data direction. When subsequent data will flow from master slave (write access); when data will flow from slave master (read access).
DS2482-800: Eight-Channel 1-Wire Master
Figure DS2482 Slave Address
7-Bit Slave Address
Most Significant
AD2, AD1, States
Determines Read Write
Definitions following terminology commonly used describe data transfers. timing references defined Figure Idle Busy: Both, SCL, inactive their logic HIGH states. START Condition: initiate communication with slave, master generate START condition. START condition defined change state from HIGH while remains HIGH. STOP Condition: communication with slave, master generate STOP condition. STOP condition defined change state from HIGH while remains HIGH. Repeated START Condition: Repeated starts commonly used read accesses select specific data source address read from. master repeated START condition data transfer immediately initiate data transfer following current one. repeated START condition generated same normal START condition, without leaving idle after STOP condition. Data Valid: With exception START STOP condition, transitions occur only during state SCL. data must remain valid unchanged during entire high pulse plus required setup hold time (tHD:DAT after falling edge tSU:DAT before rising edge SCL, Figure There clock pulse data. Data shifted into receiving device during rising edge SCL. When finished with writing, master must release line sufficient amount setup time (minimum tSU:DAT Figure before next rising edge start reading. slave shifts each data falling edge previous pulse data valid rising edge current pulse. master generates clock pulses, including those needed read from slave. Acknowledge: Usually, receiving device, when addressed, obliged generate acknowledge after receipt each byte. master must generate clock pulse that associated with this acknowledge bit. device that acknowledges must pull during acknowledge clock pulse such that stable during HIGH period acknowledge-related clock pulse plus required setup hold time (tHD:DAT after falling edge tSU:DAT before rising edge SCL). Acknowledged Slave: slave device unable receive transmit data, e.g., because busy performing some real-time function. this case slave device will acknowledge slave address leave line HIGH. slave device that ready communicate will acknowledge least slave address. However, some time later slave refuse accept data, e.g., because invalid command code parameter. this case slave device will acknowledge bytes that refuses will leave HIGH. either case, after slave failed acknowledge, master first needs generate repeated START condition STOP condition followed START condition begin data transfer.
DS2482-800: Eight-Channel 1-Wire Master Acknowledged Master: some time when receiving data, master must signal data slave device. achieve this, master does acknowledge last byte that received from slave. response, slave releases SDA, allowing master generate STOP condition.
Figure Timing Diagram
tBUF tLOW
tHD:STA
tHD:STA tHD:DAT STOP START tHIGH tSU:DAT Repeated START tSU:STA Spike Suppression tSU:STO
NOTE: Timing referenced VILMAX VIHMIN. Writing DS2482 write DS2482, master must access device write mode, i.e., slave address must sent with direction next byte sent command code, which, depending command, followed command parameter. DS2482 will acknowledge valid command codes expected/valid command parameters. Additional bytes invalid command parameters will never acknowledged. Reading from DS2482 read from DS2482, master must access device read mode, slave address must sent with direction read pointer determines register that master will read from. master continue reading same register over over again, without having re-address device, watch changing from read from different register, master must issue Read Pointer command then access DS2482 again read mode.
Communication-Legend
SYMBOL AD,0 AD,1 (Idle) <byte> DESCRIPTION START Condition Select DS2482 Write Access Select DS2482 Read Access Repeated START Condition STOP Condition Acknowledged Acknowledged Busy Transfer Byte SYMBOL DRST WCFG CHSL 1WRS 1WWB 1WRB 1WSB DESCRIPTION Command "Device Reset", Command "Write Configuration", Command "Channel Select", Command "Set Read Pointer", Command "1-Wire Reset", Command "1-Wire Write Byte", Command "1-Wire Read Byte", Command "1-Wire Single Bit", Command "1-Wire Triplet",
DS2482-800: Eight-Channel 1-Wire Master
Data Direction Codes
Master-to-Slave Slave-to-Master
Communication Examples
Device Reset, e.g., after power-up AD,0 DRST AD,1 <byte> This example includes optional read access verify success command. Write Configuration, e.g., before starting 1-Wire activity power-up Case 1-Wire idle (1WB AD,0 WCFG <byte> AD,1 <byte> This example includes optional read access verify success command. Case 1-Wire busy (1WB AD,0 WCFG
master should stop restart soon DS2482 does acknowledge command code.
Channel Select, e.g., select another 1-Wire channel Case 1-Wire idle (1WB AD,0 CHSL AD,1 <byte> valid channel selection code IO1. This example includes optional read access verify success command. Case 1-Wire idle (1WB invalid channel selection code AD,0 CHSL invalid channel selection code. Case 1-Wire busy (1WB AD,0 CHSL master should stop restart soon DS2482 does acknowledge command code. Read Pointer, e.g., read from another register Case valid read pointer code AD,0 valid read pointer code configuration register. Case invalid read pointer code AD,0 invalid read pointer code.
DS2482-800: Eight-Channel 1-Wire Master 1-Wire Reset, e.g., begin 1-Wire communication Case 1-Wire idle (1WB busy polling read result AD,0 1WRS (Idle) AD,1 <byte> first cycle, master sends command; then master waits (Idle) 1-Wire Reset complete. second cycle DS2482 accessed read result 1-Wire Reset from Status Register. Case 1-Wire idle (1WB busy polling until 1-Wire Command completed, then read result AD,0 1WRS AD,1 <byte> <byte>
Repeat until changed Case 1-Wire busy (1WB AD,0 1WRS master should stop restart soon DS2482 does acknowledge command code. 1-Wire Write Byte, e.g., send command code 1-Wire channel Case 1-Wire idle (1WB busy polling AD,0 1WWB (Idle) valid 1-Wire function command Read ROM. idle time needed 1-Wire function complete. There data read back from 1-Wire line with this command. Case 1-Wire idle (1WB busy polling until 1-Wire Command completed. AD,0 1WWB Repeat until changed
AD,1 <byte> <byte> When changed from 1-Wire Write Byte command completed.
Case 1-Wire busy (1WB AD,0 1WWB master should stop restart soon DS2482 does acknowledge command code. 1-Wire Read Byte, read byte from 1-Wire channel Case 1-Wire idle (1WB busy polling, read pointer after idle time. AD,0 1WRB (Idle) AD,0 AD,1 <byte>
idle time needed 1-Wire function complete. Then read pointer read data register (code E1h) access device again read data byte that obtained from 1-Wire channel. Case 1-Wire idle (1WB busy polling, read pointer before idle time. AD,0 1WRB AD,0 (Idle) AD,1 <byte>
read pointer read data register (code E1h) while 1-Wire Read Byte command still progress. Then, after 1-Wire function completed, device accessed read data byte that obtained from 1-Wire channel.
DS2482-800: Eight-Channel 1-Wire Master Case 1-Wire idle (1WB busy polling until 1-Wire Command completed. Repeat until AD,0 1WRB changed AD,1 <byte> <byte>
AD,0 AD,1 <byte> Poll Status Register until changed from Then read pointer read data register (code E1h) access device again read data byte that obtained from 1-Wire channel. Case 1-Wire busy (1WB AD,0 1WRB
master should stop restart soon DS2482 does acknowledge command code. 1-Wire Single Bit, generate single time slot 1-Wire channel Case 1-Wire idle (1WB busy polling AD,0 1WSB <byte> (Idle)
AD,1 <byte> idle time needed 1-Wire function complete. Then access device read mode result from 1-Wire single-bit command. Case 1-Wire idle (1WB busy polling until 1-Wire Command completed. AD,0 1WSB <byte> Repeat until changed
AD,1 <byte> <byte> When changed from Status Register holds valid result 1-Wire Single command. Case 1-Wire busy (1WB AD,0 1WSB master should stop restart soon DS2482 does acknowledge command code. 1-Wire Triplet, e.g., perform Search function 1-Wire channel Case 1-Wire idle (1WB busy polling AD,0 <byte> (Idle)
AD,1 <byte> idle time needed 1-Wire function complete. Then access device read mode result from 1-Wire Triplet command. Case 1-Wire idle (1WB busy polling until 1-Wire Command completed. Repeat until AD,0 <byte> changed AD,1 <byte> <byte> When changed from Status Register holds valid result 1-Wire Triplet command.
DS2482-800: Eight-Channel 1-Wire Master Case 1-Wire busy (1WB AD,0 master should stop restart soon DS2482 does acknowledge command code.
Figure Application Schematic
Application Information
Pullup Resistors open-drain output DS2482 that requires pullup resistor realize high logic levels. Because DS2482 uses only input clock stretching) master drive either through opendrain/collector output with pullup resistor push-pull output. Pullup Resistor Sizing According specification, slave device must able sink least 0.4V. This condition determines minimum value pullup resistor: Rpmin (VCC 0.4V)/3mA. With operating voltage 5.5V, minimum value pullup resistor 1.7k. "Minimum line Figure shows minimum pullup resistor changes with operating voltage. systems, rise time fall time measured from pullup voltage. maximum capacitance 400pF. maximum rise time standard speed must exceed 1000ns 300ns fast speed. Assuming maximum rise time, maximum resistor value given capacitance calculated Rpmaxs 1000ns/(CB*ln(7/3)) (standard speed) Rpmaxf 300ns/(CB*ln(7/3)) (fast speed). capacitance 400pF maximum pullup resistor values 2.95k standard speed fast speed. value between 1.7k 2.95k meets requirements standard speed. Since pullup resistor, would required meet rise time specification fast speed 400pF capacitance, lower than Rpmin 5.5V, different approach necessary. "Max. Load." line Figure generated first calculating minimum pullup resistor given operating voltage ("Minimum line) then calculating respective capacitance that yields rise time 300ns.
DS2482-800: Eight-Channel 1-Wire Master Only pullup voltages lower maximum permissible capacitance 400pF maintained. reduced capacitance 300pF acceptable pullup voltages lower. fast speed operation pullup voltage, capacitance must exceed 200pF. corresponding pullup resistor value voltage indicated "Minimum line.
Figure Fast Mode Pullup Resistor Selection Chart
"Minimum 2000 Minimum (Ohms) 1600 1200 Pull-up Voltage Max. Load Min. fast mode Load (pF)
PACKAGE INFORMATION
latest package outline information land patterns, www.maxim-ic.com/packages. Note that "+", "#", package code indicates RoHS status only. Package drawings show different suffix character, drawing pertains package regardless RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT (150 mil) S16+5 21-0041
DS2482-800: Eight-Channel 1-Wire Master
REVISION HISTORY
REVISION DATE 8/08 DESCRIPTION Removed 1-Wire line termination resistor references from Typical Operating Circuit Figure Conversion lead (Pb) free product. Removed presence pulse masking feature. Revised recommendation active pullup. PAGES CHANGED
11/09
Other recent searches
PT-10 - PT-10 PT-10 Datasheet
PT-20 - PT-20 PT-20 Datasheet
PD015F52 - PD015F52 PD015F52 Datasheet
MDT10P621 - MDT10P621 MDT10P621 Datasheet
LB1981V - LB1981V LB1981V Datasheet
ISP1181A - ISP1181A ISP1181A Datasheet
AVR1606 - AVR1606 AVR1606 Datasheet
1958600000 - 1958600000 1958600000 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
