Single-Channel 1-Wire Master with Sleep Mode DS2482-101 I2C-to-1-

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Single-Channel 1-Wire Master with Sleep Mode DS2482-101 I2C-to-1-

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19-4931; 11/09
Single-Channel 1-Wire Master with Sleep Mode
DS2482-101 I2C-to-1-Wire® bridge device that interfaces directly standard (100kHz max) fast (400kHz max) masters perform bidirectional protocol conversion between master downstream 1-Wire slave devices. Relative attached 1-Wire slave device, DS2482-101 1-Wire master. Internal, factory-trimmed timers relieve system host processor from generating time-critical 1-Wire waveforms, supporting both standard overdrive 1-Wire communication speeds. optimize 1-Wire waveform generation, DS2482-101 performs slew-rate control rising falling 1-Wire edges provides additional programmable features match drive characteristics 1-Wire slave environment. Programmable, strong pullup features support 1-Wire power delivery 1-Wire devices such EEPROMs sensors. DS2482-101 combines these features with output control external MOSFET enhanced strong pullup application. slave address assignment controlled binary address input, resolving potential conflicts with other slave devices system. When use, device sleep mode where power consumption minimal.
Features
Host Interface Supports 100kHz 400kHz Communication Speeds 1-Wire Master with Selectable Active Passive 1-Wire Pullup Provides Reset/Presence, 8-Bit, Single-Bit, 3-Bit 1-Wire Sequences Standard Overdrive 1-Wire Communication Speeds Slew-Controlled 1-Wire Edges Strong 1-Wire Pullup Provided Internal LowImpedance Signal Path PCTLZ Output Optionally Control External MOSFET Stronger Pullup Requirements Supports Power-Saving Sleep Mode Address Input Address Assignment Operating Range: 2.9V 5.5V, -40°C +85°C 8-Pin (150 mils) 9-Bump Packages
DS2482-101
Ordering Information
PART DS2482S-101+ DS2482S-101+T&R DS2482X-101+T TEMP RANGE -40°C +85°C -40°C +85°C -40°C +85°C PIN-PACKAGE (150 mils) (150 mils) (2.5k pieces)
Applications
Printers Medical Instruments Industrial Sensors Cell Phones, PDAs
Configurations appear data sheet.
+Denotes lead(Pb)-free/RoHS-compliant package. T/T&R Tape reel.
Typical Operating Circuit
(I2C PORT) CURRENT-LIMITING RESISTOR REFER APPLICATION NOTE 4206 PCTLZ OPTIONAL CIRCUITRY
DS2482-101
SLPZ 1-Wire LINE
1-Wire DEVICE
1-Wire DEVICE
1-Wire DEVICE
PULLUP RESISTOR (SEE APPLICATIONS INFORMATION SECTION SIZING).
1-Wire registered trademark Maxim Integrated Products, Inc.
Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim Direct 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
Single-Channel 1-Wire Master with Sleep Mode DS2482-101
ABSOLUTE MAXIMUM RATINGS
Voltage Range Relative Ground.-0.5V Maximum Current into Pin.±20mA Operating Temperature Range .-40°C +85°C Junction Temperature .+150°C Storage Temperature Range .-55°C +125°C Soldering Temperature.Refer IPC/JEDEC J-STD-020 Specification.
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC 2.9V 5.5V, -40°C +85°C.)
PARAMETER Supply Voltage Supply Current 1-Wire Input High (Notes 1-Wire Input (Notes 1-Wire Weak Pullup Resistor 1-Wire Output Active Pullup Time (Notes Strong Pullup Voltage Drop SYMBOL VIH1 VIL1 RWPU VOL1 tAPUOT VSTRPU CONDITIONS 3.3V (Note Sleep mode (SLPZ low), 5.5V 3.3V 3.3V (Note load Standard Overdrive 3.2V, 1.5mA load 5.2V, load Standard (3.3V ±10%) Overdrive (3.3V ±10%) Standard (5.0V ±10%) Overdrive (5.0V ±10%) Standard (3.3V ±10%) Overdrive (3.3V ±10%) Standard (5.0V ±10%) Overdrive (5.0V ±10%) 1675 22.1 72.8 11.0 0.59 0.44 UNITS
1000
Pulldown Slew Rate (Note
PDSRC
Pullup Slew Rate (Note
PUSRC
Power-On Reset Trip Point
VPOR Standard Overdrive Standard Overdrive Standard Overdrive Standard (3.3V Overdrive (3.3V Standard (5.0V Overdrive (5.0V 13.3 65.8 0.54 0.10 0.55 0.09 69.3 10.5
1-Wire TIMING (Note (See Figures Write-One/Read Time Read Sample Time 1-Wire Time Slot tW1L tMSR SLOT
Fall Time High-to-Low (Notes
Single-Channel 1-Wire Master with Sleep Mode
ELECTRICAL CHARACTERISTICS (continued)
(VCC 2.9V 5.5V, -40°C +85°C.)
PARAMETER Write-Zero Time Write-Zero Recovery Time Reset Time Presence-Detect Sample Time Sampling Short Interrupt Reset High Time CONTROL (PCTLZ) Output Voltage Output High Voltage SLEEP (SLPZ) 2.9V 3.7V Low-Level Input Voltage 4.5V 5.5V High-Level Input Voltage Input Leakage Current Wakeup Time from Sleep Mode Input voltage between VCC(MAX) VCC(MAX) -0.5 -0.5 0.25 0.22 0.5V 0.25 0.22 0.5V VOLP VOHP 2.9V, 1.2mA load current 0.4mA load current 0.5V SYMBOL tW0L tREC0 tRSTL tMSP tRSTH Standard Overdrive Standard Overdrive Standard Overdrive Standard Overdrive Standard Overdrive Standard Overdrive CONDITIONS 68.4 66.5 554.8 70.3 0.75 75.6 73.5 613.2 77.7 UNITS
DS2482-101
tSWUP (Notes PINS (SCL, SDA, AD0) (Note (See Figure 2.9V 3.7V Low-Level Input Voltage 4.5V 5.5V High-Level Input Voltage Hysteresis Schmitt Trigger Inputs Low-Level Output Voltage Sink Current Output Fall Time from VIH(MIN) VIL(MAX) with Capacitance from 10pF 400pF Pulse Width Spikes That Suppressed Input Filter VHYS -0.5 0.05 -0.5
pins only
Single-Channel 1-Wire Master with Sleep Mode DS2482-101
ELECTRICAL CHARACTERISTICS (continued)
(VCC 2.9V 5.5V, -40°C +85°C.)
PARAMETER Input Current Each Input/Output with Input Voltage Between VCC(MAX) VCC(MAX) Input Capacitance Clock Frequency Hold Time (Repeated) START Condition (After this period, first clock pulse generated.) Period Clock High Period Clock Setup Time Repeated START Condition Data Hold Time Data Setup Time Setup Time STOP Condition Free Time Between STOP START Condition Capacitive Load Each Line Oscillator Warmup Time SYMBOL CONDITIONS UNITS
(Notes
tHD:STA tLOW tHIGH SU:STA tHD:DAT SU:DAT SU:STO tBUF OSCWUP
(Note (Notes (Note (Note (Note
Note Note
Note Note Note
Note Note Note Note Note Note Note Note Note Note
Note
Operating current with 1-Wire write-byte sequence followed continuously reading Status Register 400kHz overdrive. With standard speed, total capacitive load 1-Wire should exceed 1nF. Otherwise, passive pullup threshold VIL1 reached available time. With overdrive speed, capacitive load 1-Wire must exceed 300pF. Active pullup guaranteed turn between VIL1(MAX) VIH1(MIN). Active resistive pullup choice configurable. Except tF1, 1-Wire timing specifications tAPUOT derived from same timing circuit. Therefore, these parameters found typical value, safe assume that these parameters deviate from their typical value same direction same degree. These values apply full load, i.e., standard speed 0.3nF overdrive speed. reduced load, pulldown slew rate slightly faster. Fall time high-to-low (tF1) derived from PDSRC, referenced from VCC. communication should take place tOSCWUP tSWUP time following power-on reset wakeup from sleep mode. Guaranteed design production tested. timing values referred VIH(MIN) VIL(MAX) levels. Applies SDA, SCL, AD0. input/output pins DS2482-101 obstruct lines switched off. DS2482-101 provides hold time least 300ns signal (referred VIH(MIN) signal) bridge undefined region falling edge SCL. maximum tHD:DAT need only device does stretch period (tLOW) signal. fast-mode device used standard-mode system, requirement tSU:DAT 250ns must then met. This automatically case device does stretch period signal. such device does stretch period signal, must output next data line tR(MAX) tSU:DAT 1000 1250ns (according standard-mode specification) before line released. CB-Total capacitance line mixed with high-speed-mode devices, faster fall times according I2CBus Specification Version allowed.
Single-Channel 1-Wire Master with Sleep Mode
Description
NAME PCTLZ SLPZ Power-Supply Input Input/Output Driver 1-Wire Line Ground Reference Serial Clock Input. Must connected through pullup resistor. Serial Data Input/Output. Must connected through pullup resistor. Active-Low Control Output External p-Channel MOSFET. Provides extra power 1-Wire line, e.g., with 1-Wire devices that require higher current temporarily operate. Active-Low Control Input Activate Low-Power Sleep Mode. This should driven push-pull port. Address Input. Must connected GND. FUNCTION
DS2482-101
CONFIGURATION REGISTER
T-TIME
INTERFACE CONTROLLER
INPUT/OUTPUT CONTROLLER
LINE XCVR
PCTLZ
SLPZ
STATUS REGISTER READ DATA REGISTER
DS2482-101
Figure Block Diagram
Detailed Description
DS2482-101 self-timed 1-Wire master that supports advanced 1-Wire waveform features including standard overdrive speeds, active pullup, strong pullup power delivery. active pullup affects rising edges 1-Wire side. strong pullup function uses same pullup transistor active pullup, with different control algorithm. addition, strong pullup activates PCTLZ pin, controlling optional external circuitry deliver additional power beyond capabilities on-chip pullup transistor. Once supplied with command data, input/output controller DS2482-101 performs
time-critical 1-Wire communication functions such reset/presence-detect cycle, read-byte, write-byte, single-bit R/W, triplet Search, without requiring interaction with host processor. host obtains feedback (completion 1-Wire function, presence pulse, 1-Wire short, search direction taken) through Status Register data through Read Data Register. DS2482-101 communicates with host processor through interface standard mode fast mode. logic state address determines slave address DS2482-101, allowing devices operating same segment without requiring hub. Figure block diagram.
Single-Channel 1-Wire Master with Sleep Mode DS2482-101
Device Registers
DS2482-101 three registers that host read: Configuration, Status, Read Data. These registers addressed read pointer. position read pointer, i.e., register that host reads subsequent read access, defined instruction DS2482-101 executed last. enable certain 1-Wire features, host read write access Configuration Register.
Active Pullup (APU) controls whether active pullup (controlled slew-rate transistor) passive pullup (RWPU resistor) used drive 1-Wire line from high. When active pullup disabled (resistor mode). Active pullup should always selected unless there only single slave 1-Wire line. active pullup does apply rising edge presence pulse recovery after short 1-Wire line.
circuit that controls rising edges (Figure operates follows: pulldown (from DS2482-101 1-Wire slave) ends. From this point 1-Wire pulled high through RWPU internal DS2482101. capacitive load 1-Wire line determine slope. case that active pullup disabled (APU resistive pullup continues, represented solid line. With active pullup enabled (APU when voltage reached level between VIL1(MAX) VIH1(MIN), DS2482-101 actively pulls 1-Wire line high, applying controlled slew rate represented dashed line. active pullup continues until tAPUOT expired From that time resistive pullup continues. Strong Pullup (SPU) section keep pullup transistor conducting beyond
Configuration Register
DS2482-101 supports three 1-Wire features that enabled selected through Configuration Register. These features are: Active Pullup (APU) Strong Pullup (SPU) 1-Wire Speed (1WS) These features selected combination. While maintain their state, returns inactive state soon strong pullup ended. After device reset (power-up cycle initiated Device Reset command), Configuration Register reads 00h. When writing Configuration Register, data accepted only upper nibble (bits one's complement lower nibble (bits When read, upper nibble always
Configuration Register Assignment
VIH1(MIN)
VIL1(MAX)
1-Wire DISCHARGED tAPUOT
Figure Rising Edge Pullup
Single-Channel 1-Wire Master with Sleep Mode
Strong Pullup (SPU) used activate strong pullup function prior 1-Wire Write Byte 1-Wire Single command. Strong pullup commonly used with 1-Wire EEPROM devices when copying scratchpad data main memory when performing SHA-1 computation with parasitically powered temperature sensors converters. respective device data sheets specify location communications protocol after which strong pullup should applied. must immediately prior issuing command that puts 1-Wire device into state where needs extra power. strong pullup uses same internal pullup transistor active pullup feature. cases where internal strong pullup insufficient strength, PCTLZ used control external p-channel MOSFET supply additional power beyond drive capability DS2482-101 1-Wire line. STRPU parameter Electrical Characteristics determine internal strong pullup sufficient given current load device. DS2482-101 treats rising edge time slot which strong pullup starts active pullup activated. However, contrast active pullup, strong pullup, i.e., internal pullup transistor, remains conducting, shown Figure until three events occurs: DS2482-101 receives command that generates 1-Wire communication (the
typical case); Configuration Register written DS2482-101 receives Device Reset command. long strong pullup active, PCTLZ output low. When strong pullup ends, automatically reset Using strong pullup feature does change state Configuration Register.
DS2482-101
1-Wire Speed (1WS) determines timing 1-Wire communication generated DS2482-101. 1-Wire slave devices support standard speed (1WS where transfer single (tSLOT Figure completed within 65µs. Many 1-Wire devices also communicate higher data rate, called overdrive speed. change from standard overdrive speed, 1-Wire device needs receive Overdrive-Skip Overdrive-Match command, explained 1-Wire device data sheets. change speed occurs immediately after 1-Wire device received speed-changing command code. DS2482-101 must take part this speed change stay synchronized. This accomplished writing Configuration Register with immediately after 1-Wire Byte command that changes speed 1-Wire device. Writing Configuration Register with followed 1-Wire Reset command, changes DS2482-101 1-Wire devices active 1-Wire line back standard speed.
LAST 1-Wire WRITE BYTE 1-Wire SINGLE FUNCTION WRITE-ONE CASE NEXT TIME SLOT 1-Wire RESET
WRITE-ZERO CASE tSLOT
PCTLZ
DS2482-101 RESISTIVE PULLUP
DS2482-101 PULLDOWN
DS2482-101 STRONG PULLUP
Figure Low-Impedance Pullup Timing
Single-Channel 1-Wire Master with Sleep Mode DS2482-101
Status Register Assignment
Status Register
read-only Status Register general means DS2482-101 report bit-type data from 1-Wire side, 1-Wire busy status, reset status host processor. 1-Wire communication commands Device Reset command position read pointer Status Register host processor read with minimal protocol overhead. Status information updated during execution certain commands only. Details given description various status bits that follow.
Logic Level (LL) reports logic state active 1-Wire line without initiating 1-Wire communication. 1-Wire line sampled this purpose every time Status Register read. sampling updating takes place when host processor addressed DS2482-101 read mode (during acknowledge cycle), provided that read pointer positioned Status Register. Device Reset (RST) DS2482-101 performed internal reset cycle, either caused power-on reset from executing Device Reset command. cleared automatically when DS2482-101 executes Write Configuration command restore selection desired 1-Wire features. Single Result (SBR) reports logic state active 1-Wire line sampled tMSR 1-Wire Single command first 1-Wire Triplet command. power-on default 1-Wire Single command sends bit, should With 1-Wire Triplet command, could well depending response 1-Wire devices connected. same result applies 1-Wire Single command that sends bit. Triplet Second (TSB) reports logic state active 1-Wire line sampled second 1-Wire Triplet command. power-on default This updated only with 1-Wire Triplet command function with other commands. Branch Direction Taken (DIR) Whenever 1-Wire Triplet command executed, this reports host processor search direction that chosen third triplet. power-on default This updated only with 1-Wire Triplet command function with other commands. additional information, description 1-Wire Triplet command Application Note 187: 1-Wire Search Algorithm.
1-Wire Busy (1WB) reports host processor whether 1-Wire line busy. During 1-Wire communication once command completed, returns default Details when changes state long remains found Function Commands section. Presence-Pulse Detect (PPD) updated with every 1-Wire Reset command. DS2482-101 detects presence pulse from 1-Wire device tMSP during presence-detect cycle, This returns default there presence pulse 1-Wire line shorted during subsequent 1-Wire Reset command. Short Detected (SD) updated with every 1-Wire Reset command. DS2482-101 detects logic 1-Wire line during presence-detect cycle, This returns default with subsequent 1-Wire Reset command provided that short been removed. DS2482-101 cannot distinguish between short DS1994 DS2404 signaling 1-Wire interrupt. this reason, DS2404 DS1994 used application, interrupt function must disabled. interrupt signaling explained respective 1-Wire device data sheets.
Single-Channel 1-Wire Master with Sleep Mode
Function Commands
DS2482-101 understands eight function commands that fall into four categories: device control, communication, 1-Wire setup, 1-Wire communication. feedback path host controlled read pointer, which automatically each function command host efficiently access relevant information. host processor sends these commands applicable parameters strings bytes using interface. protocol requires that each byte acknowledged receiving party confirm acceptance acknowledged indicate error condition (invalid code parameter) communication. Interface section details protocol including acknowledge. function commands follows: Device Reset Read Pointer Write Configuration 1-Wire Reset 1-Wire Single 1-Wire Write Byte 1-Wire Read Byte 1-Wire Triplet
DS2482-101
Table Valid Pointer Codes
REGISTER SELECTION Status Register Read Data Register Configuration Register CODE
Device Reset
Command Code Command Parameter Description Typical Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected None Performs global reset device state machine logic. Terminates ongoing 1-Wire communication. Device initialization after power-up; reinitialization (reset) desired. None (can executed time). None Maximum 525ns. Counted from falling edge command code acknowledge bit. Ends maximum 262.5ns after falling edge command code acknowledge bit. Status Register (for busy polling). 1WB, PPD, SBR, TSB, 1WS, APU,
Read Pointer
Command Code Command Parameter Description Typical Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected Pointer Code (see Table Sets read pointer specified register. Overwrites read pointer position 1-Wire communication command progress. prepare reading result from 1-Wire Read Byte command; random read access registers. None (can executed time). pointer code valid, pointer code acknowledged command ignored. None. read pointer updated rising edge pointer code acknowledge bit. affected. specified pointer code. None None
Single-Channel 1-Wire Master with Sleep Mode DS2482-101
Write Configuration
Command Code Command Parameter Description Typical Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected Configuration Byte Writes configuration byte. settings take effect immediately. Note: When writing Configuration Register, data accepted only upper nibble (bits one's complement lower nibble (bits When read, upper nibble always Defining features subsequent 1-Wire communication. 1-Wire activity must have ended before DS2482-101 process this command. Command code parameter acknowledged time command code received command ignored. None. Configuration Register updated rising edge configuration-byte acknowledge bit. None Configuration Register verify write). 1WS, SPU, updated.
1-Wire Reset
Command Code Command Parameter Description Typical Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected None Generates 1-Wire reset/presence-detect cycle (Figure 1-Wire line. state 1-Wire line sampled tMSP result reported host processor through Status Register, bits initiate 1-Wire communication sequence. 1-Wire activity must have ended before DS2482-101 process this command. Command code acknowledged time command code received command ignored. tRSTL tRSTH maximum 262.5ns, counted from falling edge command code acknowledge bit. Begins maximum 262.5ns after falling edge command code acknowledge bit. Status Register (for busy polling). (set tRSTL tRSTH), updated tRSTL tMSP, updated tRSTL apply.
Single-Channel 1-Wire Master with Sleep Mode
1-Wire Single
Command Code Command Parameter Byte Generates single 1-Wire time slot with value specified byte 1-Wire line (see Table value generates write-zero time slot (Figure value generates write-one time slot, which also functions read-data time slot (Figure either case, logic level 1-Wire line tested tMSR updated. perform single-bit writes reads 1-Wire line when single communication necessary (the exception). 1-Wire activity must have ended before DS2482-101 process this command. Command code byte acknowledged time command code received command ignored. SLOT maximum 262.5ns, counted from falling edge first (MSB) byte. Begins maximum 262.5ns after falling edge byte. Status Register (for busy polling data reading). (set SLOT), updated tMSR (may change state). 1WS, APU, apply.
DS2482-101
Description
Typical Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected
Table Allocation Byte
Don't care.
RESET PULSE VIH1 VIL1 tRSTL CONTROLLED EDGE
PRESENCE/SHORT DETECT tMSP PRESENCE PULSE
RESISTIVE PULLUP
tRSTH
PULLUP
DS2482-101 PULLDOWN
1-Wire SLAVE PULLDOWN
Figure 1-Wire Reset/Presence-Detect Cycle
Single-Channel 1-Wire Master with Sleep Mode DS2482-101
tWOL VIH1 VIL1 tSLOT tREC0 tMSR
PULLUP (SEE FIGURE
DS2482-101 PULLDOWN
Figure Write-Zero Time Slot
tMSR VIH1 VIL1 tSLOT tW1L
PULLUP (SEE FIGURE
DS2482-101 PULLDOWN
1-Wire SLAVE PULLDOWN
NOTE: DEPENDING INTERNAL STATE, 1-Wire SLAVE DEVICE TRANSMITS DATA MASTER (e.g., DS2482-101). WHEN RESPONDING WITH 1-Wire SLAVE STARTS PULLING LINE DURING tW1L. INTERNAL TIMING GENERATOR DETERMINES WHEN THIS PULLDOWN ENDS VOLTAGE STARTS RISING AGAIN. WHEN RESPONDING WITH 1-Wire SLAVE DOES HOLD LINE ALL, VOLTAGE STARTS RISING SOON tW1L OVER. 1-Wire DEVICE DATA SHEETS TERM INSTEAD tW1L DESCRIBE READ-DATA TIME SLOT. TECHNICALLY, tW1L HAVE IDENTICAL SPECIFICATIONS CANNOT DISTINGUISHED FROM EACH OTHER.
Figure Write-One Read-Data Time Slot
Single-Channel 1-Wire Master with Sleep Mode
1-Wire Write Byte
Command Code Command Parameter Description Typical Restriction Error Response Command Duration Data Byte Writes single data byte 1-Wire line. write commands data 1-Wire line. Equivalent executing eight 1-Wire Single commands, faster less traffic. 1-Wire activity must have ended before DS2482-101 process this command. Command code data byte acknowledged time command code received command ignored. SLOT maximum 262.5ns, counted from falling edge last bit) data byte. Begins maximum 262.5ns after falling edge data byte (i.e., before data byte acknowledge). Note: order 1-Wire line different (1-Wire: first; I2C: first). Therefore, 1-Wire activity cannot begin before DS2482-101 received full data byte. Status Register (for busy polling). (set SLOT). 1WS, SPU, apply.
DS2482-101
1-Wire Activity
Read Pointer Position Status Bits Affected Configuration Bits Affected
1-Wire Read Byte
Command Code Command Parameter Description Typical Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected None Generates eight read-data time slots 1-Wire line stores result Read Data Register. read data from 1-Wire line. Equivalent executing eight 1-Wire Single commands with (write-one time slot), faster less traffic. 1-Wire activity must have ended before DS2482-101 process this command. Command code acknowledged time command code received command ignored. SLOT maximum 262.5ns, counted from falling edge command code acknowledge bit. Begins maximum 262.5ns after falling edge command code acknowledge bit. Status Register (for busy polling). Note: read data byte received from 1-Wire line, issue Read Pointer command select Read Data Register. Then access DS2482-101 read mode. (set SLOT). 1WS, apply.
Single-Channel 1-Wire Master with Sleep Mode DS2482-101
1-Wire Triplet
Command Code Command Parameter Direction Byte Generates three time slots: read time slots write time slot 1-Wire line. type write time slot depends result read time slots direction byte. direction byte determines type write time slot both read time slots typical case). this case, DS2482-101 generates write-one time slot write-zero time slot Table read time slots they followed write-zero time slot. read time slots they followed write-one time slot. read time slots both (error case), subsequent write time slot write-one. perform 1-Wire Search sequence; full sequence requires this command executed times identify address device. 1-Wire activity must have ended before DS2482-101 process this command. Command code direction byte acknowledged time command code received command ignored. SLOT maximum 262.5ns, counted from falling edge first (MSB) direction byte. Begins maximum 262.5ns after falling edge direction byte. Status Register (for busy polling). (set SLOT), updated first tMSR, updated second tMSR (i.e., SLOT tMSR). 1WS, apply.
Description
Typical Restriction Error Response Command Duration 1-Wire Activity Read Pointer Position Status Bits Affected Configuration Bits Affected
Table Allocation Direction Byte
Don't care.
Single-Channel 1-Wire Master with Sleep Mode DS2482-101
FIRST
SLAVE ADDRESS
DATA
DATA
ACK/ NACK
IDLE
START CONDITION
REPEATED MORE BYTES TRANSFERRED
STOP CONDITION REPEATED START
Figure Protocol Overview
Interface
General Characteristics
uses data line (SDA) plus clock signal (SCL) communication. Both bidirectional lines, connected positive supply voltage through pullup resistor. When there communication, both lines high. output stages devices connected must have open drain open collector perform wired-AND function. Data transferred rates 100kbps standard mode 400kbps fast mode. DS2482-101 works both modes. device that sends data defined transmitter, device receiving data defined receiver. device that controls communication called master. devices that controlled master slaves. individually accessed, each device must have slave address that does conflict with other devices bus. Data transfers initiated only when busy. master generates serial clock (SCL), controls access, generates START STOP conditions, determines number data bytes transferred between START STOP (Figure Data transferred bytes with most significant being
transmitted first. After each byte follows acknowledge allow synchronization between master slave.
Slave Address
slave address which DS2482-101 responds shown Figure logic state address determines value address address allows device respond possible slave addresses. slave address part slave address/control byte. last slave address/control byte (R/W) defines data direction. When subsequent data flows from master slave (write access); when data flows from slave master (read access).
7-BIT SLAVE ADDRESS
STATE
DETERMINES READ WRITE
Figure DS2482-101 Slave Address
Single-Channel 1-Wire Master with Sleep Mode DS2482-101
tBUF tLOW tHD:STA
tHIGH tHD:STA tHD:DAT STOP START tSU:DAT REPEATED START
tSU:STA
SPIKE SUPPRESSION
tSU:STO
NOTE: TIMING REFERENCED VIL(MAX) VIH(MIN).
Figure Timing Diagram
Definitions
following terminology commonly used describe data transfers. timing references defined Figure Idle Busy: Both inactive their logic-high states. START Condition: initiate communication with slave, master must generate START condition. START condition defined change state from high while remains high. STOP Condition: communication with slave, master must generate STOP condition. STOP condition defined change state from high while remains high. Repeated START Condition: Repeated STARTs commonly used read accesses select specific data source address read from. master repeated START condition data transfer immediately initiate data transfer following current one. repeated START condition generated same normal START condition, without leaving idle after STOP condition. Data Valid: With exception START STOP condition, transitions occur only during state SCL. data must remain valid unchanged during entire high pulse plus required setup hold time (tHD:DAT after falling edge tSU:DAT
before rising edge SCL; Figure There clock pulse data. Data shifted into receiving device during rising edge SCL. When finished with writing, master must release line sufficient amount setup time (minimum tSU:DAT Figure before next rising edge start reading. slave shifts each data falling edge previous pulse data valid rising edge current pulse. master generates clock pulses, including those needed read from slave. Acknowledge: Typically receiving device, when addressed, obliged generate acknowledge after receipt each byte. master must generate clock pulse that associated with this acknowledge bit. device that acknowledges must pull during acknowledge clock pulse such that stable during high period acknowledge-related clock pulse plus required setup hold time (tHD:DAT after falling edge tSU:DAT before rising edge SCL). Acknowledged Slave: slave device unable receive transmit data, example, because busy performing some real-time function sleep mode. this case, slave device does acknowledge slave address leaves line high. slave device that ready communicate acknowledges least
Single-Channel 1-Wire Master with Sleep Mode
slave address. However, some time later slave refuse accept data, possibly because invalid command code parameter. this case, slave device does acknowledge bytes that refuses leaves high. either case, after slave failed acknowledge, master first should generate repeated START condition STOP condition followed START condition begin data transfer. Acknowledged Master: some time when receiving data, master must signal data slave device. achieve this, master does acknowledge last byte that received from slave. response, slave releases SDA, allowing master generate STOP condition.
Communication Examples
Tables communication legend data direction codes.
DS2482-101
Table Communication-Legend
SYMBOL (Idle) <byte> DRST WCFG 1WRS 1WSB 1WWB 1WRB DESCRIPTION START Condition Select DS2482-101 Write Access Select DS2482-101 Read Access Repeated START Condition STOP Condition Acknowledged Acknowledged Busy Transfer Byte Command "Device Reset", Command "Set Read Pointer", Command "Write Configuration", Command "1-Wire Reset", Command "1-Wire Single Bit", Command "1-Wire Write Byte", Command "1-Wire Read Byte", Command "1-Wire Triplet",
Writing DS2482-101
write DS2482-101, master must access device write mode, i.e., slave address must sent with direction next byte sent command code, which, depending command, followed command parameter. DS2482-101 acknowledges valid command codes expected/valid command parameters. Additional bytes invalid command parameters never acknowledged.
Reading from DS2482-101
read from DS2482-101, master must access device read mode, i.e., slave address must sent with direction read pointer determines register that master reads from. master continue reading same register over over again, without having readdress device, e.g., watch changing from read from different register, master must issue Read Pointer command then access DS2482101 again read mode.
Table Data Direction Codes
Master-to-Slave Slave-to-Master
Single-Channel 1-Wire Master with Sleep Mode DS2482-101
Communication Examples (continued)
Device Reset (After Power-Up)
AD,0 DRST AD,1 <byte>
Activities that underlined denote optional read access verify success command. Read Pointer Read from Another Register) Case Valid Read Pointer Code
AD,0
valid read pointer code Configuration Register. Case Invalid Read Pointer Code
AD,0
invalid read pointer code. Write Configuration (Before Starting 1-Wire Activity) Case 1-Wire Idle (1WB
AD,0 WCFG <byte> AD,1 <byte>
Activities that underlined denote optional read access verify success command. Case 1-Wire Busy (1WB
AD,0 WCFG
master should stop restart soon DS2482-101 does acknowledge command code. 1-Wire Reset Begin 1-Wire Communication) Case 1-Wire Idle (1WB Busy Polling Read Result
AD,0 1WRS (Idle) AD,1 <byte>
first cycle, master sends command. Then master waits (Idle) 1-Wire reset complete. second cycle, DS2482-101 accessed read result 1-Wire reset from Status Register. Case 1-Wire Idle (1WB Busy Polling Until 1-Wire Command Completed, then Read Result
AD,0 1WRS AD,1 <byte> <byte>
REPEAT UNTIL CHANGED
Case 1-Wire Busy (1WB
AD,0 1WRS
master should stop restart soon DS2482-101 does acknowledge command code.
Single-Channel 1-Wire Master with Sleep Mode
Communication Examples (continued)
1-Wire Single Generate Single Time Slot 1-Wire Line) Case 1-Wire Idle (1WB Busy Polling
AD,0 1WSB <byte> (Idle)
DS2482-101
AD,1
<byte>
idle time needed 1-Wire function complete. Then access device read mode result from 1-Wire Single command. Case 1-Wire Idle (1WB Busy Polling Until 1-Wire Command Completed
AD,0 1WSB <byte> REPEAT UNTIL CHANGED AD,1 <byte> <byte>
When changed from Status Register holds valid result 1-Wire Single command. Case 1-Wire Busy (1WB
AD,0 1WSB
master should stop restart soon DS2482-101 does acknowledge command code. 1-Wire Write Byte Send Command Code 1-Wire Line) Case 1-Wire Idle (1WB Busy Polling
AD,0 1WWB (Idle)
valid 1-Wire function command Read ROM. idle time needed 1-Wire function complete. There data read back from 1-Wire line with this command. Case 1-Wire Idle (1WB Busy Polling Until 1-Wire Command Completed.
AD,0 1WWB REPEAT UNTIL CHANGED AD,1 <byte> <byte>
When changed from 1-Wire Write Byte command completed. Case 1-Wire Busy (1WB
AD,0 1WWB
master should stop restart soon DS2482-101 does acknowledge command code.
Single-Channel 1-Wire Master with Sleep Mode DS2482-101
Communication Examples (continued)
1-Wire Read Byte Read Byte from 1-Wire Line) Case 1-Wire Idle (1WB Busy Polling, Read Pointer After Idle Time
AD,0 1WRB (Idle)
AD,0
AD,1
<byte>
idle time needed 1-Wire function complete. Then read pointer Read Data Register (code E1h) access device again read data byte that obtained from 1-Wire line. Case 1-Wire Idle (1WB Busy Polling, Read Pointer Before Idle Time
AD,0 1WRB AD,0
(Idle)
AD,1
<byte>
read pointer Read Data Register (code E1h) while 1-Wire Read Byte command still progress. Then, after 1-Wire function completed, device accessed read data byte that obtained from 1-Wire line. Case 1-Wire Idle (1WB Busy Polling Until 1-Wire Command Completed
AD,0 1WRB REPEAT UNTIL CHANGED AD,1 <byte> <byte>
AD,0
AD,1
<byte>
Poll Status Register until changed from Then read pointer Read Data Register (code E1h) access device again read data byte that obtained from 1-Wire line. Case 1-Wire Busy (1WB
AD,0 1WRB
master should stop restart soon DS2482-101 does acknowledge command code. 1-Wire Triplet Perform Search Function 1-Wire Line) Case 1-Wire Idle (1WB Busy Polling
AD,0 <byte> (Idle)
AD,1
<byte>
idle time needed 1-Wire function complete. Then access device read mode result from 1-Wire Triplet command.
Single-Channel 1-Wire Master with Sleep Mode
Communication Examples (continued)
1-Wire Triplet Perform Search Function 1-Wire Line) (continued) Case 1-Wire Idle (1WB Busy Polling Until 1-Wire Command Completed
AD,0 <byte> REPEAT UNTIL CHANGED AD,1 <byte> <byte>
DS2482-101
When changed from Status Register holds valid result 1-Wire Triplet command. Case 1-Wire Busy (1WB
AD,0
master should stop restart soon DS2482-101 does acknowledge command code.
(I2C PORT) CURRENT-LIMITING RESISTOR REFER APPLICATION NOTE 4206 PCTLZ
DS2482-101
SLPZ 1-Wire LINE
1-Wire DEVICE (WITH SPECIAL POWER REQUIREMENTS)
PCTLZ
DS2482-101
SLPZ 1-Wire LINE 1-Wire DEVICE
PULLUP RESISTOR (SEE APPLICATIONS INFORMATION SECTION SIZING).
Figure Application Schematic
Single-Channel 1-Wire Master with Sleep Mode DS2482-101
Applications Information
Pullup Resistors
open-drain output DS2482-101 that requires pullup resistor realize high-logic levels. Because DS2482-101 uses only input clock stretching), master drive either through open-drain/-collector output with pullup resistor push-pull output. maximum resistor value given capacitance calculated RPMAXS 1000ns/[CB ln(7/3)] (standard speed) RPMAXF 300ns/[CB ln(7/3)] (fast speed) capacitance 400pF, maximum pullup resistor values 2.95k standard speed fast speed. value between 1.7k 2.95k meets requirements standard speed. Because pullup resistor, would required meet rise time specification fast speed 400pF capacitance, lower than RP(MIN) 5.5V, different approach necessary. "MAX LOAD FAST MODE" line Figure generated first calculating minimum pullup resistor given operating voltage ("MINIMUM line) then calculating respective capacitance that yields 300ns rise time. Only pullup voltages lower maximum permissible capacitance 400pF maintained. reduced capacitance 300pF acceptable pullup voltages lower. fast speed operation pullup voltage, capacitance must exceed 200pF. corresponding pullup resistor value voltage indicated "MINIMUM line.
Pullup Resistor Sizing According specification, slave device must able sink least 0.4V. This condition determines minimum value pullup resistor RP(MIN) (VCC 0.4V)/3mA
With operating voltage 5.5V, minimum value pullup resistor 1.7k. "MINIMUM line Figure shows minimum pullup resistor changes with operating voltage. systems, rise time fall time measured from pullup voltage. maximum capacitance, 400pF. maximum rise time must exceed 1000ns standard speed 300ns fast speed. Assuming maximum rise time,
2000 1600 MINIMUM 1200 MINIMUM LOAD FAST MODE PULLUP VOLTAGE
LOAD (pF)
Figure Fast Mode Pullup Resistor Selection Chart
Single-Channel 1-Wire Master with Sleep Mode
Configurations
VIEW (BUMP SIDE DOWN) DS2482-101 VIEW
PCTLZ SLPZ SLPZ PCTLZ
DS2482-101
MARK
DS2482-101
DS2482-101
(150 mils)
Package Information
latest package outline information land patterns, www.maxim-ic.com/packages. PACKAGE TYPE (150 mils) PACKAGE CODE S8+4 W92A1+1 DOCUMENT 21-0041 21-0067
Single-Channel 1-Wire Master with Sleep Mode DS2482-101
Revision History
REVISION NUMBER REVISION DATE 7/08 8/08 11/09 Initial release. Removed 1-Wire line termination resistor references from Typical Operating Circuit Figure DESCRIPTION PAGES CHANGED 2-5, 11-14,
Corrected recommendation using active pullup (APU). Removed references presence-pulse masking.
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2009 Maxim Integrated Products Maxim registered trademark Maxim Integrated Products, Inc.

Single-Channel 1-Wire Master with Sleep Mode DS2482-101 I2C-to-1-

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