DS1996 64Kb Memory iButton 65536 bits read/write nonvolatile memo

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DS1996 64Kb Memory iButton 65536 bits read/write nonvolatile memo

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19-4896; 8/09
DS1996 64Kb Memory iButton
65536 bits read/write nonvolatile memory Overdrive mode boosts communication speed kbits second 256-bit scratchpad ensures integrity data transfer Memory partitioned into 256-bit pages packetizing data Data integrity assured with strict read/write protocols Operating temperature range from -40°C +70°C Over years data retention
MICROCAN
5.89 0.51
16.25
000000FBC52B
1-Wire
17.35
DATA
GROUND
dimensions shown millimeters Durable stainless steel case engraved with registration number withstands harsh environments Easily affixed with self-stick adhesive backing, latched flange, locked with ring pressed onto Presence detector acknowledges when reader first applies voltage
COMMON iButton FEATURES
Unique, factory-lasered tested 64-bit registration number (8-bit family code 48-bit serial number 8-bit tester) assures absolute traceability because parts alike Multidrop controller MicroLAN Digital identification information momentary contact Chip-based data carrier compactly stores information Data accessed while affixed object Economically communicates master with single digital signal 16.3 kbits second Standard diameter 1-Wire® protocol ensure compatibility with iButton family Button shape self-aligning with cupshaped probes
ORDERING INFORMATION
PINPACKAGE DS1996L-F5+ MicroCan -40C +70C +Denotes lead(Pb)-free/RoHS-compliant package. PART TEMP RANGE
EXAMPLES ACCESSORIES
DS9096P DS9101 DS9093RA DS9093F DS9092 Self-Stick Adhesive Multi-Purpose Clip Mounting Lock Ring Snap-In iButton Probe
iButton 1-Wire registered trademarks Maxim Integrated Products, Inc.
DS1996
iButton DESCRIPTION
DS1996 Memory iButton rugged read/write data carrier that acts localized database that easily accessed with minimal hardware. nonvolatile memory offers simple solution storing retrieving vital information pertaining object which iButton attached. Data transferred serially 1-Wire protocol which requires only single data lead ground return. scratchpad additional page that acts buffer when writing memory. Data first written scratchpad where read back. After data been verified, copy scratchpad command will transfer data memory. This process ensures data integrity when modifying memory. 48-bit serial number factory lasered into each DS1996 provide guaranteed unique identity which allows absolute traceability. durable MicroCan package highly resistant environmental hazards such dirt, moisture, shock. compact button-shaped profile self-aligning with mating receptacles, allowing DS1996 easily used human operators. Accessories permit DS1996 mounted almost surface including plastic fobs, photo-ID badges printed circuit boards. Applications include access control, work-in-progress tracking, electronic travelers, storage calibration constants, debit tokens.
OVERVIEW
block diagram Figure shows relationships between major control memory sections DS1996. DS1996 three main data components: 64-bit lasered ROM, 256-bit scratchpad 65536-bit SRAM. hierarchial structure 1-Wire protocol shown Figure master must first provide Function Commands, 1)Read ROM, Match ROM, Search ROM, Skip ROM, Overdrive-Skip Overdrive-Match ROM. Upon completion overdrive command byte executed regular speed, device will enter Overdrive mode where subsequent communication occurs higher speed. protocol required these Function Commands described Figure After Function Command successfully executed, memory functions become accessible master provide four memory function commands. protocol these memory function commands described Figure data read written least significant first.
PARASITE POWER
block diagram (Figure shows parasite-powered circuitry. This circuitry "steals" power whenever data line high. data line will provide sufficient power long specified timing voltage requirements met. advantages parasite power two-fold: parasiting this input, battery power consumed 1-Wire function commands, battery exhausted reason, still read normally. remaining circuitry DS1996 solely operated battery energy.
64-BIT LASERED
Each DS1996 contains unique code that bits long. first bits 1-Wire family code. next bits unique serial number. last bits first bits. (Figure 1-Wire generated using polynomial generator consisting shift register gates shown Figure polynomial Additional information about Dallas 1Wire Cyclic Redundancy Check available Book DS19xx iButton Standards. shift register bits initialized zero. Then starting with least significant family code, time shifted After family code been entered, then serial number entered. After 48th serial number been entered, shift register contains value. Shifting bits should return shift register zeros.
DS1996
DS1996 BLOCK DIAGRAM Figure
DS1996
HIERARCHICAL STRUCTURE 1-WIRE PROTOCOL Figure
MASTER
1-WIRE
OTHER DEVICES
1996
COMMAND LEVEL: AVAILABLE COMMANDS: READ MATCH SEARCH SKIP OVERDRIVE SKIP OVERDRIVE MATCH DATA FIELDS AFFECTED: 64-BIT 64-BIT 64-BIT 64-BIT
1-WIRE FUNCTION COMMANDS (SEE FIGURE
1996- SPECIFIC MEMORY FUNCTION COMMANDS (SEE FIGURE
WRITE SCRATCHPAD READ SCRATCHPAD COPY SCRATCHPAD READ MEMORY
256-BIT SCRATCHPAD 256-BIT SCRATCHPAD 64K-BIT MEMORY 64K-BIT MEMORY
64-BIT LASERED Figure
8-Bit Code
48-Bit Serial Number
8-Bit Family Code (0CH)
1-WIRE GENERATOR Figure
DS1996
MEMORY
memory Figure shows 32-byte page called scratchpad additional 32-byte pages called memory. DS1996 contains pages which comprise 65536-bit SRAM. scratchpad additional page that acts buffer when writing memory.
ADDRESS REGISTERS TRANSFER STATUS
Because serial data transfer, DS1996 employs three address registers, called TA1, (Figure Registers must loaded with target address which data will written from which data will sent master upon Read command. Register acts like byte counter Transfer Status register. used verify data integrity with Write commands. Therefore, master only read access this register. lower bits register indicate address last byte that been written scratchpad. This address called Ending Offset. register, called "partial byte flag," number data bits sent master integer multiple "Overflow," more bits sent master than stored scratchpad. Note that lowest bits target address also determine address within scratchpad, where intermediate storage data will begin. This address called byte offset. target address Write command 13CH example, then scratchpad will store incoming data beginning byte offset will full after only bytes. corresponding ending offset this example 1FH. best economy speed efficiency, target address writing should point beginning page, i.e., byte offset will Thus full 32-byte capacity scratchpad available, resulting also ending offset 1FH. However, possible write several contiguous bytes somewhere within page. ending offset together with Partial Overflow Flag mainly means support master checking data integrity after Write command. highest valued register, called Authorization Accepted, acts flag indicate that data stored scratchpad already been copied target memory address. Writing data scratchpad clears this flag.
WRITING WITH VERIFICATION
write data DS1996, scratchpad used intermediate storage. First master issues Write Scratchpad command specify desired target address, followed data written scratchpad. next step, master sends Read Scratchpad command read scratchpad verify data integrity. preamble scratchpad data, DS1996 sends requested target address contents register. flags set, data arrive correctly scratchpad. master does need continue reading; start trial write data scratchpad. Similarly, flag indicates that Write command recognized iButton. everything went correctly, three flags cleared ending offset indicates address last byte written scratchpad. master continue verifying every data bit. After master verified data, send Copy Scratchpad command. This command must followed exactly data three address registers TA1, master read them verifying scratchpad. soon iButton received these bytes, will copy data requested location beginning target address.
MEMORY FUNCTION COMMANDS
"Memory Function Flow Chart" (Figure describes protocols necessary accessing memory. example follows flowchart. communication between master DS1996 takes place either regular speed (default, OD=0) Overdrive Speed (OD=1). explicitely into Overdrive Mode DS1996 assumes regular speed.
DS1996
Write Scratchpad Command [0FH]
After issuing write scratchpad command, master must first provide 2-byte target address, followed data written scratchpad. data will written scratchpad starting byte offset (T4:T0). ending offset (E4: will byte offset which master stopped writing data.
Read Scratchpad Command [AAH]
This command used verify scratchpad data target address. After issuing read scratchpad command, master begins reading. first bytes will target address. next byte will ending offset/data status byte (E/S) followed scratchpad data beginning byte offset (T4: T0). master read data until scratchpad after which data read will logic 1's.
DS1996 MEMORY Figure
ADDRESS REGISTERS Figure
DS1996
MEMORY FUNCTION FLOW CHART Figure
TRANSMITTED RECEIVED OVERDRIVE SPEED OD=1 RESET PULSE TRANSMITTED OVERDRIVE SPEED OD=1; RESET PULSE TRANSMITTED REGULAR SPEED OD=0 DS1996 RESET FROM OVERDRIVE SPEED REGULAR SPEED
DS1996
MEMORY FUNCTION EXAMPLES
Example: Write data bytes memory locations 0026h 0027h (the seventh bytes page Read entire memory. MASTER MODE DATA (LSB FIRST) Reset Presence data bytes> Reset Presence data bytes> Reset Presence Reset Presence <8192 bytes> Reset Presence COMMENTS Reset pulse (480-960 Presence pulse Issue "skip ROM" command Issue "write scratchpad" command TA1, beginning offset=6 TA2, address=0026h Write bytes data scratchpad Reset pulse Presence pulse Issue "skip ROM" command Issue "read scratchpad" command Read TA1, beginning offset=6 Read TA2, address=0026h Read E/S, ending offset=7, flags=0 Read scratchpad data verify Reset pulse Presence pulse Issue "skip ROM" command Issue "copy scratchpad" command AUTHORIZATION CODE Reset pulse Presence pulse Issue "skip ROM" command Issue "read memory" command TA1, beginning offset=0 TA2, address=0000h Read entire memory Reset pulse Presence pulse, done
DS1996
Copy Scratchpad [55H]
This command used copy data from scratchpad memory. After issuing copy scratchpad command, master must provide 3-byte authorization pattern which obtained reading scratchpad verification. This pattern must exactly match data contained three address registers (TA1, TA2, E/S, that order). pattern matches, (Authorization Accepted) flag will copy will begin. logic will transmitted after data been copied until reset pulse issued master. attempt reset part will ignored while copy progress. Copy typically takes data copied determined three address registers. scratchpad data from beginning offset through ending offset, will copied memory, starting target address. Anywhere from bytes copied memory with this command. Whole bytes copied even only partially written. flag will cleared only executing write scratchpad command.
Read Memory [F0H]
read memory command used read entire memory. After issuing command, master must provide 2-byte target address. After bytes, master reads data beginning from target address continue until memory, which point logic will read. important realize that target address registers will contain address provided. ending offset/data status byte unaffected. hardware DS1996 provides means accomplish error-free writing memory section. safeguard reading data 1-Wire environment simultaneously speed data transfers, recommended packetize data into data packets size memory page each. Such packet would typically store 16-bit with each page data ensure rapid, error-free data transfers that eliminate having read page multiple times determine received data correct not. (See Book DS19xx iButton Standards, Chapter recommended file structure used with 1Wire environment.)
1-WIRE SYSTEM
1-Wire system which single master more slaves. instances DS1996 slave device. master typically microcontroller. discussion this system broken down into three topics: hardware configuration, transaction sequence, 1-Wire signaling (signal types timing). 1-Wire protocol defines transactions terms state during specified time slots that initiated falling edge sync pulses from master. more detailed protocol description, refer Chapter Book DS19xx iButton Standards.
HARDWARE CONFIGURATION
1-Wire only single line definition; important that each device able drive appropriate time. facilitate this, each device attached 1-Wire must have open drain connection 3-state outputs. 1-Wire port DS1996 open drain with internal circuit equivalent that shown Figure multidrop consists 1-Wire with multiple slaves attached. regular speed 1-Wire maximum data rate 16.3 kbits second. speed boosted kbits second activating Overdrive Mode. 1-Wire requires pullup resistor approximately idle state 1-Wire high. reason transaction needs suspended, MUST left idle state transaction resume. this does occur left more than (Overdrive Speed) more than (regular speed), more devices reset.
DS1996
HARDWARE CONFIGURATION Figure
RECEIVE TRANSMIT
TRANSACTION SEQUENCE
protocol accessing DS1996 1-Wire port follows: Initialization Function Command Memory Function Command Transaction/Data
INITIALIZATION
transactions 1-Wire begin with initialization sequence. initialization sequence consists reset pulse transmitted master followed presence pulse(s) transmitted slave(s). presence pulse lets master know that DS1996 ready operate. more details, "1-Wire Signaling" section.
FUNCTION COMMANDS
Once master detected presence, issue function commands. function commands bits long. list these commands follows (refer flowchart Figure
Read [33H]
This command allows master read DS1996's 8-bit family code, unique 48-bit serial number, 8-bit CRC. This command only used there single DS1996 bus. more than slave present bus, data collision will occur when slaves transmit same time (open drain will produce wired-AND result). resultant family code 48-bit serial number will usually result mismatch CRC.
DS1996
Match [55H]
match command, followed 64-bit sequence, allows master address specific DS1996 multidrop bus. Only DS1996 that exactly matches 64-bit sequence will respond subsequent memory function command. slaves that match 64-bit sequence will wait reset pulse. This command used with single multiple devices bus.
Skip [CCH]
This command save time single drop system allowing master access memory functions without providing 64-bit code. more than slave present read command issued following Skip command, data collision will occur multiple slaves transmit simultaneously (open drain pulldowns will produce wired-AND result).
Search [F0H]
When system initially brought master might know number devices 1Wire their 64-bit codes. search command allows master process elimination identify 64-bit codes slave devices bus. search process repetition simple 3-step routine: read bit, read complement bit, then write desired value that bit. master performs this simple, 3-step routine each ROM. After complete pass, master knows contents device. remaining number devices their codes identified additional passes. Chapter Book DS19xx iButton Standards comprehensive discussion search ROM, including actual example.
Overdrive Skip [3CH]
single-drop this command save time allowing master access memory functions without providing 64-bit code. Unlike normal Skip command Overdrive Skip sets DS1996 Overdrive Mode (OD=1). communication following this command occur Overdrive Speed until reset pulse minimum duration resets devices regular speed (OD=0). When issued multidrop this command will Overdrive-capable devices into Overdrive mode. subsequently address specific Overdrive-capable device, reset pulse Overdrive speed issued followed Match Search command sequence. This will shorten time search process. more than slave supporting Overdrive present Overdrive Skip command followed read command, data collision will occur multiple slaves transmit simultaneously (open drain pulldowns will produce wired-AND result).
Overdrive Match [69H]
Overdrive Match command, followed 64-bit sequence transmitted Overdrive Speed, allows master address specific DS1996 multidrop simultaneously Overdrive Mode. Only DS1996 that exactly matches 64-bit sequence will respond subsequent memory function command. Slaves already Overdrive mode from previous Overdrive Skip Match command will remain Overdrive mode. other slaves that match 64-bit sequence support Overdrive will return remain regular speed wait reset pulse minimum duration. Overdrive Match command used with single multiple devices bus.
DS1996
1-WIRE SIGNALING
DS1996 requires strict protocols ensure data integrity. protocol consists four types signaling line: Reset Sequence with Reset Pulse Presence Pulse, Write Write Read Data. these signals except presence pulse initiated master. DS1996 communicate different speeds, regular speed Overdrive speed. explicitly into overdrive mode, DS1996 will communicate regular speed. While Overdrive Mode fast timing applies wave forms. initialization sequence required begin communication with DS1996 shown Figure reset pulse followed presence pulse indicates DS1996 ready send receive data given correct command memory function command. master transmits (TX) reset pulse (tRSTL minimum regular speed, Overdrive speed). master then releases line goes into receive mode (RX). 1-Wire pulled high state pullup resistor. After detecting rising edge data contact, DS1996 waits (tPDH, 15-60 regular speed, Overdrive speed) then transmits presence pulse (tPDL, 60-240 regular speed, 8-24 Overdrive speed). Reset Pulse longer will exit Overdrive Mode returning device regular speed. DS1996 Overdrive Mode Reset Pulse longer than device will remain Overdrive Mode.
DS1996
FUNCTIONS FLOW CHART Figure
TRANSMITTED RECEIVED OVERDRIVE SPEED OD=1 PRESENCE PULSE WILL SHORT OD=1
DS1996
FUNCTIONS FLOW CHART Figure (cont'd)
ALWAYS TRANSMITTED OVERDRIVE SPEED
DS1996
INITIALIZATION PROCEDURE "RESET PRESENCE PULSES" Figure
RESISTOR MASTER DS1996
Regular Speed tRSTL tRSTH (includes recovery time) tPDL
Overdrive Speed tRSTL tRSTH tPDH tPDL
order mask interrupt signaling other devices 1-Wire bus, tRSTL should always less than
READ/WRITE TIME SLOTS
definitions write read time slots illustrated Figure time slots initiated master driving data line low. falling edge data line synchronizes DS1996 master triggering delay circuit DS1996. During write time slots, delay circuit determines when DS1996 will sample data line. read data time slot, transmitted, delay circuit determines long DS1996 will hold data line overriding generated master. data "1", iButton will leave read data time slot unchanged.
READ/WRITE TIMING DIAGRAM Figure Write-One Time Slot
RESISTOR MASTER
Regular Speed tSLOT tLOW1 tREC
Overdrive Speed tSLOT tLOW1 tREC
DS1996
READ/WRITE TIMING DIAGRAM Figure (cont'd) Write-Zero Time Slot
Regular Speed tLOW0 tSLOT tREC
Overdrive Speed tLOW0 tSLOT tREC
Read-Data Time Slot
RESISTOR MASTER DS1996
Regular Speed tSLOT tLOWR tRELEASE tREC tRDV
Overdrive Speed tSLOT tLOWR tRELEASE tREC tRDV
DS1996
PHYSICAL SPECIFICATIONS
Size Weight Humidity Altitude Expected Service Life mechanical drawing grams package) 50°C 10,000 feet years 25°C
ABSOLUTE MAXIMUM RATINGS*
Voltage Relative Ground Operating Temperature Storage Temperature -0.5V +7.0V -40°C +70°C -40°C +70°C
This stress rating only functional operation device these other conditions above those indicated operation sections this specification implied. Exposure absolute maximum rating conditions extended periods time affect reliability.
ELECTRICAL CHARACTERISTICS
PARAMETER Logic Logic Output Logic Input Load Current SYMBOL -0.3
(VPUP=2.8V 6.0V, -40°C +70°C)
+0.3 +0.3 UNITS NOTES
CAPACITANCE
PARAMETER (1-Wire) SYMBOL CIN/OUT
25°C)
UNITS NOTES
ELECTRICAL CHARACTERISTICS: REGULAR SPEED
PARAMETER Time Slot Write Time Write Time Read Data Valid Release Time Read Data Setup Recovery Time Reset Time High Reset Time Presence Detect High Presence Detect SYMBOL tSLOT tLOW1 tLOW0 tRDV tRELEASE tREC tRSTH tRSTL tPDH tPDL
(-40°C 70°C)
UNITS NOTES
exactly
DS1996
ELECTRICAL CHARACTERISTICS: OVERDRIVE SPEED
PARAMETER Time Slot Write Time Write Time Read Data Valid Release Time Read Data Setup Recovery Time Reset Time High Reset Time Presence Detect High Presence Detect SYMBOL tSLOT tLOW1 tLOW0 tRDV tRELEASE tREC tRSTH tRSTL tPDH tPDL
(-40°C 70°C)
UNITS NOTES
exactly
NOTES:
voltages referenced ground. Input load ground. additional reset communication sequence cannot begin until reset high time expired. Read data setup time refers time host must pull 1-Wire read bit. Data guaranteed valid within this falling edge. Capacitance data contact could when power first applied. resistor used pullup data line VCC, after power been applied, parasite capacitance will affect normal communications. reset time (tRSTL) should restricted maximum allow interrupt signaling, otherwise, could mask conceal interrupt pulses. function external pullup resistor power supply.
DS1996
REVISION HISTORY
REVISION DATE DESCRIPTION Updated Ordering Information table only show lead-free version (DS1996-F5+). Updated MicroCan marking match H020201. Updated wording Parasite Power section. Changed tPDL(MIN) spec from Figure Electrical Characteristics: Overdrive Speed table. Electrical Characteristics table, removed spec changed VIL(MAX) spec from 0.8V 0.3V. 8/09 Removed UL#913 bullet Common iButton Features section. PAGES CHANGED
070808
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600
2009 Maxim Integrated Products Maxim registered trademark Maxim Integrated Products, Inc.

DS1996 64Kb Memory iButton 65536 bits read/write nonvolatile memo

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