DS1992/DS1993 1Kb/4Kb Memory iButton® 4096 bits Read/Write Nonvol

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DS1992/DS1993 1Kb/4Kb Memory iButton® 4096 bits Read/Write Nonvol

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19-4865; 8/09
DS1992/DS1993 1Kb/4Kb Memory iButton®
4096 bits Read/Write Nonvolatile Memory (DS1993) 1024 bits Read/Write Nonvolatile Memory (DS1992) 256-bit Scratchpad Ensures Integrity Data Transfer Memory Partitioned into 256-bit Pages Packetizing Data Data Integrity Assured with Strict Read/Write Protocols Operating Temperature Range from -40°C +70°C Over years data retention MicroCan MicroCan
COMMON iButton FEATURES
Unique, Factory-Lasered Tested 64-bit Registration Number (8-bit Family Code 48-bit Serial Number 8-bit Tester) Assures Absolute Traceability Because Parts Alike Multidrop Controller MicroLAN Digital Identification Information Momentary Contact Chip-Based Data Carrier Compactly Stores Information Data Accessed While Affixed Object Economically Communicates Master with Single Digital Signal 16.3kbps Standard 16mm Diameter 1-Wire® Protocol Ensure Compatibility with iButton® Family Button Shape Self-Aligning with CupShaped Probes Durable Stainless Steel Case Engraved with Registration Number Withstands Harsh Environments Easily Affixed with Self-Stick Adhesive Backing, Latched Flange, Locked with Ring Pressed onto Presence Detector Acknowledges When Reader First Applies Voltage Meets UL#913 (4th Edit.); Intrinsically Safe Apparatus, Approved under Entity Concept Class Division Group Locations
ORDERING INFORMATION
DS1992L-F5+ DS1993L-F5+
+Denotes lead(Pb)-free/RoHS-compliant product.
EXAMPLES ACCESSORIES
DS9096P Self-Stick Adhesive DS9101 Multipurpose Clip DS9093RA Mounting Lock Ring DS9093F Snap-In DS9092 iButton Probe
MicroCan
1-Wire iButton registered trademarks Maxim Integrated Products, Inc.
DS1992/DS1993
iButton DESCRIPTION
DS1992/DS1993 memory iButtons (hereafter referred DS199_) rugged read/write data carriers that localized database, easily accessible with minimal hardware. nonvolatile memory optional timekeeping capability offer simple solution storing retrieving vital information pertaining object which iButton attached. Data transferred serially through 1-Wire protocol that requires only single data lead ground return. scratchpad additional page that acts buffer when writing memory. Data first written scratchpad where read back. After data been verified, copy scratchpad command transfers data memory. This process ensures data integrity when modifying memory. 48-bit serial number factory lasered into each DS199_ provide guaranteed unique identity that allows absolute traceability. durable MicroCan package highly resistant environmental hazards such dirt, moisture, shock. compact coin-shaped profile self-aligning with mating receptacles, allowing DS199_ easily used human operators. Accessories permit DS199_ mounted almost surface including plastic fobs, photo-ID badges, boards. Applications include access control, work-in-progress tracking, electronic travelers, storage calibration constants, debit tokens.
OPERATION
DS199_ have three main data components: 64-bit lasered ROM, 256-bit scratchpad, 1024-bit (DS1992) 4096-bit (DS1993) SRAM. data read written least significant first. memory functions available until function protocol been established. This protocol described functions flow chart (Figure master must first provide four function commands: read ROM, match ROM, search ROM, skip ROM. After function sequence been successfully executed, memory functions accessible master then provide four memory function commands (Figure
PARASITE POWER
block diagram (Figure shows parasite-powered circuitry. This circuitry steals power whenever data input high. data line provides sufficient power long specified timing voltage requirements met. advantages parasite power two-fold: parasiting this input, battery power consumed 1-Wire function commands, battery exhausted reason, still read normally. remaining circuitry DS1992 DS1993 solely operated battery energy.
64-BIT LASERED
Each DS199_ contain unique code that bits long. first bits 1-Wire family code. next bits unique serial number. last bits first bits. (See Figure 1-Wire generated using polynomial generator consisting shift register gates shown Figure polynomial Additional information about Dallas 1-Wire Cyclic Redundancy Check available Book DS19xx iButton Standards. shift register bits initialized zero. Then starting with least significant family code, time shifted After family code been entered, then serial number entered. After 48th serial number been entered, shift register contains value. Shifting bits should return shift register zeros.
DS1992/DS1993
Figure DS199_ BLOCK DIAGRAM
FUNCTION CONTROL PARASITEPOWERED CIRCUITRY
1-WIRE PORT
64-BIT LASERED
MEMORY FUNCTION CONTROL
256-BIT SCRATCHPAD
SRAM PAGES 256BITs (1993) PAGES 256BITs (1992) LITHIUM
Figure 64-BIT LASERED
8-Bit Family Code (06h)1993 (08h)1992
8-Bit Code
48-Bit Serial Number
Figure 1-WIRE CODE
Polynomial
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
INPUT DATA
DS1992/DS1993
Figure DS1993 MEMORY
SCRATCHPAD PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE MEMORY PAGE PAGE PAGE PAGE PAGE PAGE PAGE PAGE 0000h 0020h 0040h 0060h 0080h 00A0h 00C0h 00E0h 0100h 0120h 0140h 0160h 0180h 01A0h 01C0h 01E0h NOTE: Each page bytes (256 bits). values represent starting address each page register.
Figure DS1992 MEMORY
SCRATCHPAD PAGE PAGE PAGE MEMORY PAGE PAGE 0040h 0060h 0000h 0020h NOTE: Each page bytes (256 bits). values represent starting address each page register.
DS1992/DS1993
MEMORY
memory Figure shows 32-Byte page called scratchpad, additional 32-Byte pages called memory. DS1992 contains pages though that make 1024-bit SRAM. DS1993 contain pages through that make 4096-bit SRAM. scratchpad additional page that acts buffer when writing memory. Data first written scratchpad where read back. After data been verified, copy scratchpad command transfers data memory. This process ensures data integrity when modifying memory.
MEMORY FUNCTION COMMANDS
Memory Function Flow Chart (Figure describes protocols necessary accessing memory. example follows flow chart. Three address registers provided shown Figure first registers represent 16-bit target address (TA1, TA2). third register ending offset/data status byte (E/S). target address points unique Byte location memory. first bits target address (T4:T0) represent Byte offset within page. This Byte offset points possible Byte locations within given page. instance, 00000b points first Byte page where 11111b would point last Byte page. third register (E/S) read only register. first bits (E4: this register called ending offset. ending offset Byte offset within page Bytes). (PF) partial Byte flag. (OF) overflow flag. (AA) authorization accepted flag.
Figure ADDRESS REGISTERS
TARGET ADDRESS (TA1) TARGET ADDRESS (TA2) ENDING ADDRESS WITH DATA STATUS (E/S) (READ ONLY)
Write Scratchpad Command [0Fh]
After issuing write scratchpad command, user must first provide 2-Byte target address, followed data written scratchpad. data written scratchpad starting byte offset (T4:T0). ending offset (E4:E0) Byte offset which host stops writing data. maximum ending offset 11111b (31d). host attempts write data past this maximum offset, overflow flag (OF) remaining data ignored. user writes incomplete Byte overflow occurred, partial Byte flag (PF) set.
Read Scratchpad Command [AAh]
This command used verify scratchpad data target address. After issuing read scratchpad command, user begin reading. first Bytes target address. next Byte ending offset/data status Byte (E/S) followed scratchpad data beginning Byte offset (T4: T0). user read data until scratchpad, after which data read logic 1's.
DS1992/DS1993
Copy Scratchpad [55h]
This command used copy data from scratchpad memory. After issuing copy scratchpad command, user must provide 3-byte authorization pattern. This pattern must exactly match data contained three address registers (TA1, TA2, E/S, that order). pattern matches, (Authorization Accepted) flag copy begins. logic transmitted after data been copied until user issues reset pulse. attempt reset part ignored while copy progress. Copy typically takes 30s. data copied determined three address registers. scratchpad data from beginning offset through ending offset copied memory, starting target address. Anywhere from Bytes copied memory with this command. Whole Bytes copied even only partially written. flag cleared only executing write scratchpad command.
Read Memory [F0h]
read memory command used read entire memory. After issuing command, user must provide 2-Byte target address. After Bytes, user reads data beginning from target address continue until memory, which point logic read. important realize that target address registers contains address provided. ending offset/data status Byte unaffected. hardware DS1992/DS1993 provides means accomplish error-free writing memory section. safeguard reading data 1-Wire environment simultaneously speed data transfers, recommended packetize data into data packets size memory page each. Such packet would typically store 16-bit with each page data ensure rapid, error-free data transfers that eliminate having read page multiple times determine received data correct not. (See Application Note recommended file structure used with 1-Wire environment.)
DS1992/DS1993
Figure MEMORY FUNCTIONS FLOW CHART
Master Memory Function Command Write Scratchpad Master (T7:T0) Master (T15:T8) DS199X sets Scratchpad Offset (T4:T0) Clears (PF, Master Data Byte Scratchpad Offset DS199X sets (E4:E0) Scratchpad Offset Master Reset Scratchpad Offset 11111b Master Data Master Reset DS199X Increments Scratchpad Offset ScratchN Offset Partial 11111b Byte Written Master "1"s Read Scratchpad Master (T7:T0) Master (T15:T8) Master Ending Offset with Data Status (E/S) DS199X Sets Scratchpad Offset=(T4:T0) Master Data Byte From Scratchpad Offset Figure Second Part
DS199X Increments Scratchpad Offset
Master Reset From Figure Second Part DS199X Presence Pulse (See Figure
DS1992/DS1993
Figure MEMORY FUNCTIONS FLOW CHART (Continued)
From Figure First Part
Copy Scratchpad Master (T7:T0) Master (T15:T8) Master Byte Authrization Code Match DS199X "1"s DS199X Copies Scratchpad Data Memory DS199X "0"s
Read Memory
Master (T7:T0) Master (T15:T8) DS199X sets Memory Address (T15:T0)
Master Data Byte From Memory Address DS199X Increments Address Counter Master Reset Memory Address 21Dh Master "1"s
Master Reset
Master Reset
Figure First Part
DS1992/DS1993
MEMORY FUNCTION EXAMPLES
Example: Write data Bytes memory locations 0026h 0027h (the seventh eighth Bytes page Read entire memory. MASTER MODE DATA (LSB FIRST) Reset Presence data Bytes> Reset Presence data Bytes> Reset Presence Reset Presence <128 Bytes (DS1992)> <512 Bytes (DS1993)> Reset Presence COMMENTS Reset pulse (480s 960s) Presence pulse Issue skip command Issue write scratchpad command TA1, beginning offset TA2, address 0026h Write Bytes data scratchpad Reset pulse Presence pulse Issue skip command Issue read scratchpad command Read TA1, beginning offset Read TA2, address 0026h Read E/S, ending offset flags Read scratchpad data verify Reset pulse Presence pulse Issue skip command Issue copy scratchpad command AUTHORIZATION CODE Reset pulse Presence pulse Issue skip command Issue read memory command TA1, beginning offset TA2, address 0000h Read entire memory Reset pulse Presence pulse, done
DS1992/DS1993
1-WIRE SYSTEM
1-Wire system that single master more slaves. instances DS199_ slave device. master typically microcontroller small configurations 1-Wire communication signals generated under software control using single port pin. multisensor networks, DS2480B 1-Wire line driver chip serial port adapters based this chip (DS9097U series) recommended. This simplifies hardware design frees microprocessor from responding real-time. discussion this system broken down into three topics: hardware configuration, transaction sequence, 1-Wire signaling (signal types timing). 1-Wire protocol defines transactions terms state during specific time slots that initiated falling edge sync pulses from master. more detailed protocol description, refer Chapter Book DS19xx iButton Standards.
HARDWARE CONFIGURATION
1-Wire only single line definition; important that each device able drive appropriate time. facilitate this, each device attached 1-wire must have opendrain three-state outputs. 1-Wire port DS199_ open drain with internal circuit equivalent that shown Figure multidrop consists 1-Wire with multiple slaves attached. 1-Wire maximum data rate 16.3kbps requires pullup resistor approximately idle state 1-Wire high. reason transaction needs suspended, must left idle state transaction resume. this does occur left more than 120s, more devices reset.
Figure HARDWARE CONFIGURATION
MASTER VPUP DS199X 1-Wire PORT
DATA Typ. MOSFET
Open Drain Port
RECEIVE TRANSMIT
TRANSACTION SEQUENCE
protocol accessing DS199_ through 1-Wire port follows: Initialization Function Command Memory Function Command Transaction/Data
INITIALIZATION
transactions 1-wire begin with initialization sequence. initialization sequence consists reset pulse transmitted master followed presence pulse(s) transmitted
DS1992/DS1993
slave(s). presence pulse lets master know that DS199_ ready operate. more details, 1-Wire Signaling section.
FUNCTION COMMANDS
Once master detected presence, issue four function commands. function commands bits long. list these commands follows (see flow chart Figure
Read [33h]
This command allows master read DS199_'s 8-bit family code, unique 48-bit serial number, 8-bit CRC. This command should only used there single DS199_ bus. more than slave present bus, data collision occurs when slaves transmit same time (open drain produces wired-AND result). resultant family code 48-bit serial number usually result mismatch CRC.
Match [55h]
match command, followed 64-bit sequence, allows master address specific DS199_ multidrop bus. Only DS199_ that exactly matches 64-bit sequence will respond following memory function command. slaves that match 64-bit sequence wait reset pulse. This command used with single multiple devices bus.
Skip [CCh]
This command save time single drop system allowing master access memory functions without providing 64-bit code. more than slave present and, example, read command issued following Skip command, data collision will occur multiple slaves transmit simultaneously (open-drain pulldowns produce wired-AND result).
Search [F0h]
When system initially brought master know number devices 1-Wire their 64-bit codes. search command allows master process elimination identify 64-bit codes slave devices bus. search process repetition simple 3-step routine: read bit, read complement bit, then write desired value that bit. master performs this simple, 3-step routine each ROM. After complete pass, master knows 64-bit code device. Additional passes will identify codes remaining devices. Chapter Book DS19xx iButton Standards comprehensive discussion search ROM, including actual example.
1-WIRE SIGNALING
DS199_ require strict protocols ensure data integrity. protocol consists four types signaling line: reset sequence with reset pulse presence pulse, write write read data. master initiates these signals except presence pulse. initialization sequence required begin communication with DS199_ shown Figure reset pulse followed presence pulse indicates DS199_ ready send receive data given correct command memory function command. master transmits (Tx) reset pulse (tRSTL, minimum 480s). master then releases line goes into receive mode (Rx). 1-Wire pulled high state through pullup resistor. After detecting rising edge data line, DS199_ waits (tPDH, 60s) then transmits presence pulse (tPDL, 240s).
DS1992/DS1993
Figure FUNCTIONS FLOW CHART
199X Read
199X
199X ytes
199X
DS1992/DS1993
Figure INITIALIZATION PROCEDURE RESET PRESENCE PULSE
MASTER "RESET PULSE" VPULLUP VPULLUP tRSTL RESISTOR MASTER DS199X tPDH tPDL
order mask interrup signaling other devices 10Wire tRSTL should always less than Includes recovery time
MASTER "PRESENCE PULSE" tRSTH
tRSTL tRSTH tPDH tPDL
READ/WRITE TIME SLOTS
definitions write read time slots illustrated Figure master driving data line initiates time slots. falling edge data line synchronizes DS199_ master triggering delay circuit DS199_. During write time slots, delay circuit determines when DS199_ samples data line. read data time slot, transmitted, delay circuit determines long DS199_ holds data line overriding generated master. data iButton leaves read data time slot unchanged.
Figure READ/WRITE TIMING DIAGRAM Write-One Time Slot
VPULLUP tLOW1 15µs 60µs tSLOT tREC VPULLUP tSLOT tREC
DS199X Sampling Window
RESISTOR MASTER
tLOW1
DS1992/DS1993
Figure READ/WRITE TIMING DIAGRAM (continued) Write-Zero Time Slot
VPULLUP 15µs 60µs LOW0 RESISTOR MASTER tLOW0 tSLOT tREC VPULLUP tSLOT tREC
DS199X Sampling Window
Read-Data Time Slot
VPULLUP tLOWR tRDV RESISTOR MASTER DS199X tSLOT tLOWR tRELEASE tREC tRDV Master Sampling Window VPULLUP tSLOT tREC
tRELEASE
DS1992/DS1993
PHYSICAL SPECIFICATIONS
Size Weight Expected Service Life Safety mechanical drawing grams package) years +25C Meets UL#913 (4th Edit.); Intrinsically Safe Apparatus, Approved under Entity Concept Class Division Group Locations -0.5V +7.0V -40C +70C -40C +70C
ABSOLUTE MAXIMUM RATINGS*
Voltage Relative Ground Operating Temperature Range Storage Temperature Range
This stress rating only functional operation device these other conditions above those indicated operation sections this specification implied. Exposure absolute maximum rating conditions extended periods time affect reliability.
ELECTRICAL CHARACTERISTICS
PARAMETER 1-Wire Pullup Voltage (Notes Logic (Notes Logic (Note Output Logic (Note Input Load Current (Note SYMBOL VPUP SYMBOL CIN/OUT SYMBOL tSLOT tLOW1 tLOW0 tRDV tRELEASE tREC tRSTH tRSTL tPDH tPDL -0.3
(-40°C +70°C.)
+0.3 UNITS
CAPACITANCE
PARAMETER (1-Wire) (Notes PARAMETER Time Slot Write Time Write Time Read Data Valid Release Time Read Data Setup (Note Recovery Time Reset Time High (Note Reset Time (Note Presence Detect High Presence Detect
+25°C)
UNITS UNITS
ELECTRICAL CHARACTERISTICS
(VPUP 2.8V 6.0V; -40°C +70°C.)
exactly
DS1992/DS1993
Note voltages referenced ground. Note function external pullup resistor power supply. Note VPUP external pullup voltage. Note Input load ground. Note Capacitance data line could 800pF when power first applied. 5kresistor used pull data line VPUP, after power been applied, parasite capacitance does affect normal communications. Note Guaranteed design, production tested. Note Read data setup time refers time host must pull 1-Wire read bit. Data guaranteed valid within this falling edge, remains valid minimum (15s total from falling edge 1-Wire bus). Note additional reset communication sequence cannot begin until reset high time expired. Note reset time (tRSTL) should restricted maximum 960s, allow interrupt signaling; otherwise, could mask conceal interrupt pulses.
DS1992/DS1993
REVISION HISTORY
REVISION DATE 7/08 DESCRIPTION Updated MicroCan face brand with latest H020201. Change last sentence Parasite Power section "The advantages parasite power two-fold: parasiting this input, battery power consumed 1-Wire function commands, battery exhausted reason, still read normally. remaining circuitry DS1992 DS1993 solely operated battery energy." Electrical Characteristics section, relocated VPUP from header table, changed VILMAX from 0.8V 0.3V, removed parameter 1-Wire pin. Updated part numbers Ordering Information table indicate lead(Pb)-free/RoHS compliant product. PAGES CHANGED
10/08
8/09
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600
2009 Maxim Integrated Products
Maxim logo registered trademark Maxim Integrated Products, Inc.

DS1992/DS1993 1Kb/4Kb Memory iButton® 4096 bits Read/Write Nonvol

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