DS1986 64Kb Add-Only iButton® 65536 bits Electrically Programmabl

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DS1986 64Kb Add-Only iButton® 65536 bits Electrically Programmabl

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19-4893; 8/09
DS1986 64Kb Add-Only iButton®
65536 bits Electrically Programmable Read Only Memory (EPROM) communicates with economy signal plus ground Overdrive mode boosts communication speed 142kbps EPROM partitioned into two-hundred fifty-six 256-bit pages randomly accessing packetized data records Each memory page permanently writeprotected prevent tampering Device "add only" memory where additional data programmed into EPROM without disturbing existing data Architecture allows software patch data superseding page favor newly programmed page Reduces control, address, data, power, programming signals single data 8-bit family code specifies DS1986 communications requirements reader Reads over wide voltage range 2.8V 6.0V from -40°C +85°C; programs 11.5V 12.0V from -40°C +85°C
COMMON iButton FEATURES
Unique, factory-lasered tested 64-bit registration number (8-bit family code 48-bit serial number 8-bit tester) assures absolute traceability because parts alike Multidrop controller MicroLAN Digital identification information momentary contact Chip-based data carrier compactly stores information Data accessed while affixed object Economically communicates master with single digital signal 16.3kbps Standard diameter 1-Wire® protocol ensure compatibility with iButton family Button shape self-aligning with cup-shaped probes Durable stainless steel case engraved with registration number withstands harsh environments Easily affixed with self-stick adhesive backing, latched flange, locked with ring pressed onto Presence detector acknowledges when reader first applies voltage Self-Stick Adhesive Multi-Purpose Clip Mounting Lock Ring Snap-In iButton Probe
ORDERING INFORMATION
PART DS1986-F3+ DS1986F-5+ PIN-PACKAGE MicroCan MicroCan
EXAMPLES ACCESSORIES
DS9096P DS9101 DS9093RA DS9093F DS9092
+Denotes lead(Pb)-free/RoHS-compliant package.
MicroCan
MicroCan
1-Wire iButton registered trademarks Maxim Integrated Products, Inc.
DS1986
iButton DESCRIPTION
DS1986 64Kb Add-Only iButton rugged read/write data carrier that identifies stores relevant information about product person which attached. This information accessed with minimal hardware, example single port microcontroller. DS1986 consists factorylasered registration number that includes unique 48-bit serial number, 8-bit CRC, 8-bit Family Code (0Fh) plus 64Kb EPROM that user-programmable. power program read DS1986 derived entirely from 1-Wire communication line. Data transferred serially 1-Wire protocol that requires only single data lead ground return. entire device programmed then write-protected desired. Alternatively, part programmed multiple times with data being appended overwriting, existing data with each subsequent programming device. Note: Individual bits changed only from logical logical never from logical logical provision also included indicating that certain page pages data longer valid have been replaced with updated data that residing alternate page address. This page address redirection allows software patch data enhance flexibility device standalone database. 48-bit serial number that factory-lasered into each DS1986 provides guaranteed unique identity that allows absolute traceability. durable MicroCan package highly resistant harsh environments such dirt, moisture, shock. compact button-shaped profile self-aligning with cup-shaped receptacles, allowing DS1986 used easily human operators automatic equipment. Accessories permit DS1986 mounted printed circuit boards, plastic fobs, photo-ID badges, bracelets, many other objects. Applications include work-in-progress tracking, electronic travelers, access control, storage calibration constants, debit tokens.
OVERVIEW
block diagram Figure shows relationships between major control memory sections DS1986. DS1986 three main data components: 64-bit lasered ROM, 65536 bits EPROM Data Memory, 2816 bits EPROM Status Memory. device derives power read operations entirely from 1-Wire communication line storing energy internal capacitor during periods time when signal line high continues operate this "parasite" power source during times 1-Wire line until returns high replenish parasite (capacitor) supply. During programming, 1-Wire communication occurs normal voltage levels then pulsed momentarily programming voltage cause selected EPROM bits programmed. 1Wire line must able provide volts milliamperes adequately program EPROM portions part. Whenever programming voltages present 1-Wire line special high voltage detect circuit within DS1986 generates internal logic signal indicate this condition. hierarchical structure 1-Wire protocol shown Figure master must first provide Function Commands, Read ROM, Match ROM, Search ROM, Skip ROM, Overdrive-Skip ROM, Overdrive-Match ROM. Upon completion Overdrive command byte executed regular speed, device will enter Overdrive mode where subsequent communication occurs higher speed. These commands operate 64-bit lasered portion each device singulate specific device many present 1-Wire line well indicate master many what types devices present. protocol required these Function Commands described Figure After Function Command successfully executed, memory functions that operate EPROM portions DS1986 become accessible master issue five Memory Function Commands specific DS1986 read program various data fields. protocol these Memory Function Commands described Figure data read written least significant first.
DS1986
64-BIT LASERED
Each DS1986 contains unique code that bits long. first eight bits 1-Wire family code. next bits unique serial number. last eight bits first bits. (See Figure 64-bit Function Control section allow DS1986 operate 1-Wire device follow 1-Wire protocol detailed section "1-Wire System". memory functions required read program EPROM sections DS1986 accessible until function protocol been satisfied. This protocol described functions flow chart (Figure 1-Wire master must first provide function commands: Read ROM, Match ROM, Search ROM, Skip ROM, Overdrive-Skip ROM, Overdrive-Match ROM. After function sequence been successfully executed, master then provide memory function commands specific DS1986 (Figure 1-Wire lasered generated using polynomial Additional information about Dallas Semiconductor 1-Wire Cyclic Redundancy Check available Book DS19xx iButton Standards. shift register acting accumulator initialized zero. Then starting with least significant family code, time shifted After eighth family code been entered, then serial number entered. After 48th serial number been entered, shift register contains value. Shifting eight bits should return shift register zeros.
DS1986
DS1986 BLOCK DIAGRAM Figure
DS1986
HIERARCHICAL STRUCTURE 1-WIRE PROTOCOL Figure
MASTER
1-WIRE OTHER DEVICES
DS1986 COMMAND LEVEL: AVAILABLE COMMANDS: DATA FIELD AFFECTED:
1-WIRE FUNCTION COMMANDS (SEE FIGURE
READ MATCH SEARCH SKIP OVERDRIVE SKIP OVERDRIVE MATCH
64-BIT 64-BIT 64-BIT 64-BIT
DS1986 SPECIFIC MEMORY FUNCTION COMMANDS (SEE FIGURE
WRITE MEMORY WRITE STATUS READ MEMORY READ STATUS EXTENDED READ DATA
EPROM EPROM STATUS BYTES EPROM EPROM STATUS BYTES EPROM
64-BIT LASERED Figure
Code Serial Number Family Code (0FH)
65536-BITS EPROM
memory Figure shows 65536-bit EPROM section DS1986 that configured pages bytes each. 8-bit scratchpad additional register that acts buffer when programming memory. Data first written scratchpad then verified reading 16-bit from DS1986 that confirms proper receipt data address. buffer contents correct, programming voltage should applied byte data will written into selected address memory. This process ensures data integrity when programming memory. details reading programming 65536-bit EPROM portion DS1986 given Memory Function Commands section.
DS1986
EPROM STATUS BYTES
addition 65536 bits data memory DS1986 provides 2816 bits Status Memory accessible with separate commands. EPROM Status Bytes read programmed indicate various conditions software interrogating DS1986. first bytes EPROM Status Memory (addresses 01FH) contain Write Protect Page bits that inhibit programming corresponding page 65536-bit main memory area appropriate write protection programmed. Once been programmed Write Protect Page section Status Memory, entire 32-byte page that corresponds that longer altered still read. next bytes EPROM Status Memory (addresses 03FH) contain Write Protect bits that inhibit altering Page Address Redirection Byte corresponding each page 65536-bit main memory area. following bytes within EPROM Status Memory (addresses 05FH) reserved iButton operating software TMEX. Their purpose indicate which memory pages already use. Originally, these bits unprogrammed, indicating that device does store data. soon data written page device under control TMEX, inside this bitmap corresponding that page will programmed marking this page used. These bits application flags only have impact internal logic DS1986. next bytes EPROM Status Memory (addresses 100H 1FFH) contain Page Address Redirection Bytes that indicate more pages data 65536-bit EPROM section have been invalidated software redirected page address contained appropriate redirection byte. hardware DS1986 makes decisions based contents Page address Redirection Bytes. Since with EPROM technology bits only changed from logical logical programming, possible simply rewrite page data requires changing updating. with space permitting, entire page data redirected another page within DS1986. Under TMEX page redirected writing one's complement page address into Page Address Redirection Byte that corresponds original (replaced) page. This architecture allows user's software make "data patch" EPROM indicating that particular page pages should replaced with those indicated Page Address Redirection Bytes. leave authentic audit trail data patches, recommended also program write protect Page Address Redirection Byte, after page redirection programmed. Without this protection, still possible modify Page Address Redirection Byte, making point different memory page than true one. Page Address Redirection Byte value, data main memory that corresponds that page valid. Page Address Redirection Byte some other value than FFH, data page corresponding that redirection byte invalid. According TMEX definitions valid data found one's complement page address indicated value stored associated Page Address Redirection Byte. value redirection byte page example, would indicate that updated data page status memory programmed similarly data memory. Details reading programming EPROM status memory portion DS1986 given Memory Function Commands section. Status Memory address range DS1986 extends from 1FFH. memory locations 0FFH 200H higher physically implemented. Reading these locations will usually result bytes. Attempts write these locations will ignored.
DS1986
DS1986 MEMORY Figure
STARTING ADDRESS 0000H 0020H EPROM 32-BYTE FINAL STORAGE EPROM 0040H 1FE0H 32-BYTE FINAL STORAGE EPROM
REDIRECTION BYTES USED PAGES WRITE-PROTECT BITS REDIRECTION BYTES WRITE-PROTECT BITS DATA MEMORY
8-BIT SCRATCHPAD 32-BYTE FINAL STORAGE EPROM
PAGE PAGE
PAGE
BYTES STATUS MEMORY
STATUS MEMORY
BYTES
000H
WRITE-PROTECT BITS DATA MEMORY
01FH 020H
ADDRESS 000H=WRITEPROTECT PAGE ETC.
WRITE-PROTECT BITS REDIRECTION BYTES PAGES BYTES EACH
03FH 040H
USED PAGES
05FH 060H
RESERVED FUTURE EXTENSIONS
OFFH 100H 1FFH ADDRESS 100H=PAGE ADDRESS REDIRECTION BYTE PAGE ETC.
REDIRECTION BYTES
MEMORY FUNCTION COMMANDS
"Memory Function Flow Chart" (Figure describes protocols necessary accessing various data fields within DS1986. Memory Function Control section, 8-bit scratchpad, Program Voltage Detect circuit combine interpret commands issued master create correct control signals within device. three-byte protocol issued master. comprised command byte determine type operation address bytes determine specific starting byte location within data field. command byte indicates device read written. Writing data involves only issuing correct command sequence also providing
DS1986
volt programming voltage appropriate times. execute write sequence, byte data first loaded into scratchpad then programmed into selected address. Write sequences always occur byte time. execute read sequence, starting address issued master data read from part beginning that initial location continuing selected data field until reset sequence issued. bits transferred DS1986 received back master sent least significant first.
READ MEMORY [F0H]
Read Memory command used read data from 65536-bits EPROM data field. master follows command byte with two-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates starting byte location within data field. With every subsequent read data time slot master receives data from DS1986 starting initial address continuing until 65536-bits data field reached until Reset Pulse issued. reading occurs through memory space, master issue sixteen additional read time slots DS1986 will respond with 16-bit command, address bytes data bytes read from initial starting byte through last byte memory. This result clearing generator then shifting command byte followed address bytes data bytes beginning first addressed memory location continuing through last byte EPROM data memory. After received master, subsequent read time slots will appear logical until Reset Pulse issued. reads ended Reset Pulse prior reaching memory will have 16-bit available. Typically 16-bit would stored with each page data ensure rapid, error-free data transfers that eliminate having read page multiple times determine received data correct not. (See Book DS19xx iButton Standards, Chapter recommended file structure used with 1Wire environment.) values imbedded within data, Reset Pulse issued memory space during Read Memory command.
READ STATUS [AAH]
Read Status command used read data from EPROM Status data field. master follows command byte with two-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates starting byte location within data field. With every subsequent read data time slot master receives data from DS1986 starting supplied address continuing until eightbyte page EPROM Status data field reached. that point master will receive 16-bit command byte, address bytes status data bytes. This computed DS1986 read back master check command word, starting address data were received correctly. read master incorrect, Reset Pulse must issued entire sequence must repeated. Note that initial pass through Read Status flow chart will generate 16-bit value that result clearing generator then shifting command byte followed address bytes, finally data bytes beginning first addressed memory location continuing through last byte addressed EPROM Status data page. last byte Status data page always ending address xxFH. Subsequent passes through Read Status flow chart will generate 16-bit that result clearing generator then shifting data bytes starting first byte next page EPROM Status data field. This feature provided since EPROM Status information change over time making impossible program data once include accompanying that will always valid. Therefore, Read Status command supplies 16-bit that based always consistent with current data stored EPROM Status data field.
DS1986
MEMORY FUNCTION FLOW CHART Figure
NEXT PAGE
DS1986
MEMORY FUNCTION FLOW CHART Figure (cont.)
transmitted received Overdrive Speed OD=1; Reset Pulse transmitted Overdrive Speed OD=1; Reset Pulse transmitted Regular Speed OD=0 1986 reset from Overdrive Speed Regular Speed
DS1986
MEMORY FUNCTION FLOW CHART Figure (cont.)
PREVIOUS PAGE
DS1986
After 16-bit last EPROM Status data page read, master will receive logical from DS1986 until Reset Pulse issued. Read Status command sequence ended point issuing Reset Pulse.
EXTENDED READ MEMORY [A5H]
Extended Read Memory command supports page redirection when reading data from 65536-bit EPROM data field. major difference between Extended Read Memory basic Read Memory command that master receives Redirection Byte first before investing time reading data from addressed memory location. This allows master quickly decide whether continue access data selected starting page terminate restart reading process redirected page address. non-redirected page identified Redirection Byte with value (see description EPROM Status Bytes). Redirection Byte different than this, master complement obtain page number. Multiplying page number (20H) results address master send DS1986 read updated data replacing data. There logical limitation number redirections page. only limit number available memory pages within DS1986. addition page redirection, Extended Read Memory command also supports "bit-oriented" applications where user cannot store 16-bit with data itself. With bit-oriented applications EPROM information change over time within page boundary making impossible include accompanying that will always valid. Therefore, Extended Read Memory command concludes each page with DS1986 generating supplying 16-bit that based therefore always consistent with current data stored each page 65536-bit EPROM data field. After having sent command code Extended Read Memory command, master follows command byte with two-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates starting byte location within data field. sending eight read data time slots, master receives Redirection Byte associated with page given starting address. With next sixteen read data time slots, master receives 16-bit command byte, address bytes Redirection Byte. This computed DS1986 read back master check command word, starting address Redirection Byte were received correctly. read master incorrect, Reset Pulse must issued entire sequence must repeated. received master correct, master issues read time slots receives data from DS1986 starting initial address continuing until 32-byte page reached. that point master will send sixteen additional read time slots receive 16bit that result shifting into generator data bytes from initial starting byte last byte current page. With next read data time slots master will receive Redirection Byte next page followed 16-bit Redirection Byte. After this, data again read from 65536-bit EPROM data field starting beginning page. This sequence will continue until final page accompanying read master. Extended Read Memory command provides 16-bit locations within transaction flow chart: after Redirection Byte each memory page. memory page always result clearing generator shifting data bytes beginning first addressed memory location EPROM data page until last byte this page. With initial pass through Extended Read Memory flow chart 16-bit value result
DS1986
shifting command byte into cleared generator, followed address bytes Redirection Byte. Subsequent passes through Extended Read Memory flow chart will generate 16bit that result clearing generator then shifting Redirection Byte only. After 16-bit last page read, master will receive logical from DS1986 until Reset Pulse issued. Extended Read Memory command sequence exited point issuing Reset Pulse.
WRITING EPROM MEMORY
DS1986 independent EPROM memory fields, Data Memory Status Memory. function flow writing either field almost identical. After appropriate write command been issued, master will send two-byte starting address (TA1=(T7:T0), TA2=(T15:T8)) byte data (D7:D0). 16-bit command byte, address bytes, data byte computed DS1986 read back master confirm that correct command word, starting address, data byte were received. read master incorrect, Reset Pulse must issued entire sequence must repeated. received master correct, programming pulse volts 1Wire issued master. Prior programming, entire EPROM memory field will appear logical each data byte provided master that logical corresponding selected byte EPROM memory programmed logical after programming pulse been applied. After programming pulse applied data line returns idle level Volts), master issues eight read time slots verify that appropriate bits have been programmed. DS1986 responds with data from selected EPROM address sent least significant first. This byte contains bitwise logical data ever written this address. EPROM byte contains positions where byte issued master contained Reset Pulse should issued current byte address should programmed again. DS1986 EPROM byte contains same positions data byte, programming successful DS1986 will automatically increment address counter select next byte EPROM memory field. two-byte address will also loaded into 16-bit generator starting value. master will issue next byte data using eight write time slots. DS1986 receives this byte data into scratchpad, also shifts data into generator that been preloaded with current address result 16-bit data byte address. After supplying data byte, master will read this 16-bit from DS1986 with sixteen read time slots confirm that address incremented properly data byte received correctly. incorrect, Reset Pulse must issued write sequence must restarted. correct, master will issue programming pulse selected byte memory will programmed. Note that initial pass through write flow chart will generate 16-bit value that result shifting command byte into generator, followed address bytes, finally data byte. Subsequent passes through write flow chart DS1986 automatically incrementing address counter will generate 16-bit that result loading (not shifting) (incremented) address into generator then shifting data byte. both these cases, decision continue apply program pulse DS1986) made entirely master, since DS1986 will able determine 16-bit calculated
DS1986
master agrees with 16-bit calculated DS1986. incorrect ignored program pulse applied master, incorrect programming could occur within DS1986. Also note that DS1986 will always increment internal address counter after receipt eight read time slots used confirm programming selected EPROM byte. decision continue again made entirely master. Therefore EPROM data byte does match supplied data byte master continues with write command, incorrect programming could occur within DS1986. write command sequence ended point issuing Reset Pulse.
WRITE MEMORY [0FH]/SPEED WRITE MEMORY [F3H]
Write Memory command used program 65536-bit EPROM data field. details functional flow chart described section "WRITING EPROM MEMORY". data memory address range 0000H 1FFFH. master sends starting address higher than this, three most significant address bits zeros internal circuitry chip. This will result mismatch between calculated DS1986 calculated master, indicating error condition. save time when writing more than consecutive byte DS1986's data memory possible omit reading 16-bit which allows verification data address before data copied EPROM memory. regular speed this saves time slots every byte programmed. This speed programming mode accessed with command code instead 0FH. follows basically same flow chart Write Memory command, skips sending immediately preceding program pulse. This command should only used electrical contact between master DS1986 firm since poor contact result corrupted data inside EPROM memory.
WRITE STATUS [55H]/ SPEED WRITE STATUS [F5H]
Write Status command used program 2816-bit EPROM Status Memory field. details functional flow chart described section "WRITING EPROM MEMORY". Status Memory address range 0000H 01FFH. Attempts write implemented status memory locations will ignored. master sends starting address higher than 1FFFH, three most significant address bits zeros internal circuitry chip. This will result mismatch between calculated DS1986 calculated master, indicating error condition. save time when writing more than consecutive byte DS1986's status memory possible omit reading 16-bit which allows verification data address before data copied EPROM memory. regular speed this saves time slots every byte programmed. This speed-programming mode accessed with command code instead 55H. follows basically same flow chart Write Status command, skips sending immediately preceding program pulse. This command should only used electrical contact between master DS1986 firm since poor contact result corrupted data inside EPROM status memory.
DS1986
1-WIRE SYSTEM
1-Wire system that single master more slaves. instances, DS1986 slave device. master typically microcontroller. discussion this system broken down into three topics: hardware configuration, transaction sequence, 1-Wire signaling (signal type timing). 1-Wire protocol defines transactions terms state during specified time slots that initiated falling edge sync pulses from master. more detailed protocol description, refer Chapter Book DS19xx iButton Standards.
Hardware Configuration
1-Wire only single line definition; important that each device able drive appropriate time. facilitate this, each device attached 1-Wire must have open drain connection 3-state outputs. DS1986 open drain part with internal circuit equivalent that shown Figure master same equivalent circuit. bidirectional available, separate output input pins tied together. master requires pull-up resistor master bus, with master circuit equivalent shown Figures value pull-up resistor should approximately 5kfor short line lengths. multidrop consists 1-Wire with multiple slaves attached. regular speed 1-Wire maximum data rate 16.3kbps. speed boosted 142kbps activating Overdrive mode. master also required perform programming EPROM portions DS1986, programming supply capable delivering milliamps volts required. idle state 1-Wire high. reason, transaction needs suspended, MUST left idle state transaction resume. this does occur left more than (overdrive speed) more than (regular speed), more devices reset.
Transaction Sequence
sequence accessing DS1986 1-Wire port follows: Initialization Function Command Memory Function Command Read/Write Memory/Status
INITIALIZATION
transactions 1-Wire begin with initialization sequence. initialization sequence consists reset pulse transmitted master followed presence pulse(s) transmitted slave(s). presence pulse lets master know that DS1986 ready operate. more details, "1-Wire Signaling" section.
DS1986
FUNCTION COMMANDS
Once master detected presence, issue function commands. function commands eight bits long. list these commands follows (refer flowchart Figure
Read [33H]
This command allows master read DS1986's 8-bit family code, unique 48-bit serial number, 8-bit CRC. This command used only there single DS1986 bus. more than slave present bus, data collision will occur when slaves transmit same time (open drain will produce wired-AND result). resultant family code 48-bit serial number will usually result mismatch CRC.
Match [55H]
match command, followed 64-bit sequence, allows master address specific DS1986 multidrop bus. Only DS1986 that exactly matches 64-bit sequence will respond subsequent memory function command. slaves that match 64-bit sequence will wait reset pulse. This command used with single multiple devices bus.
Skip [CCH]
This command save time single drop system allowing master access memory functions without providing 64-bit code. more than slave present read command issued following Skip command, data collision will occur multiple slaves transmit simultaneously (open drain pull-downs will produce wired-AND result).
Search [F0H]
When system initially brought master might know number devices 1Wire their 64-bit codes. search command allows master process elimination identify 64-bit codes slave devices bus. search process repetition simple 3-step routine: read bit, read complement bit, then write desired value that bit. master performs this simple, 3-step routine each ROM. After complete pass, master knows contents device. remaining number devices their codes identified additional passes. Chapter Book DS19xx iButton Standards comprehensive discussion search, including actual example.
DS1986
DS1986 EQUIVALENT CIRCUIT Figure
DATA
MASTER CIRCUIT Figure
VP0300L VP0106N3 BSS110
DATA CONNECTION DS1986
CAPACITOR ADDED REDUCE COUPLING DATA LINE PROGRAMMING SIGNAL SWITCHING
DS1986
FUNCTIONS FLOW CHART Figure
transmitted received Overdrive Speed OD=1 Presence Pulse will short OD=1
DS1986
FUNCTIONS FLOW CHART Figure (cont.)
FROM FIGURE FIRST PART
FIGURE FIRST PART
Always transmitted Overdrive Speed.
DS1986
Overdrive Skip [3CH]
single-drop this command save time allowing master access memory functions without providing 64-bit code. Unlike normal Skip command Overdrive Skip sets DS1986 Overdrive Mode (OD=1). communication following this command occur Overdrive Speed until reset pulse minimum duration resets devices regular speed (OD=0). When issued multidrop this command will Overdrive-capable devices into Overdrive mode. subsequently address specific Overdrive-capable device, reset pulse Overdrive speed issued followed Match Search command sequence. This will shorten time search process. more than slave supporting Overdrive present Overdrive Skip command followed read command, data collision will occur multiple slaves transmit simultaneously (open drain pull-downs will produce wired-AND result).
Overdrive Match [69H]
Overdrive Match command, followed 64-bit sequence transmitted Overdrive Speed, allows master address specific DS1986 multidrop simultaneously Overdrive Mode. Only DS1986 that exactly matches 64-bit sequence will respond subsequent memory function command. Slaves already Overdrive mode from previous Overdrive Skip Match command will remain Overdrive mode. other slaves that match 64-bit sequence support Overdrive will return remain regular speed wait reset pulse minimum duration. Overdrive Match command used with single multiple devices bus.
1-Wire Signaling
DS1986 requires strict protocols ensure data integrity. protocol consists five types signaling line: Reset Sequence with Reset Pulse Presence Pulse, Write Write Read Data Program Pulse. these signals except presence pulse initiated master. DS1986 communicate different speeds, regular speed Overdrive Speed. explicitly into Overdrive Mode, DS1986 will communicate regular speed. While Overdrive Mode fast timing applies communication-related waveforms. initialization sequence required begin communication with DS1986 shown Figure Reset Pulse followed Presence Pulse indicates DS1986 ready accept command. master transmits (TX) reset pulse (tRSTL minimum regular speed, Overdrive Speed). master then releases line goes into receive mode (RX). 1-Wire pulled high state pull-up resistor. After detecting rising edge data pin, DS1986 waits (tPDH 15-60 regular speed, overdrive speed) then transmits presence pulse (tPDL 60-240 regular speed, 8-24 Overdrive Speed). Reset Pulse longer will exit Overdrive Mode returning device regular speed. DS1986 Overdrive Mode Reset Pulse longer than device will remain Overdrive Mode.
DS1986
Read/Write Time Slots
definitions write read time slots illustrated Figure time slots initiated master driving data line low. falling edge data line synchronizes DS1986 master triggering delay circuit DS1986. During write time slots, delay circuit determines when DS1986 will sample data line. read data time slot, transmitted, delay circuit determines long DS1986 will hold data line overriding generated master. data "1", iButton will leave read data time slot unchanged.
PROGRAM PULSE
copy data from 8-bit scratchpad EPROM Data Status Memory, program pulse volts applied data line after master confirmed that current byte correct. During programming, master controls transition from state where data line idling high pull-up resistor state where data line actively driven programming voltage volts providing minimum current DS1986. This programming voltage (Figure should applied after which master returns data line idle high state controlled pull-up resistor. Note that high voltage programming requirements 1-Wire EPROM device, possible multi-drop non-EPROM based 1-Wire devices with DS1986 during programming. internal diode within non-EPROM based 1-Wire devices will attempt clamp data line approximately volts could potentially damage these devices.
INITIALIZATION PROCEDURE "RESET PRESENCE PULSES" Figure
RESISTOR MASTER DS1986
Regular Speed tRSTL tRSTH (includes recovery time) tPDH tPDL
Overdrive Speed tRSTL tRSTH tPDH tPDL
order mask interrupt signaling other devices 1-Wire bus, tRSTL should always less than
DS1986
READ/WRITE TIMING DIAGRAM Figure Write-one Time Slot
RESISTOR MASTER DS1986
Regular Speed tSLOT tLOW1 tREC
Overdrive Speed tSLOT tLOW1 tREC
Write-zero Time Slot
Regular Speed tLOW0 tSLOT <120 tREC
Overdrive Speed tLOW0 tSLOT tREC
DS1986
READ/WRITE TIMING DIAGRAM Figure (cont.) Read-data Time Slot
RESISTOR MASTER DS1986
Regular Speed tSLOT tLOWR tRELEASE tREC tRDV
Overdrive Speed tSLOT tLOWR tRELEASE tREC tRDV
PROGRAM PULSE TIMING DIAGRAM Figure
LINE TYPE LEGEND: master active high (12V Resistor pull-up
GENERATION
With DS1986 there different types CRCs (Cyclic Redundancy Checks). 8bit type stored most significant byte 64-bit ROM. master compute value from first bits 64-bit compare value stored within DS1986 determine data been received error-free master. equivalent polynomial function this This 8-bit received true (non-inverted) form when reading DS1986. computed once factory lasered into ROM.
DS1986
other 16-bit type, generated according standardized CRC16-polynomial function This used safeguard user-defined EPROM data when reading data memory status memory. same type used with NVRAM based iButtons safeguard data packets iButton File Structure. contrast 8-bit CRC, 16-bit always returned complemented (inverted) form. CRC-generator inside DS1986 chip (Figure will calculate 16-bit every situation shown command flow chart Figure DS1986 provides this CRC-value master validate transfer command, address, data from master. When reading data memory DS1986 with Read Memory command, 16-bit only transmitted memory reached. This generated clearing generator, shifting command, address, high address every data byte starting first addressed memory location continuing until implemented data memory reached. When reading status memory with Read Status command, 16-bit transmitted when each 8-byte page status memory reached. initial pass through Read Status flow chart 16-bit will generated clearing generator, shifting command byte, address, high address data bytes beginning first addressed memory location continuing until last byte addressed EPROM Status data page reached. Subsequent passes through Read Status flow chart will generate 16-bit that result clearing generator then shifting data bytes starting first byte next page EPROM Status data field continuing until last byte page reached. When reading data memory DS1986 with Extended Read Memory command, there situations where 16-bit transmitted. 16-bit follows each Redirection Byte, another 16bit received after last byte memory data page read. memory page always result clearing generator shifting data bytes beginning first addressed memory location EPROM data page until last byte this page. With initial pass through Extended Read Memory flow chart 16-bit value result shifting command byte into cleared generator, followed address bytes Redirection Byte. Subsequent passes through Extended Read Memory flow chart will generate 16-bit that result clearing generator then shifting Redirection Byte only. When writing DS1986 (either data memory status memory), master receives 16-bit verify correctness data transfer before applying programming pulse. With initial pass through Write Memory/Status flow chart 16-bit will generated clearing CRCgenerator, shifting command, address low, address high data byte. Subsequent passes through Write Memory/Status flow chart DS1986 automatically incrementing address counter will generate 16-bit that result loading (not shifting) (incremented) address into generator then shifting data byte. comparison values decision continue with operation determined entirely master. There circuitry DS1986 that prevents command sequence from proceeding stored calculated DS1986 does match value generated master. more details generating values including example implementations both hardware software, Book DS19xx iButton Standards.
DS1986
CRC-16 HARDWARE DESCRIPTION POLYNOMIAL Figure
POLYNOMIAL
DS1986
ABSOLUTE MAXIMUM RATINGS*
Voltage Relative Ground Operating Temperature Storage Temperature -0.5V +12.0V -40°C +85°C -55°C +125°C
This stress rating only functional operation device these other conditions outside those indicated operation sections this specification implied. Exposure absolute maximum rating conditions extended periods time affect reliability.
ELECTRICAL CHARACTERISTICS
PARAMETER Logic Logic Output Logic Output Logic High Input Load Current Operating Charge Programming Voltage SYMBOL -0.3
(VPUP =2.8V 6.0V; -40°C +85°C)
+0.8 12.0 UNITS NOTES 1,10
VPUP 11.5
CAPACITANCE
PARAMETER Data 1-Wire) SYMBOL CIN/OUT
25°C)
UNITS NOTES
ELECTRICAL CHARACTERISTICS REGULAR SPEED
PARAMETER Time Slot Write Time Write Time Read Data Valid Release Time Read Data Setup Recovery Time Reset Time High Reset Time Presence Detect High Presence Detect Delay Program Delay Verify Program Pulse Width Program Voltage Rise Time Program Voltage Fall Time SYMBOL tSLOT tLOW1 tLOW0 tRDV tRELEASE tREC tRSTH tRSTL tPDH tPDL
VPUP =2.8V 6.0V; -40°C +85°C)
UNITS NOTES
exactly
DS1986
ELECTRICAL CHARACTERISTICS OVERDRIVE SPEED
PARAMETER Time Slot Write Time Write Time Read Data Valid Release Time Read Data Setup Recovery Time Reset Time High Reset Time Presence Detect High Presence Detect SYMBOL tSLOT tLOW1 tLOW0 tRDV tRELEASE tREC tRSTH tRSTL tPDH tPDL
(VPUP =2.8V 6.0V; -40°C 70°C)
UNITS NOTES
exactly
NOTES:
voltages referenced ground. VPUP external pull-up voltage. Input load ground. additional reset communication sequence cannot begin until reset high time expired. Read data setup time refers time host must pull 1-Wire read bit. Data guaranteed valid within this falling edge. function external pull-up resistor VPUP nanocoulombs time slots 5.0V. =5.0V with pull-up maximum time slot Capacitance data could when power first applied. resistor used pull data line after power been applied parasite capacitance will affect normal communications. Under certain voltage conditions VILMAX have reduced much 0.5V always guarantee presence pulse.
DS1986
REVISION HISTORY
REVISION DATE 071508 DESCRIPTION Updated MicroCan MicroCan face brands with latest H020201. Added sign PART numbers Ordering Information table, indicating lead(Pb)-free/RoHS-compliant packages. Removed UL#913 bullet from Common iButton Features section. PAGES CHANGED
8/09
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DS1986 64Kb Add-Only iButton® 65536 bits Electrically Programmabl

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