DS1982 Add-Only iButton® www.maxim-ic.com 1024 bits Electric

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DS1982 Add-Only iButton® www.maxim-ic.com 1024 bits Electric

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19-4891; 8/09
DS1982 Add-Only iButton®
www.maxim-ic.com
1024 bits Electrically Programmable ReadOnly Memory (EPROM) communicates with economy signal plus ground EPROM partitioned into four 256-bit pages randomly accessing packetized data Each memory page permanently writeprotected prevent tampering Device "add only" memory where additional data programmed into EPROM without disturbing existing data Architecture allows software patch data superseding page favor newly programmed page Reduces control, address, data, power, programming signals single data 8-bit family code specifies DS1982 communications requirements reader Reads over wide voltage range 2.8V 6.0V from -40°C +85°C; programs 11.5V 12.0V from -40°C +50°C MicroCan MicroCan
COMMON iButton FEATURES
Unique, factory-lasered tested 64-bit registration number (8-bit family code 48-bit serial number 8-bit tester) assures absolute traceability because parts alike Multidrop controller MicroLAN Digital identification information momentary contact Chip-based data carrier compactly stores information Data accessed while affixed object Economically communicates master with single digital signal 16.3kbps Standard 16mm diameter 1-Wire® protocol ensure compatibility with iButton family Button shape self-aligning with cup-shaped probes Durable stainless steel case engraved with registration number withstands harsh environments Easily affixed with self-stick adhesive backing, latched flange, locked with ring pressed onto Presence detector acknowledges when reader first applies voltage
ORDERING INFORMATION
DS1982-F3+ DS1982-F5+
+Denotes lead(Pb)-free/RoHS-compliant product.
EXAMPLES ACCESSORIES
DS9096P DS9101 DS9093RA DS9093F DS9092 Self-Stick Adhesive Multi-Purpose Clip Mounting Lock Ring Snap-In iButton Probe
iButton 1-Wire registered trademarks Maxim Integrated Products, Inc.
MicroCan
MicroCan
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DS1982
iButton DESCRIPTION
DS1982 Add-Only iButton rugged read/write data carrier that identifies stores relevant information about product person which attached. This information accessed with minimal hardware, example, single port microcontroller. DS1982 consists factorylasered registration number that includes unique 48-bit serial number, 8-bit CRC, 8-bit Family Code (09h) plus EPROM that user-programmable. power program read DS1982 derived entirely from 1-Wire communication line. Data transferred serially 1-Wire protocol that requires only single data lead ground return. entire device programmed then write-protected desired. Alternatively, part programmed multiple times with data being appended overwriting, existing data with each subsequent programming device. Note: Individual bits changed only from logical logical never from logical logical provision also included indicating that certain page pages data longer valid have been replaced with updated data that residing alternate page address. This page address redirection allows software patch data enhance flexibility device standalone database. 48-bit serial number that factory-lasered into each DS1982 provides guaranteed unique identity that allows absolute traceability. durable MicroCan package highly resistant harsh environments such dirt, moisture, shock. compact button-shaped profile self-aligning with cup-shaped receptacles, allowing DS1982 used easily human operators automatic equipment. Accessories permit DS1982 mounted printed circuit boards, plastic fobs, photo-ID badges, bracelets, many other objects. Applications include work-in-progress tracking, electronic travelers, access control, storage calibration constants, debit tokens.
OVERVIEW
block diagram Figure shows relationships between major control memory sections DS1982. DS1982 three main data components: 64-bit lasered ROM, 1024-bit EPROM, EPROM Status Bytes. device derives power read operations entirely from 1-Wire communication line storing energy internal capacitor during periods time when signal line high continues operate this "parasite" power source during times 1-Wire line until returns high replenish parasite (capacitor) supply. During programming, 1-Wire communication occurs normal voltage levels then pulsed momentarily programming voltage cause selected EPROM bits programmed. 1-Wire line must able provide volts milliamperes adequately program EPROM portions part. Whenever programming voltages present 1-Wire line special high voltage detect circuit within DS1982 generates internal logic signal indicate this condition. hierarchical structure 1Wire protocol shown Figure master must first provide four function commands: Read ROM, Match ROM, Search ROM, Skip ROM. These commands operate 64-bit lasered portion each device singulate specific device many present 1-Wire line well indicate master many what types devices present. protocol required these function commands described Figure After function command successfully executed, memory functions that operate EPROM portions DS1982 become accessible master issue five memory function commands specific DS1982 read program various data fields. protocol these memory function commands described Figure data read written least significant first.
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DS1982
64-BIT LASERED
Each DS1982 contains unique code that bits long. first bits 1-Wire family code. next bits unique serial number. last bits first bits. (See Figure 64-bit Function Control section allow DS1982 operate 1-Wire device follow 1-Wire protocol detailed section "1-Wire System." memory functions required read program EPROM sections DS1982 accessible until function protocol been satisfied. This protocol described functions flow chart (Figure 1Wire master must first provide four function commands: Read ROM, Match ROM, Search ROM, Skip ROM. After function sequence been successfully executed, master then provide memory function commands specific DS1982 (Figure 1-Wire lasered generated using polynomial Additional information about Dallas Semiconductor 1-Wire Cyclic Redundancy Check available Book DS19xx iButton Standards. shift register acting accumulator initialized Then starting with least significant family code, time shifted After family code been entered, then serial number entered. After 48th serial number been entered, shift register contains value. Shifting bits should return shift register
DS1982
DS1982 BLOCK DIAGRAM Figure
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DS1982
HIERARCHICAL STRUCTURE 1-WIRE PROTOCOL Figure
MASTER OTHER DEVICES
1982 COMMAND LEVEL: AVAILABLE COMMANDS: DATA FIELD AFFECTED:
1-WIRE FUNCTION COMMANDS (SEE FIGURE
READ MATCH SEARCH SKIP
64-BIT 64-BIT 64-BIT
DS1982-SPECIFIC MEMORY FUNCTION COMMANDS (SEE FIGURE
WRITE MEMORY WRITE STATUS BYTE READ MEMORY READ STATUS BYTE READ DATA/GENERATE 8-BIT
1024-BIT EPROM EPROM STATUS BYTES 1024-BIT EPROM EPROM STATUS BYTES 1024-BIT EPROM
64-BIT LASERED Figure
8-Bit Code Serial Number Family Code (09h)
1-WIRE GENERATOR Figure
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DS1982
1024-BIT EPROM
memory Figure shows 1024-bit EPROM section DS1982 that configured four pages bytes each. 8-bit scratchpad additional register that acts buffer when programming memory. Data first written scratchpad then verified reading 8-bit from DS1982 that confirms proper receipt data. buffer contents correct, programming voltage should applied byte data will written into selected address memory. This process ensures data integrity when programming memory. details reading programming 1024-bit EPROM portion DS1982 given "Memory Function Commands" section.
EPROM STATUS BYTES
addition 1024 bits data memory DS1982 provides bits status memory accessible with separate commands. EPROM Status Bytes read programmed indicate various conditions software interrogating DS1982. first byte EPROM status memory contains Write-Protect Page bits that inhibit programming corresponding page 1024-bit main memory area appropriate write protection programmed. Once been programmed Write-Protect Page byte, entire 32-byte page that corresponds that longer altered still read. next bytes EPROM Status Memory contain Page Address Redirection Bytes that indicate more pages data 1024-bit EPROM section have been invalidated redirected page address contained appropriate redirection byte. hardware DS1982 makes decisions based contents Page Address Redirection Bytes. These additional bytes status EPROM allow redirection entire page another page address, indicating that data original page longer considered relevant valid. With EPROM technology, bits within page changed from logical logical programming, cannot changed back. Therefore, possible simply rewrite page data requires changing updating, with space permitting, entire page data redirected another page within DS1982 writing one's complement page address into Page Address Redirection Byte that corresponds original (replaced) page. This architecture allows user's software make "data patch" EPROM indicating that particular page pages should replaced with those indicated Page Address Redirection Bytes. Page Address Redirection Byte value, data main memory that corresponds that page valid. Page Address Redirection Byte some other value, data page corresponding that redirection byte invalid, valid data found one's complement page address indicated value stored associated Page Address Redirection Byte. value redirection byte page example, would indicate that updated data page details reading programming EPROM status memory portion DS1982 given Memory Function Commands section.
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DS1982
MEMORY FUNCTION COMMANDS
"Memory Function Flow Chart" (Figure describes protocols necessary accessing various data fields within DS1982. Memory Function Control section, 8-bit scratchpad, Program Voltage Detect circuit combine interpret commands issued master create correct control signals within device. 3-byte protocol issued master. comprised command byte determine type operation address bytes determine specific starting byte location within data field. command byte indicates device read written. Writing data involves only issuing correct command sequence also providing 12volt programming voltage appropriate times. execute write sequence, byte data first loaded into scratchpad then programmed into selected address. Write sequences always occur byte time. execute read sequence, starting address issued master data read from part beginning that initial location continuing selected data field until reset sequence issued. bits transferred DS1982 received back master sent least significant first.
DS1982 MEMORY Figure
8-BIT SCRATCHPAD STARTING ADDRESS 0000h 0020h 1024-BIT EPROM 0040h 0060h
PAGE BYTES PAGE BYTES PAGE BYTES PAGE BYTES
EPROM STATUS BYTES
ADDRESS: 0007h (MSB) 0006h 0005h 0004h 0003h 0002h 0001h 0000h (LSB)
WRITE PROTECT PAGE WRITE PROTECT PAGE WRITE PROTECT PAGE WRITE PROTECT PAGE BITMAP USED PAGES (RESERVED TMEX)
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DS1982
MEMORY FUNCTION FLOW CHART Figure
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DS1982
MEMORY FUNCTION FLOW CHART (cont'd) Figure
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DS1982
MEMORY FUNCTION FLOW CHART (cont'd) Figure
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DS1982
READ MEMORY [F0h]
Read Memory command used read data from 1024-bit EPROM data field. master follows command byte with 2-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates starting byte location within data field. 8-bit command byte address bytes computed DS1982 read back master confirm that correct command word starting address were received. read master incorrect, Reset Pulse must issued entire sequence must repeated. received master correct, master issues read time slots receives data from DS1982 starting initial address continuing until 1024-bit data field reached until Reset Pulse issued. reading occurs through memory space, master issue eight additional read time slots DS1982 will respond with 8-bit data bytes read from initial starting byte through last byte memory. After received master, subsequent read time slots will appear logical until Reset Pulse issued. reads ended Reset Pulse prior reaching memory will have 8-bit available. Typically 16-bit would stored with each page data ensure rapid, error-free data transfers that eliminate having read page multiple times determine received data correct not. (See Book DS19xx iButton Standards, Chapter recommended file structure used with 1-Wire environment.) values imbedded within data, Reset Pulse issued memory space during Read Memory command.
READ STATUS [AAh]
Read Status command used read data from EPROM Status data field. master follows command byte with two-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates starting byte location within data field. 8-bit command byte address bytes computed DS1982 read back master confirm that correct command word starting address were received. read master incorrect, Reset Pulse must issued entire sequence must repeated. received master correct, master issues read time slots receives data from DS1982 starting supplied address continuing until EPROM Status data field reached. that point master will receive 8-bit that result shifting into generator data bytes from initial starting byte through final factory-programmed byte that contains value. This feature provided since EPROM Status information change over time making impossible program data once include accompanying that will always valid. Therefore, Read Status command supplies 8-bit that based always consistent with current data stored EPROM Status data field. After 8-bit read, master will receive logical from DS1982 until Reset Pulse issued. Read Status command sequence exited point issuing Reset Pulse.
READ DATA/GENERATE 8-BIT [C3h]
Read Data/Generate 8-bit command used read data from 1024-bit EPROM memory field. master follows command byte with two-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates starting byte location within data field. 8-bit command byte address bytes computed DS1982 read back master confirm that correct command word starting address were received. read master incorrect, Reset Pulse must issued entire sequence must repeated. received master correct, master issues read time slots receives data from DS1982 starting
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DS1982
initial address continuing until 32-byte page reached. that point master will send eight additional read time slots receive 8-bit that result shifting into generator data bytes from initial starting byte last byte current page. Once 8-bit been received, data again read from 1024-bit EPROM data field starting next page. This sequence will continue until final page accompanying read master. Thus each page data considered bytes long, bytes user-programmed EPROM data 8-bit that gets generated automatically each page. This type read differs from Read Memory command that simply reads each page until address space reached. Read Memory command only generates 8-bit memory space that often might ignored, since many applications user would store 16-bit with data itself each page 1024-bit EPROM data field time page programmed. Read Data/Generate 8-bit command provides alternate read capability applications that "bit-oriented" rather than "page-oriented" where 1024-bit EPROM information change over time within page boundary, making impossible program page once include accompanying that will always valid. Therefore, Read Data/Generate 8-Bit command concludes each page with DS1982 generating supplying 8-bit that based therefore always consistent with current data stored each page 1024-bit EPROM data field. After 8-bit last page read, master will receive logical from DS1982 until Reset Pulse issued. Read Data/Generate 8-Bit command sequence exited point issuing Reset Pulse.
WRITE MEMORY [0Fh]
Write Memory command used program 1024-bit EPROM data field. master will follow command byte with byte starting address (TA1=(T7:T0), TA2=(T15:T8)) byte data (D7:D0). 8-bit command byte, address bytes, data byte computed DS1982 read back master confirm that correct command word, starting address, data byte were received. highest starting address within DS1982 007FH. master sends starting address higher than this, nine most significant address bits internal circuitry chip. This will result mismatch between calculated DS1982 calculated master, indicating error condition. read master incorrect, Reset Pulse must issued entire sequence must repeated. received master correct, programming pulse volts 1Wire issued master. Prior programming, entire unprogrammed 1024-bit EPROM data field will appear logical each data byte provided master that logical corresponding selected byte 1024-bit EPROM will programmed logical after programming pulse been applied that byte location. After programming pulse applied data line returns 5-volt level, master issues eight read time slots verify that appropriate bits have been programmed. DS1982 responds with data from selected EPROM address sent least significant first. This byte contains logical bytes written this EPROM data address. EPROM data byte contains positions where byte issued master contains Reset Pulse should issued current byte address should programmed again. DS1982 EPROM data byte contains same positions data byte, programming successful DS1982 will automatically increment address counter select next byte 1024-bit EPROM data field. least
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DS1982
significant byte 2-byte address will also loaded into 8-bit generator starting value. master will issue next byte data using eight write time slots. DS1982 receives this byte data into scratchpad, also shifts data into generator that been preloaded with current address, result 8-bit data byte address. After supplying data byte, master will read this 8-bit from DS1982 with eight read time slots confirm that address incremented properly data byte received correctly. incorrect, Reset Pulse must issued Write Memory command sequence must restarted. correct, master will issue programming pulse selected byte memory will programmed. Note that initial pass through Write Memory flow chart will generate 8-bit value that result shifting command byte into generator, followed address bytes, finally data byte. Subsequent passes through Write Memory flow chart DS1982 automatically incrementing address counter will generate 8-bit that result loading (not shifting) (incremented) address into generator then shifting data byte. both these cases, decision continue apply program pulse DS1982) made entirely master, since DS1982 will able determine 8-bit calculated master agrees with 8-bit calculated DS1982. incorrect ignored program pulse applied master, incorrect programming could occur within DS1982. Also note that DS1982 will always increment internal address counter after receipt eight read time slots used confirm programming selected EPROM byte. decision continue again made entirely master; therefore EPROM data byte does match supplied data byte master continues with Write Memory command, incorrect programming could occur within DS1982. Write Memory command sequence exited point issuing Reset Pulse.
WRITE STATUS [55h]
Write Status command used program EPROM Status data field. master will follow command byte with 2-byte starting address (TA1=(T7:T0), TA2=(T15:T8)) byte status data (D7:D0). 8-bit command byte, address bytes, data byte computed DS1982 read back master confirm that correct command word, starting address, data byte were received. read master incorrect, Reset Pulse must issued entire sequence must repeated. received master correct, programming pulse volts 1Wire issued master. Prior programming, first bytes EPROM Status data field will appear logical each data byte provided master that logical corresponding selected byte EPROM Status data field will programmed logical after programming pulse been applied that byte location. byte EPROM status byte data field factory-programmed contain 00h. After programming pulse applied data line returns 5-volt level, master issues eight read time slots verify that appropriate bits have been programmed. DS1982 responds with data from selected EPROM Status address sent least significant first. This byte contains logical bytes written this EPROM Status Byte address. EPROM Status Byte contains positions where byte issued master contained Reset Pulse should issued current byte address should programmed again. DS1982 EPROM Status Byte
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DS1982
contains same positions data byte, programming successful DS1982 will automatically increment address counter select next byte EPROM Status data field. least significant byte 2-byte address will also loaded into 8-bit generator starting value. master will issue next byte data using eight write time slots. DS1982 receives this byte data into scratchpad, also shifts data into generator that been preloaded with current address result 8-bit data byte address. After supplying data byte, master will read this 8-bit from DS1982 with eight read time slots confirm that address incremented properly data byte received correctly. incorrect, Reset Pulse must issued Write Status command sequence must restarted. correct, master will issue programming pulse selected byte memory will programmed. Note that initial pass through Write Status flow chart will generate 8-bit value that result shifting command byte into generator, followed address bytes, finally data byte. Subsequent passes through Write Status flow chart DS1982 automatically incrementing address counter will generate 8-bit that result loading (not shifting) (incremented) address into generator then shifting data byte. both these cases, decision continue apply program pulse DS1982) made entirely master, since DS1982 will able determine 8-bit calculated master agrees with 8-bit calculated DS1982. incorrect ignored program pulse applied master, incorrect programming could occur within DS1982. Also note that DS1982 will always increment internal address counter after receipt eight read time slots used confirm programming selected EPROM byte. decision continue again made entirely master, therefore EPROM data byte does match supplied data byte master continues with Write Status command, incorrect programming could occur within DS1982. Write Status command sequence ended point issuing Reset Pulse.
1-WIRE SYSTEM
1-Wire system which single master more slaves. instances, DS1982 slave device. master typically microcontroller. discussion this system broken down into three topics: hardware configuration, transaction sequence, 1-Wire signaling (signal type timing). 1-Wire protocol defines transactions terms state during specified time slots that initiated falling edge sync pulses from master. more detailed protocol description, refer Chapter Book DS19xx iButton Standards.
Hardware Configuration
1-Wire only single line definition; important that each device able drive appropriate time. facilitate this, each device attached 1-Wire must have open drain connection 3-state outputs. DS1982 open drain part with internal circuit equivalent that shown Figure master same equivalent circuit. bidirectional available, separate output input pins tied together. master requires pullup resistor master bus, with master circuit equivalent shown Figures value pullup resistor should approximately kfor short line lengths.
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DS1982
multidrop consists 1-Wire with multiple slaves attached. 1-Wire maximum data rate 16.3kbps. master also required perform programming EPROM portions DS1982, programming supply capable delivering milliamps volts required. idle state 1-Wire high. reason, transaction needs suspended, MUST left idle state transaction resume. this does occur left more than more devices reset.
TRANSACTION SEQUENCE
sequence accessing DS1982 1-Wire port follows: Initialization Function Command Memory Function Command Read/Write Memory/Status
INITIALIZATION
transactions 1-Wire begin with initialization sequence. initialization sequence consists Reset Pulse transmitted master followed presence pulse(s) transmitted slave(s). presence pulse lets master know that DS1982 ready operate. more details, "1-Wire Signaling" section.
FUNCTION COMMANDS
Once master detected presence, issue four function commands. function commands bits long. list these commands follows (refer flowchart Figure
Read [33h]
This command allows master read DS1982's 8-bit family code, unique 48-bit serial number, 8-bit CRC. This command used only there single DS1982 bus. more than slave present bus, data collision will occur when slaves transmit same time (open drain will produce wired-AND result).
Match [55h]
match command, followed 64-bit sequence, allows master address specific DS1982 multidrop bus. Only DS1982 that exactly matches 64-bit sequence will respond subsequent memory function command. slaves that match 64-bit sequence will wait Reset Pulse. This command used with single multiple devices bus.
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DS1982
DS1982 EQUIVALENT CIRCUIT Figure
MASTER CIRCUIT Figure
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DS1982
FUNCTIONS FLOW CHART Figure
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DS1982
Skip [CCh]
This command save time single-drop system allowing master access memory functions without providing 64-bit code. more than slave present read command issued following Skip command, data collision will occur multiple slaves transmit simultaneously (open drain pull-downs will produce wired-AND result).
Search [F0h]
When system initially brought master might know number devices 1Wire their 64-bit codes. search command allows master process elimination identify 64-bit codes slave devices bus. search process repetition simple, three-step routine: read bit, read complement bit, then write desired value that bit. master performs this simple, three-step routine each ROM. After complete pass, master knows contents device. remaining number devices their codes identified additional passes. Chapter Book DS19xx iButton Standards comprehensive discussion search, including actual example.
1-Wire Signaling
DS1982 requires strict protocols ensure data integrity. protocol consists five types signaling line: Reset Sequence with Reset Pulse Presence Pulse, Write Write Read Data Program Pulse. these signals except presence pulse initiated master. initialization sequence required begin communication with DS1982 shown Figure Reset Pulse followed presence pulse indicates DS1982 ready accept command. master transmits (TX) Reset Pulse (tRSTL minimum master then releases line goes into receive mode (RX). 1-Wire pulled high state pullup resistor. After detecting rising edge 1-Wire line, DS1982 waits (tPDH 15-60 then transmits presence pulse (tPDL 60-240
Read/Write Time Slots
definitions write read time slots illustrated Figure time slots initiated master driving data line low. falling edge data line synchronizes DS1982 master triggering delay circuit DS1982. During write time slots, delay circuit determines when DS1982 will sample data line. read data time slot, transmitted, delay circuit determines long DS1982 will hold data line overriding generated master. data device will leave read data time slot unchanged.
PROGRAM PULSE
copy data from 8-bit scratchpad EPROM Data Status Memory, program pulse volts applied data line after master confirmed that current byte correct. During programming, master controls transition from state where data line idling high pullup resistor state where data line actively driven programming voltage volts providing minimum current DS1982. This programming voltage (Figure should applied after which master returns data line idle high state controlled pullup resistor. Note that high voltage programming requirements 1-Wire EPROM device, possible multidrop non-EPROM based 1-Wire devices with DS1982 during programming. internal diode within non-EPROM based 1-Wire devices will attempt clamp data line approximately volts could potentially damage these devices.
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DS1982
GENERATION
DS1982 8-bit stored most significant byte 64-bit ROM. master compute value from first bits 64-bit compare value stored within DS1982 determine data been received error-free master. equivalent polynomial function this Under certain conditions, DS1982 also generates 8-bit value using same polynomial function shown above provides this value master validate transfer command, address, data bytes from master DS1982. Memory Function Flow Chart Figure indicates that DS1982 computes 8-bit command, address, data bytes received Write Memory Write Status commands then outputs this value master confirm proper transfer. Similarly DS1982 computes 8-bit command address bytes received from master Read Memory, Read Status, Read Data/Generate 8-Bit commands confirm that these bytes have been received correctly. generator DS1982 also used provide verification error-free data transfer each page data from 1024bit EPROM sent master during Read Data/Generate 8-bit command, bytes information status memory field. each case where used data transfer validation, master must calculate value using polynomial function given above compare calculated value either 8-bit value stored 64-bit portion DS1982 (for reads) 8-bit value computed within DS1982. comparison values decision continue with operation determined entirely master. There circuitry DS1982 that prevents command sequence from proceeding stored calculated DS1982 does match value generated master. Proper outlined flow chart Figure result communication channel with very high level integrity. more details generating values including example implementations both hardware software, Book DS19xx iButton Standards.
INITIALIZATION PROCEDURE "RESET PRESENCE PULSES" Figure
MASTER "RESET PULSE" MASTER "RESET PULSE"
RESISTOR MASTER DS1982
tRSTL tRSTH (includes recovery time) tPDH tPDL
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order mask interrupt signaling other devices 1-Wire bus, tRSTL should always less than
DS1982
READ/WRITE TIMING DIAGRAM Figure Write-1 Time Slot
tSLOT tLOW1 tREC
Write-0 Time Slot
RESISTOR MASTER DS1982
tLOW0 tSLOT tREC
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Read-data Time Slot
RESISTOR MASTER DS1982
tSLOT tLOWR tRELEASE tREC tRDV
PROGRAM PULSE TIMING DIAGRAM Figure
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DS1982
ABSOLUTE MAXIMUM RATINGS*
Voltage Relative Ground Operating Temperature Storage Temperature -0.5V +12.0V -40°C +85°C -55°C +125°C
This stress rating only functional operation device these other conditions outside those indicated operation sections this specification implied. Exposure absolute maximum rating conditions extended periods time affect reliability.
ELECTRICAL CHARACTERISTICS
PARAMETER Logic Logic Output Logic Output Logic High Input Load Current Operating Charge Programming Voltage SYMBOL -0.3
(VPUP=2.8V 6.0V; -40C +85C)
+0.8 12.0 UNITS NOTES
VPUP 11.5
CAPACITANCE
PARAMETER Data (1-Wire) SYMBOL CIN/OUT
25C)
UNITS NOTES
ELECTRICAL CHARACTERISTICS
PARAMETER Time Slot Write Time Write Time Read Data Valid Release Time Read Data Setup Recovery Time Reset Time High Reset Time Presence Detect High Presence Detect Delay Program Delay Verify Program Pulse Width Program Voltage Rise Time Program Voltage Fall Time SYMBOL tSLOT tLOW1 tLOW0 tRDV tRELEASE tREC tRSTH tRSTL tPDHIGH tPDLOW
(VPUP=2.8V 6.0V; -40C +85C)
UNITS NOTES
exactly
5000
10,12
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DS1982
NOTES:
voltages referenced ground. VPUP external pullup voltage. Input load ground. additional reset communication sequence cannot begin until reset high time expired. Read data setup time refers time host must pull 1-Wire read bit. Data guaranteed valid within this falling edge will remain valid minimum. total from falling edge 1-Wire bus.) function external pullup resistor pullup voltage. nanocoulombs time slots 5.0V. =5.0V with pullup maximum time slot Capacitance data could when power first applied. resistor used pull data line after power been applied parasite capacitance will affect normal communications. Maximum 1-Wire voltage programming parameters 11.5V 12.0V; temperature range -40°C +50°C. Under certain voltage conditions VILMAX have reduced much 0.5V always guarantee presence pulse. accumulative duration programming pulses each address must exceed
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DS1982
REVISION HISTORY
REVISION DATE 7/08 8/09 DESCRIPTION Updated MicroCan MicroCan face brands with latest H020201. Added plus signs Ordering Information reflect conversion lead-free product. Deleted bullet from Features section. PAGES CHANGED
Maxim/Dallas Semiconductor cannot assume responsibility circuitry other than circuitry entirely embodied Maxim/Dallas Semiconductor product. circuit patent licenses implied. Maxim/Dallas Semiconductor reserves right change circuitry specifications without notice time.
Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600
2009 Maxim Integrated Products
Maxim logo registered trademark Maxim Integrated Products, Inc. Dallas logo registered trademark Dallas Semiconductor Corporation.

DS1982 Add-Only iButton® www.maxim-ic.com 1024 bits Electric

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