DS1977 Password-Protected 32KB EEPROM iButton iButton DESCRI

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DS1977 Password-Protected 32KB EEPROM iButton iButton DESCRI

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19-4890; 8/09
DS1977
Password-Protected 32KB EEPROM iButton
iButton DESCRIPTION
DS1977 32KB EEPROM rugged, iButton® enclosure. Access memory password-protected with different passwords read-only full access. Data transferred serially through 1-Wire® protocol, which requires only single data lead ground return. Every DS1977 factory lasered with guaranteed unique 64-bit registration number that allows absolute traceability. durable stainless-steel iButton package highly resistant environmental hazards such dirt, moisture, shock. Accessories permit DS1977 iButton mounted almost object, including containers, pallets, bags.
SPECIAL FEATURES
32KB EEPROM Organized Pages Bytes Each Optional Password Protection with Different 64Bit Passwords Read Full Access Communicates Host with Single Digital Signal 15.3kbps Standard Speed 125kbps Overdrive Mode Using 1-Wire Protocol Operating Range: 2.8V 5.25V, -40C +85C Minimum 100k Write Cycles Endurance 15kV Built-in Protection Unique Factory-Lasered 64-Bit Registration Number Assures Error-Free Device Selection Absolute Traceability Because Parts Alike Built-In Multidrop Controller 1-Wire Chip-Based Data Carrier Stores Digital Identification Information, Armored Durable Stainless-Steel Case Data Accessed While Affixed Object Button Shape Self-Aligning with Cup-Shaped Probes Easily Affixed with Self-Stick Adhesive Backing, Latched Flange, Locked with Ring Pressed onto Presence Detector Acknowledges when Reader First Applies Voltage
COMMON iButton FEATURES
APPLICATIONS
Maintenance/Inspection Data Storage Medical Data Carrier Health Data Carrier Audit Data Storage Carrier
MicroCAN
5.89 0.51 16.25
000000FBC52B
1-Wire
17.35
ORDERING INFORMATION
PART DS1977-F5# TEMP RANGE -40C +85C PIN-PACKAGE iButton
Denotes RoHS-compliant device that include lead(Pb) that exempt under RoHS requirements.
EXAMPLES ACCESSORIES
PART DS9096P DS9101 DS9093RA DS9093A DS9092 DESCRIPTION Self-Stick Adhesive Multipurpose Clip Mounting Lock Ring Snap-In iButton Probe
dimensions shown millimeters.
iButton 1-Wire registered trademarks Maxim Integrated Products, Inc.
DS1977
PHYSICAL SPECIFICATION
Size Weight DS1977 mechanical drawing 3.3g
ABSOLUTE MAXIMUM RATINGS
Voltage Sink Current Junction Temperature Storage Temperature Range -0.3V, +5.5V 20mA +150°C -40°C +85°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device.
ELECTRICAL CHARACTERISTICS
(VPUP 2.8V 5.25V, -40°C +85°C.) PARAMETER SYMBOL CONDITIONS General Data 1-Wire Pullup (Notes RPUP Resistance Input Capacitance (Note Input Load Current VPUP High-to-Low Switching (Notes Threshold Input Voltage (Notes Low-to-High Switching (Notes Threshold Switching Hysteresis (Note Output-Low Voltage (Note Standard speed, RPUP= 2.2k (Note Overdrive speed, RPUP= 2.2k Recovery Time tREC (Note Overdrive speed, directly prior reset pulse; RPUP= 2.2k (Note Rising-Edge Hold-off Standard speed (Note tREH Time Overdrive speed (Note Standard speed (Note Timeslot Duration tSLOT Overdrive speed (Note Pin, 1-Wire Reset, Presence Detect Cycle Standard speed (Note Reset Time tRSTL Overdrive Speed (Note Presence Detect High Standard speed (Note tPDH Time Overdrive speed (Note Standard speed, VPUP 4.5V (Note Presence Detect Fall tFPD Time Standard speed (Note Overdrive speed (Note Presence Detect Standard speed tPDL Time Overdrive speed 0.30 0.15 0.15 UNITS
DS1977 PARAMETER Presence Detect Sample Time Pin, 1-Wire Write Write-0 Time Write-1 Time Pin, 1-Wire Read Read Time Standard speed (Notes Overdrive speed (Notes Standard speed, VPUP 4.5V (Notes Standard speed (Notes Overdrive speed (Notes (Note (Note (Note 2.64 22.46 0.62 100k tW0L tW1L Standard speed (Note Overdrive speed (Note Standard speed (Notes Overdrive speed (Notes SYMBOL tMSP CONDITIONS Standard speed, VPUP 4.5V (Note Standard speed (Note Overdrive speed (Note 10.5 UNITS
Read Sample Time Pin, Strong Pullup Strong Pullup Read Strong Pullup Write Strong Pullup password verification EEPROM Programming Current Write/Erase Cycles Data Retention
Note Note
tMSR
tSPUR tSPUW tSPUV ILPROG NCYCLE tRET
years
Note Note Note Note Note Note Note Note Note Note Note Note
System requirement. Maximum allowable pullup resistance function number 1-Wire devices system 1-Wire recovery times. specified value here applies systems with only device with minimum 1-Wire recovery times. more heavily loaded systems, active pullup such that found DS2480 required. Capacitance data could when power first applied. VTL, function internal supply voltage. Voltage below which, during falling edge I/O, logic detected. voltage needs less equal VILMAX whenever master drives line low. Voltage above which, during rising edge I/O, logic detected. After crossed during rising edge I/O, voltage drop detected logic '0'. characteristic linear voltages less than earliest recognition negative edge possible tREH after been reached before. Highlighted numbers compliance with published iButton standards. comparison table below. Interval during negative edge beginning Presence Detect pulse between time which voltage VPUP time which voltage VPUP. represents time required pullup circuitry pull voltage from VTH. represents time required pullup circuitry pull voltage from input-high threshold master.
Parameter Name tSLOT (incl. tREC) tRSTL tPDH tPDL tW0L
Standard Values Standard Speed Overdrive Speed 61µs (undef.) (undef.) 480µs (undef.) 48µs 80µs 15µs 60µs 60µs 240µs 24µs 60µs 120µs 16µs
DS1977 Values Standard Speed Overdrive Speed 65µs1) (undef.) 8µs1) (undef.) 480µs 640µs 48µs 80µs 15µs 60µs 2.5µs 6.5µs 60µs 240µs 24µs 60µs 120µs 16µs
Intentional change, longer recovery time requirement modified 1-Wire front end.
DS1977
APPLICATION
DS1977 ideal device store maintenance inspection data equipment medical- healthrelated data digitally readable format. small size rugged enclosure device carried with keyring provide critical data case emergency. DS1977 also serve data shuttle transport fleet management vending machine data access point upload into remote server further processing. Software communication with DS1977 available free download from iButton website.
OVERVIEW
block diagram Figure shows relationships between major control memory sections DS1977. device four main data components: 64-bit lasered ROM, 512-bit scratchpad buffer, 32KB EEPROM, password buffers. passwords only written verified, never read. hierarchical structure 1-Wire protocol shown Figure master must first provide seven function commands: Read ROM, Match ROM, Search ROM, Skip ROM, Overdrive-Skip ROM, Overdrive-Match Resume. Upon completion Overdrive command byte executed standard speed, device will enter Overdrive mode, where subsequent communication occurs higher speed. protocol required these function commands described Figure After function command successfully executed, memory control functions become accessible master provide available commands. protocol these memory control function commands described Figure data read written least significant first.
Figure DS1977 BLOCK DIAGRAM
POWER CONTROL FUNCTION CONTROL 64-BIT LASERED
CRC16 GENERATOR
MEMORY FUNCTION CONTROL
64-BYTE SCRATCHPAD BUFFER
MEMORY ACCESS SECURITY CONTROL
32KB EEPROM
DS1977
Figure HIERARCHICAL STRUCTURE 1-WIRE PROTOCOL
MASTER 1-Wire OTHER DEVICES
DS1977 COMMAND LEVEL: AVAILABLE COMMANDS:
READ MATCH SEARCH SKIP RESUME OVERDRIVE SKIP OVERDRIVE MATCH WRITE SCRATCHPAD READ SCRATCHPAD COPY SCRATCHPAD W/PW READ MEMORY W/PW VERIFY PASSWORD READ VERSION
DATA FIELD AFFECTED:
64-BIT ROM, RC-FLAG 64-BIT ROM, RC-FLAG 64-BIT ROM, RC-FLAG RC-FLAG RC-FLAG RC-FLAG, OD-FLAG 64-BIT ROM, RC-FLAG, OD-FLAG 64-BYTE SCRATCHPAD 64-BYTE SCRATCHPAD DATA MEMORY, PASSWORDS, PASSWORD ENABLE BYTE DATA MEMORY, PASSWORDS, PASSWORD ENABLE BYTE PASSWORDS VERSION REGISTER
1-Wire FUNCTION COMMANDS
DS1977-SPECIFIC MEMORY FUNCTION COMMANDS
64-BIT LASERED
Each DS1977 contains unique code that bits long. first bits 1-Wire family code. next bits unique serial number. last bits first bits. Figure details. 1Wire generated using polynomial generator consisting Shift gates shown Figure polynomial Additional information about 1-Wire Cyclic Redundancy Check available Application Note Book DS19xx iButton Standards. Shift register bits initialized Then starting with least significant family code, time shifted After family code been entered, then serial number entered. After 48th serial number been entered, Shift register contains value. Shifting bits returns Shift register
Figure 64-BIT LASERED
8-BIT CODE 48-BIT SERIAL NUMBER 8-BIT FAMILY CODE (37h)
DS1977
Figure 1-WIRE GENERATOR
POLYNOMIAL
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
INPUT DATA
MEMORY
memory DS1977 shown Figure 32KB general-purpose EEPROM located pages through 510. passwords Password Control register take bytes page 511. remaining bytes page accessible user. scratchpad additional page that acts buffer when writing EEPROM memory setting password, when reading from EEPROM.
Figure DS1977 MEMORY
64-Byte Intermediate Storage Scratchpad ADDRESS 0000h 003Fh 0040h 7F7Fh 7F80h 7FBFh 7FC0h 7FC7h 7FC8h 7FCFh 7FD0h 7FD1h 7FFFh
64-Byte User EEPROM 64-Byte User EEPROM 64-Byte User EEPROM Read Access Password Full Access Password Password Control Register Function; Will Read FFh, Cannot Written)
Page Pages Page
SECURITY PASSWORD
DS1977 designed passwords that control read access full access. password applies when reading from writing scratchpad. Setting password enabling/disabling password checking done same writing data memory location, only address different. Since they located same memory page, both passwords redefined same time. Before changing passwords, disable passwords. When setting password, make sure that bytes password defined. Otherwise password unknown. Always verify scratchpad before issuing copy scratchpad command. After password successfully copied from scratchpad memory location, erase scratchpad filling with data. Otherwise copy password will remain accessible through scratchpad until DS1977 disconnected from 1-Wire line undergoes power-on reset.
DS1977
Read Access Password
This password only applies function "Read Memory with Password". passwords enabled (EPW AAh, Password Control register), 64-bit data pattern that 1-Wire master transmit with command flow compared passwords stored DS1977 iButton. DS1977 delivers requested data only password transmitted master correct password checking enabled.
Read Access Password Register
ADDR 7FC0h 7FC1h RP15 RP14 RP13 RP12 RP11 RP10 7FC6h RP55 RP54 RP53 RP52 RP51 RP50 RP49 RP48 7FC7h RP63 RP62 RP61 RP60 RP59 RP58 RP57 RP56 There only write access this register. Read Access Password needs transmitted exactly sequence RP0, RP1. RP62, RP63.
Full Access Password
This password applies functions "Read Memory with Password" "Copy Scratchpad with Password". passwords enabled (EPW AAh, Password Control register), 64-bit data pattern that 1-Wire master transmit with command flow compared passwords stored DS1977 iButton. DS1977 executes command only password transmitted master correct password checking enabled.
Full Access Password Register
ADDR 7FC8h 7FC9h FP15 FP14 FP13 FP12 FP11 FP10 7FCEh FP55 FP54 FP53 FP52 FP51 FP50 FP49 FP48 7FCFh FP63 FP62 FP61 FP60 FP59 FP58 FP57 FP56 There only write access this register. Full Access Password needs transmitted exactly sequence FP0, FP1. FP62, FP63.
Password Control Register
data pattern stored Password Control Register determines whether password checking enabled. password checking enabled, password transmitted compared passwords stored device. Reading from writing scratchpad does require password.
Password Control Register Bitmap
ADDR 7FD0h
Register Details
DESCRIPTION EPW: Enable Passwords BIT(S) DEFINITION This byte enables disables password protection, which applies reading from writing memory except scratchpad. bits form pattern 10101010 (AAh), device will execute these commands only correct password transmitted. default pattern different from AAh.
enable password checking, bits need form binary pattern 10101010 (AAh). pattern different from AAh, password will accepted, long length exactly bits. Before enabling
DS1977 passwords, check whether password been successfully installed. Verify Password command details. Once enabled, changing passwords disabling password checking requires knowledge current full-access password.
VERSION REGISTER
DS1977 includes read-only Version register, which component memory map. Therefore, special command used read this register. Chip Revision number enables application software automatically appropriate software driver case different logical behavior.
Version Register Bitmap
VER2 VER1 VER0 Bits have function. They always read
Register Details
DESCRIPTION (N/A) VER: Chip Revision Indicator BIT(S) These bits Chip revision code. initial version DS1977 will have revision bits DEFINITION
Figure ADDRESS REGISTERS
Target Address (TA1)
Target Address (TA2) Ending Address with Data Status (E/S) (Read Only)
ADDRESS REGISTERS TRANSFER STATUS
Because serial data transfer, DS1977 employs three address registers, called TA1, TA2, (Figure Registers must loaded with target address which data will written from which data will sent master upon Read command. Register acts like byte counter Transfer Status register. used verify data integrity with write commands. Therefore, master only read access this register. lower bits register indicate address last byte that been written scratchpad. This address called Ending Offset. register, called number data bits sent master integer multiple data scratchpad valid loss power. valid write scratchpad will clear bit. Note that lowest bits target address also determine address within scratchpad, where intermediate storage data will begin. This address called byte offset. target address Write command 103Ch example, then scratchpad will store incoming data beginning byte offset will full after only four bytes. corresponding ending offset this example 3Fh. best economy speed efficiency, target address writing should point beginning page, i.e., byte offset will Thus full 64-byte capacity scratchpad available, resulting also ending offset 3Fh. However, possible write several contiguous bytes somewhere within page. ending offset together with Partial Flag support master checking data integrity after Write command. highest valued register, called valid only flag reads copy taken place. cleared when device receives write scratchpad command.
DS1977
WRITING WITH VERIFICATION
write data DS1977 scratchpad used intermediate storage. First master issues Write Scratchpad command specify desired target address, followed data written scratchpad. Under certain conditions (see Write Scratchpad command) master will receive inverted CRC16 command, address data write scratchpad command sequence. Knowing this value, master compare value calculated itself decide whether communication successful proceed Copy Scratchpad command. master could receive CRC16, send Read Scratchpad command read back scratchpad verify data integrity. preamble scratchpad data, DS1977 repeats target address sends contents register. flag set, data arrive correctly scratchpad there loss power since data last written scratchpad. master does need continue reading; start trial write data scratchpad. Similarly, flag together with cleared flag indicates that Write command recognized device. everything went correctly, both flags cleared ending offset indicates address last byte written scratchpad; master continue reading verifying every data byte. After master verified data, send Copy Scratchpad command. This command must followed exactly data three address registers TA1, TA2, E/S. master obtain contents these registers reading scratchpad derive from target address amount data written. soon DS1977 received these bytes correctly master provided acceptable password, DS1977 will copy scratchpad data requested location beginning target address.
MEMORY FUNCTION COMMANDS
"Memory Function Flow Chart" (Figure describes protocols necessary accessing memory special function registers DS1977. Examples these functions operate DS1977 included this document, preceding Electrical Characteristics section. communication between master DS1977 takes place either standard speed (default, Overdrive Speed explicitly into Overdrive mode DS1977 assumes regular speed.
Write Scratchpad Command [0Fh]
This command used specify target address write data scratchpad verification before transfer EEPROM initiated. After issuing write scratchpad command, master must first provide 2-byte target address, followed data written scratchpad. data will written scratchpad starting byte offset (T5:T0). ending offset (E5: will byte offset which master stops writing data. Only full data bytes accepted. last data byte incomplete content will ignored partial byte flag will set. When writing password address, internal circuitry chip will force least significant address bits Only full 8-byte passwords accepted. ending offset will depending password(s) changed. When executing Write Scratchpad command generator inside DS1977 (Figure calculates inverted over entire data stream, starting command code ending last data byte sent master. This generated using CRC16 polynomial first clearing generator then shifting command code (0FH) Write Scratchpad command, Target Addresses supplied master data bytes. master Write Scratchpad command time. However, ending offset 3Fh, master send read-time slots will receive generated DS1977 memory address range DS1977 0000h 7FFFh (Figure There user-access address range 7FD1h 7FFFh. master sends target address higher than this, internal circuitry chip will most significant address zero shifted into internal address register. Read Scratchpad command will reveal target address will used DS1977 master will identify such address modifications comparing target address read back target address transmitted. master does read scratchpad, subsequent copy scratchpad command will work since most significant bits target address master sends will match value DS1977 expects.
Read Scratchpad Command [AAh]
This command used verify scratchpad data target address. After issuing Read Scratchpad command, master begins reading. first bytes will target address. next byte will ending offset/data status byte (E/S) followed scratchpad data beginning byte offset (T5:T0), shown Figure
DS1977 Regardless actual ending offset master continue reading data until scratchpad after which will receive inverted CRC16 command code, Target Addresses TA2, byte, scratchpad data starting byte offset, which determined target address. After read, master will read logical from DS1977 until reset pulse issued.
Copy Scratchpad with Password [99h]
This command used transfer data from scratchpad memory. After issuing copy scratchpad command, master must provide 3-byte authorization pattern, which obtained reading scratchpad verification. This pattern must exactly match data contained three address registers (TA1, TA2, E/S, that order). Next master must send valid full-access password, passwords enabled, dummy bytes. master must provide power bypassing 1-Wire pullup resistor with electronic switch, generating "strong pullup". authorization pattern password accepted, (Authorization Accepted) flag will copy will begin. Copy takes 10ms maximum during which voltage 1Wire must fall below 2.8V. After copy completed, master turns strong pullup begins reading from 1-Wire. pattern alternating will indicate that copy command executed successfully. copy command disturbed lack power other reasons (see Figure 7-2, "strong pullup valid?"), master will read constant stream bytes until sends 1-Wire reset pulse. this case destination memory incompletely programmed requiring write scratchpad copy scratchpad repeated ensure proper programming EEPROM. This requires careful consideration when designing application software that writes DS1977 intermittent contact environment. data copied determined three address registers (TA1, TA2, E/S). scratchpad data from beginning offset through ending offset will copied memory, starting target address. Anywhere from bytes copied memory with this command.
Read Memory with Password [69h]
This command used read entire memory, except passwords. After issuing command, master must provide 2-byte target address. Next master must send valid read access password, passwords enabled, dummy bytes. master must provide power bypassing 1-Wire pullup resistor with electronic switch, generating "strong pullup". password accepted, EEPROM data beginning specified target address ending page boundary will loaded into scratchpad starting beginning offset. This transfer takes maximum during which voltage 1-Wire must fall below 2.8V. After transfer completed, master turns strong pullup begins reading from 1-Wire. When memory page (end scratchpad) reached, master will receive inverted CRC16 command, target address page data. master wants read more data memory reached, again activate strong pullup. This will transfer full 64-byte page memory data scratchpad from where master read issuing read-time slots. This transfer only takes place DS1977 receives enough power through 1-Wire line (see Figure 7-3, "strong pullup valid?"). loop strong pullup reading bytes repeated until memory reached, which point master will read logic 1's.
Verify Password [C3h]
This command allows user verify whether process updating password successful, eliminating risk weak programming memory cells that actually store password. command allows verifying password time. After issuing command code, master must send memory address password verified. Next master transmits password itself generates strong pullup provide power password comparison. This takes maximum, during which voltage 1-Wire must fall below 2.8V. After comparison completed, master turns strong pullup begins reading from 1-Wire line. pattern alternating indicates that verification successful, password supplied master matches stored DS1977. passwords match, master will read constant stream bytes until sends reset pulse. Before changing password, first disable passwords. Then using Write Scratchpad, Read Scratchpad Copy Scratchpad, write password respective memory location. Verify Password double-check whether password reads correctly from EEPROM memory. verification successful, safe again enable passwords.
DS1977
Figure 7-1. MEMORY/CONTROL FUNCTION FLOW CHART
Master Memory Function Command Write Scratchpad Master (T7:T0), (T15:T8)
Address Password?
From Functions Flow Chart (Figure Read Scratchpad Master (T7:T0) Master (T15:T8)
DS1977 sets Scratchpad Offset (T5:T3,0,0,0) Clears (PF, T2:T0)
Figure Part
DS1977 sets Scratchpad Offset (T5:T0) Clears (PF, Master Data Byte Scratchpad Offset DS1977 sets (E5:E0) Scratchpad Offset
Master Ending Offset with Data Status (E/S) DS1977 sets Scratchpad Offset (T5:T0) Master Data Byte from Scratchpad Offset
Master both 8-byte passwords
Master Reset? DS1977 Increments Scratchpad Offset Scratchpad Offset 3Fh? Master Reset?
Master Reset? DS1977 Increments Scratchpad Offset Scratchpad Offset 3Fh?
Partial Byte Written?
Master CRC16 Command, Address Data, Byte, Data Starting Target Address
Master CRC16 Command, Address Data
Master Reset? Master "1"s
Master Reset? Master "1"s
Functions Flow Chart (Figure
From Figure Part
DS1977
Figure 7-2. MEMORY/CONTROL FUNCTION FLOW CHART
From Figure Part
Copy Scrpad. [w/PW] Master (T7:T0), (T15:T8) Master Byte Master 64-Bits [Password] Master Activates Strong Pullup
Figure Part
Authorization Code
ReadAccess Passw.?
NOTE: strong pullup must activated within 40µs after last password transmitted. Pullup duration: tSPUW
Password Accepted? Authorization Code Match?
Save Read Password Holding Register
More data
Address Password?
Save FullAccess Password Holding Register
DS1977 Copies Scratchpad Data Data from Password Holding Register Password Address) Memory Strong Pullup Valid? DS1977 Master Reset? DS1977 Master Reset? Master "1"s Master Reset?
Figure Part
From Figure Part
DS1977
Figure 7-3. MEMORY/CONTROL FUNCTION FLOW CHART
From Figure Part
Read Mem. [w/PW] Master (T7:T0), (T15:T8) Master 64-Bits [Password] DS1977 sets Memory Address (T15:T0) Master Activates Strong Pullup
Figure Part
NOTE: strong pullup must activated within 40µs after last password transmitted. Pullup duration: tSPUR continue reading next memory page, strong pullup must activated within 40µs after last CRC16 read.
Decision made DS1977 Password Accepted? Decision made Master Master Data Byte from Memory Address Password Address Master Reset? Page? Master CRC16 Command, Address, Data Pass); CRC16 Data (Subsequent Passes) Master Reset Memory? Master Reset? Figure Part From Figure Part Master "1"s Note Master Activates Strong Pullup DS1977 Increments Address Counter DS1977 Increments Address Counter
Strong pullup valid?
DS1977
Figure 7-4. MEMORY/CONTROL FUNCTION FLOW CHART
From Figure Part
Verify Password Master (T7:T0), (T15:T8) Address Password? DS1977 sets Memory Address (T15:T3, Master Password verify Master Activates Strong Pullup
Read Version
Master bytes Master copies Version Register
NOTE: strong pullup must activated within 40µs after last password transmitted. Pullup duration: tSPUV Password Match? Master byte Master byte
Master Reset?
Master Reset?
Figure Part
DS1977
Read Version Command [CCh]
This command allows master read chip revision code DS1977. After issuing command code, master sends 00h-bytes access version register. With next time slots master receives copies content version register. Additional read-time slots will read logic 1's. Only upper bits version register valid. lower bits will read
1-Wire SYSTEM
1-Wire system, which single master more slaves. instances DS1977 slave device. master typically microcontroller small configurations 1-Wire communication signals generated under software control using single port pin. second port required control strong pullup supply power commands Copy Scratchpad with Password, Read Memory with Password Verify Password. Alternatively, DS2480B 1-Wire line driver chip serial port adapters based this chip (DS9097U series) used. This simplifies hardware design frees microprocessor from responding real-time. discussion this system broken down into three topics: hardware configuration, transaction sequence, 1-Wire signaling (signal types timing). 1-Wire protocol defines transactions terms state during specific time slots that initiated falling edge sync pulses from master. more detailed protocol description, refer Chapter Book DS19xx iButton Standards.
HARDWARE CONFIGURATION
1-Wire only single line definition; important that each device able drive appropriate time. facilitate this, each device attached 1-Wire must have open drain tri-state outputs. 1-Wire port DS1977 open-drain with internal circuit equivalent that shown Figure multi-drop consists 1-Wire with multiple slaves attached. standard speed 1-Wire maximum data rate 15.3 kbits second. speed boosted kbits second activating Overdrive mode. value pullup resistor primarily depends network size load conditions. most applications optimal value pullup resistor will approximately 2.2k standard speed 1.5k Overdrive speed. idle state 1-Wire high. reason transaction needs suspended, MUST left idle state transaction resume. this does occur left more than 16µs (Overdrive speed) more than 120µs (standard speed), more devices reset.
TRANSACTION SEQUENCE
protocol accessing DS1977 through 1-Wire port follows: Initialization Function Command Memory Function Command Transaction/Data
Illustrations transaction sequence various memory function commands found later this document.
INITIALIZATION
transactions 1-Wire begin with initialization sequence. initialization sequence consists reset pulse transmitted master followed presence pulse(s) transmitted slave(s). presence pulse lets master know that DS1977 ready operate. more details, 1Wire Signaling section.
1-Wire FUNCTION COMMANDS
Once master detected presence, issue eight function commands. function commands bits long. list these commands follows (refer flowchart Figure
DS1977
Figure HARDWARE CONFIGURATION
SIMPLE MASTER
IRLMS6702 equivalent
VPUP
DS1977 1-Wire PORT
RPUP
TEXT DATA
Open Drain Port
Strong Pullup Receive Transmit MOSFET
DS2480B MASTER HOST Serial Port serial serial 1-Wire data
DS2480B
READ [33H]
This command allows master read DS1977's 8-bit family code, unique 48-bit serial number, 8-bit CRC. This command only used there single DS1977 bus. more than slave present bus, data collision will occur when slaves transmit same time (open drain will produce wiredAND result). resultant family code 48-bit serial number will result mismatch CRC.
MATCH [55H]
Match command, followed 64-bit sequence, allows master address specific DS1977 multidrop bus. Only DS1977 that exactly matches 64-bit sequence will respond following memory function command. slaves that match 64-bit sequence will wait reset pulse. This command used with single multiple devices bus.
SEARCH [F0H]
When system initially brought master might know number devices 1-Wire their 64-bit codes. Search command allows master process elimination identify 64-bit codes slave devices bus. search process repetition simple three-step routine: read bit, read complement bit, then write desired value that bit. master performs this simple, three-step routine each ROM. After complete pass, master knows contents device. remaining number devices their codes identified additional passes. Application Note comprehensive discussion 1-Wire search algorithm.
SKIP [CCH]
This command save time single-drop system allowing master access memory functions without providing 64-bit code. more than slave present Read command issued following Skip command, data collision will occur multiple slaves transmit simultaneously (open drain pulldowns will produce wired-AND result).
DS1977
Figure 9-1. FUNCTIONS FLOW CHART
Master Reset Pulse From Memory Functions Flow Chart (Figure Reset Pulse Master Function Command DS1977 Presence Pulse Figure Part Skip Command From Figure
Part
Read Command DS1977 Family Code Byte)
Match Command
Search Command DS1977
Master
DS1977 Master
Match DS1977 Serial Number Bytes) Master
Match DS1977 DS1977 Master
Match DS1977 Byte
Match DS1977
Master
DS1977 Master
Match
Match Figure Part
Memory Functions Flow Chart (Figure
From Figure Part
DS1977
Figure 9-2. FUNCTIONS FLOW CHART
Figure Part
From Figure Part
Resume Command
Overdrive Skip
Overdrive Match
Master Reset Match Master Master
Master Reset
Match
Master
Match From Figure Part
Figure Part
DS1977
RESUME COMMAND [A5h]
Resume Command function maximizes data throughput multidrop environment. This function checks status and, set, directly transfers control Memory/Control functions, similar Skip command. only through successfully executing Match ROM, Search Overdrive Match command. Once set, device repeatedly accessed through Resume Command function. Accessing another device will clear bit, preventing more devices from simultaneously responding Resume Command function.
OVERDRIVE SKIP [3CH]
single-drop this command save time allowing master access memory functions without providing 64-bit code. Unlike normal Skip command, Overdrive Skip sets DS1977 Overdrive mode communication following this command occur Overdrive speed until reset pulse minimum 480µs duration resets devices standard speed When issued multidrop this command will Overdrive-supporting devices into Overdrive mode. subsequently address specific Overdrive-supporting device, reset pulse Overdrive speed issued followed Match Search command sequence. This will speed time search process. more than slave supporting Overdrive present Overdrive Skip command followed Read command, data collision will occur multiple slaves transmit simultaneously (open drain pulldowns will produce wired-AND result).
OVERDRIVE MATCH [69H]
Overdrive Match command followed 64-bit sequence transmitted Overdrive Speed allows master address specific DS1977 multidrop simultaneously Overdrive mode. Only DS1977 that exactly matches 64-bit sequence will respond subsequent memory function command. Slaves already Overdrive mode from previous Overdrive Skip Match command will remain Overdrive mode. overdrive-capable slaves will return standard speed next Reset Pulse minimum 480µs duration. Overdrive Match command used with single multiple devices bus.
1-Wire SIGNALING
DS1977 requires strict protocols ensure data integrity. protocol consists five types signaling line: Reset Sequence with Reset Pulse Presence Pulse, Write-Zero, Write-One Read-Data, strong pullup supply power over 1-Wire line. Except presence pulse master initiates these signals. DS1977 communicate different speeds, standard speed Overdrive Speed. explicitly into Overdrive mode, DS1977 will communicate standard speed. While Overdrive mode fast timing applies waveforms. from idle active, voltage 1-Wire line needs fall from VPUP below threshold VTL. from active idle, voltage needs rise from VILMAX past threshold VTH. time takes voltage make this rise, Figure duration depends pullup resistor (RPUP) used capacitance 1-Wire network attached. voltage VILMAX relevant DS1977 when determining logical level, triggering events. initialization sequence required begin communication with DS1977 shown Figure Reset Pulse followed Presence Pulse indicates DS1977 ready receive data, given correct memory function command. master uses slew-rate control falling edge, must pull down line tRSTL compensate edge. tRSTL duration 480µs longer will exit Overdrive mode returning device standard speed. DS1977 Overdrive Mode tRSTL longer than 80µs device will remain Overdrive mode.
DS1977
Figure INITIALIZATION PROCEDURE "RESET PRESENCE PULSES"
MASTER "RESET PULSE" MASTER "PRESENCE PULSE" VPUP VIHMASTER VILMAX tRSTL tPDH MASTER tPDL tRSTH tREC DS1977 tMSP
RESISTOR
After master released line goes into receive mode (RX). 1-Wire pulled VPUP pullup resistor case DS2480B driver, active circuitry. When threshold crossed, DS1977 waits tPDH then transmits Presence Pulse pulling line tPDL. detect presence pulse, master must test logical state 1-Wire line tMSP. tRSTH window must least tPDHMAX, tPDLMAX, tRECMIN. Immediately after tRSTH expired, DS1977 ready data communication. mixed population network tRSTH should extended minimum 480µs standard speed 48µs Overdrive speed accommodate other 1-Wire devices.
READ/WRITE-TIME SLOTS
Data communication with DS1977 takes place time slots, which carry single each. Write-time slots transport data from master slave. Read-time slots transfer data from slave master. definitions write read-time slots illustrated Figure communication begins with master pulling data line low. voltage 1-Wire line falls below threshold VTL, DS1977 starts internal timing generator that determines when data line will sampled during write-time slot long data will valid during read-time slot.
MASTER-TO-SLAVE
write-one time slot, voltage data line must have crossed VTHMAX threshold after write-one time tW1LMAX expired. write-zero time slot, voltage data line must stay below VTHMIN threshold until write-zero time tW0LMIN expired. most reliable communication voltage data line should exceed VILMAX during entire tW0L window. After VTHMAX threshold been crossed, DS1977 needs recovery time tREC before ready next time slot.
Figure READ/WRITE TIMING DIAGRAM
Write-One Time Slot
VPUP VIHMASTER VILMAX tW1L
tSLOT RESISTOR MASTER
DS1977
Figure READ/WRITE TIMING DIAGRAM (continued)
Write-Zero Time Slot
VPUP VIHMASTER VILMAX RESISTOR MASTER tREC tSLOT tW0L
Read-Data Time Slot
VPUP VIHMASTER VILMAX tSLOT RESISTOR MASTER DS1977 tMSR Master Sampling Window tREC
SLAVE-TO-MASTER
read-data time slot begins like write-one time slot. voltage data line must remain below VTLMIN until read time expired. During window, when responding with DS1977 will start pulling data line low; internal timing generator determines when this pulldown ends voltage starts rising again. When responding with DS1977 will hold data line all, voltage starts rising soon over. (rise rime) side internal timing generator DS1977 other side define master sampling window (tMSRMIN tMSRMAX) which master must perform read from data line. most reliable communication, should short permissible master should read close later than tMSRMAX. After reading from data line, master must wait until tSLOT expired. This guarantees sufficient recovery time tREC DS1977 ready next time slot.
IMPROVED NETWORK BEHAVIOR
1-Wire networks only terminated during transients controlled master (1-Wire driver) therefore susceptible noise various origins. Depending physical size topology network, reflections from points branch points cancel each other some extent. Such reflections visible glitches ringing 1-Wire communication line. glitch during rising edge time slot cause slave device lose synchronization with master and, consequence, result search command coming dead end. better performance network applications, DS1977 uses 1-Wire front end, which makes less sensitive noise also reduces magnitude noise injected slave device itself. 1-Wire front DS1977 differs from traditional slave devices four characteristics. falling edge presence pulse controlled slew rate. This provides better match line impedance than digitally switched transistor, converting high frequency ringing known from traditional
DS1977 devices into smoother low-bandwidth transition. slew rate control specified parameter tFPD, which different values standard Overdrive speed. There additional low-pass filtering circuit that detects falling edge beginning time slot. This reduces sensitivity high-frequency noise. This additional filtering does apply Overdrive speed. There hysteresis low-to-high switching threshold VTH. negative glitch crosses doesn't below VHY, will recognized (Figure Case hysteresis effective 1-Wire speed. There time window specified rising edge hold-off time tREH during which glitches will ignored, even they extend below threshold (Figure Case tREH). Deep voltage droops glitches that appear late after crossing threshold extend beyond tREH window cannot filtered will taken beginning time slot (Figure Case tREH). Only devices which have parameters tFPD, tREH specified their electrical characteristics improved 1-Wire front end.
Figure NOISE SUPPRESSION SCHEME
VPUP Case Case Case tREH tREH
GENERATION
With DS1977 there different types CRCs (Cyclic Redundancy Checks). 8-bit type stored most significant byte 64-bit ROM. master compute value from first bits 64-bit compare value stored within DS1977 determine data been received error-free. equivalent polynomial function this This 8-bit received true (non-inverted) form. computed factory lasered into ROM. other 16-bit type, generated according standardized CRC16-polynomial function This used error detection when reading memory using Read Memory with Password command fast verification data transfer when writing reading from scratchpad. contrast 8-bit CRC, 16-bit always communicated inverted form. CRC-generator inside DS1977 chip (Figure will calculate 16-bit shown command flow chart Figure master compares value read from device calculates from data decides whether continue with operation reread portion data with error. With initial pass through Read Memory with Password flow chart, 16-bit value result shifting command byte into cleared generator, followed address bytes data bytes. password excluded from calculation. Subsequent passes through Read Memory with Password flow chart will generate 16-bit that result clearing generator then shifting data bytes. With Write Scratchpad command generated first clearing generator then shifting command code, Target Addresses data bytes. DS1977 will transmit this only data bytes written scratchpad include scratchpad ending offset 3Fh. data start location within scratchpad. With Read Scratchpad command generated first clearing generator then shifting command code, Target Addresses TA2, byte, scratchpad data starting target address. DS1977 will transmit this only reading continues through scratchpad, regardless actual ending offset. more information generating values Application Note
DS1977
Figure CRC16 HARDWARE DESCRIPTION POLYNOMIAL
Polynomial
STAGE
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STAGE
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STAGE
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STAGE
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INPUT DATA
OUTPUT
COMMAND-SPECIFIC 1-Wire COMMUNICATION PROTOCOL-LEGEND
SYMBOL Select TA-E/S <data EOS> <data EOP> <PW/dummy> bytes> <data> Password Version CRC16\ loop loop Strong Pullup DESCRIPTION 1-Wire Reset Pulse Generated Master 1-Wire Presence Pulse Generated Slave Command Data Satisfy Function Protocol Command "Write Scratchpad" Command "Read Scratchpad" Command "Copy Scratchpad with Password" Command "Read Memory with Password" Command "Verify Password" Command "Read Version" Target Address TA1, Target Address TA1, with Byte Transfer Many Data Bytes Needed Reach Scratchpad Offset Transfer Many Data Bytes Needed Reach Memory Page Transfer Bytes that Either Represent Valid Password Acceptable Dummy Data Transfer Bytes Transfer Undetermined Amount Data Transmission Byte Transmission Password Transmission Device Version Number Transfer Inverted CRC16 Indefinite Loop Where Master Reads Bytes Indefinite Loop Where Master Reads Bytes Data Transfer to/from EEPROM (Data Passwords Memory); Activity 1-Wire Permitted During this Time
DS1977
COMMAND-SPECIFIC 1-WIRE COMMUNICATION PROTOCOL-COLOR CODES
Master slave Slave master Strong Pullup
WRITE SCRATCHPAD, REACHING SCRATCHPAD (CANNOT FAIL)
Select <data EOS> CRC16\ loop
WRITE SCRATCHPAD, REACHING SCRATCHPAD (CANNOT FAIL)
Select <data>
READ SCRATCHPAD (CANNOT FAIL)
Select TA-E/S <data EOS> CRC16\ loop
COPY SCRATCHPAD WITH PASSWORD (SUCCESS)
Select TA-E/S <PW/dummy> Strong Pullup loop
COPY SCRATCHPAD WITH PASSWORD (FAIL TA-E/S PASSWORD)
Select TA-E/S <PW/dummy> Strong Pullup loop
READ MEMORY WITH PASSWORD (SUCCESS)
Select <PW/dummy> Strong Pullup <data EOP> CRC16\
Strong Pullup
bytes>
CRC16\
loop Loop
READ MEMORY WITH PASSWORD (FAIL PASSWORD)
Select <PW/dummy> Strong Pullup loop
DS1977
VERIFY PASSWORD (SUCCESS)
Select Password Strong Pullup loop
VERIFY PASSWORD (FAIL ADDRESS PASSWORD)
Select Password Strong Pullup loop
READ VERSION (CANNOT FAIL)
Select Version Version loop
COMMUNICATION EXAMPLES
examples this section demonstrate memory functions typical situations. first example shows read version register. second example, passwords installed. third example shows write couple bytes read adjacent memory pages.
EXAMPLE
Task: Read version register With only single DS1977 connected master, communication follows: MASTER MODE DATA (LSB FIRST) (Reset) (Presence) Bytes 00h, <Version>, <Version> (Reset) (Presence) COMMENTS Reset Pulse Presence Pulse Issue Read Command Read Issue Read Version Register Command Write Bytes Read Chip Version Code Twice Additional Reads Result Bytes Reset Pulse Presence pulse
EXAMPLE
Task: Install activate passwords; passwords currently activated This task broken into following steps: Write passwords scratchpad Read Scratchpad Copy scratchpad Verify passwords Activate password
DS1977 With only single DS1977 connected master, communication follows: MASTER MODE Step DATA (LSB FIRST) (Reset) (Presence) <Read Password> <Full-Access Password> (Reset) (Presence) Bytes> (Reset) (Presence) Bytes> (Activate Strong Pullup tPROG) (Reset) (Presence) <Read Password> (Activate Strong Pullup tPROG) (Reset) (Presence) COMMENTS Reset Pulse Presence Pulse Issue Skip Command Issue Write Scratchpad Command TA1, Target Address (Password Start Address) TA2, Target Address 7FC0h Write 8-Byte Read Password Scratchpad Write 8-Byte Full-Access Password Scratchpad Reset Pulse Presence Pulse Issue Skip Command Issue Read Scratchpad Command Read TA1, Target Address Read TA2, Target Address 7FC0h Read E/S-Byte Read Both Passwords from Scratchpad Compare what Written Reset Pulse Presence Pulse Issue Skip Command Issue Copy Scratchpad with Password Command TA1, Target Address TA2, Target Address 7FC0h E/S-byte Transmit Dummy Bytes Password, Because Passwords Enabled Supply Power Programming Read Check Programming Success; Means Success Reset Pulse Presence Pulse Issue Skip Command Issue Verify Password Command TA1, Target Address (Read Password Address) TA2, target address 7FC0h Transmit Read Password Supply Power Password Comparison Check Password Match; Match Reset Pulse Presence Pulse Issue Skip Command Issue Verify Password Command TA1, Target Address (Full-Access
Step
Step
Step
DS1977 MASTER MODE DATA (LSB FIRST) <Full-Access Password> (Activate Strong Pullup tPROG) (Reset) (Presence) (Reset) (Presence) (Reset) (Presence) Bytes> (Activate Strong Pullup tPROG) (Reset) (Presence) COMMENTS Password Address) TA2, Target Address 7FC8h Transmit Full-Access Password Supply Power Password Comparison Check Password Match; Match Reset Pulse Presence Pulse Issue Skip Command Issue Write Scratchpad Command TA1, Target Address (Password Control Register Address) TA2, Target Address 7FD0h Write Password Enabling Pattern Reset Pulse Presence Pulse Issue Skip Command Issue Read Scratchpad Command Read TA1, Target Address Read TA2, Target Address 7FD0h Read E/S-Byte Verify Password Enabling Pattern Reset Pulse Presence Pulse Issue Skip Command Issue Copy Scratchpad with Password Command TA1, Target Address TA2, Target Address 7FD0h E/S-Byte Transmit Dummy Bytes Password, Because Passwords Enabled Supply Power Programming Read Check Programming Success; Means Success Reset Pulse Presence Pulse
Step
Instead always using Skip ROM, could Read first learn device's identification (see Example next access would Match command send correct identification address device. Subsequent accesses could Resume command. This procedure ensures that devices cannot swapped during communication session.
EXAMPLE
Task: write data bytes starting address 00A0h page read memory pages device passwords installed activated. This task broken into following steps: Write data scratchpad Read Scratchpad Copy scratchpad Read entire memory page Continue reading through page
DS1977 With only single DS1977 connected master, communication follows: MASTER MODE Step Step DATA (LSB FIRST) (Reset) (Presence) Data Bytes> (Reset) (Presence) Bytes> (Reset) (Presence) <Full-Access Password> (Activate Strong Pullup tPROG) (Reset) (Presence) <Read Password> (Activate Strong Pullup tPROG) Bytes> Bytes CRC16> (Activate Strong Pullup tPROG) Bytes> Bytes CRC16> (Reset) (Presence) COMMENTS Reset Pulse Presence Pulse Issue Skip Command Issue Write Scratchpad Command TA1, Target Address (Start Address) TA2, Target Address 00A0h Write Data Bytes Scratchpad Reset Pulse Presence Pulse Issue Skip Command Issue Read Scratchpad Command Read TA1, Target Address Read TA2, Target Address 00A0h Read E/S-Byte Read from Scratchpad Compare what Written Reset Pulse Presence Pulse Issue Skip Command Issue Copy Scratchpad with Password Command TA1, Target Address TA2, Target Address 00A0h E/S-Byte Transmit Full-Access Password Bytes) Supply Power Programming Read Check Programming Success; Means Success Reset Pulse Presence Pulse Issue Skip Command Issue Read Memory with Password Command TA1, Target Address TA2, Target Address 0080h Transmit Read Password Bytes) Supply Power Reading Read Data from Page Read Inverted CRC16 Supply Power Reading Read Data from Page Read Inverted CRC16 Reset Pulse Presence Pulse
Step
Step
Step
DS1977
REVISION HISTORY
REVISION DATE 8/09 DESCRIPTION Added sign PART number Ordering Information table, indicating RoHS-compliant product Removed UL#913 bullet from Common iButton Features section. PAGES CHANGED
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600
2009 Maxim Integrated Products Maxim registered trademark Maxim Integrated Products, Inc.

DS1977 Password-Protected 32KB EEPROM iButton iButton DESCRI

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