DS1972 1024-Bit EEPROM iButton iButton DESCRIPTION DS1972 10

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

DS1972 1024-Bit EEPROM iButton iButton DESCRIPTION DS1972 10

Datasheet Thumbnail

Top Searches for this datasheet

19-4888; 8/09
DS1972 1024-Bit EEPROM iButton
iButton DESCRIPTION
DS1972 1024-bit, 1-Wire EEPROM organized four memory pages bits each rugged iButton® package. Data written 8byte scratchpad, verified, then copied EEPROM memory. special feature, four memory pages individually write protected EPROM-emulation mode, where bits only changed from state. DS1972 communicates over single-conductor 1-Wire bus. communication follows standard Maxim 1-Wire protocol. Each device unalterable unique 64-bit registration number that factory lasered into device. registration number used address device multidrop 1-Wire environment.
SPECIAL FEATURES
1024 Bits EEPROM Memory Partitioned into Four Pages Bits Individual Memory Pages Permanently Write Protected EPROM-Emulation Mode ("Write Switchpoint Hysteresis Filtering Optimize Performance Presence Noise 1000-4-2 Level Protection (8kV Contact, 15kV Air, typical) Reads Writes Over Wide Voltage Range 2.8V 5.25V from -40°C +85°C Communicates Host with Single Digital Signal 15.4kbps 125kbps Using 1-Wire Protocol Unique Factory-Lasered 64-Bit Registration Number Assures Error-Free Device Selection Absolute Traceability Because Parts Alike Built-In Multidrop Controller 1-Wire Chip-Based Data Carrier Stores Digital Identification Information, Armored Durable Stainless-Steel Case Data Accessed While Affixed Object Button Shape Self-Aligning with Cup-Shaped Probes Easily Affixed with Self-Stick Adhesive Backing, Latched Flange, Locked with Ring Pressed onto Presence Detector Acknowledges when Reader First Applies Voltage
COMMON iButton FEATURES
APPLICATIONS
Access Control/Parking Meter Work-In-Progress Tracking Tool Management Inventory Control Maintenance/Inspection Data Storage
MicroCAN
size
3.10 0.51
size
5.89 0.51
Branding
16.25
0000006234FB
1-Wire
17.35
ORDERING INFORMATION
PART DS1972-F5+ DS1972-F3+ TEMP RANGE -40°C 85°C -40°C 85°C PIN-PACKAGE iButton iButton
+Denotes lead(Pb)-free/RoHS-compliant package.
Commands, Registers, Modes capitalized clarity.
iButton 1-Wire registered trademarks Maxim Integrated Products, Inc.
DS1972
ABSOLUTE MAXIMUM RATINGS
Voltage Sink Current Operating Temperature Range Junction Temperature Storage Temperature Range -0.5V, 20mA -40°C +85°C +150°C -40°C +85°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
-40°C +85°C; Note
PARAMETER GENERAL DATA 1-Wire Pullup Voltage 1-Wire Pullup Resistance Input Capacitance Input Load Current High-to-Low Switching Threshold Input Voltage Low-to-High Switching Threshold Switching Hysteresis Output Voltage SYMBOL VPUP RPUP CONDITIONS (Notes (Notes (Notes VPUP (Notes (Notes (Notes 0.21 applicable 15.5 15.5 0.05 0.46 5.25 1000 1.70 UNITS
(Notes (Note Standard speed, RPUP 2.2k Recovery Time Overdrive speed, RPUP 2.2k tREC (Notes 2,12) Overdrive speed, directly prior Reset Pulse; RPUP 2.2k Rising-Edge Hold-off Time Standard speed tREH (Notes Overdrive speed Timeslot Duration Standard speed tSLOT (Note Overdrive speed PIN, 1-WIRE RESET, PRESENCE DETECT CYCLE Standard speed Reset Time (Note tRSTL Overdrive speed Standard speed Presence Detect High tPDH Time Overdrive speed Standard speed Presence Detect tPDL Time Overdrive speed Standard speed Presence Detect Sample tMSP Time (Notes Overdrive speed PIN, 1-Wire WRITE Standard speed Write-0 Time (Notes tW0L Overdrive speed, VPUP 4.5V Overdrive speed Standard speed Write-1 Time tW1L (Notes Overdrive speed PIN, 1-Wire READ Standard speed Read Time (Notes Overdrive speed Standard speed Read Sample Time tMSR (Notes Overdrive speed
DS1972
PARAMETER EEPROM Programming Current Programming Time Write/Erase Cycles (Endurance) (Notes Data Retention (Notes
Note Note Note
SYMBOL IPROG tPROG (Note
CONDITIONS
UNITS -years
(Note 25°C 85°C (worst case) 85°C (worst case)
200k
Note Note Note
Note Note Note Note Note Note Note Note Note Note Note Note Note
Note
Note Note Note Note
Specifications -40°C guaranteed design only production-tested. System requirement. Maximum allowable pullup resistance function number 1-Wire devices system 1-Wire recovery times. specified value here applies systems with only device with minimum 1-Wire recovery times. more heavily loaded systems, active pullup such that found DS2482-x00, DS2480B, DS2490 required. Maximum value represents internal parasite capacitance when VPUP first applied. 2.2k resistor used pull data line, 2.5µs after VPUP been applied parasite capacitance will affect normal communications. Guaranteed design, characterization and/or simulation only. production tested. VTL, VTH, function internal supply voltage which itself function VPUP, RPUP, 1-Wire timing, capacitive loading Lower VPUP, higher RPUP, shorter tREC, heavier capacitive loading lead lower values VTL, VTH, VHY. Voltage below which, during falling edge logic detected. voltage needs less equal VIL(MAX) times master driving logic-0 level. Voltage above which, during rising edge logic detected. After crossed during rising edge voltage drop least detected logic '0'. characteristic linear voltages less than Applies single device attached 1-Wire line. earliest recognition negative edge possible tREH after been reached preceding rising edge. Defines maximum possible rate. Equal tW0L(min) tREC(min). Interval after tRSTL during which master guaranteed sample logic-0 there DS1972 present. Minimum limit tPDH(max); maximum limit tPDH(min) tPDL(min). Highlighted numbers compliance with legacy 1-Wire product standards. comparison table below. represents time required pullup circuitry pull voltage from VTH. represents time required pullup circuitry pull voltage from input high threshold master. Current drawn from during EEPROM programming interval. pullup circuit during programming interval should such that voltage greater than equal Vpup(min). Vpup system close Vpup(min) then impedance bypass Rpup which activated during programming need added. Interval begins tWiLMIN after leading negative edge last timeslot byte valid Copy Scratchpad sequence. Interval ends once device's self-timed EEPROM programming cycle complete current drawn device returned from IPROG Write-cycle endurance degraded increases. 100% production-tested; guaranteed reliability monitor sampling. Data retention degraded increases. Guaranteed 100% production test elevated temperature shorter time; equivalence this production test data sheet limit operating temperature range established reliability testing.
PARAMETER tSLOT (incl. tREC) tRSTL tPDH tPDL tW0L
LEGACY VALUES STANDARD SPEED OVERDRIVE SPEED 61µs (undef.) (undef.) 480µs (undef.) 48µs 80µs 15µs 60µs 60µs 240µs 24µs 60µs 120µs 16µs
DS1972 VALUES STANDARD SPEED OVERDRIVE SPEED 65µs1) (undef.) 8µs1) (undef.) 480µs 640µs 48µs 80µs 15µs 60µs 60µs 240µs 24µs 60µs 120µs 15.5µs
Intentional change, longer recovery time requirement modified 1-Wire front end.
EXAMPLES ACCESSORIES
PART DS9096P DS9101 DS9093RA DS9093A DS9092 DESCRIPTION Self-Stick Adhesive Multipurpose Clip Mounting Lock Ring Snap-In iButton Probe
DS1972
DESCRIPTION
DS1972 combines 1024 bits EEPROM, 8-byte register/control page with user read/write bytes, fully-featured 1-Wire interface rugged iButton package. Each DS1972 64-bit registration number that factory lasered provide guaranteed unique identity absolute traceability. Data transferred serially 1-Wire protocol, which requires only single data contact ground return. DS1972 additional memory area called scratchpad that acts buffer when writing main memory register page. Data first written scratchpad from which read back. After data been verified, Copy Scratchpad command transfers data final memory location. Applications DS1972 include access control/parking meter, Work-In-Progress tracking, tool management, inventory control, maintenance/inspection data storage. Software communication with DS1972 available free download from website.
OVERVIEW
block diagram Figure shows relationships between major control memory sections DS1972. DS1972 four main data components: 64-bit lasered ROM, 64-bit scratchpad, four 32-byte pages EEPROM, 64-bit register page. hierarchical structure 1-Wire protocol shown Figure master must first provide seven Function Commands, Read ROM, Match ROM, Search ROM, Skip ROM, Resume, Overdrive-Skip Overdrive-Match ROM. Upon completion Overdrive command byte executed standard speed, device enters Overdrive mode where subsequent communication occurs higher speed. protocol required these function commands described Figure After function command successfully executed, memory functions become accessible master provide four memory function commands. protocol these memory function commands described Figure data read written least significant first.
Figure Block Diagram
PARASITE POWER
1-Wire Function Control
64-bit Lasered
Memory Function Control Unit
DS1972
CRC16 Generator 64-bit Scratchpad Data Memory Pages bits each
Register Page bits
DS1972
Figure Hierarchical Structure 1-Wire Protocol
Available Commands:
Read Match Search Skip Resume Overdrive-Skip Overdrive-Match Write Scratchpad Read Scratchpad Copy Scratchpad Read Memory
DS1972 Command Level:
Data Field Affected:
64-bit Reg. RC-Flag 64-bit Reg. RC-Flag 64-bit Reg. RC-Flag RC-Flag RC-Flag RC-Flag, OD-Flag 64-bit Reg. RC-Flag, OD-Flag 64-bit Scratchpad, Flags 64-bit Scratchpad Data Memory, Register Page Data Memory, Register Page
1-Wire Function Commands (see Figure
DS1972-specific Memory Function Commands (see Figure
64-BIT LASERED
Each DS1972 contains unique code that bits long. first bits 1-Wire family code. next bits unique serial number. last bits (Cyclic Redundancy Check) first bits. Figure details. 1-Wire generated using polynomial generator consisting shift register gates shown Figure polynomial Additional information about Dallas 1-Wire available Application Note shift register bits initialized Then starting with least significant family code, time shifted After family code been entered, then serial number entered. After last serial number been entered, shift register contains value. Shifting bits returns shift register
Figure 64-Bit Lasered
8-Bit Code 48-Bit Serial Number 8-Bit Family Code (2Dh)
Figure 1-Wire Generator
Polynomial
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
INPUT DATA
DS1972
Figure Memory
ADDRESS RANGE 0000h 001Fh 0020h 003Fh 0040h 005Fh 0060h 007Fh 0080h
TYPE R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W)
DESCRIPTION Data Memory Page Data Memory Page Data Memory Page Data Memory Page Protection Control Byte Page Protection Control Byte Page Protection Control Byte Page Protection Control Byte Page Copy Protection Byte Factory byte. Factory. User Byte/Manufacturer User Byte/Manufacturer Reserved
PROTECTION CODES
55h: Write Protect AAh: EPROM mode AAh: Write Protect 55h: Write Protect AAh: EPROM mode AAh: Write Protect 55h: Write Protect AAh: EPROM mode AAh: Write Protect 55h: Write Protect AAh: EPROM mode AAh: Write Protect AAh: Copy Protect 0080:008Fh, write-protected Pages AAh:Write Protect 85h, 86h, 87h; 55h: Write Protect 85h, unprotect 86h,
0081h1) 0082h1) 0083h1) 0084h1) 0085h 0086h 0087h 0088h 008Fh
Once programmed this address becomes read-only. other codes stored will neither write-protect address activate function.
MEMORY
Data memory registers located linear address space, shown Figure data memory registers have unrestricted read access. DS1972 EEPROM array consists rows bytes each. first rows divided equally into memory pages bytes each). These pages primary data memory. Each page individually Open (unprotected), Write-Protected, EPROM mode setting associated protection byte register row. last rows contain protection registers, reserved bytes. register consists protection control bytes, copy protection byte, factory byte, user byte/manufacture bytes. manufacturer customer-supplied identification code that assists application software identifying product DS1972 associated with. Contact factory register custom manufacturer last reserved future use. undefined terms functionality should used. addition main EEPROM array, 8-byte volatile scratchpad included. Writes EEPROM array two-step process. First, data written scratchpad, then copied into main array. This allows user first verify data written scratchpad prior copying into main array. device only supports full (8-byte) copy operations. order data scratchpad valid copy operation, address supplied with Write Scratchpad must start boundary, full bytes must written into scratchpad.
DS1972 protection control registers determine incoming data Write Scratchpad command loaded into scratchpad. protection setting (Write Protect) causes incoming data ingnored target address main memory data loaded into scratchpad. protection setting (EPROM mode) causes logical incoming data target address main memory data loaded into scratchpad. other protection control register setting leaves associated memory page open unrestricted write access. Protection control byte settings also write protects protection control byte. protection-control byte setting does block copy. This allows write-protected data refreshed reprogrammed with current data) device. copy protection byte used higher level security, should only used after other protection control bytes, user bytes, write-protected pages their final value. copy protection byte AAh, copy attempts register user byte blocked. addition, copy attempts write-protected main memory pages refresh) blocked.
ADDRESS REGISTERS TRANSFER STATUS
DS1972 employs three address registers: TA1, TA2, (Figure These registers common many other 1-Wire devices operate slightly differently with DS1972. Registers must loaded with target address which data written from which data read. Register read-only transferstatus register, used verify data integrity with write commands. bits E2:E0 loaded with incoming T2:T0 Write Scratchpad command, increment each subsequent data byte. This effect byteending offset counter within 8-byte scratchpad. register, called logic data scratchpad valid loss power master sends less bytes than needed reach scratchpad. valid write scratchpad, T2:T0 must master must have sent data bytes. Bits have function; they always read highest valued register, called Authorization Accepted, acts flag indicate that data stored scratchpad already been copied target memory address. Writing data scratchpad clears this flag.
Figure Address Registers
Target Address (TA1)
Target Address (TA2) Ending Address with Data Status (E/S) (Read Only)
DS1972
WRITING WITH VERIFICATION
write data DS1972, scratchpad used intermediate storage. First master issues Write Scratchpad command specify desired target address, followed data written scratchpad. Note that Copy Scratchpad commands must performed 8-byte boundaries, LSBs target address (T2.T0) must equal 000b. T2.T0 sent with non-zero values, copy function will blocked. Under certain conditions (see Write Scratchpad command) master will receive inverted CRC16 command, address (actual address sent) data Write Scratchpad command sequence. Knowing this value, master compare value calculated itself decide communication successful proceed Copy Scratchpad command. master could receive CRC16, should send Read Scratchpad command verify data integrity. preamble scratchpad data, DS1972 repeats target address sends contents register. flag set, data arrive correctly scratchpad there loss power since data last written scratchpad. master does need continue reading; start trial write data scratchpad. Similarly, flag together with cleared flag indicates that device recognize Write command. everything went correctly, both flags cleared. master continue reading verifying every data byte. After master verified data, send Copy Scratchpad command, example. This command must followed exactly data three address registers, TA1, TA2, E/S. master should obtain contents these registers reading scratchpad.
MEMORY FUNCTION COMMANDS
Memory Function Flow Chart (Figure describes protocols necessary accessing memory DS1972. example these functions write read from device included this document. communication between master DS1972 takes place either regular speed (default, Overdrive Speed explicitly into Overdrive mode, DS1972 assumes regular speed.
WRITE SCRATCHPAD COMMAND [0Fh]
Write Scratchpad command applies data memory, writable addresses register page. order scratchpad data valid copying array, user must perform Write Scratchpad command bytes starting valid boundary. Write Scratchpad command accepts invalid addresses, partial rows, subsequent Copy Scratchpad commands blocked. After issuing Write Scratchpad command, master must first provide 2-byte target address, followed data written scratchpad. data written scratchpad starting byte offset T2:T0. bits E2:E0 loaded with starting byte offset, increment with each susequent byte. Effectively, E2:E0 byte offset last full byte written scratchpad. Only full data bytes accepted. When executing Write Scratchpad command, generator inside DS1972 (Figure calculates entire data stream, starting command code ending last data byte sent master. This generated using CRC16 polynomial first clearing generator then shifting command code (0Fh) Write Scratchpad command, Target Addresses (TA1 TA2), data bytes. Note that CRC16 calculation performed with actual data sent master. master Write Scratchpad command time. However, scratchpad reached (E2:E0 111b), master send read-time slots receive generated DS1972. Write Scratchpad attempted write-protected location, scratchpad loaded with data already memory, rather than data transmitted. Similarly, target address page EPROM mode, scratchpad loaded with bitwise logical transmitted data data already memory.
DS1972
Figure 7-1. Memory Function Flow Chart
Master Memory Function Command Write Scratchpad Master (T7:T0), (T15:T8) From Functions Flow Chart (Figure Figure Part
DS1972 sets Sets Clears Sets E2:E0 T2:T0
Master Data Byte Scratchpad
Applies only memory area protected. write-protected, then DS1972 copies data byte from target address into EPROM mode, then DS1972 loads bitwise logical transmitted byte data byte from targeted address into
Master Reset DS1972 Increments E2:E0 E2:E0 T2:T0
DS1972 CRC16 Command, Address, Data Bytes they were sent master
Master "1"s
Master Reset From Figure Part
Functions Flow Chart (Figure
DS1972
Figure 7-2. Memory Function Flow Chart (continued)
From Figure Part
Read ScratchPad
Figure Part
Master (T7:T0), (T15:T8) Byte DS1972 sets Scratchpad Byte Counter T2:T0
Master Data Byte from Scratchpad
DS1972 Increments Byte Counter
Master Reset Byte Counter E2:E0
Master CRC16 Command, Address, Byte, Data Bytes sent DS1972
Master "1"s
Master Reset
Figure Part
From Figure Part
DS1972
Figure 7-3. Memory Function Flow Chart (continued)
From Figure Part
Copy ScratchPad
Figure Part
Master (T7:T0), (T15:T8) Byte
Applicable memory locations.
Auth. Code Match
T15:T0 0090h
CopyProtected Duration: tPROG DS1972 copies Scratchpad Data Address DS1972
Master "1"s
Master Reset
Master Reset
DS1972
Master Reset
Figure Part
1-Wire idle high power
From Figure Part
DS1972
Figure 7-4. Memory Function Flow Chart (continued)
From Figure Part
Read Memory Master (T7:T0), (T15:T8)
Address
DS1972 sets Memory Address (T15:T0)
DS1972 Increments Address Counter
Master Data Byte from Memory Address
Master Reset Address Master "1"s Master Reset
Master "1"s
Master Reset
Figure Part
DS1972
READ SCRATCHPAD COMMAND [AAh]
Read Scratchpad command allows verifying target address integrity scratchpad data. After issuing command code, master begins reading. first bytes target address. next byte ending offset/data status byte (E/S) followed scratchpad data, which different from what master originally sent. This particular importance target address within register page page either Write Protection EPROM modes. Write Scratchpad description details. master should read through scratchpad (E2:E0 T2:T0 bytes), after which will receive inverted CRC, based data sent DS1972. master continues reading after CRC, data will logic
COPY SCRATCHPAD [55h]
Copy Scratchpad command used copy data from scratchpad writable memory sections. After issuing Copy Scratchpad command, master must provide 3-byte authorization pattern, which should have been obtained immediately preceding Read Scratchpad command. This 3-byte pattern must exactly match data contained three address registers (TA1, TA2, E/S, that order). pattern matches, target address valid, flag set, target memory copy-protected, (Authorization Accepted) flag copy begins. eight bytes scratchpad contents copied target memory location. duration device's internal data transfer tPROG during which voltage 1-Wire must fall below 2.8V. pattern alternating transmitted after data been copied until master issues Reset Pulse. flag target memory copy-protected, copy will begin flag will set. copy command disturbed lack power other reasons, master will read constant stream bytes until sends 1-Wire Reset Pulse. this case destination memory incompletely programmed requiring write scratchpad copy scratchpad repeated ensure proper programming EEPROM. This requires careful consideration when designing application software that writes DS1972 intermittent contact environment.
READ MEMORY [F0h]
Read Memory command general function read data from DS1972. After issuing command, master must provide 2-byte target address. After these bytes, master reads data beginning from target address continue until address 008Fh. master continues reading, result will logic device's internal TA1, TA2, E/S, scratchpad contents affected Read Memory command.
1-Wire SYSTEM
1-Wire system that single master more slaves. instances DS1972 slave device. master typically microcontroller. discussion this system broken down into three topics: hardware configuration, transaction sequence, 1-Wire signaling (signal types timing). 1-Wire protocol defines transactions terms state during specific time slots, which initiated falling edge sync pulses from master.
HARDWARE CONFIGURATION
1-Wire only single line definition; important that each device able drive appropriate time. facilitate this, each device attached 1-Wire must have open-drain tri-state outputs. 1-Wire port DS1972 open drain with internal circuit equivalent that shown Figure multidrop consists 1-Wire with multiple slaves attached. DS1972 supports both Standard Overdrive communication speed 15.4kbps (max) 125kbps (max), respectively. Note that legacy 1-Wire products support standard communication speed 16.3kbps Overdrive 142kbps. slightly reduced rates DS1972 result additional recovery times, which turn were driven 1-Wire physical interface enhancement improve noise immunity. value pullup resistor primarily depends network size load conditions. DS1972 requires pullup resistor 2.2k (max) speed. idle state 1-Wire high. reason transaction needs suspended, MUST left idle state transaction resume. this does occur left more than 16µs (Overdrive speed) more than 120µs (standard speed), more devices reset.
DS1972
Figure Hardware Configuration
MASTER VPUP RPUP DATA MOSFET DS1972 1-Wire PORT
Open Drain Port RECEIVE TRANSMIT
TRANSACTION SEQUENCE
protocol accessing DS1972 through 1-Wire port follows: Initialization Function Command Memory Function Command Transaction/Data
INITIALIZATION
transactions 1-Wire begin with initialization sequence. initialization sequence consists Reset Pulse transmitted master followed Presence Pulse(s) transmitted slave(s). Presence Pulse lets master know that DS1972 ready operate. more details, 1-Wire Signaling section.
1-Wire FUNCTION COMMANDS
Once master detected presence, issue seven function commands that DS1972 supports. function commands bits long. list these commands follows (refer flow chart Figure
READ [33h]
This command allows master read DS1972's 8-bit family code, unique 48-bit serial number, 8-bit CRC. This command only used there single slave bus. more than slave present bus, data collision occurs when slaves transmit same time (open drain produces wired-AND result). resultant family code 48-bit serial number result mismatch CRC.
MATCH [55h]
Match command, followed 64-bit sequence, allows master address specific DS1972 multidrop bus. Only DS1972 that exactly matches 64-bit sequence responds following memory function command. other slaves wait Reset Pulse. This command used with single multiple devices bus.
DS1972
SEARCH [F0h]
When system initially brought master might know number devices 1-Wire their registration numbers. taking advantage wired-AND property bus, master process elimination identify registration numbers slave devices. each registration number, starting with least significant bit, master issues triplet time slots. first slot, each slave device participating search outputs true value registration number bit. second slot, each slave device participating search outputs complemented value registration number bit. third slot, master writes true value selected. slave devices that match written master stop participating search. both read bits zero, master knows that slave devices exist with both states bit. choosing which state write, master branches romcode tree. After complete pass, master knows registration number single device. Additional passes identify registration numbers remaining devices. Refer Application Note 187: 1-Wire Search Algorithm detailed discussion, including example.
SKIP [CCh]
This command save time single-drop system allowing master access memory functions without providing 64-bit code. more than slave present and, example, Read command issued following Skip command, data collision occurs multiple slaves transmit simultaneously (open-drain pulldowns produce wired-AND result).
RESUME [A5h]
maximize data throughput multidrop environment, Resume function available. This function checks status and, set, directly transfers control memory functions, similar Skip command. only through successfully executing Match ROM, Search ROM, Overdrive-Match command. Once set, device repeatedly accessed through Resume Command function. Accessing another device clears bit, preventing more devices from simultaneously responding Resume Command function.
OVERDRIVE-SKIP [3Ch]
single-drop this command save time allowing master access memory functions without providing 64-bit code. Unlike normal Skip command, Overdrive-Skip sets DS1972 Overdrive mode communication following this command occur Overdrive speed until Reset Pulse minimum 480µs duration resets devices standard speed When issued multidrop bus, this command sets Overdrive-supporting devices into Overdrive mode. subsequently address specific Overdrive-supporting device, Reset Pulse Overdrive speed issued followed Match Search command sequence. This speeds time search process. more than slave supporting Overdrive present Overdrive-Skip command followed Read command, data collision occurs multiple slaves transmit simultaneously (open-drain pulldowns produce wired-AND result).
OVERDRIVE-MATCH [69h]
Overdrive-Match command followed 64-bit sequence transmitted Overdrive Speed allows master address specific DS1972 multidrop simultaneously Overdrive mode. Only DS1972 that exactly matches 64-bit sequence responds subsequent memory function command. Slaves already Overdrive mode from previous Overdrive-Skip successful Overdrive-Match command remain Overdrive mode. overdrive-capable slaves return standard speed next Reset Pulse minimum 480µs duration. Overdrive-Match command used with single multiple devices bus.
DS1972
Figure 9-1. Functions Flow Chart
Master Reset Pulse From Memory Functions Flow Chart (Figure Reset Pulse Master Function Command DS1972 Presence Pulse Figure Part Skip Command From Figure
Part
Read Command DS1972 Family Code Byte)
Match Command
Search Command DS1972
Master
DS1972 Master
Match DS1972 Serial Number Bytes) Master
Match DS1972 DS1972 Master
Match DS1972 Byte
Match DS1972
Master
DS1972 Master
Match
Match Figure Part
Memory Functions Flow Chart (Figure
From Figure Part
DS1972
Figure 9-2. Functions Flow Chart (continued)
Figure Part
From Figure Part
Resume Command
OverdriveSkip
Overdrive-Match
Master Reset Match Master Master
Master Reset
Match
Master
Match From Figure Part
Figure Part
DS1972
1-Wire SIGNALING
DS1972 requires strict protocols ensure data integrity. protocol consists four types signaling line: Reset Sequence with Reset Pulse Presence Pulse, Write-Zero, Write-One, Read-Data. Except Presence Pulse, master initiates falling edges. DS1972 communicate different speeds, standard speed, Overdrive Speed. explicitly into Overdrive mode, DS1972 communicates standard speed. While Overdrive mode fast timing applies waveforms. from idle active, voltage 1-Wire line needs fall from VPUP below threshold VTL. from active idle, voltage needs rise from VILMAX past threshold VTH. time takes voltage make this rise seen Figure duration depends pullup resistor (RPUP) used capacitance 1-Wire network attached. voltage VILMAX relevant DS1972 when determining logical level, triggering events. Figure shows initialization sequence required begin communication with DS1972. Reset Pulse followed Presence Pulse indicates DS1972 ready receive data, given correct memory function command. master uses slew-rate control falling edge, must pull down line tRSTL compensate edge. tRSTL duration 480µs longer exits Overdrive mode, returning device standard speed. DS1972 Overdrive mode tRSTL longer than 80µs. device remains Overdrive mode. device Overdrive mode tRSTL between 80µs 480µs, device will reset, communication speed undetermined.
Figure Initialization Procedure: Reset Presence Pulse
MASTER "RESET PULSE" MASTER "PRESENCE PULSE" VPUP VIHMASTER VILMAX tRSTL tPDH MASTER tPDL tRSTH tREC DS1972 tMSP
RESISTOR
After master released line goes into Receive mode. 1-Wire pulled VPUP through pullup resistor, case DS2482-x00 DS2480B driver, active circuitry. When threshold crossed, DS1972 waits tPDH then transmits Presence Pulse pulling line tPDL. detect Presence Pulse, master must test logical state 1-Wire line tMSP. tRSTH window must least tPDHMAX, tPDLMAX, tRECMIN. Immediately after tRSTH expired, DS1972 ready data communication. mixed population network, tRSTH should extended minimum 480µs standard speed 48µs Overdrive speed accommodate other 1-Wire devices.
Read-/Write-Time Slots
Data communication with DS1972 takes place time slots, which carry single each. Write-time slots transport data from master slave. Read-time slots transfer data from slave master. Figure illustrates definitions write- read-time slots. communication begins with master pulling data line low. voltage 1-Wire line falls below threshold VTL, DS1972 starts internal timing generator that determines when data line sampled during write-time slot long data valid during read-time slot.
DS1972
Master-to-Slave
write-one time slot, voltage data line must have crossed threshold before write-one time tW1LMAX expired. write-zero time slot, voltage data line must stay below threshold until write-zero time tW0LMIN expired. most reliable communication, voltage data line should exceed VILMAX during entire tW0L tW1L window. After threshold been crossed, DS1972 needs recovery time tREC before ready next time slot.
Figure Read/Write Timing Diagram Write-One Time Slot
VPUP VIHMASTER VILMAX tW1L
RESISTOR
tSLOT MASTER
Write-Zero Time Slot
VPUP VIHMASTER VILMAX RESISTOR tSLOT MASTER tREC tW0L
Read-Data Time Slot
VPUP VIHMASTER VILMAX RESISTOR tSLOT MASTER DS1972 tMSR Master Sampling Window tREC
DS1972
Slave-to-Master
read-data time slot begins like write-one time slot. voltage data line must remain below until read time expired. During window, when responding with DS1972 starts pulling data line low; internal timing generator determines when this pulldown ends voltage starts rising again. When responding with DS1972 does hold data line all, voltage starts rising soon over. (rise time) side internal timing generator DS1972 other side define master sampling window (tMSRMIN tMSRMAX) which master must perform read from data line. most reliable communication, should short permissible, master should read close later than tMSRMAX. After reading from data line, master must wait until tSLOT expired. This guarantees sufficient recovery time tREC DS1972 ready next time slot. Note that tREC specified herein applies only single DS1972 attached 1-Wire line. multidevice configurations, tREC needs extended accommodate additional 1-Wire device input capacitance. Alternatively, interface that performs active pullup during 1-Wire recovery time such DS2482-x00 DS2480B 1-Wire line drivers used.
IMPROVED NETWORK BEHAVIOR (SWITCHPOINT HYSTERESIS)
1-Wire environment, line termination possible only during transients controlled master (1-Wire driver). 1-Wire networks, therefore, susceptible noise various origins. Depending physical size topology network, reflections from points branch points cancel each other some extent. Such reflections visible glitches ringing 1-Wire communication line. Noise coupled onto 1-Wire line from external sources also result signal glitching. glitch during rising edge time slot cause slave device lose synchronization with master and, consequently, result Search command coming dead cause device-specific function command abort. better performance network applications, DS1972 uses 1-Wire front end, which makes less sensitive noise. 1-Wire front DS1972 differs from traditional slave devices three characteristics. There additional low-pass filtering circuit that detects falling edge beginning time slot. This reduces sensitivity high-frequency noise. This additional filtering does apply Overdrive speed. There hysteresis low-to-high switching threshold VTH. negative glitch crosses does below VHY, will recognized (Figure Case hysteresis effective 1-Wire speed. There time window specified rising edge hold-off time tREH during which glitches ignored, even they extend below threshold (Figure Case tREH). Deep voltage droops glitches that appear late after crossing threshold extend beyond tREH window cannot filtered taken beginning time slot (Figure Case tREH). Devices that have parameters VHY, tREH specified their electrical characteristics improved 1-Wire front end.
Figure Noise Suppression Scheme
VPUP Case Case Case tREH tREH
DS1972
GENERATION
With DS1972 there different types CRCs. 8-bit type stored most significant byte 64-bit ROM. master compute value from first bits 64-bit compare value stored within DS1972 determine data been received errorfree. equivalent polynomial function this This 8-bit received true (noninverted) form. computed factory lasered into ROM. other 16-bit type, generated according standardized CRC16-polynomial function This used fast verification data transfer when writing reading from scratchpad. contrast 8-bit CRC, 16-bit always communicated inverted form. generator inside DS1972 iButton (Figure calculates 16-bit CRC, shown command flow chart (Figure master compares value read from device calculates from data, decides whether continue with operation reread portion data with error. With Write Scratchpad command, generated first clearing generator then shifting command code, Target Addresses TA2, data bytes they were sent master. DS1972 transmits this only E2:E0 111b. With Read Scratchpad command, generated first clearing generator then shifting Command code, target addresses TA2, byte, scratchpad data they were sent DS1972. DS1972 transmits this only reading continues through scratchpad. more information generating values, refer Application Note
Figure CRC-16 Hardware Description Polynomial
Polynomial
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
INPUT DATA
OUTPUT
COMMAND-SPECIFIC 1-Wire COMMUNICATION PROTOCOL-COLOR CODES
Master slave Slave master Programming
DS1972
COMMAND-SPECIFIC 1-Wire COMMUNICATION PROTOCOL-LEGEND
SYMBOL Select TA-E/S T2:T0 bytes> <data EOM> CRC16\ loop loop Programming DESCRIPTION 1-Wire Reset Pulse generated master. 1-Wire Presence Pulse generated slave. Command data satisfy function protocol. Command "Write Scratchpad". Command "Read Scratchpad". Command "Copy Scratchpad". Command "Read Memory". Target Address TA1, TA2. Target Address TA1, with byte. Transfer many bytes needed reach scratchpad given target address. Transfer many data bytes needed reach memory. Transfer inverted CRC16. Indefinite loop where master reads bytes. Indefinite loop where master reads bytes. Data transfer EEPROM; activity 1-Wire permitted during this time.
WRITE SCRATCHPAD (CANNOT FAIL)
Select T2:T0 bytes> CRC16\ loop
READ SCRATCHPAD (CANNOT FAIL)
Select TA-E/S T2:T0 bytes> CRC16\ loop
COPY SCRATCHPAD (SUCCESS)
Select TA-E/S Programming loop
COPY SCRATCHPAD (INVALID ADDRESS COPY PROTECTED)
Select TA-E/S loop
READ MEMORY (SUCCESS)
Select <data EOM> loop
READ MEMORY (INVALID ADDRESS)
Select loop
DS1972
MEMORY FUNCTION EXAMPLE
Write first bytes memory page Read entire memory. With only single DS1972 connected master, communication looks like this: MASTER MODE DATA (LSB FIRST) (Reset) (Presence) data bytes> bytes CRC16\> (Reset) (Presence) data bytes> bytes CRC16\> (Reset) (Presence) <1-Wire idle high> (Reset) (Presence) <144 data bytes> (Reset) (Presence) COMMENTS Reset Pulse Presence Pulse Issue "Skip ROM" command Issue "Write scratchpad" command TA1, beginning offset TA2, address 0020h Write bytes data scratchpad Read check data integrity Reset Pulse Presence Pulse Issue "Skip ROM" command Issue "Read scratchpad" command Read TA1, beginning offset Read TA2, address 0020h Read E/S, ending offset 111b, Read scratchpad data verify Read check data integrity Reset Pulse Presence Pulse Issue "Skip ROM" command Issue "Copy scratchpad" command (AUTHORIZATION CODE) Wait tPROGmax copy function complete Read copy status, success Reset Pulse Presence Pulse Issue "Skip ROM" command Issue "Read Memory" command TA1, beginning offset TA2, address 0000h Read entire memory Reset Pulse Presence Pulse
DS1972
REVISION HISTORY
REVISION DATE 8/09 DESCRIPTION Changed RoHS packages lead(Pb)-free packages Ordering Information table. Removed UL#913 bullet from Common iButton Features section. PAGES CHANGED
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600
2009 Maxim Integrated Products Maxim registered trademark Maxim Integrated Products, Inc.

DS1972 1024-Bit EEPROM iButton iButton DESCRIPTION DS1972 10

Top Searches for this datasheet

Other recent searches